1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _input_system_defs_h 17 #define _input_system_defs_h 18 19 /* csi controller modes */ 20 #define HIVE_CSI_CONFIG_MAIN 0 21 #define HIVE_CSI_CONFIG_STEREO1 4 22 #define HIVE_CSI_CONFIG_STEREO2 8 23 24 /* general purpose register IDs */ 25 26 /* Stream Multicast select modes */ 27 #define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 28 #define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 29 #define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 30 31 /* Stream Mux select modes */ 32 #define HIVE_ISYS_GPREG_MUX_IDX 3 33 34 /* streaming monitor status and control */ 35 #define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 36 #define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 37 #define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 38 #define HIVE_ISYS_GPREG_SRST_IDX 7 39 #define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 40 #define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 41 #define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 42 43 /* Bit numbers of the soft reset register */ 44 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 45 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 46 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 47 #define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 48 #define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 49 #define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 50 #define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 51 #define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 52 #define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 53 #define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 54 /* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ 55 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ 56 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 57 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 58 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 59 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 60 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 61 /* -- */ 62 #define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 63 #define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 64 #define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 65 #define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv 66 #define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 67 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 68 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 69 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 70 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 71 #define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 72 73 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 74 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 75 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 76 #define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 77 #define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 78 #define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 79 80 /* streaming monitor port id's */ 81 #define HIVE_ISYS_STR_MON_PORT_CAPA 0 82 #define HIVE_ISYS_STR_MON_PORT_CAPB 1 83 #define HIVE_ISYS_STR_MON_PORT_CAPC 2 84 #define HIVE_ISYS_STR_MON_PORT_ACQ 3 85 #define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 86 #define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 87 #define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 88 #define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 89 #define HIVE_ISYS_STR_MON_PORT_PIXA 8 90 #define HIVE_ISYS_STR_MON_PORT_PIXB 9 91 92 /* interrupt bit ID's */ 93 #define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 94 #define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 95 #define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 96 #define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 97 #define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 98 #define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 99 #define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 100 #define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 101 /*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ 102 #define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 103 #define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 104 /*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ 105 #define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 106 #define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 107 /*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ 108 #define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 109 /*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ 110 #define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 111 #define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 112 #define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 113 #define HIVE_ISYS_IRQ_CIO2AHB 16 114 #define HIVE_ISYS_IRQ_DMA_BIT_ID 17 115 #define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 116 #define HIVE_ISYS_IRQ_NUM_BITS 19 117 118 /* DMA */ 119 #define HIVE_ISYS_DMA_CHANNEL 0 120 #define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 121 #define HIVE_ISYS_DMA_HEIGHT 1 122 #define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ 123 #define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ 124 #define HIVE_ISYS_DMA_CROP 0 /* no cropping */ 125 #define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ 126 127 #endif /* _input_system_defs_h */ 128