1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/dmaengine.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/dma/qcom-gpi-dma.h>
9 #include <linux/err.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/soc/qcom/geni-se.h>
18 #include <linux/spinlock.h>
19 #include <linux/units.h>
20
21 #define SE_I2C_TX_TRANS_LEN 0x26c
22 #define SE_I2C_RX_TRANS_LEN 0x270
23 #define SE_I2C_SCL_COUNTERS 0x278
24
25 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
26 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
27 #define SE_I2C_ABORT BIT(1)
28
29 /* M_CMD OP codes for I2C */
30 #define I2C_WRITE 0x1
31 #define I2C_READ 0x2
32 #define I2C_WRITE_READ 0x3
33 #define I2C_ADDR_ONLY 0x4
34 #define I2C_BUS_CLEAR 0x6
35 #define I2C_STOP_ON_BUS 0x7
36 /* M_CMD params for I2C */
37 #define PRE_CMD_DELAY BIT(0)
38 #define TIMESTAMP_BEFORE BIT(1)
39 #define STOP_STRETCH BIT(2)
40 #define TIMESTAMP_AFTER BIT(3)
41 #define POST_COMMAND_DELAY BIT(4)
42 #define IGNORE_ADD_NACK BIT(6)
43 #define READ_FINISHED_WITH_ACK BIT(7)
44 #define BYPASS_ADDR_PHASE BIT(8)
45 #define SLV_ADDR_MSK GENMASK(15, 9)
46 #define SLV_ADDR_SHFT 9
47 /* I2C SCL COUNTER fields */
48 #define HIGH_COUNTER_MSK GENMASK(29, 20)
49 #define HIGH_COUNTER_SHFT 20
50 #define LOW_COUNTER_MSK GENMASK(19, 10)
51 #define LOW_COUNTER_SHFT 10
52 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
53
54 #define I2C_PACK_TX BIT(0)
55 #define I2C_PACK_RX BIT(1)
56
57 enum geni_i2c_err_code {
58 GP_IRQ0,
59 NACK,
60 GP_IRQ2,
61 BUS_PROTO,
62 ARB_LOST,
63 GP_IRQ5,
64 GENI_OVERRUN,
65 GENI_ILLEGAL_CMD,
66 GENI_ABORT_DONE,
67 GENI_TIMEOUT,
68 };
69
70 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
71 << 5)
72
73 #define I2C_AUTO_SUSPEND_DELAY 250
74 #define PACKING_BYTES_PW 4
75
76 #define ABORT_TIMEOUT HZ
77 #define XFER_TIMEOUT HZ
78 #define RST_TIMEOUT HZ
79
80 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2
81
82 /**
83 * struct geni_i2c_gpi_multi_desc_xfer - Structure for multi transfer support
84 *
85 * @msg_idx_cnt: Current message index being processed in the transfer
86 * @unmap_msg_cnt: Number of messages that have been unmapped
87 * @irq_cnt: Number of transfer completion interrupts received
88 * @dma_buf: Array of virtual addresses for DMA-safe buffers
89 * @dma_addr: Array of DMA addresses corresponding to the buffers
90 */
91 struct geni_i2c_gpi_multi_desc_xfer {
92 u32 msg_idx_cnt;
93 u32 unmap_msg_cnt;
94 u32 irq_cnt;
95 void **dma_buf;
96 dma_addr_t *dma_addr;
97 };
98
99 struct geni_i2c_dev {
100 struct geni_se se;
101 u32 tx_wm;
102 int irq;
103 int err;
104 struct i2c_adapter adap;
105 struct completion done;
106 struct i2c_msg *cur;
107 int cur_wr;
108 int cur_rd;
109 spinlock_t lock;
110 struct clk *core_clk;
111 u32 clk_freq_out;
112 const struct geni_i2c_clk_fld *clk_fld;
113 int suspended;
114 void *dma_buf;
115 size_t xfer_len;
116 dma_addr_t dma_addr;
117 struct dma_chan *tx_c;
118 struct dma_chan *rx_c;
119 bool gpi_mode;
120 bool abort_done;
121 bool is_tx_multi_desc_xfer;
122 u32 num_msgs;
123 struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config;
124 };
125
126 struct geni_i2c_desc {
127 bool has_core_clk;
128 char *icc_ddr;
129 bool no_dma_support;
130 unsigned int tx_fifo_depth;
131 };
132
133 struct geni_i2c_err_log {
134 int err;
135 const char *msg;
136 };
137
138 static const struct geni_i2c_err_log gi2c_log[] = {
139 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
140 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
141 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
142 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
143 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
144 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
145 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
146 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
147 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
148 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
149 };
150
151 struct geni_i2c_clk_fld {
152 u32 clk_freq_out;
153 u8 clk_div;
154 u8 t_high_cnt;
155 u8 t_low_cnt;
156 u8 t_cycle_cnt;
157 };
158
159 /*
160 * Hardware uses the underlying formula to calculate time periods of
161 * SCL clock cycle. Firmware uses some additional cycles excluded from the
162 * below formula and it is confirmed that the time periods are within
163 * specification limits.
164 *
165 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
166 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
167 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
168 * clk_freq_out = t / t_cycle
169 * source_clock = 19.2 MHz
170 */
171 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
172 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 },
173 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 },
174 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 },
175 {}
176 };
177
178 /* source_clock = 32 MHz */
179 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
180 { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 },
181 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
182 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
183 {}
184 };
185
geni_i2c_clk_map_idx(struct geni_i2c_dev * gi2c)186 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
187 {
188 const struct geni_i2c_clk_fld *itr;
189
190 if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
191 itr = geni_i2c_clk_map_32mhz;
192 else
193 itr = geni_i2c_clk_map_19p2mhz;
194
195 while (itr->clk_freq_out != 0) {
196 if (itr->clk_freq_out == gi2c->clk_freq_out) {
197 gi2c->clk_fld = itr;
198 return 0;
199 }
200 itr++;
201 }
202 return -EINVAL;
203 }
204
qcom_geni_i2c_conf(struct geni_i2c_dev * gi2c)205 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
206 {
207 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
208 u32 val;
209
210 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
211
212 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
213 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
214
215 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
216 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
217 val |= itr->t_cycle_cnt;
218 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
219 }
220
geni_i2c_err_misc(struct geni_i2c_dev * gi2c)221 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
222 {
223 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
224 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
225 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
226 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
227 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
228 u32 rx_st, tx_st;
229
230 if (dma) {
231 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
232 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
233 } else {
234 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
235 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
236 }
237 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
238 dma, tx_st, rx_st, m_stat);
239 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
240 m_cmd, geni_s, geni_ios);
241 }
242
geni_i2c_err(struct geni_i2c_dev * gi2c,int err)243 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
244 {
245 if (!gi2c->err)
246 gi2c->err = gi2c_log[err].err;
247 if (gi2c->cur)
248 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
249 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
250
251 switch (err) {
252 case GENI_ABORT_DONE:
253 gi2c->abort_done = true;
254 break;
255 case NACK:
256 case GENI_TIMEOUT:
257 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
258 break;
259 default:
260 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
261 geni_i2c_err_misc(gi2c);
262 break;
263 }
264 }
265
geni_i2c_irq(int irq,void * dev)266 static irqreturn_t geni_i2c_irq(int irq, void *dev)
267 {
268 struct geni_i2c_dev *gi2c = dev;
269 void __iomem *base = gi2c->se.base;
270 int j, p;
271 u32 m_stat;
272 u32 rx_st;
273 u32 dm_tx_st;
274 u32 dm_rx_st;
275 u32 dma;
276 u32 val;
277 struct i2c_msg *cur;
278
279 spin_lock(&gi2c->lock);
280 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
281 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
282 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
283 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
284 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
285 cur = gi2c->cur;
286
287 if (!cur ||
288 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
289 dm_rx_st & (DM_I2C_CB_ERR)) {
290 if (m_stat & M_GP_IRQ_1_EN)
291 geni_i2c_err(gi2c, NACK);
292 if (m_stat & M_GP_IRQ_3_EN)
293 geni_i2c_err(gi2c, BUS_PROTO);
294 if (m_stat & M_GP_IRQ_4_EN)
295 geni_i2c_err(gi2c, ARB_LOST);
296 if (m_stat & M_CMD_OVERRUN_EN)
297 geni_i2c_err(gi2c, GENI_OVERRUN);
298 if (m_stat & M_ILLEGAL_CMD_EN)
299 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
300 if (m_stat & M_CMD_ABORT_EN)
301 geni_i2c_err(gi2c, GENI_ABORT_DONE);
302 if (m_stat & M_GP_IRQ_0_EN)
303 geni_i2c_err(gi2c, GP_IRQ0);
304
305 /* Disable the TX Watermark interrupt to stop TX */
306 if (!dma)
307 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
308 } else if (dma) {
309 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
310 dm_tx_st, dm_rx_st);
311 } else if (cur->flags & I2C_M_RD &&
312 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
313 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
314
315 for (j = 0; j < rxcnt; j++) {
316 p = 0;
317 val = readl_relaxed(base + SE_GENI_RX_FIFOn);
318 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
319 cur->buf[gi2c->cur_rd++] = val & 0xff;
320 val >>= 8;
321 p++;
322 }
323 if (gi2c->cur_rd == cur->len)
324 break;
325 }
326 } else if (!(cur->flags & I2C_M_RD) &&
327 m_stat & M_TX_FIFO_WATERMARK_EN) {
328 for (j = 0; j < gi2c->tx_wm; j++) {
329 u32 temp;
330
331 val = 0;
332 p = 0;
333 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
334 temp = cur->buf[gi2c->cur_wr++];
335 val |= temp << (p * 8);
336 p++;
337 }
338 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
339 /* TX Complete, Disable the TX Watermark interrupt */
340 if (gi2c->cur_wr == cur->len) {
341 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
342 break;
343 }
344 }
345 }
346
347 if (m_stat)
348 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
349
350 if (dma && dm_tx_st)
351 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
352 if (dma && dm_rx_st)
353 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
354
355 /* if this is err with done-bit not set, handle that through timeout. */
356 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
357 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
358 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
359 complete(&gi2c->done);
360
361 spin_unlock(&gi2c->lock);
362
363 return IRQ_HANDLED;
364 }
365
geni_i2c_abort_xfer(struct geni_i2c_dev * gi2c)366 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
367 {
368 unsigned long time_left = ABORT_TIMEOUT;
369 unsigned long flags;
370
371 spin_lock_irqsave(&gi2c->lock, flags);
372 geni_i2c_err(gi2c, GENI_TIMEOUT);
373 gi2c->cur = NULL;
374 gi2c->abort_done = false;
375 geni_se_abort_m_cmd(&gi2c->se);
376 spin_unlock_irqrestore(&gi2c->lock, flags);
377
378 do {
379 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
380 } while (!gi2c->abort_done && time_left);
381
382 if (!time_left)
383 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
384 }
385
geni_i2c_rx_fsm_rst(struct geni_i2c_dev * gi2c)386 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
387 {
388 u32 val;
389 unsigned long time_left = RST_TIMEOUT;
390
391 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
392 do {
393 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
394 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
395 } while (!(val & RX_RESET_DONE) && time_left);
396
397 if (!(val & RX_RESET_DONE))
398 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
399 }
400
geni_i2c_tx_fsm_rst(struct geni_i2c_dev * gi2c)401 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
402 {
403 u32 val;
404 unsigned long time_left = RST_TIMEOUT;
405
406 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
407 do {
408 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
409 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
410 } while (!(val & TX_RESET_DONE) && time_left);
411
412 if (!(val & TX_RESET_DONE))
413 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
414 }
415
geni_i2c_rx_msg_cleanup(struct geni_i2c_dev * gi2c,struct i2c_msg * cur)416 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
417 struct i2c_msg *cur)
418 {
419 gi2c->cur_rd = 0;
420 if (gi2c->dma_buf) {
421 if (gi2c->err)
422 geni_i2c_rx_fsm_rst(gi2c);
423 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
424 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
425 }
426 }
427
geni_i2c_tx_msg_cleanup(struct geni_i2c_dev * gi2c,struct i2c_msg * cur)428 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
429 struct i2c_msg *cur)
430 {
431 gi2c->cur_wr = 0;
432 if (gi2c->dma_buf) {
433 if (gi2c->err)
434 geni_i2c_tx_fsm_rst(gi2c);
435 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
436 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
437 }
438 }
439
geni_i2c_rx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)440 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
441 u32 m_param)
442 {
443 dma_addr_t rx_dma = 0;
444 unsigned long time_left;
445 void *dma_buf;
446 struct geni_se *se = &gi2c->se;
447 size_t len = msg->len;
448 struct i2c_msg *cur;
449
450 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
451 if (dma_buf)
452 geni_se_select_mode(se, GENI_SE_DMA);
453 else
454 geni_se_select_mode(se, GENI_SE_FIFO);
455
456 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
457 geni_se_setup_m_cmd(se, I2C_READ, m_param);
458
459 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
460 geni_se_select_mode(se, GENI_SE_FIFO);
461 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
462 dma_buf = NULL;
463 } else {
464 gi2c->xfer_len = len;
465 gi2c->dma_addr = rx_dma;
466 gi2c->dma_buf = dma_buf;
467 }
468
469 cur = gi2c->cur;
470 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
471 if (!time_left)
472 geni_i2c_abort_xfer(gi2c);
473
474 geni_i2c_rx_msg_cleanup(gi2c, cur);
475
476 return gi2c->err;
477 }
478
geni_i2c_tx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)479 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
480 u32 m_param)
481 {
482 dma_addr_t tx_dma = 0;
483 unsigned long time_left;
484 void *dma_buf;
485 struct geni_se *se = &gi2c->se;
486 size_t len = msg->len;
487 struct i2c_msg *cur;
488
489 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
490 if (dma_buf)
491 geni_se_select_mode(se, GENI_SE_DMA);
492 else
493 geni_se_select_mode(se, GENI_SE_FIFO);
494
495 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
496 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
497
498 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
499 geni_se_select_mode(se, GENI_SE_FIFO);
500 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
501 dma_buf = NULL;
502 } else {
503 gi2c->xfer_len = len;
504 gi2c->dma_addr = tx_dma;
505 gi2c->dma_buf = dma_buf;
506 }
507
508 if (!dma_buf) /* Get FIFO IRQ */
509 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
510
511 cur = gi2c->cur;
512 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
513 if (!time_left)
514 geni_i2c_abort_xfer(gi2c);
515
516 geni_i2c_tx_msg_cleanup(gi2c, cur);
517
518 return gi2c->err;
519 }
520
i2c_gpi_cb_result(void * cb,const struct dmaengine_result * result)521 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result)
522 {
523 struct geni_i2c_dev *gi2c = cb;
524 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer;
525
526 if (result->result != DMA_TRANS_NOERROR) {
527 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
528 gi2c->err = -EIO;
529 } else if (result->residue) {
530 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
531 }
532
533 if (gi2c->is_tx_multi_desc_xfer) {
534 tx_multi_xfer = &gi2c->i2c_multi_desc_config;
535 tx_multi_xfer->irq_cnt++;
536 }
537
538 complete(&gi2c->done);
539 }
540
geni_i2c_gpi_unmap(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,void * tx_buf,dma_addr_t tx_addr,void * rx_buf,dma_addr_t rx_addr)541 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
542 void *tx_buf, dma_addr_t tx_addr,
543 void *rx_buf, dma_addr_t rx_addr)
544 {
545 if (tx_buf) {
546 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
547 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err);
548 }
549
550 if (rx_buf) {
551 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
552 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err);
553 }
554 }
555
556 /**
557 * geni_i2c_gpi_multi_desc_unmap() - Unmaps DMA buffers post multi message TX transfers
558 * @gi2c: I2C dev handle
559 * @msgs: Array of I2C messages
560 * @peripheral: Pointer to gpi_i2c_config
561 */
geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],struct gpi_i2c_config * peripheral)562 static void geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
563 struct gpi_i2c_config *peripheral)
564 {
565 u32 msg_xfer_cnt, wr_idx = 0;
566 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer = &gi2c->i2c_multi_desc_config;
567
568 msg_xfer_cnt = gi2c->err ? tx_multi_xfer->msg_idx_cnt : tx_multi_xfer->irq_cnt;
569
570 /* Unmap the processed DMA buffers based on the received interrupt count */
571 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) {
572 wr_idx = tx_multi_xfer->unmap_msg_cnt;
573 geni_i2c_gpi_unmap(gi2c, &msgs[wr_idx],
574 tx_multi_xfer->dma_buf[wr_idx],
575 tx_multi_xfer->dma_addr[wr_idx],
576 NULL, 0);
577
578 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs - 1) {
579 kfree(tx_multi_xfer->dma_buf);
580 kfree(tx_multi_xfer->dma_addr);
581 break;
582 }
583 }
584 }
585
586 /**
587 * geni_i2c_gpi_multi_xfer_timeout_handler() - Handles multi message transfer timeout
588 * @dev: Pointer to the corresponding dev node
589 * @multi_xfer: Pointer to the geni_i2c_gpi_multi_desc_xfer
590 * @transfer_timeout_msecs: Timeout value in milliseconds
591 * @transfer_comp: Completion object of the transfer
592 *
593 * This function waits for the completion of each processed transfer messages
594 * based on the interrupts generated upon transfer completion.
595 *
596 * Return: On success returns 0, -ETIMEDOUT on timeout.
597 */
geni_i2c_gpi_multi_xfer_timeout_handler(struct device * dev,struct geni_i2c_gpi_multi_desc_xfer * multi_xfer,u32 transfer_timeout_msecs,struct completion * transfer_comp)598 static int geni_i2c_gpi_multi_xfer_timeout_handler(struct device *dev,
599 struct geni_i2c_gpi_multi_desc_xfer *multi_xfer,
600 u32 transfer_timeout_msecs,
601 struct completion *transfer_comp)
602 {
603 int i;
604 u32 time_left;
605
606 for (i = 0; i < multi_xfer->msg_idx_cnt - 1; i++) {
607 reinit_completion(transfer_comp);
608
609 if (multi_xfer->msg_idx_cnt != multi_xfer->irq_cnt) {
610 time_left = wait_for_completion_timeout(transfer_comp,
611 transfer_timeout_msecs);
612 if (!time_left) {
613 dev_err(dev, "%s: Transfer timeout\n", __func__);
614 return -ETIMEDOUT;
615 }
616 }
617 }
618 return 0;
619 }
620
geni_i2c_gpi(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],struct dma_slave_config * config,dma_addr_t * dma_addr_p,void ** buf,unsigned int op,struct dma_chan * dma_chan)621 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
622 struct dma_slave_config *config, dma_addr_t *dma_addr_p,
623 void **buf, unsigned int op, struct dma_chan *dma_chan)
624 {
625 struct gpi_i2c_config *peripheral;
626 unsigned int flags;
627 void *dma_buf;
628 dma_addr_t addr;
629 enum dma_data_direction map_dirn;
630 enum dma_transfer_direction dma_dirn;
631 struct dma_async_tx_descriptor *desc;
632 int ret;
633 struct geni_i2c_gpi_multi_desc_xfer *gi2c_gpi_xfer;
634 dma_cookie_t cookie;
635 u32 msg_idx;
636
637 peripheral = config->peripheral_config;
638 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config;
639 msg_idx = gi2c_gpi_xfer->msg_idx_cnt;
640
641 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1);
642 if (!dma_buf) {
643 ret = -ENOMEM;
644 goto out;
645 }
646
647 if (op == I2C_WRITE)
648 map_dirn = DMA_TO_DEVICE;
649 else
650 map_dirn = DMA_FROM_DEVICE;
651
652 addr = dma_map_single(gi2c->se.dev->parent, dma_buf,
653 msgs[msg_idx].len, map_dirn);
654 if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
655 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false);
656 ret = -ENOMEM;
657 goto out;
658 }
659
660 if (gi2c->is_tx_multi_desc_xfer) {
661 flags = DMA_CTRL_ACK;
662
663 /* BEI bit to be cleared for last TRE */
664 if (msg_idx == gi2c->num_msgs - 1)
665 flags |= DMA_PREP_INTERRUPT;
666 } else {
667 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
668 }
669
670 /* set the length as message for rx txn */
671 peripheral->rx_len = msgs[msg_idx].len;
672 peripheral->op = op;
673
674 ret = dmaengine_slave_config(dma_chan, config);
675 if (ret) {
676 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
677 goto err_config;
678 }
679
680 peripheral->set_config = 0;
681 peripheral->multi_msg = true;
682
683 if (op == I2C_WRITE)
684 dma_dirn = DMA_MEM_TO_DEV;
685 else
686 dma_dirn = DMA_DEV_TO_MEM;
687
688 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len,
689 dma_dirn, flags);
690 if (!desc && !(flags & DMA_PREP_INTERRUPT)) {
691 /* Retry with interrupt if not enough TREs */
692 flags |= DMA_PREP_INTERRUPT;
693 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len,
694 dma_dirn, flags);
695 }
696
697 if (!desc) {
698 dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
699 ret = -EIO;
700 goto err_config;
701 }
702
703 desc->callback_result = i2c_gpi_cb_result;
704 desc->callback_param = gi2c;
705
706 if (!((msgs[msg_idx].flags & I2C_M_RD) && op == I2C_WRITE))
707 gi2c_gpi_xfer->msg_idx_cnt++;
708
709 cookie = dmaengine_submit(desc);
710 if (dma_submit_error(cookie)) {
711 dev_err(gi2c->se.dev,
712 "%s: dmaengine_submit failed (%d)\n", __func__, cookie);
713 ret = -EINVAL;
714 goto err_config;
715 }
716
717 if (gi2c->is_tx_multi_desc_xfer) {
718 gi2c_gpi_xfer->dma_buf[msg_idx] = dma_buf;
719 gi2c_gpi_xfer->dma_addr[msg_idx] = addr;
720
721 dma_async_issue_pending(gi2c->tx_c);
722
723 if ((msg_idx == (gi2c->num_msgs - 1)) || flags & DMA_PREP_INTERRUPT) {
724 ret = geni_i2c_gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer,
725 XFER_TIMEOUT, &gi2c->done);
726 if (ret) {
727 dev_err(gi2c->se.dev,
728 "I2C multi write msg transfer timeout: %d\n",
729 ret);
730 gi2c->err = ret;
731 return ret;
732 }
733 }
734 } else {
735 /* Non multi descriptor message transfer */
736 *buf = dma_buf;
737 *dma_addr_p = addr;
738 }
739 return 0;
740
741 err_config:
742 dma_unmap_single(gi2c->se.dev->parent, addr,
743 msgs[msg_idx].len, map_dirn);
744 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false);
745
746 out:
747 gi2c->err = ret;
748 return ret;
749 }
750
geni_i2c_gpi_xfer(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],int num)751 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num)
752 {
753 struct dma_slave_config config = {};
754 struct gpi_i2c_config peripheral = {};
755 int i, ret = 0;
756 unsigned long time_left;
757 dma_addr_t tx_addr, rx_addr;
758 void *tx_buf = NULL, *rx_buf = NULL;
759 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer;
760 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
761
762 config.peripheral_config = &peripheral;
763 config.peripheral_size = sizeof(peripheral);
764
765 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX;
766 peripheral.cycle_count = itr->t_cycle_cnt;
767 peripheral.high_count = itr->t_high_cnt;
768 peripheral.low_count = itr->t_low_cnt;
769 peripheral.clk_div = itr->clk_div;
770 peripheral.set_config = 1;
771 peripheral.multi_msg = false;
772
773 gi2c->num_msgs = num;
774 gi2c->is_tx_multi_desc_xfer = false;
775
776 tx_multi_xfer = &gi2c->i2c_multi_desc_config;
777 memset(tx_multi_xfer, 0, sizeof(struct geni_i2c_gpi_multi_desc_xfer));
778
779 /*
780 * If number of write messages are two and higher then
781 * configure hardware for multi descriptor transfers with BEI.
782 */
783 if (num >= QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC) {
784 gi2c->is_tx_multi_desc_xfer = true;
785 for (i = 0; i < num; i++) {
786 if (msgs[i].flags & I2C_M_RD) {
787 /*
788 * Multi descriptor transfer with BEI
789 * support is enabled for write transfers.
790 * TODO: Add BEI optimization support for
791 * read transfers later.
792 */
793 gi2c->is_tx_multi_desc_xfer = false;
794 break;
795 }
796 }
797 }
798
799 if (gi2c->is_tx_multi_desc_xfer) {
800 tx_multi_xfer->dma_buf = kcalloc(num, sizeof(void *), GFP_KERNEL);
801 tx_multi_xfer->dma_addr = kcalloc(num, sizeof(dma_addr_t), GFP_KERNEL);
802 if (!tx_multi_xfer->dma_buf || !tx_multi_xfer->dma_addr) {
803 ret = -ENOMEM;
804 goto err;
805 }
806 }
807
808 for (i = 0; i < num; i++) {
809 gi2c->cur = &msgs[i];
810 gi2c->err = 0;
811 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
812
813 peripheral.stretch = 0;
814 if (i < num - 1)
815 peripheral.stretch = 1;
816
817 peripheral.addr = msgs[i].addr;
818 if (i > 0 && (!(msgs[i].flags & I2C_M_RD)))
819 peripheral.multi_msg = false;
820
821 ret = geni_i2c_gpi(gi2c, msgs, &config,
822 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
823 if (ret)
824 goto err;
825
826 if (msgs[i].flags & I2C_M_RD) {
827 ret = geni_i2c_gpi(gi2c, msgs, &config,
828 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
829 if (ret)
830 goto err;
831
832 dma_async_issue_pending(gi2c->rx_c);
833 }
834
835 if (!gi2c->is_tx_multi_desc_xfer) {
836 dma_async_issue_pending(gi2c->tx_c);
837 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
838 if (!time_left) {
839 dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__);
840 gi2c->err = -ETIMEDOUT;
841 }
842 }
843
844 if (gi2c->err) {
845 ret = gi2c->err;
846 goto err;
847 }
848
849 if (!gi2c->is_tx_multi_desc_xfer)
850 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
851 else if (tx_multi_xfer->unmap_msg_cnt != tx_multi_xfer->irq_cnt)
852 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
853 }
854
855 return num;
856
857 err:
858 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
859 dmaengine_terminate_sync(gi2c->rx_c);
860 dmaengine_terminate_sync(gi2c->tx_c);
861 if (gi2c->is_tx_multi_desc_xfer)
862 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
863 else
864 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
865
866 return ret;
867 }
868
geni_i2c_fifo_xfer(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],int num)869 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c,
870 struct i2c_msg msgs[], int num)
871 {
872 int i, ret = 0;
873
874 for (i = 0; i < num; i++) {
875 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
876
877 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
878
879 gi2c->cur = &msgs[i];
880 if (msgs[i].flags & I2C_M_RD)
881 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
882 else
883 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
884
885 if (ret)
886 return ret;
887 }
888
889 return num;
890 }
891
geni_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)892 static int geni_i2c_xfer(struct i2c_adapter *adap,
893 struct i2c_msg msgs[],
894 int num)
895 {
896 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
897 int ret;
898
899 gi2c->err = 0;
900 reinit_completion(&gi2c->done);
901 ret = pm_runtime_get_sync(gi2c->se.dev);
902 if (ret < 0) {
903 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
904 pm_runtime_put_noidle(gi2c->se.dev);
905 /* Set device in suspended since resume failed */
906 pm_runtime_set_suspended(gi2c->se.dev);
907 return ret;
908 }
909
910 qcom_geni_i2c_conf(gi2c);
911
912 if (gi2c->gpi_mode)
913 ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
914 else
915 ret = geni_i2c_fifo_xfer(gi2c, msgs, num);
916
917 pm_runtime_put_autosuspend(gi2c->se.dev);
918 gi2c->cur = NULL;
919 gi2c->err = 0;
920 return ret;
921 }
922
geni_i2c_func(struct i2c_adapter * adap)923 static u32 geni_i2c_func(struct i2c_adapter *adap)
924 {
925 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
926 }
927
928 static const struct i2c_algorithm geni_i2c_algo = {
929 .xfer = geni_i2c_xfer,
930 .functionality = geni_i2c_func,
931 };
932
933 #ifdef CONFIG_ACPI
934 static const struct acpi_device_id geni_i2c_acpi_match[] = {
935 { "QCOM0220"},
936 { "QCOM0411" },
937 { }
938 };
939 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
940 #endif
941
release_gpi_dma(struct geni_i2c_dev * gi2c)942 static void release_gpi_dma(struct geni_i2c_dev *gi2c)
943 {
944 if (gi2c->rx_c)
945 dma_release_channel(gi2c->rx_c);
946
947 if (gi2c->tx_c)
948 dma_release_channel(gi2c->tx_c);
949 }
950
setup_gpi_dma(struct geni_i2c_dev * gi2c)951 static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
952 {
953 int ret;
954
955 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
956 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
957 if (IS_ERR(gi2c->tx_c)) {
958 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
959 "Failed to get tx DMA ch\n");
960 goto err_tx;
961 }
962
963 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
964 if (IS_ERR(gi2c->rx_c)) {
965 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
966 "Failed to get rx DMA ch\n");
967 goto err_rx;
968 }
969
970 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
971 return 0;
972
973 err_rx:
974 dma_release_channel(gi2c->tx_c);
975 err_tx:
976 return ret;
977 }
978
geni_i2c_probe(struct platform_device * pdev)979 static int geni_i2c_probe(struct platform_device *pdev)
980 {
981 struct geni_i2c_dev *gi2c;
982 u32 proto, tx_depth, fifo_disable;
983 int ret;
984 struct device *dev = &pdev->dev;
985 const struct geni_i2c_desc *desc = NULL;
986
987 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
988 if (!gi2c)
989 return -ENOMEM;
990
991 gi2c->se.dev = dev;
992 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
993 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0);
994 if (IS_ERR(gi2c->se.base))
995 return PTR_ERR(gi2c->se.base);
996
997 desc = device_get_match_data(&pdev->dev);
998
999 if (desc && desc->has_core_clk) {
1000 gi2c->core_clk = devm_clk_get(dev, "core");
1001 if (IS_ERR(gi2c->core_clk))
1002 return PTR_ERR(gi2c->core_clk);
1003 }
1004
1005 gi2c->se.clk = devm_clk_get(dev, "se");
1006 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
1007 return PTR_ERR(gi2c->se.clk);
1008
1009 ret = device_property_read_u32(dev, "clock-frequency",
1010 &gi2c->clk_freq_out);
1011 if (ret) {
1012 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
1013 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
1014 }
1015
1016 if (has_acpi_companion(dev))
1017 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
1018
1019 gi2c->irq = platform_get_irq(pdev, 0);
1020 if (gi2c->irq < 0)
1021 return gi2c->irq;
1022
1023 ret = geni_i2c_clk_map_idx(gi2c);
1024 if (ret)
1025 return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n",
1026 gi2c->clk_freq_out);
1027
1028 gi2c->adap.algo = &geni_i2c_algo;
1029 init_completion(&gi2c->done);
1030 spin_lock_init(&gi2c->lock);
1031 platform_set_drvdata(pdev, gi2c);
1032
1033 /* Keep interrupts disabled initially to allow for low-power modes */
1034 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
1035 dev_name(dev), gi2c);
1036 if (ret)
1037 return dev_err_probe(dev, ret,
1038 "Request_irq failed: %d\n", gi2c->irq);
1039
1040 i2c_set_adapdata(&gi2c->adap, gi2c);
1041 gi2c->adap.dev.parent = dev;
1042 gi2c->adap.dev.of_node = dev->of_node;
1043 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
1044
1045 ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory");
1046 if (ret)
1047 return ret;
1048 /*
1049 * Set the bus quota for core and cpu to a reasonable value for
1050 * register access.
1051 * Set quota for DDR based on bus speed.
1052 */
1053 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1054 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1055 if (!desc || desc->icc_ddr)
1056 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
1057
1058 ret = geni_icc_set_bw(&gi2c->se);
1059 if (ret)
1060 return ret;
1061
1062 ret = clk_prepare_enable(gi2c->core_clk);
1063 if (ret)
1064 return ret;
1065
1066 ret = geni_se_resources_on(&gi2c->se);
1067 if (ret) {
1068 dev_err_probe(dev, ret, "Error turning on resources\n");
1069 goto err_clk;
1070 }
1071 proto = geni_se_read_proto(&gi2c->se);
1072 if (proto == GENI_SE_INVALID_PROTO) {
1073 ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C);
1074 if (ret) {
1075 dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret);
1076 goto err_resources;
1077 }
1078 } else if (proto != GENI_SE_I2C) {
1079 ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto);
1080 goto err_resources;
1081 }
1082
1083 if (desc && desc->no_dma_support)
1084 fifo_disable = false;
1085 else
1086 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
1087
1088 if (fifo_disable) {
1089 /* FIFO is disabled, so we can only use GPI DMA */
1090 gi2c->gpi_mode = true;
1091 ret = setup_gpi_dma(gi2c);
1092 if (ret)
1093 goto err_resources;
1094
1095 dev_dbg(dev, "Using GPI DMA mode for I2C\n");
1096 } else {
1097 gi2c->gpi_mode = false;
1098 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
1099
1100 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
1101 if (!tx_depth && desc)
1102 tx_depth = desc->tx_fifo_depth;
1103
1104 if (!tx_depth) {
1105 ret = dev_err_probe(dev, -EINVAL,
1106 "Invalid TX FIFO depth\n");
1107 goto err_resources;
1108 }
1109
1110 gi2c->tx_wm = tx_depth - 1;
1111 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
1112 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
1113 PACKING_BYTES_PW, true, true, true);
1114
1115 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
1116 }
1117
1118 clk_disable_unprepare(gi2c->core_clk);
1119 ret = geni_se_resources_off(&gi2c->se);
1120 if (ret) {
1121 dev_err_probe(dev, ret, "Error turning off resources\n");
1122 goto err_dma;
1123 }
1124
1125 ret = geni_icc_disable(&gi2c->se);
1126 if (ret)
1127 goto err_dma;
1128
1129 gi2c->suspended = 1;
1130 pm_runtime_set_suspended(gi2c->se.dev);
1131 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
1132 pm_runtime_use_autosuspend(gi2c->se.dev);
1133 pm_runtime_enable(gi2c->se.dev);
1134
1135 ret = i2c_add_adapter(&gi2c->adap);
1136 if (ret) {
1137 dev_err_probe(dev, ret, "Error adding i2c adapter\n");
1138 pm_runtime_disable(gi2c->se.dev);
1139 goto err_dma;
1140 }
1141
1142 dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
1143
1144 return ret;
1145
1146 err_resources:
1147 geni_se_resources_off(&gi2c->se);
1148 err_clk:
1149 clk_disable_unprepare(gi2c->core_clk);
1150
1151 return ret;
1152
1153 err_dma:
1154 release_gpi_dma(gi2c);
1155
1156 return ret;
1157 }
1158
geni_i2c_remove(struct platform_device * pdev)1159 static void geni_i2c_remove(struct platform_device *pdev)
1160 {
1161 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
1162
1163 i2c_del_adapter(&gi2c->adap);
1164 release_gpi_dma(gi2c);
1165 pm_runtime_disable(gi2c->se.dev);
1166 }
1167
geni_i2c_shutdown(struct platform_device * pdev)1168 static void geni_i2c_shutdown(struct platform_device *pdev)
1169 {
1170 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
1171
1172 /* Make client i2c transfers start failing */
1173 i2c_mark_adapter_suspended(&gi2c->adap);
1174 }
1175
geni_i2c_runtime_suspend(struct device * dev)1176 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
1177 {
1178 int ret;
1179 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1180
1181 disable_irq(gi2c->irq);
1182 ret = geni_se_resources_off(&gi2c->se);
1183 if (ret) {
1184 enable_irq(gi2c->irq);
1185 return ret;
1186
1187 } else {
1188 gi2c->suspended = 1;
1189 }
1190
1191 clk_disable_unprepare(gi2c->core_clk);
1192
1193 return geni_icc_disable(&gi2c->se);
1194 }
1195
geni_i2c_runtime_resume(struct device * dev)1196 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
1197 {
1198 int ret;
1199 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1200
1201 ret = geni_icc_enable(&gi2c->se);
1202 if (ret)
1203 return ret;
1204
1205 ret = clk_prepare_enable(gi2c->core_clk);
1206 if (ret)
1207 goto out_icc_disable;
1208
1209 ret = geni_se_resources_on(&gi2c->se);
1210 if (ret)
1211 goto out_clk_disable;
1212
1213 enable_irq(gi2c->irq);
1214 gi2c->suspended = 0;
1215
1216 return 0;
1217
1218 out_clk_disable:
1219 clk_disable_unprepare(gi2c->core_clk);
1220 out_icc_disable:
1221 geni_icc_disable(&gi2c->se);
1222
1223 return ret;
1224 }
1225
geni_i2c_suspend_noirq(struct device * dev)1226 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
1227 {
1228 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1229
1230 i2c_mark_adapter_suspended(&gi2c->adap);
1231
1232 if (!gi2c->suspended) {
1233 geni_i2c_runtime_suspend(dev);
1234 pm_runtime_disable(dev);
1235 pm_runtime_set_suspended(dev);
1236 pm_runtime_enable(dev);
1237 }
1238 return 0;
1239 }
1240
geni_i2c_resume_noirq(struct device * dev)1241 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
1242 {
1243 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1244
1245 i2c_mark_adapter_resumed(&gi2c->adap);
1246 return 0;
1247 }
1248
1249 static const struct dev_pm_ops geni_i2c_pm_ops = {
1250 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
1251 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
1252 NULL)
1253 };
1254
1255 static const struct geni_i2c_desc i2c_master_hub = {
1256 .has_core_clk = true,
1257 .icc_ddr = NULL,
1258 .no_dma_support = true,
1259 .tx_fifo_depth = 16,
1260 };
1261
1262 static const struct of_device_id geni_i2c_dt_match[] = {
1263 { .compatible = "qcom,geni-i2c" },
1264 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
1265 {}
1266 };
1267 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
1268
1269 static struct platform_driver geni_i2c_driver = {
1270 .probe = geni_i2c_probe,
1271 .remove = geni_i2c_remove,
1272 .shutdown = geni_i2c_shutdown,
1273 .driver = {
1274 .name = "geni_i2c",
1275 .pm = &geni_i2c_pm_ops,
1276 .of_match_table = geni_i2c_dt_match,
1277 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
1278 },
1279 };
1280
1281 module_platform_driver(geni_i2c_driver);
1282
1283 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
1284 MODULE_LICENSE("GPL v2");
1285