1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Li Peng <peng.li@intel.com>
25 */
26
27 #include <linux/export.h>
28 #include <linux/mutex.h>
29 #include <linux/pci.h>
30 #include <linux/i2c.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33
34 #include <drm/drm_print.h>
35
36 #include "psb_drv.h"
37
38 #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
39 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
40
41 #define HDMI_HCR 0x1000
42 #define HCR_DETECT_HDP (1 << 6)
43 #define HCR_ENABLE_HDCP (1 << 5)
44 #define HCR_ENABLE_AUDIO (1 << 2)
45 #define HCR_ENABLE_PIXEL (1 << 1)
46 #define HCR_ENABLE_TMDS (1 << 0)
47 #define HDMI_HICR 0x1004
48 #define HDMI_INTR_I2C_ERROR (1 << 4)
49 #define HDMI_INTR_I2C_FULL (1 << 3)
50 #define HDMI_INTR_I2C_DONE (1 << 2)
51 #define HDMI_INTR_HPD (1 << 0)
52 #define HDMI_HSR 0x1008
53 #define HDMI_HISR 0x100C
54 #define HDMI_HI2CRDB0 0x1200
55 #define HDMI_HI2CHCR 0x1240
56 #define HI2C_HDCP_WRITE (0 << 2)
57 #define HI2C_HDCP_RI_READ (1 << 2)
58 #define HI2C_HDCP_READ (2 << 2)
59 #define HI2C_EDID_READ (3 << 2)
60 #define HI2C_READ_CONTINUE (1 << 1)
61 #define HI2C_ENABLE_TRANSACTION (1 << 0)
62
63 #define HDMI_ICRH 0x1100
64 #define HDMI_HI2CTDR0 0x1244
65 #define HDMI_HI2CTDR1 0x1248
66
67 #define I2C_STAT_INIT 0
68 #define I2C_READ_DONE 1
69 #define I2C_TRANSACTION_DONE 2
70
71 struct hdmi_i2c_dev {
72 struct i2c_adapter *adap;
73 struct mutex i2c_lock;
74 struct completion complete;
75 int status;
76 struct i2c_msg *msg;
77 int buf_offset;
78 };
79
hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev * hdmi_dev)80 static void hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev *hdmi_dev)
81 {
82 u32 temp;
83
84 temp = HDMI_READ(HDMI_HICR);
85 temp |= (HDMI_INTR_I2C_ERROR | HDMI_INTR_I2C_FULL | HDMI_INTR_I2C_DONE);
86 HDMI_WRITE(HDMI_HICR, temp);
87 HDMI_READ(HDMI_HICR);
88 }
89
hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev * hdmi_dev)90 static void hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev *hdmi_dev)
91 {
92 HDMI_WRITE(HDMI_HICR, 0x0);
93 HDMI_READ(HDMI_HICR);
94 }
95
xfer_read(struct i2c_adapter * adap,struct i2c_msg * pmsg)96 static int xfer_read(struct i2c_adapter *adap, struct i2c_msg *pmsg)
97 {
98 struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
99 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
100 u32 temp;
101 int ret;
102
103 i2c_dev->status = I2C_STAT_INIT;
104 i2c_dev->msg = pmsg;
105 i2c_dev->buf_offset = 0;
106 reinit_completion(&i2c_dev->complete);
107
108 /* Enable I2C transaction */
109 temp = ((pmsg->len) << 20) | HI2C_EDID_READ | HI2C_ENABLE_TRANSACTION;
110 HDMI_WRITE(HDMI_HI2CHCR, temp);
111 HDMI_READ(HDMI_HI2CHCR);
112
113 while (i2c_dev->status != I2C_TRANSACTION_DONE) {
114 ret = wait_for_completion_interruptible_timeout(&i2c_dev->complete,
115 10 * HZ);
116 if (ret < 0)
117 return ret;
118 if (!ret)
119 return -ETIMEDOUT;
120 }
121
122 return 0;
123 }
124
xfer_write(struct i2c_adapter * adap,struct i2c_msg * pmsg)125 static int xfer_write(struct i2c_adapter *adap, struct i2c_msg *pmsg)
126 {
127 /*
128 * XXX: i2c write seems isn't useful for EDID probe, don't do anything
129 */
130 return 0;
131 }
132
oaktrail_hdmi_i2c_access(struct i2c_adapter * adap,struct i2c_msg * pmsg,int num)133 static int oaktrail_hdmi_i2c_access(struct i2c_adapter *adap,
134 struct i2c_msg *pmsg,
135 int num)
136 {
137 struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
138 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
139 int i, ret = 0;
140
141 mutex_lock(&i2c_dev->i2c_lock);
142
143 /* Enable i2c unit */
144 HDMI_WRITE(HDMI_ICRH, 0x00008760);
145
146 /* Enable irq */
147 hdmi_i2c_irq_enable(hdmi_dev);
148 for (i = 0; i < num; i++) {
149 if (pmsg->len && pmsg->buf) {
150 if (pmsg->flags & I2C_M_RD)
151 ret = xfer_read(adap, pmsg);
152 else
153 ret = xfer_write(adap, pmsg);
154 if (ret)
155 break;
156 }
157 pmsg++; /* next message */
158 }
159
160 /* Disable irq */
161 hdmi_i2c_irq_disable(hdmi_dev);
162
163 mutex_unlock(&i2c_dev->i2c_lock);
164
165 if (ret)
166 return ret;
167
168 return i;
169 }
170
oaktrail_hdmi_i2c_func(struct i2c_adapter * adapter)171 static u32 oaktrail_hdmi_i2c_func(struct i2c_adapter *adapter)
172 {
173 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
174 }
175
176 static const struct i2c_algorithm oaktrail_hdmi_i2c_algorithm = {
177 .master_xfer = oaktrail_hdmi_i2c_access,
178 .functionality = oaktrail_hdmi_i2c_func,
179 };
180
181 static struct i2c_adapter oaktrail_hdmi_i2c_adapter = {
182 .name = "oaktrail_hdmi_i2c",
183 .nr = 3,
184 .owner = THIS_MODULE,
185 .algo = &oaktrail_hdmi_i2c_algorithm,
186 };
187
hdmi_i2c_read(struct oaktrail_hdmi_dev * hdmi_dev)188 static void hdmi_i2c_read(struct oaktrail_hdmi_dev *hdmi_dev)
189 {
190 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
191 struct i2c_msg *msg = i2c_dev->msg;
192 u8 *buf = msg->buf;
193 u32 temp;
194 int i, offset;
195
196 offset = i2c_dev->buf_offset;
197 for (i = 0; i < 0x10; i++) {
198 temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
199 memcpy(buf + (offset + i * 4), &temp, 4);
200 }
201 i2c_dev->buf_offset += (0x10 * 4);
202
203 /* clearing read buffer full intr */
204 temp = HDMI_READ(HDMI_HISR);
205 HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_FULL);
206 HDMI_READ(HDMI_HISR);
207
208 /* continue read transaction */
209 temp = HDMI_READ(HDMI_HI2CHCR);
210 HDMI_WRITE(HDMI_HI2CHCR, temp | HI2C_READ_CONTINUE);
211 HDMI_READ(HDMI_HI2CHCR);
212
213 i2c_dev->status = I2C_READ_DONE;
214 return;
215 }
216
hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev * hdmi_dev)217 static void hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev *hdmi_dev)
218 {
219 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
220 u32 temp;
221
222 /* clear transaction done intr */
223 temp = HDMI_READ(HDMI_HISR);
224 HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_DONE);
225 HDMI_READ(HDMI_HISR);
226
227
228 temp = HDMI_READ(HDMI_HI2CHCR);
229 HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION);
230 HDMI_READ(HDMI_HI2CHCR);
231
232 i2c_dev->status = I2C_TRANSACTION_DONE;
233 return;
234 }
235
oaktrail_hdmi_i2c_handler(int this_irq,void * dev)236 static irqreturn_t oaktrail_hdmi_i2c_handler(int this_irq, void *dev)
237 {
238 struct oaktrail_hdmi_dev *hdmi_dev = dev;
239 struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
240 u32 stat;
241
242 stat = HDMI_READ(HDMI_HISR);
243
244 if (stat & HDMI_INTR_HPD) {
245 HDMI_WRITE(HDMI_HISR, stat | HDMI_INTR_HPD);
246 HDMI_READ(HDMI_HISR);
247 }
248
249 if (stat & HDMI_INTR_I2C_FULL)
250 hdmi_i2c_read(hdmi_dev);
251
252 if (stat & HDMI_INTR_I2C_DONE)
253 hdmi_i2c_transaction_done(hdmi_dev);
254
255 complete(&i2c_dev->complete);
256
257 return IRQ_HANDLED;
258 }
259
260 /*
261 * choose alternate function 2 of GPIO pin 52, 53,
262 * which is used by HDMI I2C logic
263 */
oaktrail_hdmi_i2c_gpio_fix(void)264 static void oaktrail_hdmi_i2c_gpio_fix(void)
265 {
266 void __iomem *base;
267 unsigned int gpio_base = 0xff12c000;
268 int gpio_len = 0x1000;
269 u32 temp;
270
271 base = ioremap((resource_size_t)gpio_base, gpio_len);
272 if (base == NULL) {
273 DRM_ERROR("gpio ioremap fail\n");
274 return;
275 }
276
277 temp = readl(base + 0x44);
278 DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
279 writel((temp | 0x00000a00), (base + 0x44));
280 temp = readl(base + 0x44);
281 DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
282
283 iounmap(base);
284 }
285
oaktrail_hdmi_i2c_init(struct pci_dev * dev)286 int oaktrail_hdmi_i2c_init(struct pci_dev *dev)
287 {
288 struct oaktrail_hdmi_dev *hdmi_dev;
289 struct hdmi_i2c_dev *i2c_dev;
290 int ret;
291
292 hdmi_dev = pci_get_drvdata(dev);
293
294 i2c_dev = kzalloc_obj(struct hdmi_i2c_dev);
295 if (!i2c_dev)
296 return -ENOMEM;
297
298 i2c_dev->adap = &oaktrail_hdmi_i2c_adapter;
299 i2c_dev->status = I2C_STAT_INIT;
300 init_completion(&i2c_dev->complete);
301 mutex_init(&i2c_dev->i2c_lock);
302 i2c_set_adapdata(&oaktrail_hdmi_i2c_adapter, hdmi_dev);
303 hdmi_dev->i2c_dev = i2c_dev;
304
305 /* Enable HDMI I2C function on gpio */
306 oaktrail_hdmi_i2c_gpio_fix();
307
308 /* request irq */
309 ret = request_irq(dev->irq, oaktrail_hdmi_i2c_handler, IRQF_SHARED,
310 oaktrail_hdmi_i2c_adapter.name, hdmi_dev);
311 if (ret) {
312 DRM_ERROR("Failed to request IRQ for I2C controller\n");
313 goto free_dev;
314 }
315
316 /* Adapter registration */
317 ret = i2c_add_numbered_adapter(&oaktrail_hdmi_i2c_adapter);
318 if (ret) {
319 DRM_ERROR("Failed to add I2C adapter\n");
320 goto free_irq;
321 }
322
323 return 0;
324
325 free_irq:
326 free_irq(dev->irq, hdmi_dev);
327 free_dev:
328 kfree(i2c_dev);
329
330 return ret;
331 }
332
oaktrail_hdmi_i2c_exit(struct pci_dev * dev)333 void oaktrail_hdmi_i2c_exit(struct pci_dev *dev)
334 {
335 struct oaktrail_hdmi_dev *hdmi_dev;
336 struct hdmi_i2c_dev *i2c_dev;
337
338 hdmi_dev = pci_get_drvdata(dev);
339 i2c_del_adapter(&oaktrail_hdmi_i2c_adapter);
340
341 i2c_dev = hdmi_dev->i2c_dev;
342 kfree(i2c_dev);
343 free_irq(dev->irq, hdmi_dev);
344 }
345