1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 #include <linux/etherdevice.h> 9 #include "hnae3.h" 10 #include "hclge_comm_cmd.h" 11 12 struct hclge_dev; 13 14 #define HCLGE_CMDQ_RX_INVLD_B 0 15 #define HCLGE_CMDQ_RX_OUTVLD_B 1 16 17 struct hclge_misc_vector { 18 u8 __iomem *addr; 19 int vector_irq; 20 char name[HNAE3_INT_NAME_LEN]; 21 }; 22 23 #define hclge_cmd_setup_basic_desc(desc, opcode, is_read) \ 24 hclge_comm_cmd_setup_basic_desc(desc, opcode, is_read) 25 26 #define HCLGE_TQP_REG_OFFSET 0x80000 27 #define HCLGE_TQP_REG_SIZE 0x200 28 29 #define HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 128 30 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024 31 #define HCLGE_TQP_EXT_REG_OFFSET 0x100 32 33 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 34 #define HCLGE_RCB_INIT_FLAG_EN_B 0 35 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 36 struct hclge_config_rcb_init_cmd { 37 __le16 rcb_init_flag; 38 u8 rsv[22]; 39 }; 40 41 struct hclge_tqp_map_cmd { 42 __le16 tqp_id; /* Absolute tqp id for in this pf */ 43 u8 tqp_vf; /* VF id */ 44 #define HCLGE_TQP_MAP_TYPE_PF 0 45 #define HCLGE_TQP_MAP_TYPE_VF 1 46 #define HCLGE_TQP_MAP_TYPE_B 0 47 #define HCLGE_TQP_MAP_EN_B 1 48 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 49 __le16 tqp_vid; /* Virtual id in this pf/vf */ 50 u8 rsv[18]; 51 }; 52 53 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 54 55 enum hclge_int_type { 56 HCLGE_INT_TX, 57 HCLGE_INT_RX, 58 HCLGE_INT_EVENT, 59 }; 60 61 struct hclge_ctrl_vector_chain_cmd { 62 #define HCLGE_VECTOR_ID_L_S 0 63 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0) 64 u8 int_vector_id_l; 65 u8 int_cause_num; 66 #define HCLGE_INT_TYPE_S 0 67 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 68 #define HCLGE_TQP_ID_S 2 69 #define HCLGE_TQP_ID_M GENMASK(12, 2) 70 #define HCLGE_INT_GL_IDX_S 13 71 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 72 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 73 u8 vfid; 74 #define HCLGE_VECTOR_ID_H_S 8 75 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8) 76 u8 int_vector_id_h; 77 }; 78 79 #define HCLGE_MAX_TC_NUM 8 80 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 81 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 82 struct hclge_tx_buff_alloc_cmd { 83 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 84 u8 tx_buff_rsv[8]; 85 }; 86 87 struct hclge_rx_priv_buff_cmd { 88 __le16 buf_num[HCLGE_MAX_TC_NUM]; 89 __le16 shared_buf; 90 u8 rsv[6]; 91 }; 92 93 #define HCLGE_RX_PRIV_EN_B 15 94 #define HCLGE_TC_NUM_ONE_DESC 4 95 struct hclge_priv_wl { 96 __le16 high; 97 __le16 low; 98 }; 99 100 struct hclge_rx_priv_wl_buf { 101 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 102 }; 103 104 struct hclge_rx_com_thrd { 105 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 106 }; 107 108 struct hclge_rx_com_wl { 109 struct hclge_priv_wl com_wl; 110 }; 111 112 struct hclge_waterline { 113 u32 low; 114 u32 high; 115 }; 116 117 struct hclge_tc_thrd { 118 u32 low; 119 u32 high; 120 }; 121 122 struct hclge_priv_buf { 123 struct hclge_waterline wl; /* Waterline for low and high */ 124 u32 buf_size; /* TC private buffer size */ 125 u32 tx_buf_size; 126 u32 enable; /* Enable TC private buffer or not */ 127 }; 128 129 struct hclge_shared_buf { 130 struct hclge_waterline self; 131 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 132 u32 buf_size; 133 }; 134 135 struct hclge_pkt_buf_alloc { 136 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 137 struct hclge_shared_buf s_buf; 138 }; 139 140 #define HCLGE_RX_COM_WL_EN_B 15 141 struct hclge_rx_com_wl_buf_cmd { 142 __le16 high_wl; 143 __le16 low_wl; 144 u8 rsv[20]; 145 }; 146 147 #define HCLGE_RX_PKT_EN_B 15 148 struct hclge_rx_pkt_buf_cmd { 149 __le16 high_pkt; 150 __le16 low_pkt; 151 u8 rsv[20]; 152 }; 153 154 #define HCLGE_PF_STATE_DONE_B 0 155 #define HCLGE_PF_STATE_MAIN_B 1 156 #define HCLGE_PF_STATE_BOND_B 2 157 #define HCLGE_PF_STATE_MAC_N_B 6 158 #define HCLGE_PF_MAC_NUM_MASK 0x3 159 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 160 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 161 #define HCLGE_VF_RST_STATUS_CMD 4 162 163 struct hclge_func_status_cmd { 164 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; 165 u8 pf_state; 166 u8 mac_id; 167 u8 rsv1; 168 u8 pf_cnt_in_mac; 169 u8 pf_num; 170 u8 vf_num; 171 u8 rsv[2]; 172 }; 173 174 struct hclge_pf_res_cmd { 175 __le16 tqp_num; 176 __le16 buf_size; 177 __le16 msixcap_localid_ba_nic; 178 __le16 msixcap_localid_number_nic; 179 __le16 pf_intr_vector_number_roce; 180 __le16 pf_own_fun_number; 181 __le16 tx_buf_size; 182 __le16 dv_buf_size; 183 __le16 ext_tqp_num; 184 u8 rsv[6]; 185 }; 186 187 #define HCLGE_CFG_OFFSET_S 0 188 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 189 #define HCLGE_CFG_RD_LEN_S 24 190 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 191 #define HCLGE_CFG_RD_LEN_BYTES 16 192 #define HCLGE_CFG_RD_LEN_UNIT 4 193 194 #define HCLGE_CFG_TC_NUM_S 8 195 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 196 #define HCLGE_CFG_TQP_DESC_N_S 16 197 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 198 #define HCLGE_CFG_PHY_ADDR_S 0 199 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 200 #define HCLGE_CFG_MEDIA_TP_S 8 201 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 202 #define HCLGE_CFG_RX_BUF_LEN_S 16 203 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 204 #define HCLGE_CFG_MAC_ADDR_H_S 0 205 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 206 #define HCLGE_CFG_DEFAULT_SPEED_S 16 207 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 208 #define HCLGE_CFG_RSS_SIZE_S 24 209 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 210 #define HCLGE_CFG_SPEED_ABILITY_S 0 211 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 212 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10 213 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10) 214 #define HCLGE_CFG_VLAN_FLTR_CAP_S 8 215 #define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8) 216 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 217 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 218 #define HCLGE_CFG_PF_RSS_SIZE_S 0 219 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0) 220 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_S 4 221 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4) 222 223 #define HCLGE_CFG_CMD_CNT 4 224 225 struct hclge_cfg_param_cmd { 226 __le32 offset; 227 __le32 rsv; 228 __le32 param[HCLGE_CFG_CMD_CNT]; 229 }; 230 231 #define HCLGE_MAC_MODE 0x0 232 #define HCLGE_DESC_NUM 0x40 233 234 #define HCLGE_ALLOC_VALID_B 0 235 struct hclge_vf_num_cmd { 236 u8 alloc_valid; 237 u8 rsv[23]; 238 }; 239 240 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 241 242 #define HCLGE_RSS_CFG_TBL_SIZE_H 4 243 #define HCLGE_RSS_CFG_TBL_BW_L 8U 244 245 #define HCLGE_RSS_TC_OFFSET_S 0 246 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0) 247 #define HCLGE_RSS_TC_SIZE_MSB_B 11 248 #define HCLGE_RSS_TC_SIZE_S 12 249 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 250 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3 251 #define HCLGE_RSS_TC_VALID_B 15 252 253 #define HCLGE_LINK_STATUS_UP_B 0 254 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 255 struct hclge_link_status_cmd { 256 u8 status; 257 u8 rsv[23]; 258 }; 259 260 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */ 261 #define HCLGE_PROMISC_EN_UC 1 262 #define HCLGE_PROMISC_EN_MC 2 263 #define HCLGE_PROMISC_EN_BC 3 264 #define HCLGE_PROMISC_TX_EN 4 265 #define HCLGE_PROMISC_RX_EN 5 266 267 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */ 268 #define HCLGE_PROMISC_UC_RX_EN 2 269 #define HCLGE_PROMISC_MC_RX_EN 3 270 #define HCLGE_PROMISC_BC_RX_EN 4 271 #define HCLGE_PROMISC_UC_TX_EN 5 272 #define HCLGE_PROMISC_MC_TX_EN 6 273 #define HCLGE_PROMISC_BC_TX_EN 7 274 275 struct hclge_promisc_cfg_cmd { 276 u8 promisc; 277 u8 vf_id; 278 u8 extend_promisc; 279 u8 rsv0[21]; 280 }; 281 282 enum hclge_promisc_type { 283 HCLGE_UNICAST = 1, 284 HCLGE_MULTICAST = 2, 285 HCLGE_BROADCAST = 3, 286 }; 287 288 #define HCLGE_MAC_TX_EN_B 6 289 #define HCLGE_MAC_RX_EN_B 7 290 #define HCLGE_MAC_PAD_TX_B 11 291 #define HCLGE_MAC_PAD_RX_B 12 292 #define HCLGE_MAC_1588_TX_B 13 293 #define HCLGE_MAC_1588_RX_B 14 294 #define HCLGE_MAC_APP_LP_B 15 295 #define HCLGE_MAC_LINE_LP_B 16 296 #define HCLGE_MAC_FCS_TX_B 17 297 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 298 #define HCLGE_MAC_RX_FCS_STRIP_B 19 299 #define HCLGE_MAC_RX_FCS_B 20 300 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 301 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 302 303 struct hclge_config_mac_mode_cmd { 304 __le32 txrx_pad_fcs_loop_en; 305 u8 rsv[20]; 306 }; 307 308 struct hclge_pf_rst_sync_cmd { 309 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 310 u8 all_vf_ready; 311 u8 rsv[23]; 312 }; 313 314 #define HCLGE_CFG_SPEED_S 0 315 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 316 317 #define HCLGE_CFG_DUPLEX_B 7 318 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 319 320 struct hclge_config_mac_speed_dup_cmd { 321 u8 speed_dup; 322 323 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 324 u8 mac_change_fec_en; 325 u8 rsv[4]; 326 u8 lane_num; 327 u8 rsv1[17]; 328 }; 329 330 #define HCLGE_TQP_ENABLE_B 0 331 332 #define HCLGE_MAC_CFG_AN_EN_B 0 333 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 334 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 335 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 336 #define HCLGE_MAC_CFG_AN_RST_B 4 337 338 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 339 340 struct hclge_config_auto_neg_cmd { 341 __le32 cfg_an_cmd_flag; 342 u8 rsv[20]; 343 }; 344 345 struct hclge_sfp_info_cmd { 346 __le32 speed; 347 u8 query_type; /* 0: sfp speed, 1: active speed */ 348 u8 active_fec; 349 u8 autoneg; /* autoneg state */ 350 u8 autoneg_ability; /* whether support autoneg */ 351 __le32 speed_ability; /* speed ability for current media */ 352 __le32 module_type; 353 u8 fec_ability; 354 u8 lane_num; 355 u8 rsv[6]; 356 }; 357 358 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 359 #define HCLGE_MAC_CFG_FEC_MODE_S 1 360 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 361 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 362 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 363 364 #define HCLGE_MAC_FEC_OFF 0 365 #define HCLGE_MAC_FEC_BASER 1 366 #define HCLGE_MAC_FEC_RS 2 367 #define HCLGE_MAC_FEC_LLRS 3 368 struct hclge_config_fec_cmd { 369 u8 fec_mode; 370 u8 default_config; 371 u8 rsv[22]; 372 }; 373 374 #define HCLGE_FEC_STATS_CMD_NUM 4 375 376 struct hclge_query_fec_stats_cmd { 377 /* fec rs mode total stats */ 378 __le32 rs_fec_corr_blocks; 379 __le32 rs_fec_uncorr_blocks; 380 __le32 rs_fec_error_blocks; 381 /* fec base-r mode per lanes stats */ 382 u8 base_r_lane_num; 383 u8 rsv[3]; 384 __le32 base_r_fec_corr_blocks; 385 __le32 base_r_fec_uncorr_blocks; 386 }; 387 388 #define HCLGE_MAC_UPLINK_PORT 0x100 389 390 struct hclge_config_max_frm_size_cmd { 391 __le16 max_frm_size; 392 u8 min_frm_size; 393 u8 rsv[21]; 394 }; 395 396 enum hclge_mac_vlan_tbl_opcode { 397 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 398 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 399 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 400 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 401 }; 402 403 enum hclge_mac_vlan_add_resp_code { 404 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 405 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 406 }; 407 408 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 409 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 410 #define HCLGE_MAC_EPORT_SW_EN_B 12 411 #define HCLGE_MAC_EPORT_TYPE_B 11 412 #define HCLGE_MAC_EPORT_VFID_S 3 413 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 414 #define HCLGE_MAC_EPORT_PFID_S 0 415 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 416 struct hclge_mac_vlan_tbl_entry_cmd { 417 u8 flags; 418 u8 resp_code; 419 __le16 vlan_tag; 420 __le32 mac_addr_hi32; 421 __le16 mac_addr_lo16; 422 __le16 rsv1; 423 u8 entry_type; 424 u8 mc_mac_en; 425 __le16 egress_port; 426 __le16 egress_queue; 427 u8 rsv2[6]; 428 }; 429 430 #define HCLGE_UMV_SPC_ALC_B 0 431 struct hclge_umv_spc_alc_cmd { 432 u8 allocate; 433 u8 rsv1[3]; 434 __le32 space_size; 435 u8 rsv2[16]; 436 }; 437 438 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 439 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 440 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 441 442 struct hclge_mac_mgr_tbl_entry_cmd { 443 u8 flags; 444 u8 resp_code; 445 __le16 vlan_tag; 446 u8 mac_addr[ETH_ALEN]; 447 __le16 rsv1; 448 __le16 ethter_type; 449 __le16 egress_port; 450 __le16 egress_queue; 451 u8 sw_port_id_aware; 452 u8 rsv2; 453 u8 i_port_bitmap; 454 u8 i_port_direction; 455 u8 rsv3[2]; 456 }; 457 458 struct hclge_vlan_filter_ctrl_cmd { 459 u8 vlan_type; 460 u8 vlan_fe; 461 u8 rsv1[2]; 462 u8 vf_id; 463 u8 rsv2[19]; 464 }; 465 466 #define HCLGE_VLAN_ID_OFFSET_STEP 160 467 #define HCLGE_VLAN_BYTE_SIZE 8 468 #define HCLGE_VLAN_OFFSET_BITMAP \ 469 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) 470 471 struct hclge_vlan_filter_pf_cfg_cmd { 472 u8 vlan_offset; 473 u8 vlan_cfg; 474 u8 rsv[2]; 475 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; 476 }; 477 478 #define HCLGE_MAX_VF_BYTES 16 479 480 struct hclge_vlan_filter_vf_cfg_cmd { 481 __le16 vlan_id; 482 u8 resp_code; 483 u8 rsv; 484 u8 vlan_cfg; 485 u8 rsv1[3]; 486 u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; 487 }; 488 489 #define HCLGE_INGRESS_BYPASS_B 0 490 struct hclge_port_vlan_filter_bypass_cmd { 491 u8 bypass_state; 492 u8 rsv1[3]; 493 u8 vf_id; 494 u8 rsv2[19]; 495 }; 496 497 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U 498 #define HCLGE_SWITCH_ALW_LPBK_B 1U 499 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U 500 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U 501 #define HCLGE_SWITCH_NO_MASK 0x0 502 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE 503 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD 504 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB 505 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 506 507 struct hclge_mac_vlan_switch_cmd { 508 u8 roce_sel; 509 u8 rsv1[3]; 510 __le32 func_id; 511 u8 switch_param; 512 u8 rsv2[3]; 513 u8 param_mask; 514 u8 rsv3[11]; 515 }; 516 517 enum hclge_mac_vlan_cfg_sel { 518 HCLGE_MAC_VLAN_NIC_SEL = 0, 519 HCLGE_MAC_VLAN_ROCE_SEL, 520 }; 521 522 #define HCLGE_ACCEPT_TAG1_B 0 523 #define HCLGE_ACCEPT_UNTAG1_B 1 524 #define HCLGE_PORT_INS_TAG1_EN_B 2 525 #define HCLGE_PORT_INS_TAG2_EN_B 3 526 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 527 #define HCLGE_ACCEPT_TAG2_B 5 528 #define HCLGE_ACCEPT_UNTAG2_B 6 529 #define HCLGE_TAG_SHIFT_MODE_EN_B 7 530 #define HCLGE_VF_NUM_PER_BYTE 8 531 532 struct hclge_vport_vtag_tx_cfg_cmd { 533 u8 vport_vlan_cfg; 534 u8 vf_offset; 535 u8 rsv1[2]; 536 __le16 def_vlan_tag1; 537 __le16 def_vlan_tag2; 538 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 539 u8 rsv2[8]; 540 }; 541 542 #define HCLGE_REM_TAG1_EN_B 0 543 #define HCLGE_REM_TAG2_EN_B 1 544 #define HCLGE_SHOW_TAG1_EN_B 2 545 #define HCLGE_SHOW_TAG2_EN_B 3 546 #define HCLGE_DISCARD_TAG1_EN_B 5 547 #define HCLGE_DISCARD_TAG2_EN_B 6 548 struct hclge_vport_vtag_rx_cfg_cmd { 549 u8 vport_vlan_cfg; 550 u8 vf_offset; 551 u8 rsv1[6]; 552 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 553 u8 rsv2[8]; 554 }; 555 556 struct hclge_tx_vlan_type_cfg_cmd { 557 __le16 ot_vlan_type; 558 __le16 in_vlan_type; 559 u8 rsv[20]; 560 }; 561 562 struct hclge_rx_vlan_type_cfg_cmd { 563 __le16 ot_fst_vlan_type; 564 __le16 ot_sec_vlan_type; 565 __le16 in_fst_vlan_type; 566 __le16 in_sec_vlan_type; 567 u8 rsv[16]; 568 }; 569 570 struct hclge_cfg_com_tqp_queue_cmd { 571 __le16 tqp_id; 572 __le16 stream_id; 573 u8 enable; 574 u8 rsv[19]; 575 }; 576 577 struct hclge_cfg_tx_queue_pointer_cmd { 578 __le16 tqp_id; 579 __le16 tx_tail; 580 __le16 tx_head; 581 __le16 fbd_num; 582 __le16 ring_offset; 583 u8 rsv[14]; 584 }; 585 586 #pragma pack(1) 587 struct hclge_mac_ethertype_idx_rd_cmd { 588 u8 flags; 589 u8 resp_code; 590 __le16 vlan_tag; 591 u8 mac_addr[ETH_ALEN]; 592 __le16 index; 593 __le16 ethter_type; 594 __le16 egress_port; 595 __le16 egress_queue; 596 __le16 rev0; 597 u8 i_port_bitmap; 598 u8 i_port_direction; 599 u8 rev1[2]; 600 }; 601 602 #pragma pack() 603 604 #define HCLGE_TSO_MSS_MIN_S 0 605 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 606 607 #define HCLGE_TSO_MSS_MAX_S 16 608 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 609 610 struct hclge_cfg_tso_status_cmd { 611 __le16 tso_mss_min; 612 __le16 tso_mss_max; 613 u8 rsv[20]; 614 }; 615 616 #define HCLGE_GRO_EN_B 0 617 struct hclge_cfg_gro_status_cmd { 618 u8 gro_en; 619 u8 rsv[23]; 620 }; 621 622 #define HCLGE_TSO_MSS_MIN 256 623 #define HCLGE_TSO_MSS_MAX 9668 624 625 #define HCLGE_TQP_RESET_B 0 626 struct hclge_reset_tqp_queue_cmd { 627 __le16 tqp_id; 628 u8 reset_req; 629 u8 ready_to_reset; 630 u8 rsv[20]; 631 }; 632 633 #define HCLGE_CFG_RESET_MAC_B 3 634 #define HCLGE_CFG_RESET_FUNC_B 7 635 #define HCLGE_CFG_RESET_RCB_B 1 636 struct hclge_reset_cmd { 637 u8 mac_func_reset; 638 u8 fun_reset_vfid; 639 u8 fun_reset_rcb; 640 u8 rsv; 641 __le16 fun_reset_rcb_vqid_start; 642 __le16 fun_reset_rcb_vqid_num; 643 u8 fun_reset_rcb_return_status; 644 u8 rsv1[15]; 645 }; 646 647 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 648 649 struct hclge_pf_rst_done_cmd { 650 u8 pf_rst_done; 651 u8 rsv[23]; 652 }; 653 654 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 655 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 656 #define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3) 657 #define HCLGE_CMD_COMMON_LB_DONE_B BIT(0) 658 #define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1) 659 struct hclge_common_lb_cmd { 660 u8 mask; 661 u8 enable; 662 u8 result; 663 u8 rsv[21]; 664 }; 665 666 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 667 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 668 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 669 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 670 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 671 672 #define HCLGE_LED_LOCATE_STATE_S 0 673 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 674 675 struct hclge_set_led_state_cmd { 676 u8 rsv1[3]; 677 u8 locate_led_config; 678 u8 rsv2[20]; 679 }; 680 681 struct hclge_get_fd_mode_cmd { 682 u8 mode; 683 u8 enable; 684 u8 rsv[22]; 685 }; 686 687 struct hclge_get_fd_allocation_cmd { 688 __le32 stage1_entry_num; 689 __le32 stage2_entry_num; 690 __le16 stage1_counter_num; 691 __le16 stage2_counter_num; 692 u8 rsv[12]; 693 }; 694 695 struct hclge_set_fd_key_config_cmd { 696 u8 stage; 697 u8 key_select; 698 u8 inner_sipv6_word_en; 699 u8 inner_dipv6_word_en; 700 u8 outer_sipv6_word_en; 701 u8 outer_dipv6_word_en; 702 u8 rsv1[2]; 703 __le32 tuple_mask; 704 __le32 meta_data_mask; 705 u8 rsv2[8]; 706 }; 707 708 #define HCLGE_FD_EPORT_SW_EN_B 0 709 struct hclge_fd_tcam_config_1_cmd { 710 u8 stage; 711 u8 xy_sel; 712 u8 port_info; 713 u8 rsv1[1]; 714 __le32 index; 715 u8 entry_vld; 716 u8 rsv2[7]; 717 u8 tcam_data[8]; 718 }; 719 720 struct hclge_fd_tcam_config_2_cmd { 721 u8 tcam_data[24]; 722 }; 723 724 struct hclge_fd_tcam_config_3_cmd { 725 u8 tcam_data[20]; 726 u8 rsv[4]; 727 }; 728 729 #define HCLGE_FD_AD_DROP_B 0 730 #define HCLGE_FD_AD_DIRECT_QID_B 1 731 #define HCLGE_FD_AD_QID_L_S 2 732 #define HCLGE_FD_AD_QID_L_M GENMASK(11, 2) 733 #define HCLGE_FD_AD_USE_COUNTER_B 12 734 #define HCLGE_FD_AD_COUNTER_NUM_L_S 13 735 #define HCLGE_FD_AD_COUNTER_NUM_L_M GENMASK(19, 13) 736 #define HCLGE_FD_AD_NXT_STEP_B 20 737 #define HCLGE_FD_AD_NXT_KEY_S 21 738 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21) 739 #define HCLGE_FD_AD_WR_RULE_ID_B 0 740 #define HCLGE_FD_AD_RULE_ID_S 1 741 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1) 742 #define HCLGE_FD_AD_TC_OVRD_B 16 743 #define HCLGE_FD_AD_TC_SIZE_S 17 744 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17) 745 #define HCLGE_FD_AD_QID_H_B 21 746 #define HCLGE_FD_AD_COUNTER_NUM_H_B 26 747 748 struct hclge_fd_ad_config_cmd { 749 u8 stage; 750 u8 rsv1[3]; 751 __le32 index; 752 __le64 ad_data; 753 u8 rsv2[8]; 754 }; 755 756 struct hclge_fd_ad_cnt_read_cmd { 757 u8 rsv0[4]; 758 __le16 index; 759 u8 rsv1[2]; 760 __le64 cnt; 761 u8 rsv2[8]; 762 }; 763 764 #define HCLGE_FD_USER_DEF_OFT_S 0 765 #define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0) 766 #define HCLGE_FD_USER_DEF_EN_B 15 767 struct hclge_fd_user_def_cfg_cmd { 768 __le16 ol2_cfg; 769 __le16 l2_cfg; 770 __le16 ol3_cfg; 771 __le16 l3_cfg; 772 __le16 ol4_cfg; 773 __le16 l4_cfg; 774 u8 rsv[12]; 775 }; 776 777 struct hclge_get_imp_bd_cmd { 778 __le32 bd_num; 779 u8 rsv[20]; 780 }; 781 782 struct hclge_query_ppu_pf_other_int_dfx_cmd { 783 __le16 over_8bd_no_fe_qid; 784 __le16 over_8bd_no_fe_vf_id; 785 __le16 tso_mss_cmp_min_err_qid; 786 __le16 tso_mss_cmp_min_err_vf_id; 787 __le16 tso_mss_cmp_max_err_qid; 788 __le16 tso_mss_cmp_max_err_vf_id; 789 __le16 tx_rd_fbd_poison_qid; 790 __le16 tx_rd_fbd_poison_vf_id; 791 __le16 rx_rd_fbd_poison_qid; 792 __le16 rx_rd_fbd_poison_vf_id; 793 u8 rsv[4]; 794 }; 795 796 #define HCLGE_SFP_INFO_CMD_NUM 6 797 #define HCLGE_SFP_INFO_BD0_LEN 20 798 #define HCLGE_SFP_INFO_BDX_LEN 24 799 #define HCLGE_SFP_INFO_MAX_LEN \ 800 (HCLGE_SFP_INFO_BD0_LEN + \ 801 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN) 802 803 struct hclge_sfp_info_bd0_cmd { 804 __le16 offset; 805 __le16 read_len; 806 u8 data[HCLGE_SFP_INFO_BD0_LEN]; 807 }; 808 809 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4 810 811 struct hclge_dev_specs_0_cmd { 812 __le32 rsv0; 813 __le32 mac_entry_num; 814 __le32 mng_entry_num; 815 __le16 rss_ind_tbl_size; 816 __le16 rss_key_size; 817 __le16 int_ql_max; 818 u8 max_non_tso_bd_num; 819 u8 rsv1; 820 __le32 max_tm_rate; 821 }; 822 823 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U 824 825 struct hclge_dev_specs_1_cmd { 826 __le16 max_frm_size; 827 __le16 max_qset_num; 828 __le16 max_int_gl; 829 u8 rsv0[2]; 830 __le16 umv_size; 831 __le16 mc_mac_size; 832 u8 rsv1[6]; 833 u8 tnl_num; 834 u8 hilink_version; 835 u8 rsv2[4]; 836 }; 837 838 /* mac speed type defined in firmware command */ 839 enum HCLGE_FIRMWARE_MAC_SPEED { 840 HCLGE_FW_MAC_SPEED_1G, 841 HCLGE_FW_MAC_SPEED_10G, 842 HCLGE_FW_MAC_SPEED_25G, 843 HCLGE_FW_MAC_SPEED_40G, 844 HCLGE_FW_MAC_SPEED_50G, 845 HCLGE_FW_MAC_SPEED_100G, 846 HCLGE_FW_MAC_SPEED_10M, 847 HCLGE_FW_MAC_SPEED_100M, 848 HCLGE_FW_MAC_SPEED_200G, 849 }; 850 851 #define HCLGE_PHY_LINK_SETTING_BD_NUM 2 852 853 struct hclge_phy_link_ksetting_0_cmd { 854 __le32 speed; 855 u8 duplex; 856 u8 autoneg; 857 u8 eth_tp_mdix; 858 u8 eth_tp_mdix_ctrl; 859 u8 port; 860 u8 transceiver; 861 u8 phy_address; 862 u8 rsv; 863 __le32 supported; 864 __le32 advertising; 865 __le32 lp_advertising; 866 }; 867 868 struct hclge_phy_link_ksetting_1_cmd { 869 u8 master_slave_cfg; 870 u8 master_slave_state; 871 u8 rsv[22]; 872 }; 873 874 struct hclge_phy_reg_cmd { 875 __le16 reg_addr; 876 u8 rsv0[2]; 877 __le16 reg_val; 878 u8 rsv1[18]; 879 }; 880 881 struct hclge_wol_cfg_cmd { 882 __le32 wake_on_lan_mode; 883 u8 sopass[SOPASS_MAX]; 884 u8 sopass_size; 885 u8 rsv[13]; 886 }; 887 888 struct hclge_query_wol_supported_cmd { 889 __le32 supported_wake_mode; 890 u8 rsv[20]; 891 }; 892 893 struct hclge_hw; 894 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 895 #endif 896