1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * xHCI Host Controller Capability Registers. 4 * xHCI Specification Section 5.3, Revision 1.2. 5 */ 6 7 #include <linux/bits.h> 8 9 /* hc_capbase - bitmasks */ 10 /* bits 7:0 - Capability Registers Length */ 11 #define HC_LENGTH(p) ((p) & 0xff) 12 /* bits 15:8 - Rsvd */ 13 /* bits 31:16 - Host Controller Interface Version Number */ 14 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 15 16 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 17 /* bits 7:0 - Number of Device Slots */ 18 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 19 #define HCS_SLOTS_MASK 0xff 20 /* bits 18:8 - Number of Interrupters, max values is 1024 */ 21 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 22 /* bits 31:24, Max Ports - max value is 255 */ 23 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) 24 25 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 26 /* 27 * bits 3:0 - Isochronous Scheduling Threshold, frames or uframes that SW 28 * needs to queue transactions ahead of the HW to meet periodic deadlines. 29 * - Bits 2:0: Threshold value 30 * - Bit 3: Unit indicator 31 * - '1': Threshold in Frames 32 * - '0': Threshold in Microframes (uframes) 33 * Note: 1 Frame = 8 Microframes 34 * xHCI specification section 5.3.4. 35 */ 36 #define HCS_IST_VALUE(p) ((p) & 0x7) 37 #define HCS_IST_UNIT BIT(3) 38 /* bits 7:4 - Event Ring Segment Table Max, 2^(n) */ 39 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 40 /* bits 20:8 - Rsvd */ 41 /* bits 25:21 - Max Scratchpad Buffers (Hi), 5 Most significant bits */ 42 #define HCS_MAX_SP_HI(p) (((p) >> 21) & 0x1f) 43 /* bit 26 - Scratchpad restore, for save/restore HW state */ 44 /* bits 31:27 - Max Scratchpad Buffers (Lo), 5 Least significant bits */ 45 #define HCS_MAX_SP_LO(p) (((p) >> 27) & 0x1f) 46 #define HCS_MAX_SCRATCHPAD(p) (HCS_MAX_SP_HI(p) << 5 | HCS_MAX_SP_LO(p)) 47 48 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 49 /* bits 7:0 - U1 Device Exit Latency, Max U1 to U0 latency for the roothub ports */ 50 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 51 /* bits 15:8 - Rsvd */ 52 /* bits 31:16 - U2 Device Exit Latency, Max U2 to U0 latency for the roothub ports */ 53 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 54 55 /* HCCPARAMS1 - hcc_params - bitmasks */ 56 /* bit 0 - 64-bit Addressing Capability */ 57 #define HCC_64BIT_ADDR BIT(0) 58 /* bit 1 - BW Negotiation Capability */ 59 #define HCC_BANDWIDTH_NEG BIT(1) 60 /* bit 2 - Context Size */ 61 #define HCC_64BYTE_CONTEXT BIT(2) 62 #define CTX_SIZE(_hcc) (_hcc & HCC_64BYTE_CONTEXT ? 64 : 32) 63 /* bit 3 - Port Power Control */ 64 #define HCC_PPC BIT(3) 65 /* bit 4 - Port Indicators */ 66 #define HCS_INDICATOR BIT(4) 67 /* bit 5 - Light HC Reset Capability */ 68 #define HCC_LIGHT_RESET BIT(5) 69 /* bit 6 - Latency Tolerance Messaging Capability */ 70 #define HCC_LTC BIT(6) 71 /* bit 7 - No Secondary Stream ID Support */ 72 #define HCC_NSS BIT(7) 73 /* bit 8 - Parse All Event Data */ 74 /* bit 9 - Short Packet Capability */ 75 #define HCC_SPC BIT(9) 76 /* bit 10 - Stopped EDTLA Capability */ 77 /* bit 11 - Contiguous Frame ID Capability */ 78 #define HCC_CFC BIT(11) 79 /* bits 15:12 - Max size for Primary Stream Arrays, 2^(n+1) */ 80 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 81 /* bits 31:16 - xHCI Extended Capabilities Pointer, from PCI base: 2^(n) */ 82 #define HCC_EXT_CAPS(p) (((p) >> 16) & 0xffff) 83 84 /* DBOFF - db_off - bitmasks */ 85 /* bits 1:0 - Rsvd */ 86 /* bits 31:2 - Doorbell Array Offset */ 87 #define DBOFF_MASK (0xfffffffc) 88 89 /* RTSOFF - run_regs_off - bitmasks */ 90 /* bits 4:0 - Rsvd */ 91 /* bits 31:5 - Runtime Register Space Offse */ 92 #define RTSOFF_MASK (~0x1f) 93 94 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 95 /* bit 0 - U3 Entry Capability */ 96 #define HCC2_U3C BIT(0) 97 /* bit 1 - Configure Endpoint Command Max Exit Latency Too Large Capability */ 98 #define HCC2_CMC BIT(1) 99 /* bit 2 - Force Save Context Capabilitu */ 100 #define HCC2_FSC BIT(2) 101 /* bit 3 - Compliance Transition Capability, false: compliance is enabled by default */ 102 #define HCC2_CTC BIT(3) 103 /* bit 4 - Large ESIT Payload Capability, true: HC support ESIT payload > 48k */ 104 #define HCC2_LEC BIT(4) 105 /* bit 5 - Configuration Information Capability */ 106 #define HCC2_CIC BIT(5) 107 /* bit 6 - Extended TBC Capability, true: Isoc burst count > 65535 */ 108 #define HCC2_ETC BIT(6) 109 /* bit 7 - Extended TBC TRB Status Capability */ 110 #define HCC2_ETC_TSC BIT(7) 111 /* bit 8 - Get/Set Extended Property Capability */ 112 #define HCC2_GSC BIT(8) 113 /* bit 9 - Virtualization Based Trusted I/O Capability */ 114 #define HCC2_VTC BIT(9) 115 /* bit 10 - Rsvd */ 116 /* bit 11 - HC support Double BW on a eUSB2 HS ISOC EP */ 117 #define HCC2_EUSB2_DIC BIT(11) 118 /* bit 12 - HC support eUSB2V2 capability */ 119 #define HCC2_E2V2C BIT(12) 120 /* bits 31:13 - Rsvd */ 121