1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2024 Hisilicon Limited. */ 3 4 #ifndef __HBG_REG_H 5 #define __HBG_REG_H 6 7 /* DEV SPEC */ 8 #define HBG_REG_SPEC_VALID_ADDR 0x0000 9 #define HBG_REG_EVENT_REQ_ADDR 0x0004 10 #define HBG_REG_MAC_ID_ADDR 0x0008 11 #define HBG_REG_PHY_ID_ADDR 0x000C 12 #define HBG_REG_MAC_ADDR_ADDR 0x0010 13 #define HBG_REG_MAC_ADDR_HIGH_ADDR 0x0014 14 #define HBG_REG_UC_MAC_NUM_ADDR 0x0018 15 #define HBG_REG_MDIO_FREQ_ADDR 0x0024 16 #define HBG_REG_MAX_MTU_ADDR 0x0028 17 #define HBG_REG_MIN_MTU_ADDR 0x002C 18 #define HBG_REG_TX_FIFO_NUM_ADDR 0x0030 19 #define HBG_REG_RX_FIFO_NUM_ADDR 0x0034 20 #define HBG_REG_VLAN_LAYERS_ADDR 0x0038 21 #define HBG_REG_PUSH_REQ_ADDR 0x00F0 22 #define HBG_REG_MSG_HEADER_ADDR 0x00F4 23 #define HBG_REG_MSG_HEADER_OPCODE_M GENMASK(7, 0) 24 #define HBG_REG_MSG_HEADER_STATUS_M GENMASK(11, 8) 25 #define HBG_REG_MSG_HEADER_DATA_NUM_M GENMASK(19, 12) 26 #define HBG_REG_MSG_HEADER_RESP_CODE_M GENMASK(27, 20) 27 #define HBG_REG_MSG_DATA_BASE_ADDR 0x0100 28 29 /* MDIO */ 30 #define HBG_REG_MDIO_BASE 0x8000 31 #define HBG_REG_MDIO_COMMAND_ADDR (HBG_REG_MDIO_BASE + 0x0000) 32 #define HBG_REG_MDIO_COMMAND_CLK_SEL_EXP_B BIT(17) 33 #define HBG_REG_MDIO_COMMAND_AUTO_SCAN_B BIT(16) 34 #define HBG_REG_MDIO_COMMAND_CLK_SEL_B BIT(15) 35 #define HBG_REG_MDIO_COMMAND_START_B BIT(14) 36 #define HBG_REG_MDIO_COMMAND_ST_M GENMASK(13, 12) 37 #define HBG_REG_MDIO_COMMAND_OP_M GENMASK(11, 10) 38 #define HBG_REG_MDIO_COMMAND_PRTAD_M GENMASK(9, 5) 39 #define HBG_REG_MDIO_COMMAND_DEVAD_M GENMASK(4, 0) 40 #define HBG_REG_MDIO_ADDR_ADDR (HBG_REG_MDIO_BASE + 0x0004) 41 #define HBG_REG_MDIO_WDATA_ADDR (HBG_REG_MDIO_BASE + 0x0008) 42 #define HBG_REG_MDIO_WDATA_M GENMASK(15, 0) 43 #define HBG_REG_MDIO_RDATA_ADDR (HBG_REG_MDIO_BASE + 0x000C) 44 #define HBG_REG_MDIO_STA_ADDR (HBG_REG_MDIO_BASE + 0x0010) 45 46 /* GMAC */ 47 #define HBG_REG_SGMII_BASE 0x10000 48 #define HBG_REG_DUPLEX_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x0008) 49 #define HBG_REG_FD_FC_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x000C) 50 #define HBG_REG_FC_TX_TIMER_ADDR (HBG_REG_SGMII_BASE + 0x001C) 51 #define HBG_REG_FD_FC_ADDR_LOW_ADDR (HBG_REG_SGMII_BASE + 0x0020) 52 #define HBG_REG_FD_FC_ADDR_HIGH_ADDR (HBG_REG_SGMII_BASE + 0x0024) 53 #define HBG_REG_DUPLEX_B BIT(0) 54 #define HBG_REG_MAX_FRAME_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x003C) 55 #define HBG_REG_PORT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x0040) 56 #define HBG_REG_PORT_MODE_M GENMASK(3, 0) 57 #define HBG_REG_PORT_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0044) 58 #define HBG_REG_PORT_ENABLE_RX_B BIT(1) 59 #define HBG_REG_PORT_ENABLE_TX_B BIT(2) 60 #define HBG_REG_PAUSE_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0048) 61 #define HBG_REG_PAUSE_ENABLE_RX_B BIT(0) 62 #define HBG_REG_PAUSE_ENABLE_TX_B BIT(1) 63 #define HBG_REG_AN_NEG_STATE_ADDR (HBG_REG_SGMII_BASE + 0x0058) 64 #define HBG_REG_AN_NEG_STATE_NP_LINK_OK_B BIT(15) 65 #define HBG_REG_TRANSMIT_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x0060) 66 #define HBG_REG_TRANSMIT_CTRL_PAD_EN_B BIT(7) 67 #define HBG_REG_TRANSMIT_CTRL_CRC_ADD_B BIT(6) 68 #define HBG_REG_TRANSMIT_CTRL_AN_EN_B BIT(5) 69 #define HBG_REG_REC_FILT_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x0064) 70 #define HBG_REG_REC_FILT_CTRL_UC_MATCH_EN_B BIT(0) 71 #define HBG_REG_RX_OCTETS_TOTAL_OK_ADDR (HBG_REG_SGMII_BASE + 0x0080) 72 #define HBG_REG_RX_OCTETS_BAD_ADDR (HBG_REG_SGMII_BASE + 0x0084) 73 #define HBG_REG_RX_UC_PKTS_ADDR (HBG_REG_SGMII_BASE + 0x0088) 74 #define HBG_REG_RX_MC_PKTS_ADDR (HBG_REG_SGMII_BASE + 0x008C) 75 #define HBG_REG_RX_BC_PKTS_ADDR (HBG_REG_SGMII_BASE + 0x0090) 76 #define HBG_REG_RX_PKTS_64OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0094) 77 #define HBG_REG_RX_PKTS_65TO127OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0098) 78 #define HBG_REG_RX_PKTS_128TO255OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x009C) 79 #define HBG_REG_RX_PKTS_256TO511OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x00A0) 80 #define HBG_REG_RX_PKTS_512TO1023OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x00A4) 81 #define HBG_REG_RX_PKTS_1024TO1518OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x00A8) 82 #define HBG_REG_RX_PKTS_1519TOMAXOCTETS_ADDR (HBG_REG_SGMII_BASE + 0x00AC) 83 #define HBG_REG_RX_FCS_ERRORS_ADDR (HBG_REG_SGMII_BASE + 0x00B0) 84 #define HBG_REG_RX_TAGGED_ADDR (HBG_REG_SGMII_BASE + 0x00B4) 85 #define HBG_REG_RX_DATA_ERR_ADDR (HBG_REG_SGMII_BASE + 0x00B8) 86 #define HBG_REG_RX_ALIGN_ERRORS_ADDR (HBG_REG_SGMII_BASE + 0x00BC) 87 #define HBG_REG_RX_LONG_ERRORS_ADDR (HBG_REG_SGMII_BASE + 0x00C0) 88 #define HBG_REG_RX_JABBER_ERRORS_ADDR (HBG_REG_SGMII_BASE + 0x00C4) 89 #define HBG_REG_RX_PAUSE_MACCTL_FRAMCOUNTER_ADDR (HBG_REG_SGMII_BASE + 0x00C8) 90 #define HBG_REG_RX_UNKNOWN_MACCTL_FRAMCOUNTER_ADDR (HBG_REG_SGMII_BASE + 0x00CC) 91 #define HBG_REG_RX_VERY_LONG_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x00D0) 92 #define HBG_REG_RX_RUNT_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x00D4) 93 #define HBG_REG_RX_SHORT_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x00D8) 94 #define HBG_REG_RX_FILT_PKT_CNT_ADDR (HBG_REG_SGMII_BASE + 0x00E8) 95 #define HBG_REG_RX_OCTETS_TOTAL_FILT_ADDR (HBG_REG_SGMII_BASE + 0x00EC) 96 #define HBG_REG_OCTETS_TRANSMITTED_OK_ADDR (HBG_REG_SGMII_BASE + 0x0100) 97 #define HBG_REG_OCTETS_TRANSMITTED_BAD_ADDR (HBG_REG_SGMII_BASE + 0x0104) 98 #define HBG_REG_TX_UC_PKTS_ADDR (HBG_REG_SGMII_BASE + 0x0108) 99 #define HBG_REG_TX_MC_PKTS_ADDR (HBG_REG_SGMII_BASE + 0x010C) 100 #define HBG_REG_TX_BC_PKTS_ADDR (HBG_REG_SGMII_BASE + 0x0110) 101 #define HBG_REG_TX_PKTS_64OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0114) 102 #define HBG_REG_TX_PKTS_65TO127OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0118) 103 #define HBG_REG_TX_PKTS_128TO255OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x011C) 104 #define HBG_REG_TX_PKTS_256TO511OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0120) 105 #define HBG_REG_TX_PKTS_512TO1023OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0124) 106 #define HBG_REG_TX_PKTS_1024TO1518OCTETS_ADDR (HBG_REG_SGMII_BASE + 0x0128) 107 #define HBG_REG_TX_PKTS_1519TOMAXOCTETS_ADDR (HBG_REG_SGMII_BASE + 0x012C) 108 #define HBG_REG_TX_EXCESSIVE_LENGTH_DROP_ADDR (HBG_REG_SGMII_BASE + 0x014C) 109 #define HBG_REG_TX_UNDERRUN_ADDR (HBG_REG_SGMII_BASE + 0x0150) 110 #define HBG_REG_TX_TAGGED_ADDR (HBG_REG_SGMII_BASE + 0x0154) 111 #define HBG_REG_TX_CRC_ERROR_ADDR (HBG_REG_SGMII_BASE + 0x0158) 112 #define HBG_REG_TX_PAUSE_FRAMES_ADDR (HBG_REG_SGMII_BASE + 0x015C) 113 #define HBG_REG_LINE_LOOP_BACK_ADDR (HBG_REG_SGMII_BASE + 0x01A8) 114 #define HBG_REG_CF_CRC_STRIP_ADDR (HBG_REG_SGMII_BASE + 0x01B0) 115 #define HBG_REG_CF_CRC_STRIP_B BIT(0) 116 #define HBG_REG_MODE_CHANGE_EN_ADDR (HBG_REG_SGMII_BASE + 0x01B4) 117 #define HBG_REG_MODE_CHANGE_EN_B BIT(0) 118 #define HBG_REG_LOOP_REG_ADDR (HBG_REG_SGMII_BASE + 0x01DC) 119 #define HBG_REG_RECV_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x01E0) 120 #define HBG_REG_RECV_CTRL_STRIP_PAD_EN_B BIT(3) 121 #define HBG_REG_VLAN_CODE_ADDR (HBG_REG_SGMII_BASE + 0x01E8) 122 #define HBG_REG_RX_OVERRUN_CNT_ADDR (HBG_REG_SGMII_BASE + 0x01EC) 123 #define HBG_REG_RX_LENGTHFIELD_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x01F4) 124 #define HBG_REG_RX_FAIL_COMMA_CNT_ADDR (HBG_REG_SGMII_BASE + 0x01F8) 125 #define HBG_REG_STATION_ADDR_LOW_0_ADDR (HBG_REG_SGMII_BASE + 0x0200) 126 #define HBG_REG_STATION_ADDR_HIGH_0_ADDR (HBG_REG_SGMII_BASE + 0x0204) 127 #define HBG_REG_STATION_ADDR_LOW_1_ADDR (HBG_REG_SGMII_BASE + 0x0208) 128 #define HBG_REG_STATION_ADDR_HIGH_1_ADDR (HBG_REG_SGMII_BASE + 0x020C) 129 #define HBG_REG_STATION_ADDR_LOW_2_ADDR (HBG_REG_SGMII_BASE + 0x0210) 130 #define HBG_REG_STATION_ADDR_HIGH_2_ADDR (HBG_REG_SGMII_BASE + 0x0214) 131 #define HBG_REG_STATION_ADDR_LOW_3_ADDR (HBG_REG_SGMII_BASE + 0x0218) 132 #define HBG_REG_STATION_ADDR_HIGH_3_ADDR (HBG_REG_SGMII_BASE + 0x021C) 133 #define HBG_REG_STATION_ADDR_LOW_4_ADDR (HBG_REG_SGMII_BASE + 0x0220) 134 #define HBG_REG_STATION_ADDR_HIGH_4_ADDR (HBG_REG_SGMII_BASE + 0x0224) 135 #define HBG_REG_STATION_ADDR_LOW_5_ADDR (HBG_REG_SGMII_BASE + 0x0228) 136 #define HBG_REG_STATION_ADDR_HIGH_5_ADDR (HBG_REG_SGMII_BASE + 0x022C) 137 138 /* PCU */ 139 #define HBG_REG_TX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0420) 140 #define HBG_REG_RX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0424) 141 #define HBG_REG_CFG_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0428) 142 #define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C) 143 #define HBG_INT_MSK_WE_ERR_B BIT(31) 144 #define HBG_INT_MSK_RBREQ_ERR_B BIT(30) 145 #define HBG_INT_MSK_MAC_FIFO_ERR_B BIT(29) 146 #define HBG_INT_MSK_RX_AHB_ERR_B BIT(28) 147 #define HBG_INT_MSK_RX_DROP_B BIT(26) 148 #define HBG_INT_MSK_TX_DROP_B BIT(25) 149 #define HBG_INT_MSK_TXCFG_AVL_B BIT(24) 150 #define HBG_INT_MSK_REL_BUF_ERR_B BIT(23) 151 #define HBG_INT_MSK_RX_BUF_AVL_B BIT(22) 152 #define HBG_INT_MSK_TX_AHB_ERR_B BIT(21) 153 #define HBG_INT_MSK_SRAM_PARITY_ERR_B BIT(20) 154 #define HBG_INT_MSK_MAC_APP_TX_FIFO_ERR_B BIT(19) 155 #define HBG_INT_MSK_MAC_APP_RX_FIFO_ERR_B BIT(18) 156 #define HBG_INT_MSK_MAC_PCS_TX_FIFO_ERR_B BIT(17) 157 #define HBG_INT_MSK_MAC_PCS_RX_FIFO_ERR_B BIT(16) 158 #define HBG_INT_MSK_MAC_MII_FIFO_ERR_B BIT(15) 159 #define HBG_INT_MSK_TX_PKT_CPL_B BIT(14) 160 #define HBG_INT_MSK_TX_B BIT(1) /* just used in driver */ 161 #define HBG_INT_MSK_RX_B BIT(0) /* just used in driver */ 162 #define HBG_REG_CF_INTRPT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0434) 163 #define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438) 164 #define HBG_REG_TX_BUS_ERR_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x043C) 165 #define HBG_REG_RX_BUS_ERR_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x0440) 166 #define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444) 167 #define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0) 168 #define HBG_REG_TX_DROP_CNT_ADDR (HBG_REG_SGMII_BASE + 0x0448) 169 #define HBG_REG_RX_OVER_FLOW_CNT_ADDR (HBG_REG_SGMII_BASE + 0x044C) 170 #define HBG_REG_DEBUG_ST_MCH_ADDR (HBG_REG_SGMII_BASE + 0x0450) 171 #define HBG_REG_FIFO_CURR_STATUS_ADDR (HBG_REG_SGMII_BASE + 0x0454) 172 #define HBG_REG_FIFO_HIST_STATUS_ADDR (HBG_REG_SGMII_BASE + 0x0458) 173 #define HBG_REG_CF_CFF_DATA_NUM_ADDR (HBG_REG_SGMII_BASE + 0x045C) 174 #define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0) 175 #define HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M GENMASK(24, 16) 176 #define HBG_REG_TX_CS_FAIL_CNT_ADDR (HBG_REG_SGMII_BASE + 0x0460) 177 #define HBG_REG_RX_TRANS_PKG_CNT_ADDR (HBG_REG_SGMII_BASE + 0x0464) 178 #define HBG_REG_TX_TRANS_PKG_CNT_ADDR (HBG_REG_SGMII_BASE + 0x0468) 179 #define HBG_REG_CF_TX_PAUSE_ADDR (HBG_REG_SGMII_BASE + 0x0470) 180 #define HBG_REG_TX_CFF_ADDR_0_ADDR (HBG_REG_SGMII_BASE + 0x0488) 181 #define HBG_REG_TX_CFF_ADDR_1_ADDR (HBG_REG_SGMII_BASE + 0x048C) 182 #define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490) 183 #define HBG_REG_TX_CFF_ADDR_3_ADDR (HBG_REG_SGMII_BASE + 0x0494) 184 #define HBG_REG_RX_CFF_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x04A0) 185 #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) 186 #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) 187 #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) 188 #define HBG_REG_BUS_CTRL_ENDIAN_M GENMASK(2, 1) 189 #define HBG_REG_RX_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04F0) 190 #define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE_M GENMASK(31, 28) 191 #define HBG_REG_RX_CTRL_TIME_INF_EN_B BIT(23) 192 #define HBG_REG_RX_CTRL_RX_ALIGN_NUM_M GENMASK(18, 17) 193 #define HBG_REG_RX_CTRL_PORT_NUM GENMASK(16, 13) 194 #define HBG_REG_RX_CTRL_RX_GET_ADDR_MODE_B BIT(12) 195 #define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0) 196 #define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4) 197 #define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21) 198 #define HBG_REG_RX_BUFRQ_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x058C) 199 #define HBG_REG_TX_BUFRL_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x0590) 200 #define HBG_REG_RX_WE_ERR_CNT_ADDR (HBG_REG_SGMII_BASE + 0x0594) 201 #define HBG_REG_DBG_ST0_ADDR (HBG_REG_SGMII_BASE + 0x05E4) 202 #define HBG_REG_DBG_ST1_ADDR (HBG_REG_SGMII_BASE + 0x05E8) 203 #define HBG_REG_DBG_ST2_ADDR (HBG_REG_SGMII_BASE + 0x05EC) 204 #define HBG_REG_BUS_RST_EN_ADDR (HBG_REG_SGMII_BASE + 0x0688) 205 #define HBG_REG_CF_IND_TXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x0694) 206 #define HBG_REG_IND_INTR_MASK_B BIT(0) 207 #define HBG_REG_CF_IND_TXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0698) 208 #define HBG_REG_CF_IND_TXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x069C) 209 #define HBG_REG_CF_IND_RXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x06a0) 210 #define HBG_REG_CF_IND_RXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x06a4) 211 #define HBG_REG_CF_IND_RXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x06a8) 212 213 enum hbg_port_mode { 214 /* 0x0 ~ 0x5 are reserved */ 215 HBG_PORT_MODE_SGMII_10M = 0x6, 216 HBG_PORT_MODE_SGMII_100M = 0x7, 217 HBG_PORT_MODE_SGMII_1000M = 0x8, 218 }; 219 220 struct hbg_tx_desc { 221 u32 word0; 222 u32 word1; 223 u32 word2; /* pkt_addr */ 224 u32 word3; /* clear_addr */ 225 }; 226 227 #define HBG_TX_DESC_W0_IP_OFF_M GENMASK(30, 26) 228 #define HBG_TX_DESC_W0_l3_CS_B BIT(2) 229 #define HBG_TX_DESC_W0_WB_B BIT(1) 230 #define HBG_TX_DESC_W0_l4_CS_B BIT(0) 231 #define HBG_TX_DESC_W1_SEND_LEN_M GENMASK(19, 4) 232 233 struct hbg_rx_desc { 234 u32 word0; 235 u32 word1; /* tag */ 236 u32 word2; 237 u32 word3; 238 u32 word4; 239 u32 word5; 240 }; 241 242 #define HBG_RX_DESC_W2_PKT_LEN_M GENMASK(31, 16) 243 #define HBG_RX_DESC_W2_PORT_NUM_M GENMASK(15, 12) 244 #define HBG_RX_DESC_W4_IP_TCP_UDP_M GENMASK(31, 30) 245 #define HBG_RX_DESC_W4_IPSEC_B BIT(29) 246 #define HBG_RX_DESC_W4_IP_VERSION_B BIT(28) 247 #define HBG_RX_DESC_W4_L4_ERR_CODE_M GENMASK(26, 23) 248 #define HBG_RX_DESC_W4_FRAG_B BIT(22) 249 #define HBG_RX_DESC_W4_OPT_B BIT(21) 250 #define HBG_RX_DESC_W4_IP_VERSION_ERR_B BIT(20) 251 #define HBG_RX_DESC_W4_BRD_CST_B BIT(19) 252 #define HBG_RX_DESC_W4_MUL_CST_B BIT(18) 253 #define HBG_RX_DESC_W4_ARP_B BIT(17) 254 #define HBG_RX_DESC_W4_RARP_B BIT(16) 255 #define HBG_RX_DESC_W4_ICMP_B BIT(15) 256 #define HBG_RX_DESC_W4_VLAN_FLAG_B BIT(14) 257 #define HBG_RX_DESC_W4_DROP_B BIT(13) 258 #define HBG_RX_DESC_W4_L3_ERR_CODE_M GENMASK(12, 9) 259 #define HBG_RX_DESC_W4_L2_ERR_B BIT(8) 260 #define HBG_RX_DESC_W4_IDX_MATCH_B BIT(7) 261 262 enum hbg_l3_err_code { 263 HBG_L3_OK = 0, 264 HBG_L3_WRONG_HEAD, 265 HBG_L3_CSUM_ERR, 266 HBG_L3_LEN_ERR, 267 HBG_L3_ZERO_TTL, 268 HBG_L3_RSVD, 269 }; 270 271 enum hbg_l4_err_code { 272 HBG_L4_OK = 0, 273 HBG_L4_WRONG_HEAD, 274 HBG_L4_LEN_ERR, 275 HBG_L4_CSUM_ERR, 276 HBG_L4_ZERO_PORT_NUM, 277 HBG_L4_RSVD, 278 }; 279 280 enum hbg_pkt_type_code { 281 HBG_NO_IP_PKT = 0, 282 HBG_IP_PKT, 283 HBG_TCP_PKT, 284 HBG_UDP_PKT, 285 }; 286 287 #endif 288