1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_HAL_TX_H 8 #define ATH12K_HAL_TX_H 9 10 #include "hal_desc.h" 11 #include "core.h" 12 13 #define HAL_TX_ADDRX_EN 1 14 #define HAL_TX_ADDRY_EN 2 15 16 #define HAL_TX_ADDR_SEARCH_DEFAULT 0 17 #define HAL_TX_ADDR_SEARCH_INDEX 1 18 19 /* TODO: check all these data can be managed with struct ath12k_tx_desc_info for perf */ 20 struct hal_tx_info { 21 u16 meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */ 22 u8 ring_id; 23 u8 rbm_id; 24 u32 desc_id; 25 enum hal_tcl_desc_type type; 26 enum hal_tcl_encap_type encap_type; 27 dma_addr_t paddr; 28 u32 data_len; 29 u32 pkt_offset; 30 enum hal_encrypt_type encrypt_type; 31 u32 flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */ 32 u32 flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */ 33 u16 addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */ 34 u16 bss_ast_hash; 35 u16 bss_ast_idx; 36 u8 tid; 37 u8 search_type; /* %HAL_TX_ADDR_SEARCH_ */ 38 u8 lmac_id; 39 u8 vdev_id; 40 u8 dscp_tid_tbl_idx; 41 bool enable_mesh; 42 int bank_id; 43 }; 44 45 /* TODO: Check if the actual desc macros can be used instead */ 46 #define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0) 47 #define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1) 48 #define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2) 49 #define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3) 50 #define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4) 51 #define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5) 52 #define HAL_TX_STATUS_FLAGS_OFDMA BIT(6) 53 54 #define HAL_TX_STATUS_DESC_LEN sizeof(struct hal_wbm_release_ring) 55 56 /* Tx status parsed from srng desc */ 57 struct hal_tx_status { 58 enum hal_wbm_rel_src_module buf_rel_source; 59 enum hal_wbm_tqm_rel_reason status; 60 s8 ack_rssi; 61 u32 flags; /* %HAL_TX_STATUS_FLAGS_ */ 62 u32 ppdu_id; 63 u8 try_cnt; 64 u8 tid; 65 u16 peer_id; 66 u32 rate_stats; 67 }; 68 69 #define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16) 70 #define HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B BIT(20) 71 #define HAL_TX_PHY_DESC_INFO0_PKT_TYPE GENMASK(24, 21) 72 #define HAL_TX_PHY_DESC_INFO0_BANDWIDTH GENMASK(30, 28) 73 #define HAL_TX_PHY_DESC_INFO1_MCS GENMASK(3, 0) 74 #define HAL_TX_PHY_DESC_INFO1_STBC BIT(6) 75 #define HAL_TX_PHY_DESC_INFO2_NSS GENMASK(23, 21) 76 #define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW GENMASK(6, 4) 77 #define HAL_TX_PHY_DESC_INFO3_LTF_SIZE GENMASK(20, 19) 78 #define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL GENMASK(17, 15) 79 80 struct hal_tx_phy_desc { 81 __le32 info0; 82 __le32 info1; 83 __le32 info2; 84 __le32 info3; 85 } __packed; 86 87 #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0 GENMASK(15, 0) 88 #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16 GENMASK(31, 16) 89 #define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0 GENMASK(15, 0) 90 #define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16 GENMASK(31, 16) 91 92 struct hal_tx_fes_status_prot { 93 __le64 reserved; 94 __le32 info0; 95 __le32 info1; 96 __le32 reserved1[11]; 97 } __packed; 98 99 #define HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION GENMASK(15, 0) 100 101 struct hal_tx_fes_status_user_ppdu { 102 __le64 reserved; 103 __le32 info0; 104 __le32 reserved1[3]; 105 } __packed; 106 107 #define HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32 GENMASK(31, 0) 108 #define HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32 GENMASK(31, 0) 109 110 struct hal_tx_fes_status_start_prot { 111 __le32 info0; 112 __le32 info1; 113 __le64 reserved; 114 } __packed; 115 116 #define HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE GENMASK(29, 27) 117 118 struct hal_tx_fes_status_start { 119 __le32 reserved; 120 __le32 info0; 121 __le64 reserved1; 122 } __packed; 123 124 #define HAL_TX_Q_EXT_INFO0_FRAME_CTRL GENMASK(15, 0) 125 #define HAL_TX_Q_EXT_INFO0_QOS_CTRL GENMASK(31, 16) 126 #define HAL_TX_Q_EXT_INFO1_AMPDU_FLAG BIT(0) 127 128 struct hal_tx_queue_exten { 129 __le32 info0; 130 __le32 info1; 131 } __packed; 132 133 #define HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS GENMASK(28, 23) 134 135 struct hal_tx_fes_setup { 136 __le32 schedule_id; 137 __le32 info0; 138 __le64 reserved; 139 } __packed; 140 141 #define HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE GENMASK(2, 0) 142 #define HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0 GENMASK(31, 0) 143 #define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32 GENMASK(15, 0) 144 #define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0 GENMASK(31, 16) 145 #define HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16 GENMASK(31, 0) 146 #define HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0 GENMASK(31, 0) 147 #define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32 GENMASK(15, 0) 148 #define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0 GENMASK(31, 16) 149 #define HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16 GENMASK(31, 0) 150 151 struct hal_tx_pcu_ppdu_setup_init { 152 __le32 info0; 153 __le32 info1; 154 __le32 info2; 155 __le32 info3; 156 __le32 reserved; 157 __le32 info4; 158 __le32 info5; 159 __le32 info6; 160 } __packed; 161 162 #define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0 GENMASK(15, 0) 163 #define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16 GENMASK(31, 16) 164 165 struct hal_tx_fes_status_end { 166 __le32 reserved[2]; 167 __le32 info0; 168 __le32 reserved1[19]; 169 } __packed; 170 171 #define HAL_TX_BANK_CONFIG_EPD BIT(0) 172 #define HAL_TX_BANK_CONFIG_ENCAP_TYPE GENMASK(2, 1) 173 #define HAL_TX_BANK_CONFIG_ENCRYPT_TYPE GENMASK(6, 3) 174 #define HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP BIT(7) 175 #define HAL_TX_BANK_CONFIG_LINK_META_SWAP BIT(8) 176 #define HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN BIT(9) 177 #define HAL_TX_BANK_CONFIG_ADDRX_EN BIT(10) 178 #define HAL_TX_BANK_CONFIG_ADDRY_EN BIT(11) 179 #define HAL_TX_BANK_CONFIG_MESH_EN GENMASK(13, 12) 180 #define HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN BIT(14) 181 #define HAL_TX_BANK_CONFIG_PMAC_ID GENMASK(16, 15) 182 /* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */ 183 #define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID GENMASK(22, 17) 184 185 void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab, 186 struct hal_tcl_data_cmd *tcl_cmd, 187 struct hal_tx_info *ti); 188 void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id); 189 int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, 190 enum hal_reo_cmd_type type, 191 struct ath12k_hal_reo_cmd *cmd); 192 void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config, 193 u8 bank_id); 194 #endif 195