1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HAL_RX_H
8 #define ATH12K_HAL_RX_H
9
10 struct hal_rx_wbm_rel_info {
11 u32 cookie;
12 enum hal_wbm_rel_src_module err_rel_src;
13 enum hal_reo_dest_ring_push_reason push_reason;
14 u32 err_code;
15 bool first_msdu;
16 bool last_msdu;
17 bool continuation;
18 void *rx_desc;
19 bool hw_cc_done;
20 };
21
22 #define HAL_INVALID_PEERID 0x3fff
23 #define VHT_SIG_SU_NSS_MASK 0x7
24
25 #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
26 le32_get_bits((__val), GENMASK(7, 0))
27
28 #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
29 le32_get_bits((__val), GENMASK(15, 8))
30
31 #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
32 le32_get_bits((__val), GENMASK(23, 16))
33
34 #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
35 le32_get_bits((__val), GENMASK(31, 24))
36
37 struct hal_rx_mon_status_tlv_hdr {
38 u32 hdr;
39 u8 value[];
40 };
41
42 enum hal_rx_su_mu_coding {
43 HAL_RX_SU_MU_CODING_BCC,
44 HAL_RX_SU_MU_CODING_LDPC,
45 HAL_RX_SU_MU_CODING_MAX,
46 };
47
48 enum hal_rx_gi {
49 HAL_RX_GI_0_8_US,
50 HAL_RX_GI_0_4_US,
51 HAL_RX_GI_1_6_US,
52 HAL_RX_GI_3_2_US,
53 HAL_RX_GI_MAX,
54 };
55
56 enum hal_rx_bw {
57 HAL_RX_BW_20MHZ,
58 HAL_RX_BW_40MHZ,
59 HAL_RX_BW_80MHZ,
60 HAL_RX_BW_160MHZ,
61 HAL_RX_BW_320MHZ,
62 HAL_RX_BW_MAX,
63 };
64
65 enum hal_rx_preamble {
66 HAL_RX_PREAMBLE_11A,
67 HAL_RX_PREAMBLE_11B,
68 HAL_RX_PREAMBLE_11N,
69 HAL_RX_PREAMBLE_11AC,
70 HAL_RX_PREAMBLE_11AX,
71 HAL_RX_PREAMBLE_11BA,
72 HAL_RX_PREAMBLE_11BE,
73 HAL_RX_PREAMBLE_MAX,
74 };
75
76 enum hal_rx_reception_type {
77 HAL_RX_RECEPTION_TYPE_SU,
78 HAL_RX_RECEPTION_TYPE_MU_MIMO,
79 HAL_RX_RECEPTION_TYPE_MU_OFDMA,
80 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
81 HAL_RX_RECEPTION_TYPE_MAX,
82 };
83
84 enum hal_rx_legacy_rate {
85 HAL_RX_LEGACY_RATE_1_MBPS,
86 HAL_RX_LEGACY_RATE_2_MBPS,
87 HAL_RX_LEGACY_RATE_5_5_MBPS,
88 HAL_RX_LEGACY_RATE_6_MBPS,
89 HAL_RX_LEGACY_RATE_9_MBPS,
90 HAL_RX_LEGACY_RATE_11_MBPS,
91 HAL_RX_LEGACY_RATE_12_MBPS,
92 HAL_RX_LEGACY_RATE_18_MBPS,
93 HAL_RX_LEGACY_RATE_24_MBPS,
94 HAL_RX_LEGACY_RATE_36_MBPS,
95 HAL_RX_LEGACY_RATE_48_MBPS,
96 HAL_RX_LEGACY_RATE_54_MBPS,
97 HAL_RX_LEGACY_RATE_INVALID,
98 };
99
100 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
101 #define HAL_TLV_STATUS_PPDU_DONE 1
102 #define HAL_TLV_STATUS_BUF_DONE 2
103 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
104 #define HAL_RX_FCS_LEN 4
105
106 enum hal_rx_mon_status {
107 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
108 HAL_RX_MON_STATUS_PPDU_DONE,
109 HAL_RX_MON_STATUS_BUF_DONE,
110 HAL_RX_MON_STATUS_BUF_ADDR,
111 HAL_RX_MON_STATUS_MPDU_END,
112 HAL_RX_MON_STATUS_MSDU_END,
113 };
114
115 #define HAL_RX_MAX_MPDU 256
116 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5)
117
118 struct hal_rx_user_status {
119 u32 mcs:4,
120 nss:3,
121 ofdma_info_valid:1,
122 ul_ofdma_ru_start_index:7,
123 ul_ofdma_ru_width:7,
124 ul_ofdma_ru_size:8;
125 u32 ul_ofdma_user_v0_word0;
126 u32 ul_ofdma_user_v0_word1;
127 u32 ast_index;
128 u32 tid;
129 u16 tcp_msdu_count;
130 u16 tcp_ack_msdu_count;
131 u16 udp_msdu_count;
132 u16 other_msdu_count;
133 u16 frame_control;
134 u8 frame_control_info_valid;
135 u8 data_sequence_control_info_valid;
136 u16 first_data_seq_ctrl;
137 u32 preamble_type;
138 u16 ht_flags;
139 u16 vht_flags;
140 u16 he_flags;
141 u8 rs_flags;
142 u8 ldpc;
143 u32 mpdu_cnt_fcs_ok;
144 u32 mpdu_cnt_fcs_err;
145 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
146 u32 mpdu_ok_byte_count;
147 u32 mpdu_err_byte_count;
148 bool ampdu_present;
149 u16 ampdu_id;
150 };
151
152 #define HAL_MAX_UL_MU_USERS 37
153
154 struct hal_rx_u_sig_info {
155 bool ul_dl;
156 u8 bw;
157 u8 ppdu_type_comp_mode;
158 u8 eht_sig_mcs;
159 u8 num_eht_sig_sym;
160 struct ieee80211_radiotap_eht_usig usig;
161 };
162
163 #define HAL_RX_MON_MAX_AGGR_SIZE 128
164
165 struct hal_rx_tlv_aggr_info {
166 bool in_progress;
167 u16 cur_len;
168 u16 tlv_tag;
169 u8 buf[HAL_RX_MON_MAX_AGGR_SIZE];
170 };
171
172 struct hal_rx_radiotap_eht {
173 __le32 known;
174 __le32 data[9];
175 };
176
177 #define EHT_MAX_USER_INFO 4
178
179 struct hal_rx_eht_info {
180 u8 num_user_info;
181 struct hal_rx_radiotap_eht eht;
182 u32 user_info[EHT_MAX_USER_INFO];
183 };
184
185 struct hal_rx_mon_ppdu_info {
186 u32 ppdu_id;
187 u32 last_ppdu_id;
188 u64 ppdu_ts;
189 u32 num_mpdu_fcs_ok;
190 u32 num_mpdu_fcs_err;
191 u32 preamble_type;
192 u32 mpdu_len;
193 u16 chan_num;
194 u16 freq;
195 u16 tcp_msdu_count;
196 u16 tcp_ack_msdu_count;
197 u16 udp_msdu_count;
198 u16 other_msdu_count;
199 u16 peer_id;
200 u8 rate;
201 u8 mcs;
202 u8 nss;
203 u8 bw;
204 u8 vht_flag_values1;
205 u8 vht_flag_values2;
206 u8 vht_flag_values3[4];
207 u8 vht_flag_values4;
208 u8 vht_flag_values5;
209 u16 vht_flag_values6;
210 u8 is_stbc;
211 u8 gi;
212 u8 sgi;
213 u8 ldpc;
214 u8 beamformed;
215 u8 rssi_comb;
216 u16 tid;
217 u8 fc_valid;
218 u16 ht_flags;
219 u16 vht_flags;
220 u16 he_flags;
221 u16 he_mu_flags;
222 u8 dcm;
223 u8 ru_alloc;
224 u8 reception_type;
225 u64 tsft;
226 u64 rx_duration;
227 u16 frame_control;
228 u32 ast_index;
229 u8 rs_fcs_err;
230 u8 rs_flags;
231 u8 cck_flag;
232 u8 ofdm_flag;
233 u8 ulofdma_flag;
234 u8 frame_control_info_valid;
235 u16 he_per_user_1;
236 u16 he_per_user_2;
237 u8 he_per_user_position;
238 u8 he_per_user_known;
239 u16 he_flags1;
240 u16 he_flags2;
241 u8 he_RU[4];
242 u16 he_data1;
243 u16 he_data2;
244 u16 he_data3;
245 u16 he_data4;
246 u16 he_data5;
247 u16 he_data6;
248 u32 ppdu_len;
249 u32 prev_ppdu_id;
250 u32 device_id;
251 u16 first_data_seq_ctrl;
252 u8 monitor_direct_used;
253 u8 data_sequence_control_info_valid;
254 u8 ltf_size;
255 u8 rxpcu_filter_pass;
256 s8 rssi_chain[8][8];
257 u32 num_users;
258 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
259 u8 addr1[ETH_ALEN];
260 u8 addr2[ETH_ALEN];
261 u8 addr3[ETH_ALEN];
262 u8 addr4[ETH_ALEN];
263 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
264 u8 userid;
265 bool first_msdu_in_mpdu;
266 bool is_ampdu;
267 u8 medium_prot_type;
268 bool ppdu_continuation;
269 bool eht_usig;
270 struct hal_rx_u_sig_info u_sig_info;
271 bool is_eht;
272 struct hal_rx_eht_info eht_info;
273 struct hal_rx_tlv_aggr_info tlv_aggr;
274 };
275
276 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
277 #define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0)
278 #define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16)
279
280 struct hal_rx_ppdu_start {
281 __le32 info0;
282 __le32 info1;
283 __le32 ppdu_start_ts_31_0;
284 __le32 ppdu_start_ts_63_32;
285 __le32 rsvd[2];
286 } __packed;
287
288 #define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0)
289 #define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID GENMASK(15, 14)
290 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16)
291
292 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0)
293 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(11)
294 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(12)
295 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(13)
296 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21)
297
298 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
299 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
300
301 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
302
303 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
304 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
305
306 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
307 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
308
309 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
310 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
311
312 #define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
313 #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
314
315 struct hal_rx_ppdu_end_user_stats {
316 __le32 rsvd0[2];
317 __le32 info0;
318 __le32 info1;
319 __le32 info2;
320 __le32 info3;
321 __le32 ht_ctrl;
322 __le32 rsvd1[2];
323 __le32 info4;
324 __le32 info5;
325 __le32 usr_resp_ref;
326 __le32 info6;
327 __le32 rsvd3[4];
328 __le32 info7;
329 __le32 rsvd4;
330 __le32 info8;
331 __le32 rsvd5[2];
332 __le32 usr_resp_ref_ext;
333 __le32 rsvd6;
334 } __packed;
335
336 struct hal_rx_ppdu_end_user_stats_ext {
337 __le32 info0;
338 __le32 info1;
339 __le32 info2;
340 __le32 info3;
341 __le32 info4;
342 __le32 info5;
343 __le32 info6;
344 __le32 rsvd;
345 } __packed;
346
347 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
348 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
349
350 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
351 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
352 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
353
354 struct hal_rx_ht_sig_info {
355 __le32 info0;
356 __le32 info1;
357 } __packed;
358
359 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
360 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
361
362 struct hal_rx_lsig_b_info {
363 __le32 info0;
364 } __packed;
365
366 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
367 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
368 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
369
370 struct hal_rx_lsig_a_info {
371 __le32 info0;
372 } __packed;
373
374 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
375 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
376 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
377 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
378
379 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
380 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
381 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
382 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
383
384 struct hal_rx_vht_sig_a_info {
385 __le32 info0;
386 __le32 info1;
387 } __packed;
388
389 enum hal_rx_vht_sig_a_gi_setting {
390 HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
391 HAL_RX_VHT_SIG_A_SHORT_GI = 1,
392 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
393 };
394
395 #define HE_GI_0_8 0
396 #define HE_GI_0_4 1
397 #define HE_GI_1_6 2
398 #define HE_GI_3_2 3
399
400 #define HE_LTF_1_X 0
401 #define HE_LTF_2_X 1
402 #define HE_LTF_4_X 2
403
404 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
405 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
406 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
407 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
408 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
409 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
410 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
411 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
412 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
413 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
414
415 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
416 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
417 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
418 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
419 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
420 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
421 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
422 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
423
424 struct hal_rx_he_sig_a_su_info {
425 __le32 info0;
426 __le32 info1;
427 } __packed;
428
429 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1)
430 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1)
431 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4)
432 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)
433 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11)
434 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15)
435 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
436 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22)
437 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23)
438 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25)
439
440 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0)
441 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
442 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11)
443 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12)
444 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
445 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15)
446
447 struct hal_rx_he_sig_a_mu_dl_info {
448 __le32 info0;
449 __le32 info1;
450 } __packed;
451
452 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
453
454 struct hal_rx_he_sig_b1_mu_info {
455 __le32 info0;
456 } __packed;
457
458 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
459 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
460 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
461 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
462
463 struct hal_rx_he_sig_b2_mu_info {
464 __le32 info0;
465 } __packed;
466
467 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
468 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
469 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(14)
470 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
471 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
472 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
473
474 struct hal_rx_he_sig_b2_ofdma_info {
475 __le32 info0;
476 } __packed;
477
478 enum hal_rx_ul_reception_type {
479 HAL_RECEPTION_TYPE_ULOFMDA,
480 HAL_RECEPTION_TYPE_ULMIMO,
481 HAL_RECEPTION_TYPE_OTHER,
482 HAL_RECEPTION_TYPE_FRAMELESS
483 };
484
485 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0)
486 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5)
487 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)
488
489 struct hal_rx_phyrx_rssi_legacy_info {
490 __le32 info0;
491 __le32 rsvd0[39];
492 __le32 info1;
493 __le32 rsvd1;
494 } __packed;
495
496 #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16)
497 #define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16)
498 #define HAL_RX_MPDU_START_INFO1_DEVICE_ID GENMASK(31, 30)
499 #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0)
500 struct hal_rx_mpdu_start {
501 __le32 rsvd0[9];
502 __le32 info0;
503 __le32 info1;
504 __le32 rsvd1[2];
505 __le32 info2;
506 __le32 rsvd2[16];
507 } __packed;
508
509 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
510 struct hal_rx_ppdu_end_duration {
511 __le32 rsvd0[9];
512 __le32 info0;
513 __le32 rsvd1[18];
514 } __packed;
515
516 struct hal_rx_rxpcu_classification_overview {
517 u32 rsvd0;
518 } __packed;
519
520 struct hal_rx_msdu_desc_info {
521 u32 msdu_flags;
522 u16 msdu_len; /* 14 bits for length */
523 };
524
525 #define HAL_RX_NUM_MSDU_DESC 6
526 struct hal_rx_msdu_list {
527 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
528 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
529 u8 rbm[HAL_RX_NUM_MSDU_DESC];
530 };
531
532 #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0)
533 #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0)
534 #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16)
535 #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0)
536
537 struct hal_rx_frame_bitmap_ack {
538 __le32 reserved;
539 __le32 info0;
540 __le32 info1;
541 __le32 info2;
542 __le32 reserved1[10];
543 } __packed;
544
545 #define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0)
546 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16)
547 #define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0)
548 #define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21)
549 #define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25)
550 #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27)
551 #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28)
552 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29)
553 #define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0)
554 #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0)
555 #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0)
556 #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16)
557 #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0)
558
559 struct hal_rx_resp_req_info {
560 __le32 info0;
561 __le32 reserved[1];
562 __le32 info1;
563 __le32 info2;
564 __le32 reserved1[2];
565 __le32 info3;
566 __le32 info4;
567 __le32 info5;
568 __le32 reserved2[5];
569 } __packed;
570
571 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
572 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
573 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
574 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
575
576 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30)
577 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31)
578 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0)
579 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3)
580 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7)
581 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8)
582 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9)
583 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16)
584
585 /* HE Radiotap data1 Mask */
586 #define HE_SU_FORMAT_TYPE 0x0000
587 #define HE_EXT_SU_FORMAT_TYPE 0x0001
588 #define HE_MU_FORMAT_TYPE 0x0002
589 #define HE_TRIG_FORMAT_TYPE 0x0003
590 #define HE_BEAM_CHANGE_KNOWN 0x0008
591 #define HE_DL_UL_KNOWN 0x0010
592 #define HE_MCS_KNOWN 0x0020
593 #define HE_DCM_KNOWN 0x0040
594 #define HE_CODING_KNOWN 0x0080
595 #define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
596 #define HE_STBC_KNOWN 0x0200
597 #define HE_DATA_BW_RU_KNOWN 0x4000
598 #define HE_DOPPLER_KNOWN 0x8000
599 #define HE_BSS_COLOR_KNOWN 0x0004
600
601 /* HE Radiotap data2 Mask */
602 #define HE_GI_KNOWN 0x0002
603 #define HE_TXBF_KNOWN 0x0010
604 #define HE_PE_DISAMBIGUITY_KNOWN 0x0020
605 #define HE_TXOP_KNOWN 0x0040
606 #define HE_LTF_SYMBOLS_KNOWN 0x0004
607 #define HE_PRE_FEC_PADDING_KNOWN 0x0008
608 #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
609
610 /* HE radiotap data3 shift values */
611 #define HE_BEAM_CHANGE_SHIFT 6
612 #define HE_DL_UL_SHIFT 7
613 #define HE_TRANSMIT_MCS_SHIFT 8
614 #define HE_DCM_SHIFT 12
615 #define HE_CODING_SHIFT 13
616 #define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
617 #define HE_STBC_SHIFT 15
618
619 /* HE radiotap data4 shift values */
620 #define HE_STA_ID_SHIFT 4
621
622 /* HE radiotap data5 */
623 #define HE_GI_SHIFT 4
624 #define HE_LTF_SIZE_SHIFT 6
625 #define HE_LTF_SYM_SHIFT 8
626 #define HE_TXBF_SHIFT 14
627 #define HE_PE_DISAMBIGUITY_SHIFT 15
628 #define HE_PRE_FEC_PAD_SHIFT 12
629
630 /* HE radiotap data6 */
631 #define HE_DOPPLER_SHIFT 4
632 #define HE_TXOP_SHIFT 8
633
634 /* HE radiotap HE-MU flags1 */
635 #define HE_SIG_B_MCS_KNOWN 0x0010
636 #define HE_SIG_B_DCM_KNOWN 0x0040
637 #define HE_SIG_B_SYM_NUM_KNOWN 0x8000
638 #define HE_RU_0_KNOWN 0x0100
639 #define HE_RU_1_KNOWN 0x0200
640 #define HE_RU_2_KNOWN 0x0400
641 #define HE_RU_3_KNOWN 0x0800
642 #define HE_DCM_FLAG_1_SHIFT 5
643 #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
644 #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
645
646 /* HE radiotap HE-MU flags2 */
647 #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
648 #define HE_BW_KNOWN 0x0004
649 #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
650 #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
651 #define HE_NUM_SIG_B_FLAG_2_SHIFT 9
652 #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
653 #define HE_LTF_KNOWN 0x8000
654
655 /* HE radiotap per_user_1 */
656 #define HE_STA_SPATIAL_SHIFT 11
657 #define HE_TXBF_SHIFT 14
658 #define HE_RESERVED_SET_TO_1_SHIFT 19
659 #define HE_STA_CODING_SHIFT 20
660
661 /* HE radiotap per_user_2 */
662 #define HE_STA_MCS_SHIFT 4
663 #define HE_STA_DCM_SHIFT 5
664
665 /* HE radiotap per user known */
666 #define HE_USER_FIELD_POSITION_KNOWN 0x01
667 #define HE_STA_ID_PER_USER_KNOWN 0x02
668 #define HE_STA_NSTS_KNOWN 0x04
669 #define HE_STA_TX_BF_KNOWN 0x08
670 #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
671 #define HE_STA_MCS_KNOWN 0x20
672 #define HE_STA_DCM_KNOWN 0x40
673 #define HE_STA_CODING_KNOWN 0x80
674
675 #define HAL_RX_MPDU_ERR_FCS BIT(0)
676 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
677 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
678 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
679 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
680 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
681 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
682 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
683
684 #define HAL_RX_PHY_CMN_USER_INFO0_GI GENMASK(17, 16)
685
686 struct hal_phyrx_common_user_info {
687 __le32 rsvd[2];
688 __le32 info0;
689 __le32 rsvd1;
690 } __packed;
691
692 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE GENMASK(3, 0)
693 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_GI_LTF GENMASK(5, 4)
694 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM GENMASK(8, 6)
695 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS GENMASK(10, 7)
696 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED BIT(11)
697 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD GENMASK(13, 12)
698 #define HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC GENMASK(17, 14)
699
700 struct hal_eht_sig_ndp_cmn_eb {
701 __le32 info0;
702 } __packed;
703
704 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE GENMASK(3, 0)
705 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_GI_LTF GENMASK(5, 4)
706 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM GENMASK(8, 6)
707 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM BIT(9)
708 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)
709 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY BIT(12)
710 #define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD GENMASK(16, 13)
711
712 struct hal_eht_sig_usig_overflow {
713 __le32 info0;
714 } __packed;
715
716 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)
717 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)
718 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_VALIDATE BIT(15)
719 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS GENMASK(19, 16)
720 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED BIT(20)
721 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING BIT(21)
722 #define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CRC GENMASK(25, 22)
723
724 struct hal_eht_sig_non_mu_mimo {
725 __le32 info0;
726 } __packed;
727
728 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)
729 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)
730 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING BIT(15)
731 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING GENMASK(22, 16)
732 #define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CRC GENMASK(26, 23)
733
734 struct hal_eht_sig_mu_mimo {
735 __le32 info0;
736 } __packed;
737
738 union hal_eht_sig_user_field {
739 struct hal_eht_sig_mu_mimo mu_mimo;
740 struct hal_eht_sig_non_mu_mimo n_mu_mimo;
741 };
742
743 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_SPATIAL_REUSE GENMASK(3, 0)
744 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_GI_LTF GENMASK(5, 4)
745 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_LTF_SYM GENMASK(8, 6)
746 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_LDPC_EXTA_SYM BIT(9)
747 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)
748 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISAMBIGUITY BIT(12)
749 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISREGARD GENMASK(16, 13)
750 #define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS GENMASK(19, 17)
751
752 struct hal_eht_sig_non_ofdma_cmn_eb {
753 __le32 info0;
754 union hal_eht_sig_user_field user_field;
755 } __packed;
756
757 #define HAL_RX_EHT_SIG_OFDMA_EB1_SPATIAL_REUSE GENMASK_ULL(3, 0)
758 #define HAL_RX_EHT_SIG_OFDMA_EB1_GI_LTF GENMASK_ULL(5, 4)
759 #define HAL_RX_EHT_SIG_OFDMA_EB1_NUM_LFT_SYM GENMASK_ULL(8, 6)
760 #define HAL_RX_EHT_SIG_OFDMA_EB1_LDPC_EXTRA_SYM BIT(9)
761 #define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_FEC_PAD_FACTOR GENMASK_ULL(11, 10)
762 #define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_DISAMBIGUITY BIT(12)
763 #define HAL_RX_EHT_SIG_OFDMA_EB1_DISREGARD GENMASK_ULL(16, 13)
764 #define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1 GENMASK_ULL(25, 17)
765 #define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2 GENMASK_ULL(34, 26)
766 #define HAL_RX_EHT_SIG_OFDMA_EB1_CRC GENMASK_ULL(30, 27)
767
768 struct hal_eht_sig_ofdma_cmn_eb1 {
769 __le64 info0;
770 } __packed;
771
772 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1 GENMASK_ULL(8, 0)
773 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2 GENMASK_ULL(17, 9)
774 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3 GENMASK_ULL(26, 18)
775 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4 GENMASK_ULL(35, 27)
776 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5 GENMASK_ULL(44, 36)
777 #define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6 GENMASK_ULL(53, 45)
778 #define HAL_RX_EHT_SIG_OFDMA_EB2_MCS GNEMASK_ULL(57, 54)
779
780 struct hal_eht_sig_ofdma_cmn_eb2 {
781 __le64 info0;
782 } __packed;
783
784 struct hal_eht_sig_ofdma_cmn_eb {
785 struct hal_eht_sig_ofdma_cmn_eb1 eb1;
786 struct hal_eht_sig_ofdma_cmn_eb2 eb2;
787 union hal_eht_sig_user_field user_field;
788 } __packed;
789
790 enum hal_eht_bw {
791 HAL_EHT_BW_20,
792 HAL_EHT_BW_40,
793 HAL_EHT_BW_80,
794 HAL_EHT_BW_160,
795 HAL_EHT_BW_320_1,
796 HAL_EHT_BW_320_2,
797 };
798
799 #define HAL_RX_USIG_CMN_INFO0_PHY_VERSION GENMASK(2, 0)
800 #define HAL_RX_USIG_CMN_INFO0_BW GENMASK(5, 3)
801 #define HAL_RX_USIG_CMN_INFO0_UL_DL BIT(6)
802 #define HAL_RX_USIG_CMN_INFO0_BSS_COLOR GENMASK(12, 7)
803 #define HAL_RX_USIG_CMN_INFO0_TXOP GENMASK(19, 13)
804 #define HAL_RX_USIG_CMN_INFO0_DISREGARD GENMASK(25, 20)
805 #define HAL_RX_USIG_CMN_INFO0_VALIDATE BIT(26)
806
807 struct hal_mon_usig_cmn {
808 __le32 info0;
809 } __packed;
810
811 #define HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)
812 #define HAL_RX_USIG_TB_INFO0_VALIDATE BIT(2)
813 #define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1 GENMASK(6, 3)
814 #define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2 GENMASK(10, 7)
815 #define HAL_RX_USIG_TB_INFO0_DISREGARD_1 GENMASK(15, 11)
816 #define HAL_RX_USIG_TB_INFO0_CRC GENMASK(19, 16)
817 #define HAL_RX_USIG_TB_INFO0_TAIL GENMASK(25, 20)
818 #define HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS BIT(31)
819
820 struct hal_mon_usig_tb {
821 __le32 info0;
822 } __packed;
823
824 #define HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)
825 #define HAL_RX_USIG_MU_INFO0_VALIDATE_1 BIT(2)
826 #define HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO GENMASK(7, 3)
827 #define HAL_RX_USIG_MU_INFO0_VALIDATE_2 BIT(8)
828 #define HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS GENMASK(10, 9)
829 #define HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM GENMASK(15, 11)
830 #define HAL_RX_USIG_MU_INFO0_CRC GENMASK(20, 16)
831 #define HAL_RX_USIG_MU_INFO0_TAIL GENMASK(26, 21)
832 #define HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS BIT(31)
833
834 struct hal_mon_usig_mu {
835 __le32 info0;
836 } __packed;
837
838 union hal_mon_usig_non_cmn {
839 struct hal_mon_usig_tb tb;
840 struct hal_mon_usig_mu mu;
841 };
842
843 struct hal_mon_usig_hdr {
844 struct hal_mon_usig_cmn cmn;
845 union hal_mon_usig_non_cmn non_cmn;
846 } __packed;
847
848 #define HAL_RX_USR_INFO0_PHY_PPDU_ID GENMASK(15, 0)
849 #define HAL_RX_USR_INFO0_USR_RSSI GENMASK(23, 16)
850 #define HAL_RX_USR_INFO0_PKT_TYPE GENMASK(27, 24)
851 #define HAL_RX_USR_INFO0_STBC BIT(28)
852 #define HAL_RX_USR_INFO0_RECEPTION_TYPE GENMASK(31, 29)
853
854 #define HAL_RX_USR_INFO1_MCS GENMASK(3, 0)
855 #define HAL_RX_USR_INFO1_SGI GENMASK(5, 4)
856 #define HAL_RX_USR_INFO1_HE_RANGING_NDP BIT(6)
857 #define HAL_RX_USR_INFO1_MIMO_SS_BITMAP GENMASK(15, 8)
858 #define HAL_RX_USR_INFO1_RX_BW GENMASK(18, 16)
859 #define HAL_RX_USR_INFO1_DL_OFMDA_USR_IDX GENMASK(31, 24)
860
861 #define HAL_RX_USR_INFO2_DL_OFDMA_CONTENT_CHAN BIT(0)
862 #define HAL_RX_USR_INFO2_NSS GENMASK(10, 8)
863 #define HAL_RX_USR_INFO2_STREAM_OFFSET GENMASK(13, 11)
864 #define HAL_RX_USR_INFO2_STA_DCM BIT(14)
865 #define HAL_RX_USR_INFO2_LDPC BIT(15)
866 #define HAL_RX_USR_INFO2_RU_TYPE_80_0 GENMASK(19, 16)
867 #define HAL_RX_USR_INFO2_RU_TYPE_80_1 GENMASK(23, 20)
868 #define HAL_RX_USR_INFO2_RU_TYPE_80_2 GENMASK(27, 24)
869 #define HAL_RX_USR_INFO2_RU_TYPE_80_3 GENMASK(31, 28)
870
871 #define HAL_RX_USR_INFO3_RU_START_IDX_80_0 GENMASK(5, 0)
872 #define HAL_RX_USR_INFO3_RU_START_IDX_80_1 GENMASK(13, 8)
873 #define HAL_RX_USR_INFO3_RU_START_IDX_80_2 GENMASK(21, 16)
874 #define HAL_RX_USR_INFO3_RU_START_IDX_80_3 GENMASK(29, 24)
875
876 struct hal_receive_user_info {
877 __le32 info0;
878 __le32 info1;
879 __le32 info2;
880 __le32 info3;
881 __le32 user_fd_rssi_seg0;
882 __le32 user_fd_rssi_seg1;
883 __le32 user_fd_rssi_seg2;
884 __le32 user_fd_rssi_seg3;
885 } __packed;
886
887 enum hal_mon_reception_type {
888 HAL_RECEPTION_TYPE_SU,
889 HAL_RECEPTION_TYPE_DL_MU_MIMO,
890 HAL_RECEPTION_TYPE_DL_MU_OFMA,
891 HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
892 HAL_RECEPTION_TYPE_UL_MU_MIMO,
893 HAL_RECEPTION_TYPE_UL_MU_OFDMA,
894 HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
895 };
896
897 /* Different allowed RU in 11BE */
898 #define HAL_EHT_RU_26 0ULL
899 #define HAL_EHT_RU_52 1ULL
900 #define HAL_EHT_RU_78 2ULL
901 #define HAL_EHT_RU_106 3ULL
902 #define HAL_EHT_RU_132 4ULL
903 #define HAL_EHT_RU_242 5ULL
904 #define HAL_EHT_RU_484 6ULL
905 #define HAL_EHT_RU_726 7ULL
906 #define HAL_EHT_RU_996 8ULL
907 #define HAL_EHT_RU_996x2 9ULL
908 #define HAL_EHT_RU_996x3 10ULL
909 #define HAL_EHT_RU_996x4 11ULL
910 #define HAL_EHT_RU_NONE 15ULL
911 #define HAL_EHT_RU_INVALID 31ULL
912 /* MRUs spanning above 80Mhz
913 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved)
914 */
915 #define HAL_EHT_RU_996_484 18ULL
916 #define HAL_EHT_RU_996x2_484 28ULL
917 #define HAL_EHT_RU_996x3_484 40ULL
918 #define HAL_EHT_RU_996_484_242 23ULL
919
920 #define NUM_RU_BITS_PER80 16
921 #define NUM_RU_BITS_PER20 4
922
923 /* Different per_80Mhz band in 320Mhz bandwidth */
924 #define HAL_80_0 0
925 #define HAL_80_1 1
926 #define HAL_80_2 2
927 #define HAL_80_3 3
928
929 #define HAL_RU_80MHZ(num_band) ((num_band) * NUM_RU_BITS_PER80)
930 #define HAL_RU_20MHZ(idx_per_80) ((idx_per_80) * NUM_RU_BITS_PER20)
931
932 #define HAL_RU_SHIFT(num_band, idx_per_80) \
933 (HAL_RU_80MHZ(num_band) + HAL_RU_20MHZ(idx_per_80))
934
935 #define HAL_RU(ru, num_band, idx_per_80) \
936 ((u64)(ru) << HAL_RU_SHIFT(num_band, idx_per_80))
937
938 /* MRU-996+484 */
939 #define HAL_EHT_RU_996_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
940 HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
941 #define HAL_EHT_RU_996_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
942 HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
943 #define HAL_EHT_RU_996_484_2 (HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) | \
944 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1))
945 #define HAL_EHT_RU_996_484_3 (HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) | \
946 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0))
947 #define HAL_EHT_RU_996_484_4 (HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
948 HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
949 #define HAL_EHT_RU_996_484_5 (HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
950 HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
951 #define HAL_EHT_RU_996_484_6 (HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) | \
952 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
953 #define HAL_EHT_RU_996_484_7 (HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) | \
954 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
955
956 /* MRU-996x2+484 */
957 #define HAL_EHT_RU_996x2_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
958 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
959 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
960 #define HAL_EHT_RU_996x2_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
961 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
962 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
963 #define HAL_EHT_RU_996x2_484_2 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
964 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
965 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
966 #define HAL_EHT_RU_996x2_484_3 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
967 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
968 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
969 #define HAL_EHT_RU_996x2_484_4 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
970 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
971 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1))
972 #define HAL_EHT_RU_996x2_484_5 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
973 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
974 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0))
975 #define HAL_EHT_RU_996x2_484_6 (HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
976 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
977 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
978 #define HAL_EHT_RU_996x2_484_7 (HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
979 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
980 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
981 #define HAL_EHT_RU_996x2_484_8 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
982 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
983 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
984 #define HAL_EHT_RU_996x2_484_9 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
985 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
986 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
987 #define HAL_EHT_RU_996x2_484_10 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
988 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
989 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
990 #define HAL_EHT_RU_996x2_484_11 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
991 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
992 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
993
994 /* MRU-996x3+484 */
995 #define HAL_EHT_RU_996x3_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
996 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
997 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
998 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
999 #define HAL_EHT_RU_996x3_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
1000 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1001 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1002 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1003 #define HAL_EHT_RU_996x3_484_2 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1004 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
1005 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1006 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1007 #define HAL_EHT_RU_996x3_484_3 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1008 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
1009 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1010 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1011 #define HAL_EHT_RU_996x3_484_4 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1012 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1013 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
1014 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1015 #define HAL_EHT_RU_996x3_484_5 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1016 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1017 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
1018 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1019 #define HAL_EHT_RU_996x3_484_6 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1020 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1021 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1022 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
1023 #define HAL_EHT_RU_996x3_484_7 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
1024 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
1025 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
1026 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
1027
1028 #define HAL_RU_PER80(ru_per80, num_80mhz, ru_idx_per80mhz) \
1029 (HAL_RU(ru_per80, num_80mhz, ru_idx_per80mhz))
1030
1031 #define RU_INVALID 0
1032 #define RU_26 1
1033 #define RU_52 2
1034 #define RU_106 4
1035 #define RU_242 9
1036 #define RU_484 18
1037 #define RU_996 37
1038 #define RU_2X996 74
1039 #define RU_3X996 111
1040 #define RU_4X996 148
1041 #define RU_52_26 (RU_52 + RU_26)
1042 #define RU_106_26 (RU_106 + RU_26)
1043 #define RU_484_242 (RU_484 + RU_242)
1044 #define RU_996_484 (RU_996 + RU_484)
1045 #define RU_996_484_242 (RU_996 + RU_484_242)
1046 #define RU_2X996_484 (RU_2X996 + RU_484)
1047 #define RU_3X996_484 (RU_3X996 + RU_484)
1048
1049 enum ath12k_eht_ru_size {
1050 ATH12K_EHT_RU_26,
1051 ATH12K_EHT_RU_52,
1052 ATH12K_EHT_RU_106,
1053 ATH12K_EHT_RU_242,
1054 ATH12K_EHT_RU_484,
1055 ATH12K_EHT_RU_996,
1056 ATH12K_EHT_RU_996x2,
1057 ATH12K_EHT_RU_996x4,
1058 ATH12K_EHT_RU_52_26,
1059 ATH12K_EHT_RU_106_26,
1060 ATH12K_EHT_RU_484_242,
1061 ATH12K_EHT_RU_996_484,
1062 ATH12K_EHT_RU_996_484_242,
1063 ATH12K_EHT_RU_996x2_484,
1064 ATH12K_EHT_RU_996x3,
1065 ATH12K_EHT_RU_996x3_484,
1066
1067 /* Keep last */
1068 ATH12K_EHT_RU_INVALID,
1069 };
1070
1071 #define HAL_RX_RU_ALLOC_TYPE_MAX ATH12K_EHT_RU_INVALID
1072
1073 static inline
ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)1074 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
1075 {
1076 enum nl80211_he_ru_alloc ret;
1077
1078 switch (ru_tones) {
1079 case RU_52:
1080 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
1081 break;
1082 case RU_106:
1083 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
1084 break;
1085 case RU_242:
1086 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
1087 break;
1088 case RU_484:
1089 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
1090 break;
1091 case RU_996:
1092 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
1093 break;
1094 case RU_2X996:
1095 ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
1096 break;
1097 case RU_26:
1098 fallthrough;
1099 default:
1100 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
1101 break;
1102 }
1103 return ret;
1104 }
1105
1106 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
1107 struct hal_tlv_64_hdr *tlv,
1108 struct hal_reo_status *status);
1109 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
1110 struct hal_tlv_64_hdr *tlv,
1111 struct hal_reo_status *status);
1112 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
1113 struct hal_tlv_64_hdr *tlv,
1114 struct hal_reo_status *status);
1115 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
1116 struct hal_tlv_64_hdr *tlv,
1117 struct hal_reo_status *status);
1118 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
1119 struct hal_tlv_64_hdr *tlv,
1120 struct hal_reo_status *status);
1121 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
1122 struct hal_tlv_64_hdr *tlv,
1123 struct hal_reo_status *status);
1124 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
1125 struct hal_tlv_64_hdr *tlv,
1126 struct hal_reo_status *status);
1127 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
1128 u32 *msdu_cookies,
1129 enum hal_rx_buf_return_buf_manager *rbm);
1130 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
1131 struct hal_wbm_release_ring *dst_desc,
1132 struct hal_wbm_release_ring *src_desc,
1133 enum hal_wbm_rel_bm_act action);
1134 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
1135 dma_addr_t paddr, u32 cookie, u8 manager);
1136 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
1137 dma_addr_t *paddr,
1138 u32 *cookie, u8 *rbm);
1139 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
1140 struct hal_reo_dest_ring *desc,
1141 dma_addr_t *paddr, u32 *desc_bank);
1142 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
1143 struct hal_rx_wbm_rel_info *rel_info);
1144 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
1145 struct ath12k_buffer_addr *buff_addr,
1146 dma_addr_t *paddr, u32 *cookie);
1147
1148 #endif
1149