xref: /linux/drivers/gpu/drm/xe/regs/xe_gt_regs.h (revision de848da12f752170c2ebe114804a985314fd5a6a)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef _XE_GT_REGS_H_
7 #define _XE_GT_REGS_H_
8 
9 #include "regs/xe_reg_defs.h"
10 
11 /*
12  * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
13  * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically
14  * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
15  */
16 #define MEDIA_GT_GSI_OFFSET				0x380000
17 #define MEDIA_GT_GSI_LENGTH				0x40000
18 
19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
20 #define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)
21 #define   MTL_CAGF_MASK					REG_GENMASK(8, 0)
22 #define   MTL_CC_MASK					REG_GENMASK(12, 9)
23 
24 /* RPM unit config (Gen8+) */
25 #define RPM_CONFIG0					XE_REG(0xd00)
26 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
27 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0
28 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
29 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
30 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3
31 #define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
32 
33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)
34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)
35 #define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)
36 
37 #define GMD_ID					XE_REG(0xd8c)
38 #define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
39 #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
40 #define   GMD_ID_REVID				REG_GENMASK(5, 0)
41 
42 #define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
43 #define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)
44 
45 #define MCFG_MCR_SELECTOR			XE_REG(0xfd0)
46 #define MTL_MCR_SELECTOR			XE_REG(0xfd4)
47 #define SF_MCR_SELECTOR				XE_REG(0xfd8)
48 #define MCR_SELECTOR				XE_REG(0xfdc)
49 #define GAM_MCR_SELECTOR			XE_REG(0xfe0)
50 #define   MCR_MULTICAST				REG_BIT(31)
51 #define   MCR_SLICE_MASK			REG_GENMASK(30, 27)
52 #define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
53 #define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
54 #define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
55 #define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
56 #define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
57 
58 #define PS_INVOCATION_COUNT			XE_REG(0x2348)
59 
60 #define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)
61 #define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)
62 #define   LE_SSE_MASK				REG_GENMASK(18, 17)
63 #define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
64 #define   LE_COS_MASK				REG_GENMASK(16, 15)
65 #define   LE_COS(value)				REG_FIELD_PREP(LE_COS_MASK)
66 #define   LE_SCF_MASK				REG_BIT(14)
67 #define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
68 #define   LE_PFM_MASK				REG_GENMASK(13, 11)
69 #define   LE_PFM(value)				REG_FIELD_PREP(LE_PFM_MASK, value)
70 #define   LE_SCC_MASK				REG_GENMASK(10, 8)
71 #define   LE_SCC(value)				REG_FIELD_PREP(LE_SCC_MASK, value)
72 #define   LE_RSC_MASK				REG_BIT(7)
73 #define   LE_RSC(value)				REG_FIELD_PREP(LE_RSC_MASK, value)
74 #define   LE_AOM_MASK				REG_BIT(6)
75 #define   LE_AOM(value)				REG_FIELD_PREP(LE_AOM_MASK, value)
76 #define   LE_LRUM_MASK				REG_GENMASK(5, 4)
77 #define   LE_LRUM(value)			REG_FIELD_PREP(LE_LRUM_MASK, value)
78 #define   LE_TGT_CACHE_MASK			REG_GENMASK(3, 2)
79 #define   LE_TGT_CACHE(value)			REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
80 #define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
81 #define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
82 
83 #define STATELESS_COMPRESSION_CTRL		XE_REG_MCR(0x4148)
84 #define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)
85 
86 #define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)
87 #define   CG_DIS_CNTLBUS			REG_BIT(6)
88 
89 #define CCS_AUX_INV				XE_REG(0x4208)
90 
91 #define VD0_AUX_INV				XE_REG(0x4218)
92 #define VE0_AUX_INV				XE_REG(0x4238)
93 
94 #define VE1_AUX_INV				XE_REG(0x42b8)
95 #define   AUX_INV				REG_BIT(0)
96 
97 #define XE2_LMEM_CFG				XE_REG(0x48b0)
98 
99 #define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)
100 #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
101 #define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
102 
103 #define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
104 #define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
105 
106 #define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
107 #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
108 #define   DIS_CLIP_NEGATIVE_BOUNDING_BOX	REG_BIT(6)
109 
110 #define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
111 #define   TBIMR_FAST_CLIP			REG_BIT(5)
112 
113 #define FF_MODE					XE_REG_MCR(0x6210)
114 #define   DIS_TE_AUTOSTRIP			REG_BIT(31)
115 #define   VS_HIT_MAX_VALUE_MASK			REG_GENMASK(25, 20)
116 #define   DIS_MESH_PARTIAL_AUTOSTRIP		REG_BIT(16)
117 #define   DIS_MESH_AUTOSTRIP			REG_BIT(15)
118 
119 #define VFLSKPD					XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
120 #define   DIS_PARTIAL_AUTOSTRIP			REG_BIT(9)
121 #define   DIS_AUTOSTRIP				REG_BIT(6)
122 #define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
123 #define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
124 
125 #define FF_MODE2				XE_REG(0x6604)
126 #define XEHP_FF_MODE2				XE_REG_MCR(0x6604)
127 #define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)
128 #define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
129 #define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)
130 #define   FF_MODE2_TDS_TIMER_128		REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
131 
132 #define XEHPG_INSTDONE_GEOM_SVGUNIT		XE_REG_MCR(0x666c)
133 
134 #define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)
135 #define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)
136 
137 #define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)
138 #define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)
139 
140 #define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)
141 #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
142 #define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE		REG_BIT(13)
143 
144 #define XEHP_PSS_MODE2				XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
145 #define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)
146 
147 #define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
148 #define   FLSH_IGNORES_PSD			REG_BIT(10)
149 #define   FD_END_COLLECT			REG_BIT(5)
150 
151 #define SC_INSTDONE				XE_REG(0x7100)
152 #define SC_INSTDONE_EXTRA			XE_REG(0x7104)
153 #define SC_INSTDONE_EXTRA2			XE_REG(0x7108)
154 
155 #define XEHPG_SC_INSTDONE			XE_REG_MCR(0x7100)
156 #define XEHPG_SC_INSTDONE_EXTRA			XE_REG_MCR(0x7104)
157 #define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)
158 
159 #define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)
160 #define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
161 
162 #define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)
163 #define XEHP_COMMON_SLICE_CHICKEN3			XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)
164 #define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
165 #define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)
166 #define   BLEND_EMB_FIX_DISABLE_IN_RCC			REG_BIT(11)
167 #define   DISABLE_CPS_AWARE_COLOR_PIPE			REG_BIT(9)
168 
169 #define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
170 #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)
171 
172 #define VF_PREEMPTION				XE_REG(0x83a4, XE_REG_OPTION_MASKED)
173 #define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)
174 
175 #define VF_SCRATCHPAD				XE_REG(0x83a8, XE_REG_OPTION_MASKED)
176 #define   XE2_VFG_TED_CREDIT_INTERFACE_DISABLE	REG_BIT(13)
177 
178 #define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4, XE_REG_OPTION_MASKED)
179 #define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)
180 
181 #define SQCNT1					XE_REG_MCR(0x8718)
182 #define XELPMP_SQCNT1				XE_REG(0x8718)
183 #define   SQCNT1_PMON_ENABLE			REG_BIT(30)
184 #define   SQCNT1_OABPC				REG_BIT(29)
185 #define   ENFORCE_RAR				REG_BIT(23)
186 
187 #define XEHP_SQCM				XE_REG_MCR(0x8724)
188 #define   EN_32B_ACCESS				REG_BIT(30)
189 
190 #define XE2_FLAT_CCS_BASE_RANGE_LOWER		XE_REG_MCR(0x8800)
191 #define   XE2_FLAT_CCS_ENABLE			REG_BIT(0)
192 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK	REG_GENMASK(31, 6)
193 
194 #define XE2_FLAT_CCS_BASE_RANGE_UPPER		XE_REG_MCR(0x8804)
195 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK	REG_GENMASK(7, 0)
196 
197 #define GSCPSMI_BASE				XE_REG(0x880c)
198 
199 #define CCCHKNREG1				XE_REG_MCR(0x8828)
200 #define   L3CMPCTRL				REG_BIT(23)
201 #define   ENCOMPPERFFIX				REG_BIT(18)
202 
203 /* Fuse readout registers for GT */
204 #define XEHP_FUSE4				XE_REG(0x9114)
205 #define   CFEG_WMTP_DISABLE			REG_BIT(20)
206 #define   CCS_EN_MASK				REG_GENMASK(19, 16)
207 #define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
208 
209 #define	MIRROR_FUSE3				XE_REG(0x9118)
210 #define   XE2_NODE_ENABLE_MASK			REG_GENMASK(31, 16)
211 #define   L3BANK_PAIR_COUNT			4
212 #define   XEHPC_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
213 #define   XE2_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
214 #define   L3BANK_MASK				REG_GENMASK(3, 0)
215 #define   XELP_GT_L3_MODE_MASK			REG_GENMASK(7, 0)
216 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */
217 #define   MAX_MSLICES				4
218 #define   MEML3_EN_MASK				REG_GENMASK(3, 0)
219 
220 #define MIRROR_FUSE1				XE_REG(0x911c)
221 
222 #define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */
223 #define   XELP_EU_MASK				REG_GENMASK(7, 0)
224 #define XELP_GT_SLICE_ENABLE			XE_REG(0x9138)
225 #define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
226 
227 #define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)
228 #define   GT_VEBOX_DISABLE_MASK			REG_GENMASK(19, 16)
229 #define   GT_VDBOX_DISABLE_MASK			REG_GENMASK(7, 0)
230 
231 #define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)
232 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)
233 #define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)
234 #define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
235 #define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
236 
237 #define GDRST					XE_REG(0x941c)
238 #define   GRDOM_GUC				REG_BIT(3)
239 #define   GRDOM_FULL				REG_BIT(0)
240 
241 #define MISCCPCTL				XE_REG(0x9424)
242 #define   DOP_CLOCK_GATE_RENDER_ENABLE		REG_BIT(1)
243 
244 #define UNSLCGCTL9430				XE_REG(0x9430)
245 #define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)
246 
247 #define UNSLICE_UNIT_LEVEL_CLKGATE		XE_REG(0x9434)
248 #define   VFUNIT_CLKGATE_DIS			REG_BIT(20)
249 #define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */
250 #define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */
251 #define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)
252 #define   HSUNIT_CLKGATE_DIS			REG_BIT(8)
253 #define   VSUNIT_CLKGATE_DIS			REG_BIT(3)
254 
255 #define UNSLCGCTL9440				XE_REG(0x9440)
256 #define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)
257 #define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)
258 #define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)
259 #define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)
260 #define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)
261 #define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)
262 #define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)
263 #define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)
264 #define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)
265 #define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)
266 #define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)
267 #define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)
268 
269 #define UNSLCGCTL9444				XE_REG(0x9444)
270 #define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)
271 #define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)
272 #define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)
273 #define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)
274 #define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)
275 #define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)
276 #define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)
277 #define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)
278 #define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)
279 #define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)
280 #define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)
281 #define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)
282 #define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)
283 #define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)
284 #define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)
285 #define   LTCDD_CLKGATE_DIS			REG_BIT(10)
286 
287 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)
288 #define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)
289 #define   L3_CLKGATE_DIS			REG_BIT(16)
290 #define   NODEDSS_CLKGATE_DIS			REG_BIT(12)
291 #define   MSCUNIT_CLKGATE_DIS			REG_BIT(10)
292 #define   RCCUNIT_CLKGATE_DIS			REG_BIT(7)
293 #define   SARBUNIT_CLKGATE_DIS			REG_BIT(5)
294 #define   SBEUNIT_CLKGATE_DIS			REG_BIT(4)
295 
296 #define UNSLICE_UNIT_LEVEL_CLKGATE2		XE_REG(0x94e4)
297 #define   VSUNIT_CLKGATE2_DIS			REG_BIT(19)
298 
299 #define SUBSLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x9524)
300 #define   DSS_ROUTER_CLKGATE_DIS		REG_BIT(28)
301 #define   GWUNIT_CLKGATE_DIS			REG_BIT(16)
302 
303 #define SUBSLICE_UNIT_LEVEL_CLKGATE2		XE_REG_MCR(0x9528)
304 #define   CPSSUNIT_CLKGATE_DIS			REG_BIT(9)
305 
306 #define SSMCGCTL9530				XE_REG_MCR(0x9530)
307 #define   RTFUNIT_CLKGATE_DIS			REG_BIT(18)
308 
309 #define DFR_RATIO_EN_AND_CHICKEN		XE_REG_MCR(0x9550)
310 #define   DFR_DISABLE				REG_BIT(9)
311 
312 #define RPNSWREQ				XE_REG(0xa008)
313 #define   REQ_RATIO_MASK			REG_GENMASK(31, 23)
314 
315 #define RP_CONTROL				XE_REG(0xa024)
316 #define   RPSWCTL_MASK				REG_GENMASK(10, 9)
317 #define   RPSWCTL_ENABLE			REG_FIELD_PREP(RPSWCTL_MASK, 2)
318 #define   RPSWCTL_DISABLE			REG_FIELD_PREP(RPSWCTL_MASK, 0)
319 #define RC_CONTROL				XE_REG(0xa090)
320 #define   RC_CTL_HW_ENABLE			REG_BIT(31)
321 #define   RC_CTL_TO_MODE			REG_BIT(28)
322 #define   RC_CTL_RC6_ENABLE			REG_BIT(18)
323 #define RC_STATE				XE_REG(0xa094)
324 #define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)
325 #define MEDIA_POWERGATE_IDLE_HYSTERESIS		XE_REG(0xa0c4)
326 #define RENDER_POWERGATE_IDLE_HYSTERESIS	XE_REG(0xa0c8)
327 
328 #define PMINTRMSK				XE_REG(0xa168)
329 #define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)
330 #define   ARAT_EXPIRED_INTRMSK			REG_BIT(9)
331 
332 #define FORCEWAKE_GT				XE_REG(0xa188)
333 
334 #define POWERGATE_ENABLE			XE_REG(0xa210)
335 #define   RENDER_POWERGATE_ENABLE		REG_BIT(0)
336 #define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)
337 #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
338 #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
339 
340 #define CTC_MODE				XE_REG(0xa26c)
341 #define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
342 #define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
343 
344 #define FORCEWAKE_RENDER			XE_REG(0xa278)
345 #define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)
346 #define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
347 #define FORCEWAKE_GSC				XE_REG(0xa618)
348 
349 #define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
350 #define   XEHPC_OVRLSCCC			REG_BIT(0)
351 
352 /* L3 Cache Control */
353 #define LNCFCMOCS_REG_COUNT			32
354 #define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
355 #define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
356 #define   L3_UPPER_LKUP_MASK			REG_BIT(23)
357 #define   L3_UPPER_GLBGO_MASK			REG_BIT(22)
358 #define   L3_UPPER_IDX_CACHEABILITY_MASK	REG_GENMASK(21, 20)
359 #define   L3_UPPER_IDX_SCC_MASK			REG_GENMASK(19, 17)
360 #define   L3_UPPER_IDX_ESC_MASK			REG_BIT(16)
361 #define   L3_LKUP_MASK				REG_BIT(7)
362 #define   L3_LKUP(value)			REG_FIELD_PREP(L3_LKUP_MASK, value)
363 #define   L3_GLBGO_MASK				REG_BIT(6)
364 #define   L3_GLBGO(value)			REG_FIELD_PREP(L3_GLBGO_MASK, value)
365 #define   L3_CACHEABILITY_MASK			REG_GENMASK(5, 4)
366 #define   L3_CACHEABILITY(value)		REG_FIELD_PREP(L3_CACHEABILITY_MASK, value)
367 #define   L3_SCC_MASK				REG_GENMASK(3, 1)
368 #define   L3_SCC(value)				REG_FIELD_PREP(L3_SCC_MASK, value)
369 #define   L3_ESC_MASK				REG_BIT(0)
370 #define   L3_ESC(value)				REG_FIELD_PREP(L3_ESC_MASK, value)
371 
372 #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
373 #define   XEHP_LNESPARE				REG_BIT(19)
374 
375 #define L3SQCREG2				XE_REG_MCR(0xb104)
376 #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
377 
378 #define L3SQCREG3				XE_REG_MCR(0xb108)
379 #define   COMPPWOVERFETCHEN			REG_BIT(28)
380 
381 #define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
382 #define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
383 
384 #define XEHP_L3SCQREG7				XE_REG_MCR(0xb188)
385 #define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
386 
387 #define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)
388 
389 #define XE2_GLOBAL_INVAL			XE_REG(0xb404)
390 
391 #define SCRATCH1LPFC				XE_REG(0xb474)
392 #define   EN_L3_RW_CCS_CACHE_FLUSH		REG_BIT(0)
393 
394 #define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
395 
396 #define XE2_TDF_CTRL				XE_REG(0xb418)
397 #define   TRANSIENT_FLUSH_REQUEST		REG_BIT(0)
398 
399 #define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)
400 #define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
401 #define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
402 #define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)
403 #define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)
404 #define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)
405 #define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)
406 #define   FORCE_MISS_FTLB			REG_BIT(3)
407 
408 #define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
409 #define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
410 #define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
411 #define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
412 
413 #define XEHP_GAMCNTRL_CTRL			XE_REG_MCR(0xcf54)
414 #define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
415 #define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
416 
417 #define LMEM_CFG				XE_REG(0xcf58)
418 #define   LMEM_EN				REG_BIT(31)
419 #define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */
420 
421 #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
422 #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
423 
424 #define SAMPLER_INSTDONE			XE_REG_MCR(0xe160)
425 #define ROW_INSTDONE				XE_REG_MCR(0xe164)
426 
427 #define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
428 #define   ENABLE_SMALLPL			REG_BIT(15)
429 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
430 #define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)
431 #define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
432 
433 #define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
434 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
435 #define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
436 
437 #define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
438 #define   DISABLE_ECC				REG_BIT(5)
439 #define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
440 
441 #define ROW_CHICKEN4				XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
442 #define   DISABLE_GRF_CLEAR			REG_BIT(13)
443 #define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)
444 #define   DISABLE_TDL_PUSH			REG_BIT(9)
445 #define   DIS_PICK_2ND_EU			REG_BIT(7)
446 #define   DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)
447 #define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)
448 #define   THREAD_EX_ARB_MODE_RR_AFTER_DEP	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
449 
450 #define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
451 #define   XE2_EUPEND_CHK_FLUSH_DIS		REG_BIT(14)
452 #define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
453 
454 #define TDL_TSL_CHICKEN				XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
455 #define   STK_ID_RESTRICT			REG_BIT(12)
456 #define   SLM_WMTP_RESTORE			REG_BIT(11)
457 
458 #define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
459 #define   UGM_BACKUP_MODE			REG_BIT(13)
460 #define   MDQ_ARBITRATION_MODE			REG_BIT(12)
461 #define   STALL_DOP_GATING_DISABLE		REG_BIT(5)
462 #define   EARLY_EOT_DIS				REG_BIT(1)
463 
464 #define ROW_CHICKEN2				XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
465 #define   DISABLE_READ_SUPPRESSION		REG_BIT(15)
466 #define   DISABLE_EARLY_READ			REG_BIT(14)
467 #define   ENABLE_LARGE_GRF_MODE			REG_BIT(12)
468 #define   PUSH_CONST_DEREF_HOLD_DIS		REG_BIT(8)
469 #define   DISABLE_TDL_SVHS_GATING		REG_BIT(1)
470 #define   DISABLE_DOP_GATING			REG_BIT(0)
471 
472 #define RT_CTRL					XE_REG_MCR(0xe530)
473 #define   DIS_NULL_QUERY			REG_BIT(10)
474 
475 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
476 #define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
477 
478 #define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
479 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
480 #define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
481 
482 #define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
483 #define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
484 #define   WR_REQ_CHAINING_DIS			REG_BIT(26)
485 #define   TGM_WRITE_EOM_FORCE			REG_BIT(17)
486 #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)
487 #define   SEQUENTIAL_ACCESS_UPGRADE_DISABLE	REG_BIT(13)
488 
489 #define LSC_CHICKEN_BIT_0_UDW			XE_REG_MCR(0xe7c8 + 4)
490 #define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
491 #define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
492 #define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
493 #define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
494 #define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
495 #define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
496 #define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
497 #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
498 
499 #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
500 #define   COMP_CKN_IN				REG_GENMASK(30, 29)
501 
502 #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
503 #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
504 #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
505 
506 /*
507  * Total of 4 cslices, where each cslice is in the form:
508  *   [0-3]     CCS ID
509  *   [4-6]     RSVD
510  *   [7]       Disabled
511  */
512 #define CCS_MODE				XE_REG(0x14804)
513 #define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */
514 #define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */
515 #define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)
516 #define   CCS_MODE_CSLICE(cslice, ccs) \
517 	((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
518 
519 #define FORCEWAKE_ACK_GT			XE_REG(0x130044)
520 
521 /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */
522 #define   FORCEWAKE_KERNEL			0
523 #define   FORCEWAKE_MT(bit)			BIT(bit)
524 #define   FORCEWAKE_MT_MASK(bit)		BIT((bit) + 16)
525 
526 #define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)
527 #define MTL_MEDIA_MC6				XE_REG(0x138048)
528 
529 #define GT_CORE_STATUS				XE_REG(0x138060)
530 #define   RCN_MASK				REG_GENMASK(2, 0)
531 #define   GT_C0					0
532 #define   GT_C6					3
533 
534 #define GT_GFX_RC6_LOCKED			XE_REG(0x138104)
535 #define GT_GFX_RC6				XE_REG(0x138108)
536 
537 #define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
538 #define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
539 #define   PROCHOT_MASK				REG_BIT(0)
540 #define   THERMAL_LIMIT_MASK			REG_BIT(1)
541 #define   RATL_MASK				REG_BIT(5)
542 #define   VR_THERMALERT_MASK			REG_BIT(6)
543 #define   VR_TDC_MASK				REG_BIT(7)
544 #define   POWER_LIMIT_4_MASK			REG_BIT(8)
545 #define   POWER_LIMIT_1_MASK			REG_BIT(10)
546 #define   POWER_LIMIT_2_MASK			REG_BIT(11)
547 
548 #define GT_PERF_STATUS				XE_REG(0x1381b4)
549 #define   VOLTAGE_MASK				REG_GENMASK(10, 0)
550 
551 /*
552  * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
553  *       On newer platforms, VFs are using memory-based interrupts instead.
554  *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
555  */
556 
557 #define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
558 #define   INTR_GSC				REG_BIT(31)
559 #define   INTR_GUC				REG_BIT(25)
560 #define   INTR_MGUC				REG_BIT(24)
561 #define   INTR_BCS8				REG_BIT(23)
562 #define   INTR_BCS(x)				REG_BIT(15 - (x))
563 #define   INTR_CCS(x)				REG_BIT(4 + (x))
564 #define   INTR_RCS0				REG_BIT(0)
565 #define   INTR_VECS(x)				REG_BIT(31 - (x))
566 #define   INTR_VCS(x)				REG_BIT(x)
567 
568 #define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030, XE_REG_OPTION_VF)
569 #define VCS_VECS_INTR_ENABLE			XE_REG(0x190034, XE_REG_OPTION_VF)
570 #define GUC_SG_INTR_ENABLE			XE_REG(0x190038, XE_REG_OPTION_VF)
571 #define   ENGINE1_MASK				REG_GENMASK(31, 16)
572 #define   ENGINE0_MASK				REG_GENMASK(15, 0)
573 #define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c, XE_REG_OPTION_VF)
574 #define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044, XE_REG_OPTION_VF)
575 #define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048, XE_REG_OPTION_VF)
576 
577 #define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
578 #define   INTR_DATA_VALID			REG_BIT(31)
579 #define   INTR_ENGINE_INSTANCE(x)		REG_FIELD_GET(GENMASK(25, 20), x)
580 #define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)
581 #define   INTR_ENGINE_INTR(x)			REG_FIELD_GET(GENMASK(15, 0), x)
582 #define   OTHER_GUC_INSTANCE			0
583 #define   OTHER_GSC_HECI2_INSTANCE		3
584 #define   OTHER_GSC_INSTANCE			6
585 
586 #define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
587 #define RCS0_RSVD_INTR_MASK			XE_REG(0x190090, XE_REG_OPTION_VF)
588 #define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
589 #define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
590 #define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
591 #define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
592 #define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
593 #define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
594 #define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
595 #define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4, XE_REG_OPTION_VF)
596 #define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)
597 #define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)
598 #define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)
599 #define XEHPC_BCS3_BCS4_INTR_MASK		XE_REG(0x190114)
600 #define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)
601 #define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)
602 #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
603 #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
604 #define   GSC_ER_COMPLETE			REG_BIT(5)
605 #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
606 #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
607 #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
608 
609 #endif
610