1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPMC support functions 4 * 5 * Copyright (C) 2005-2006 Nokia Corporation 6 * 7 * Author: Juha Yrjola 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 */ 12 #include <linux/cleanup.h> 13 #include <linux/cpu_pm.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/ioport.h> 21 #include <linux/spinlock.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */ 25 #include <linux/gpio/machine.h> 26 #include <linux/interrupt.h> 27 #include <linux/irqdomain.h> 28 #include <linux/platform_device.h> 29 #include <linux/of.h> 30 #include <linux/of_address.h> 31 #include <linux/of_device.h> 32 #include <linux/of_platform.h> 33 #include <linux/omap-gpmc.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/sizes.h> 36 37 #include <linux/platform_data/mtd-nand-omap2.h> 38 39 #define DEVICE_NAME "omap-gpmc" 40 41 /* GPMC register offsets */ 42 #define GPMC_REVISION 0x00 43 #define GPMC_SYSCONFIG 0x10 44 #define GPMC_SYSSTATUS 0x14 45 #define GPMC_IRQSTATUS 0x18 46 #define GPMC_IRQENABLE 0x1c 47 #define GPMC_TIMEOUT_CONTROL 0x40 48 #define GPMC_ERR_ADDRESS 0x44 49 #define GPMC_ERR_TYPE 0x48 50 #define GPMC_CONFIG 0x50 51 #define GPMC_STATUS 0x54 52 #define GPMC_PREFETCH_CONFIG1 0x1e0 53 #define GPMC_PREFETCH_CONFIG2 0x1e4 54 #define GPMC_PREFETCH_CONTROL 0x1ec 55 #define GPMC_PREFETCH_STATUS 0x1f0 56 #define GPMC_ECC_CONFIG 0x1f4 57 #define GPMC_ECC_CONTROL 0x1f8 58 #define GPMC_ECC_SIZE_CONFIG 0x1fc 59 #define GPMC_ECC1_RESULT 0x200 60 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ 61 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ 62 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ 63 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ 64 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ 65 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ 66 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ 67 68 /* GPMC ECC control settings */ 69 #define GPMC_ECC_CTRL_ECCCLEAR 0x100 70 #define GPMC_ECC_CTRL_ECCDISABLE 0x000 71 #define GPMC_ECC_CTRL_ECCREG1 0x001 72 #define GPMC_ECC_CTRL_ECCREG2 0x002 73 #define GPMC_ECC_CTRL_ECCREG3 0x003 74 #define GPMC_ECC_CTRL_ECCREG4 0x004 75 #define GPMC_ECC_CTRL_ECCREG5 0x005 76 #define GPMC_ECC_CTRL_ECCREG6 0x006 77 #define GPMC_ECC_CTRL_ECCREG7 0x007 78 #define GPMC_ECC_CTRL_ECCREG8 0x008 79 #define GPMC_ECC_CTRL_ECCREG9 0x009 80 81 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) 82 83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) 84 85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) 86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) 87 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) 88 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) 89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) 90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) 91 92 #define GPMC_CS0_OFFSET 0x60 93 #define GPMC_CS_SIZE 0x30 94 #define GPMC_BCH_SIZE 0x10 95 96 /* 97 * The first 1MB of GPMC address space is typically mapped to 98 * the internal ROM. Never allocate the first page, to 99 * facilitate bug detection; even if we didn't boot from ROM. 100 * As GPMC minimum partition size is 16MB we can only start from 101 * there. 102 */ 103 #define GPMC_MEM_START 0x1000000 104 #define GPMC_MEM_END 0x3FFFFFFF 105 106 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 107 #define GPMC_SECTION_SHIFT 28 /* 128 MB */ 108 109 #define CS_NUM_SHIFT 24 110 #define ENABLE_PREFETCH (0x1 << 7) 111 #define DMA_MPU_MODE 2 112 113 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf) 114 #define GPMC_REVISION_MINOR(l) ((l) & 0xf) 115 116 #define GPMC_HAS_WR_ACCESS 0x1 117 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 118 #define GPMC_HAS_MUX_AAD 0x4 119 120 #define GPMC_NR_WAITPINS 4 121 122 #define GPMC_CS_CONFIG1 0x00 123 #define GPMC_CS_CONFIG2 0x04 124 #define GPMC_CS_CONFIG3 0x08 125 #define GPMC_CS_CONFIG4 0x0c 126 #define GPMC_CS_CONFIG5 0x10 127 #define GPMC_CS_CONFIG6 0x14 128 #define GPMC_CS_CONFIG7 0x18 129 #define GPMC_CS_NAND_COMMAND 0x1c 130 #define GPMC_CS_NAND_ADDRESS 0x20 131 #define GPMC_CS_NAND_DATA 0x24 132 133 /* Control Commands */ 134 #define GPMC_CONFIG_RDY_BSY 0x00000001 135 #define GPMC_CONFIG_DEV_SIZE 0x00000002 136 #define GPMC_CONFIG_DEV_TYPE 0x00000003 137 138 #define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) 139 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 140 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 141 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 142 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 143 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 144 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 145 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 146 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25) 147 /** CLKACTIVATIONTIME Max Ticks */ 148 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 149 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23) 150 /** ATTACHEDDEVICEPAGELENGTH Max Value */ 151 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 152 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 153 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 154 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18) 155 /** WAITMONITORINGTIME Max Ticks */ 156 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 157 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16) 158 #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12) 159 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 160 /** DEVICESIZE Max Value */ 161 #define GPMC_CONFIG1_DEVICESIZE_MAX 1 162 #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10) 163 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 164 #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8) 165 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 166 #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3) 167 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 168 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 169 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 170 #define GPMC_CONFIG7_CSVALID (1 << 6) 171 172 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f 173 #define GPMC_CONFIG7_CSVALID_MASK BIT(6) 174 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 175 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) 176 /* All CONFIG7 bits except reserved bits */ 177 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ 178 GPMC_CONFIG7_CSVALID_MASK | \ 179 GPMC_CONFIG7_MASKADDRESS_MASK) 180 181 #define GPMC_DEVICETYPE_NOR 0 182 #define GPMC_DEVICETYPE_NAND 2 183 #define GPMC_CONFIG_WRITEPROTECT 0x00000010 184 #define WR_RD_PIN_MONITORING 0x00600000 185 186 /* ECC commands */ 187 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 188 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 189 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 190 191 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */ 192 193 enum gpmc_clk_domain { 194 GPMC_CD_FCLK, 195 GPMC_CD_CLK 196 }; 197 198 struct gpmc_cs_data { 199 const char *name; 200 201 #define GPMC_CS_RESERVED (1 << 0) 202 u32 flags; 203 204 struct resource mem; 205 }; 206 207 /* Structure to save gpmc cs context */ 208 struct gpmc_cs_config { 209 u32 config1; 210 u32 config2; 211 u32 config3; 212 u32 config4; 213 u32 config5; 214 u32 config6; 215 u32 config7; 216 int is_valid; 217 }; 218 219 /* 220 * Structure to save/restore gpmc context 221 * to support core off on OMAP3 222 */ 223 struct omap3_gpmc_regs { 224 u32 sysconfig; 225 u32 irqenable; 226 u32 timeout_ctrl; 227 u32 config; 228 u32 prefetch_config1; 229 u32 prefetch_config2; 230 u32 prefetch_control; 231 struct gpmc_cs_config cs_context[GPMC_CS_NUM]; 232 }; 233 234 struct gpmc_waitpin { 235 u32 pin; 236 u32 polarity; 237 struct gpio_desc *desc; 238 }; 239 240 struct gpmc_device { 241 struct device *dev; 242 int irq; 243 struct irq_chip irq_chip; 244 struct gpio_chip gpio_chip; 245 struct notifier_block nb; 246 struct omap3_gpmc_regs context; 247 struct gpmc_waitpin *waitpins; 248 int nirqs; 249 unsigned int is_suspended:1; 250 struct resource *data; 251 }; 252 253 static struct irq_domain *gpmc_irq_domain; 254 255 static struct resource gpmc_mem_root; 256 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; 257 static DEFINE_SPINLOCK(gpmc_mem_lock); 258 /* Define chip-selects as reserved by default until probe completes */ 259 static unsigned int gpmc_cs_num = GPMC_CS_NUM; 260 static unsigned int gpmc_nr_waitpins; 261 static unsigned int gpmc_capability; 262 static void __iomem *gpmc_base; 263 264 static struct clk *gpmc_l3_clk; 265 266 static irqreturn_t gpmc_handle_irq(int irq, void *dev); 267 268 static void gpmc_write_reg(int idx, u32 val) 269 { 270 writel_relaxed(val, gpmc_base + idx); 271 } 272 273 static u32 gpmc_read_reg(int idx) 274 { 275 return readl_relaxed(gpmc_base + idx); 276 } 277 278 void gpmc_cs_write_reg(int cs, int idx, u32 val) 279 { 280 void __iomem *reg_addr; 281 282 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 283 writel_relaxed(val, reg_addr); 284 } 285 286 static u32 gpmc_cs_read_reg(int cs, int idx) 287 { 288 void __iomem *reg_addr; 289 290 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 291 return readl_relaxed(reg_addr); 292 } 293 294 /* TODO: Add support for gpmc_fck to clock framework and use it */ 295 static unsigned long gpmc_get_fclk_period(void) 296 { 297 unsigned long rate = clk_get_rate(gpmc_l3_clk); 298 299 rate /= 1000; 300 rate = 1000000000 / rate; /* In picoseconds */ 301 302 return rate; 303 } 304 305 /** 306 * gpmc_get_clk_period - get period of selected clock domain in ps 307 * @cs: Chip Select Region. 308 * @cd: Clock Domain. 309 * 310 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup 311 * prior to calling this function with GPMC_CD_CLK. 312 */ 313 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) 314 { 315 unsigned long tick_ps = gpmc_get_fclk_period(); 316 u32 l; 317 int div; 318 319 switch (cd) { 320 case GPMC_CD_CLK: 321 /* get current clk divider */ 322 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 323 div = (l & 0x03) + 1; 324 /* get GPMC_CLK period */ 325 tick_ps *= div; 326 break; 327 case GPMC_CD_FCLK: 328 default: 329 break; 330 } 331 332 return tick_ps; 333 } 334 335 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, 336 enum gpmc_clk_domain cd) 337 { 338 unsigned long tick_ps; 339 340 /* Calculate in picosecs to yield more exact results */ 341 tick_ps = gpmc_get_clk_period(cs, cd); 342 343 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 344 } 345 346 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 347 { 348 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); 349 } 350 351 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) 352 { 353 unsigned long tick_ps; 354 355 /* Calculate in picosecs to yield more exact results */ 356 tick_ps = gpmc_get_fclk_period(); 357 358 return (time_ps + tick_ps - 1) / tick_ps; 359 } 360 361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks) 362 { 363 return ticks * gpmc_get_fclk_period(); 364 } 365 366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) 367 { 368 unsigned long ticks = gpmc_ps_to_ticks(time_ps); 369 370 return ticks * gpmc_get_fclk_period(); 371 } 372 373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) 374 { 375 u32 l; 376 377 l = gpmc_cs_read_reg(cs, reg); 378 if (value) 379 l |= mask; 380 else 381 l &= ~mask; 382 gpmc_cs_write_reg(cs, reg, l); 383 } 384 385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) 386 { 387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, 388 GPMC_CONFIG1_TIME_PARA_GRAN, 389 p->time_para_granularity); 390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, 391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); 392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, 393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); 394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); 396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); 398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, 400 p->cycle2cyclesamecsen); 401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, 403 p->cycle2cyclediffcsen); 404 } 405 406 #ifdef CONFIG_OMAP_GPMC_DEBUG 407 408 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, 409 enum gpmc_clk_domain cd) 410 { 411 return ticks * gpmc_get_clk_period(cs, cd) / 1000; 412 } 413 414 /** 415 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. 416 * @cs: Chip Select Region 417 * @reg: GPMC_CS_CONFIGn register offset. 418 * @st_bit: Start Bit 419 * @end_bit: End Bit. Must be >= @st_bit. 420 * @max: Maximum parameter value (before optional @shift). 421 * If 0, maximum is as high as @st_bit and @end_bit allow. 422 * @name: DTS node name, w/o "gpmc," 423 * @cd: Clock Domain of timing parameter. 424 * @shift: Parameter value left shifts @shift, which is then printed instead of value. 425 * @raw: Raw Format Option. 426 * raw format: gpmc,name = <value> 427 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/ 428 * Where x ns -- y ns result in the same tick value. 429 * When @max is exceeded, "invalid" is printed inside comment. 430 * @noval: Parameter values equal to 0 are not printed. 431 * @return: Specified timing parameter (after optional @shift). 432 * 433 */ 434 static int get_gpmc_timing_reg( 435 int cs, int reg, int st_bit, int end_bit, int max, 436 const char *name, const enum gpmc_clk_domain cd, 437 int shift, bool raw, bool noval) 438 { 439 u32 l; 440 int nr_bits; 441 int mask; 442 bool invalid; 443 444 l = gpmc_cs_read_reg(cs, reg); 445 nr_bits = end_bit - st_bit + 1; 446 mask = (1 << nr_bits) - 1; 447 l = (l >> st_bit) & mask; 448 if (!max) 449 max = mask; 450 invalid = l > max; 451 if (shift) 452 l = (shift << l); 453 if (noval && (l == 0)) 454 return 0; 455 if (!raw) { 456 /* DTS tick format for timings in ns */ 457 unsigned int time_ns; 458 unsigned int time_ns_min = 0; 459 460 if (l) 461 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; 462 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); 463 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", 464 name, time_ns, time_ns_min, time_ns, l, 465 invalid ? "; invalid " : " "); 466 } else { 467 /* raw format */ 468 pr_info("gpmc,%s = <%u>;%s\n", name, l, 469 invalid ? " /* invalid */" : ""); 470 } 471 472 return l; 473 } 474 475 #define GPMC_PRINT_CONFIG(cs, config) \ 476 pr_info("cs%i %s: 0x%08x\n", cs, #config, \ 477 gpmc_cs_read_reg(cs, config)) 478 #define GPMC_GET_RAW(reg, st, end, field) \ 479 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) 480 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ 481 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) 482 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ 483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) 484 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ 485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) 486 #define GPMC_GET_TICKS(reg, st, end, field) \ 487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) 488 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ 489 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) 490 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ 491 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) 492 493 static void gpmc_show_regs(int cs, const char *desc) 494 { 495 pr_info("gpmc cs%i %s:\n", cs, desc); 496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); 497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); 498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); 499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); 500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); 501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); 502 } 503 504 /* 505 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, 506 * see commit c9fb809. 507 */ 508 static void gpmc_cs_show_timings(int cs, const char *desc) 509 { 510 gpmc_show_regs(cs, desc); 511 512 pr_info("gpmc cs%i access configuration:\n", cs); 513 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); 514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); 515 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, 516 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); 517 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); 518 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); 519 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); 520 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, 521 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, 522 "burst-length"); 523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); 524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); 525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); 526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); 527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); 528 529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); 530 531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); 532 533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); 534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); 535 536 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); 537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); 538 539 pr_info("gpmc cs%i timings configuration:\n", cs); 540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); 541 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); 542 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); 543 544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); 545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); 546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); 547 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); 549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, 550 "adv-aad-mux-rd-off-ns"); 551 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, 552 "adv-aad-mux-wr-off-ns"); 553 } 554 555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); 556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); 557 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); 559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); 560 } 561 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); 562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); 563 564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); 565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); 566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); 567 568 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); 569 570 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); 571 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); 572 573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, 574 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 575 "wait-monitoring-ns", GPMC_CD_CLK); 576 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, 577 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 578 "clk-activation-ns", GPMC_CD_FCLK); 579 580 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); 581 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); 582 } 583 #else 584 static inline void gpmc_cs_show_timings(int cs, const char *desc) 585 { 586 } 587 #endif 588 589 /** 590 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. 591 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER 592 * prior to calling this function with @cd equal to GPMC_CD_CLK. 593 * 594 * @cs: Chip Select Region. 595 * @reg: GPMC_CS_CONFIGn register offset. 596 * @st_bit: Start Bit 597 * @end_bit: End Bit. Must be >= @st_bit. 598 * @max: Maximum parameter value. 599 * If 0, maximum is as high as @st_bit and @end_bit allow. 600 * @time: Timing parameter in ns. 601 * @cd: Timing parameter clock domain. 602 * @name: Timing parameter name. 603 * @return: 0 on success, -1 on error. 604 */ 605 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, 606 int time, enum gpmc_clk_domain cd, const char *name) 607 { 608 u32 l; 609 int ticks, mask, nr_bits; 610 611 if (time == 0) 612 ticks = 0; 613 else 614 ticks = gpmc_ns_to_clk_ticks(time, cs, cd); 615 nr_bits = end_bit - st_bit + 1; 616 mask = (1 << nr_bits) - 1; 617 618 if (!max) 619 max = mask; 620 621 if (ticks > max) { 622 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", 623 __func__, cs, name, time, ticks, max); 624 625 return -1; 626 } 627 628 l = gpmc_cs_read_reg(cs, reg); 629 #ifdef CONFIG_OMAP_GPMC_DEBUG 630 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", 631 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, 632 (l >> st_bit) & mask, time); 633 #endif 634 l &= ~(mask << st_bit); 635 l |= ticks << st_bit; 636 gpmc_cs_write_reg(cs, reg, l); 637 638 return 0; 639 } 640 641 /** 642 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME 643 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. 644 * read --> don't sample bus too early 645 * write --> data is longer on bus 646 * 647 * Formula: 648 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) 649 * / waitmonitoring_ticks) 650 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by 651 * div <= 0 check. 652 * 653 * @wait_monitoring: WAITMONITORINGTIME in ns. 654 * @return: -1 on failure to scale, else proper divider > 0. 655 */ 656 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) 657 { 658 int div = gpmc_ns_to_ticks(wait_monitoring); 659 660 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; 661 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; 662 663 if (div > 4) 664 return -1; 665 if (div <= 0) 666 div = 1; 667 668 return div; 669 } 670 671 /** 672 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. 673 * @sync_clk: GPMC_CLK period in ps. 674 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. 675 * Else, returns -1. 676 */ 677 int gpmc_calc_divider(unsigned int sync_clk) 678 { 679 int div = gpmc_ps_to_ticks(sync_clk); 680 681 if (div > 4) 682 return -1; 683 if (div <= 0) 684 div = 1; 685 686 return div; 687 } 688 689 /** 690 * gpmc_cs_set_timings - program timing parameters for Chip Select Region. 691 * @cs: Chip Select Region. 692 * @t: GPMC timing parameters. 693 * @s: GPMC timing settings. 694 * @return: 0 on success, -1 on error. 695 */ 696 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, 697 const struct gpmc_settings *s) 698 { 699 int div, ret; 700 u32 l; 701 702 div = gpmc_calc_divider(t->sync_clk); 703 if (div < 0) 704 return -EINVAL; 705 706 /* 707 * See if we need to change the divider for waitmonitoringtime. 708 * 709 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for 710 * pure asynchronous accesses, i.e. both read and write asynchronous. 711 * However, only do so if WAITMONITORINGTIME is actually used, i.e. 712 * either WAITREADMONITORING or WAITWRITEMONITORING is set. 713 * 714 * This statement must not change div to scale async WAITMONITORINGTIME 715 * to protect mixed synchronous and asynchronous accesses. 716 * 717 * We raise an error later if WAITMONITORINGTIME does not fit. 718 */ 719 if (!s->sync_read && !s->sync_write && 720 (s->wait_on_read || s->wait_on_write) 721 ) { 722 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); 723 if (div < 0) { 724 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", 725 __func__, 726 t->wait_monitoring 727 ); 728 return -ENXIO; 729 } 730 } 731 732 ret = 0; 733 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on, 734 GPMC_CD_FCLK, "cs_on"); 735 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off, 736 GPMC_CD_FCLK, "cs_rd_off"); 737 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off, 738 GPMC_CD_FCLK, "cs_wr_off"); 739 if (ret) 740 return -ENXIO; 741 742 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on, 743 GPMC_CD_FCLK, "adv_on"); 744 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off, 745 GPMC_CD_FCLK, "adv_rd_off"); 746 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off, 747 GPMC_CD_FCLK, "adv_wr_off"); 748 if (ret) 749 return -ENXIO; 750 751 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 752 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0, 753 t->adv_aad_mux_on, GPMC_CD_FCLK, 754 "adv_aad_mux_on"); 755 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0, 756 t->adv_aad_mux_rd_off, GPMC_CD_FCLK, 757 "adv_aad_mux_rd_off"); 758 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0, 759 t->adv_aad_mux_wr_off, GPMC_CD_FCLK, 760 "adv_aad_mux_wr_off"); 761 if (ret) 762 return -ENXIO; 763 } 764 765 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on, 766 GPMC_CD_FCLK, "oe_on"); 767 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off, 768 GPMC_CD_FCLK, "oe_off"); 769 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 770 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0, 771 t->oe_aad_mux_on, GPMC_CD_FCLK, 772 "oe_aad_mux_on"); 773 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0, 774 t->oe_aad_mux_off, GPMC_CD_FCLK, 775 "oe_aad_mux_off"); 776 } 777 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on, 778 GPMC_CD_FCLK, "we_on"); 779 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off, 780 GPMC_CD_FCLK, "we_off"); 781 if (ret) 782 return -ENXIO; 783 784 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle, 785 GPMC_CD_FCLK, "rd_cycle"); 786 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle, 787 GPMC_CD_FCLK, "wr_cycle"); 788 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access, 789 GPMC_CD_FCLK, "access"); 790 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0, 791 t->page_burst_access, GPMC_CD_FCLK, 792 "page_burst_access"); 793 if (ret) 794 return -ENXIO; 795 796 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0, 797 t->bus_turnaround, GPMC_CD_FCLK, 798 "bus_turnaround"); 799 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0, 800 t->cycle2cycle_delay, GPMC_CD_FCLK, 801 "cycle2cycle_delay"); 802 if (ret) 803 return -ENXIO; 804 805 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) { 806 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0, 807 t->wr_data_mux_bus, GPMC_CD_FCLK, 808 "wr_data_mux_bus"); 809 if (ret) 810 return -ENXIO; 811 } 812 if (gpmc_capability & GPMC_HAS_WR_ACCESS) { 813 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0, 814 t->wr_access, GPMC_CD_FCLK, 815 "wr_access"); 816 if (ret) 817 return -ENXIO; 818 } 819 820 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 821 l &= ~0x03; 822 l |= (div - 1); 823 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); 824 825 ret = 0; 826 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19, 827 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 828 t->wait_monitoring, GPMC_CD_CLK, 829 "wait_monitoring"); 830 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26, 831 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 832 t->clk_activation, GPMC_CD_FCLK, 833 "clk_activation"); 834 if (ret) 835 return -ENXIO; 836 837 #ifdef CONFIG_OMAP_GPMC_DEBUG 838 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", 839 cs, (div * gpmc_get_fclk_period()) / 1000, div); 840 #endif 841 842 gpmc_cs_bool_timings(cs, &t->bool_timings); 843 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); 844 845 return 0; 846 } 847 848 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) 849 { 850 u32 l; 851 u32 mask; 852 853 /* 854 * Ensure that base address is aligned on a 855 * boundary equal to or greater than size. 856 */ 857 if (base & (size - 1)) 858 return -EINVAL; 859 860 base >>= GPMC_CHUNK_SHIFT; 861 mask = (1 << GPMC_SECTION_SHIFT) - size; 862 mask >>= GPMC_CHUNK_SHIFT; 863 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; 864 865 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 866 l &= ~GPMC_CONFIG7_MASK; 867 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; 868 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; 869 l |= GPMC_CONFIG7_CSVALID; 870 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 871 872 return 0; 873 } 874 875 static void gpmc_cs_enable_mem(int cs) 876 { 877 u32 l; 878 879 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 880 l |= GPMC_CONFIG7_CSVALID; 881 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 882 } 883 884 static void gpmc_cs_disable_mem(int cs) 885 { 886 u32 l; 887 888 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 889 l &= ~GPMC_CONFIG7_CSVALID; 890 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 891 } 892 893 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) 894 { 895 u32 l; 896 u32 mask; 897 898 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 899 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; 900 mask = (l >> 8) & 0x0f; 901 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); 902 } 903 904 static int gpmc_cs_mem_enabled(int cs) 905 { 906 u32 l; 907 908 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 909 return l & GPMC_CONFIG7_CSVALID; 910 } 911 912 static void gpmc_cs_set_reserved(int cs, int reserved) 913 { 914 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 915 916 gpmc->flags |= GPMC_CS_RESERVED; 917 } 918 919 static bool gpmc_cs_reserved(int cs) 920 { 921 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 922 923 return gpmc->flags & GPMC_CS_RESERVED; 924 } 925 926 static unsigned long gpmc_mem_align(unsigned long size) 927 { 928 int order; 929 930 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); 931 order = GPMC_CHUNK_SHIFT - 1; 932 do { 933 size >>= 1; 934 order++; 935 } while (size); 936 size = 1 << order; 937 return size; 938 } 939 940 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) 941 { 942 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 943 struct resource *res = &gpmc->mem; 944 int r; 945 946 size = gpmc_mem_align(size); 947 spin_lock(&gpmc_mem_lock); 948 res->start = base; 949 res->end = base + size - 1; 950 r = request_resource(&gpmc_mem_root, res); 951 spin_unlock(&gpmc_mem_lock); 952 953 return r; 954 } 955 956 static int gpmc_cs_delete_mem(int cs) 957 { 958 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 959 struct resource *res = &gpmc->mem; 960 int r; 961 962 spin_lock(&gpmc_mem_lock); 963 r = release_resource(res); 964 res->start = 0; 965 res->end = 0; 966 spin_unlock(&gpmc_mem_lock); 967 968 return r; 969 } 970 971 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 972 { 973 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 974 struct resource *res = &gpmc->mem; 975 int r = -1; 976 977 if (cs >= gpmc_cs_num) { 978 pr_err("%s: requested chip-select is disabled\n", __func__); 979 return -ENODEV; 980 } 981 size = gpmc_mem_align(size); 982 if (size > (1 << GPMC_SECTION_SHIFT)) 983 return -ENOMEM; 984 985 guard(spinlock)(&gpmc_mem_lock); 986 987 if (gpmc_cs_reserved(cs)) 988 return -EBUSY; 989 990 if (gpmc_cs_mem_enabled(cs)) 991 r = adjust_resource(res, res->start & ~(size - 1), size); 992 if (r < 0) 993 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, 994 size, NULL, NULL); 995 if (r < 0) 996 return r; 997 998 /* Disable CS while changing base address and size mask */ 999 gpmc_cs_disable_mem(cs); 1000 1001 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); 1002 if (r < 0) { 1003 release_resource(res); 1004 return r; 1005 } 1006 1007 /* Enable CS */ 1008 gpmc_cs_enable_mem(cs); 1009 *base = res->start; 1010 gpmc_cs_set_reserved(cs, 1); 1011 1012 return 0; 1013 } 1014 EXPORT_SYMBOL(gpmc_cs_request); 1015 1016 void gpmc_cs_free(int cs) 1017 { 1018 struct gpmc_cs_data *gpmc; 1019 struct resource *res; 1020 1021 guard(spinlock)(&gpmc_mem_lock); 1022 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 1023 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs); 1024 return; 1025 } 1026 gpmc = &gpmc_cs[cs]; 1027 res = &gpmc->mem; 1028 1029 gpmc_cs_disable_mem(cs); 1030 if (res->flags) 1031 release_resource(res); 1032 gpmc_cs_set_reserved(cs, 0); 1033 } 1034 EXPORT_SYMBOL(gpmc_cs_free); 1035 1036 static bool gpmc_is_valid_waitpin(u32 waitpin) 1037 { 1038 return waitpin < gpmc_nr_waitpins; 1039 } 1040 1041 static int gpmc_alloc_waitpin(struct gpmc_device *gpmc, 1042 struct gpmc_settings *p) 1043 { 1044 int ret; 1045 struct gpmc_waitpin *waitpin; 1046 struct gpio_desc *waitpin_desc; 1047 1048 if (!gpmc_is_valid_waitpin(p->wait_pin)) 1049 return -EINVAL; 1050 1051 waitpin = &gpmc->waitpins[p->wait_pin]; 1052 1053 if (!waitpin->desc) { 1054 /* Reserve the GPIO for wait pin usage. 1055 * GPIO polarity doesn't matter here. Wait pin polarity 1056 * is set in GPMC_CONFIG register. 1057 */ 1058 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, 1059 p->wait_pin, "WAITPIN", 1060 GPIO_ACTIVE_HIGH, 1061 GPIOD_IN); 1062 1063 ret = PTR_ERR(waitpin_desc); 1064 if (IS_ERR(waitpin_desc) && ret != -EBUSY) 1065 return ret; 1066 1067 /* New wait pin */ 1068 waitpin->desc = waitpin_desc; 1069 waitpin->pin = p->wait_pin; 1070 waitpin->polarity = p->wait_pin_polarity; 1071 } else { 1072 /* Shared wait pin */ 1073 if (p->wait_pin_polarity != waitpin->polarity || 1074 p->wait_pin != waitpin->pin) { 1075 dev_err(gpmc->dev, 1076 "shared-wait-pin: invalid configuration\n"); 1077 return -EINVAL; 1078 } 1079 dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin); 1080 } 1081 1082 return 0; 1083 } 1084 1085 static void gpmc_free_waitpin(struct gpmc_device *gpmc, 1086 int wait_pin) 1087 { 1088 if (gpmc_is_valid_waitpin(wait_pin)) 1089 gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc); 1090 } 1091 1092 /** 1093 * gpmc_configure - write request to configure gpmc 1094 * @cmd: command type 1095 * @wval: value to write 1096 * @return status of the operation 1097 */ 1098 int gpmc_configure(int cmd, int wval) 1099 { 1100 u32 regval; 1101 1102 switch (cmd) { 1103 case GPMC_CONFIG_WP: 1104 regval = gpmc_read_reg(GPMC_CONFIG); 1105 if (wval) 1106 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ 1107 else 1108 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ 1109 gpmc_write_reg(GPMC_CONFIG, regval); 1110 break; 1111 1112 default: 1113 pr_err("%s: command not supported\n", __func__); 1114 return -EINVAL; 1115 } 1116 1117 return 0; 1118 } 1119 EXPORT_SYMBOL(gpmc_configure); 1120 1121 static bool gpmc_nand_writebuffer_empty(void) 1122 { 1123 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS) 1124 return true; 1125 1126 return false; 1127 } 1128 1129 static struct gpmc_nand_ops nand_ops = { 1130 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, 1131 }; 1132 1133 /** 1134 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface 1135 * @reg: the GPMC NAND register map exclusive for NAND use. 1136 * @cs: GPMC chip select number on which the NAND sits. The 1137 * register map returned will be specific to this chip select. 1138 * 1139 * Returns NULL on error e.g. invalid cs. 1140 */ 1141 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) 1142 { 1143 int i; 1144 1145 if (cs >= gpmc_cs_num) 1146 return NULL; 1147 1148 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + 1149 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; 1150 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + 1151 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; 1152 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + 1153 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; 1154 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; 1155 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; 1156 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; 1157 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; 1158 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; 1159 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; 1160 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; 1161 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; 1162 1163 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { 1164 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + 1165 GPMC_BCH_SIZE * i; 1166 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + 1167 GPMC_BCH_SIZE * i; 1168 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + 1169 GPMC_BCH_SIZE * i; 1170 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + 1171 GPMC_BCH_SIZE * i; 1172 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + 1173 i * GPMC_BCH_SIZE; 1174 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + 1175 i * GPMC_BCH_SIZE; 1176 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + 1177 i * GPMC_BCH_SIZE; 1178 } 1179 1180 return &nand_ops; 1181 } 1182 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops); 1183 1184 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t, 1185 struct gpmc_settings *s, 1186 int freq, int latency) 1187 { 1188 struct gpmc_device_timings dev_t; 1189 const int t_cer = 15; 1190 const int t_avdp = 12; 1191 const int t_cez = 20; /* max of t_cez, t_oez */ 1192 const int t_wpl = 40; 1193 const int t_wph = 30; 1194 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 1195 1196 switch (freq) { 1197 case 104: 1198 min_gpmc_clk_period = 9600; /* 104 MHz */ 1199 t_ces = 3; 1200 t_avds = 4; 1201 t_avdh = 2; 1202 t_ach = 3; 1203 t_aavdh = 6; 1204 t_rdyo = 6; 1205 break; 1206 case 83: 1207 min_gpmc_clk_period = 12000; /* 83 MHz */ 1208 t_ces = 5; 1209 t_avds = 4; 1210 t_avdh = 2; 1211 t_ach = 6; 1212 t_aavdh = 6; 1213 t_rdyo = 9; 1214 break; 1215 case 66: 1216 min_gpmc_clk_period = 15000; /* 66 MHz */ 1217 t_ces = 6; 1218 t_avds = 5; 1219 t_avdh = 2; 1220 t_ach = 6; 1221 t_aavdh = 6; 1222 t_rdyo = 11; 1223 break; 1224 default: 1225 min_gpmc_clk_period = 18500; /* 54 MHz */ 1226 t_ces = 7; 1227 t_avds = 7; 1228 t_avdh = 7; 1229 t_ach = 9; 1230 t_aavdh = 7; 1231 t_rdyo = 15; 1232 break; 1233 } 1234 1235 /* Set synchronous read timings */ 1236 memset(&dev_t, 0, sizeof(dev_t)); 1237 1238 if (!s->sync_write) { 1239 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; 1240 dev_t.t_wpl = t_wpl * 1000; 1241 dev_t.t_wph = t_wph * 1000; 1242 dev_t.t_aavdh = t_aavdh * 1000; 1243 } 1244 dev_t.ce_xdelay = true; 1245 dev_t.avd_xdelay = true; 1246 dev_t.oe_xdelay = true; 1247 dev_t.we_xdelay = true; 1248 dev_t.clk = min_gpmc_clk_period; 1249 dev_t.t_bacc = dev_t.clk; 1250 dev_t.t_ces = t_ces * 1000; 1251 dev_t.t_avds = t_avds * 1000; 1252 dev_t.t_avdh = t_avdh * 1000; 1253 dev_t.t_ach = t_ach * 1000; 1254 dev_t.cyc_iaa = (latency + 1); 1255 dev_t.t_cez_r = t_cez * 1000; 1256 dev_t.t_cez_w = dev_t.t_cez_r; 1257 dev_t.cyc_aavdh_oe = 1; 1258 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; 1259 1260 gpmc_calc_timings(t, s, &dev_t); 1261 } 1262 1263 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq, 1264 int latency, 1265 struct gpmc_onenand_info *info) 1266 { 1267 int ret; 1268 struct gpmc_timings gpmc_t; 1269 struct gpmc_settings gpmc_s; 1270 1271 gpmc_read_settings_dt(dev->of_node, &gpmc_s); 1272 1273 info->sync_read = gpmc_s.sync_read; 1274 info->sync_write = gpmc_s.sync_write; 1275 info->burst_len = gpmc_s.burst_len; 1276 1277 if (!gpmc_s.sync_read && !gpmc_s.sync_write) 1278 return 0; 1279 1280 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency); 1281 1282 ret = gpmc_cs_program_settings(cs, &gpmc_s); 1283 if (ret < 0) 1284 return ret; 1285 1286 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 1287 } 1288 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings); 1289 1290 static int gpmc_irq_endis(unsigned long hwirq, bool endis) 1291 { 1292 u32 regval; 1293 1294 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */ 1295 if (hwirq >= GPMC_NR_NAND_IRQS) 1296 hwirq += 8 - GPMC_NR_NAND_IRQS; 1297 1298 regval = gpmc_read_reg(GPMC_IRQENABLE); 1299 if (endis) 1300 regval |= BIT(hwirq); 1301 else 1302 regval &= ~BIT(hwirq); 1303 gpmc_write_reg(GPMC_IRQENABLE, regval); 1304 1305 return 0; 1306 } 1307 1308 static void gpmc_irq_disable(struct irq_data *p) 1309 { 1310 gpmc_irq_endis(p->hwirq, false); 1311 } 1312 1313 static void gpmc_irq_enable(struct irq_data *p) 1314 { 1315 gpmc_irq_endis(p->hwirq, true); 1316 } 1317 1318 static void gpmc_irq_mask(struct irq_data *d) 1319 { 1320 gpmc_irq_endis(d->hwirq, false); 1321 } 1322 1323 static void gpmc_irq_unmask(struct irq_data *d) 1324 { 1325 gpmc_irq_endis(d->hwirq, true); 1326 } 1327 1328 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge) 1329 { 1330 u32 regval; 1331 1332 /* NAND IRQs polarity is not configurable */ 1333 if (hwirq < GPMC_NR_NAND_IRQS) 1334 return; 1335 1336 /* WAITPIN starts at BIT 8 */ 1337 hwirq += 8 - GPMC_NR_NAND_IRQS; 1338 1339 regval = gpmc_read_reg(GPMC_CONFIG); 1340 if (rising_edge) 1341 regval &= ~BIT(hwirq); 1342 else 1343 regval |= BIT(hwirq); 1344 1345 gpmc_write_reg(GPMC_CONFIG, regval); 1346 } 1347 1348 static void gpmc_irq_ack(struct irq_data *d) 1349 { 1350 unsigned int hwirq = d->hwirq; 1351 1352 /* skip reserved bits */ 1353 if (hwirq >= GPMC_NR_NAND_IRQS) 1354 hwirq += 8 - GPMC_NR_NAND_IRQS; 1355 1356 /* Setting bit to 1 clears (or Acks) the interrupt */ 1357 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq)); 1358 } 1359 1360 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger) 1361 { 1362 /* can't set type for NAND IRQs */ 1363 if (d->hwirq < GPMC_NR_NAND_IRQS) 1364 return -EINVAL; 1365 1366 /* We can support either rising or falling edge at a time */ 1367 if (trigger == IRQ_TYPE_EDGE_FALLING) 1368 gpmc_irq_edge_config(d->hwirq, false); 1369 else if (trigger == IRQ_TYPE_EDGE_RISING) 1370 gpmc_irq_edge_config(d->hwirq, true); 1371 else 1372 return -EINVAL; 1373 1374 return 0; 1375 } 1376 1377 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq, 1378 irq_hw_number_t hw) 1379 { 1380 struct gpmc_device *gpmc = d->host_data; 1381 1382 irq_set_chip_data(virq, gpmc); 1383 if (hw < GPMC_NR_NAND_IRQS) { 1384 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN); 1385 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1386 handle_simple_irq); 1387 } else { 1388 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1389 handle_edge_irq); 1390 } 1391 1392 return 0; 1393 } 1394 1395 static const struct irq_domain_ops gpmc_irq_domain_ops = { 1396 .map = gpmc_irq_map, 1397 .xlate = irq_domain_xlate_twocell, 1398 }; 1399 1400 static irqreturn_t gpmc_handle_irq(int irq, void *data) 1401 { 1402 int hwirq, virq; 1403 u32 regval, regvalx; 1404 struct gpmc_device *gpmc = data; 1405 1406 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1407 regvalx = regval; 1408 1409 if (!regval) 1410 return IRQ_NONE; 1411 1412 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) { 1413 /* skip reserved status bits */ 1414 if (hwirq == GPMC_NR_NAND_IRQS) 1415 regvalx >>= 8 - GPMC_NR_NAND_IRQS; 1416 1417 if (regvalx & BIT(hwirq)) { 1418 virq = irq_find_mapping(gpmc_irq_domain, hwirq); 1419 if (!virq) { 1420 dev_warn(gpmc->dev, 1421 "spurious irq detected hwirq %d, virq %d\n", 1422 hwirq, virq); 1423 } 1424 1425 generic_handle_irq(virq); 1426 } 1427 } 1428 1429 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1430 1431 return IRQ_HANDLED; 1432 } 1433 1434 static int gpmc_setup_irq(struct gpmc_device *gpmc) 1435 { 1436 u32 regval; 1437 int rc; 1438 1439 /* Disable interrupts */ 1440 gpmc_write_reg(GPMC_IRQENABLE, 0); 1441 1442 /* clear interrupts */ 1443 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1444 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1445 1446 gpmc->irq_chip.name = "gpmc"; 1447 gpmc->irq_chip.irq_enable = gpmc_irq_enable; 1448 gpmc->irq_chip.irq_disable = gpmc_irq_disable; 1449 gpmc->irq_chip.irq_ack = gpmc_irq_ack; 1450 gpmc->irq_chip.irq_mask = gpmc_irq_mask; 1451 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask; 1452 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type; 1453 1454 gpmc_irq_domain = irq_domain_create_linear(dev_fwnode(gpmc->dev), gpmc->nirqs, 1455 &gpmc_irq_domain_ops, gpmc); 1456 if (!gpmc_irq_domain) { 1457 dev_err(gpmc->dev, "IRQ domain add failed\n"); 1458 return -ENODEV; 1459 } 1460 1461 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); 1462 if (rc) { 1463 dev_err(gpmc->dev, "failed to request irq %d: %d\n", 1464 gpmc->irq, rc); 1465 irq_domain_remove(gpmc_irq_domain); 1466 gpmc_irq_domain = NULL; 1467 } 1468 1469 return rc; 1470 } 1471 1472 static int gpmc_free_irq(struct gpmc_device *gpmc) 1473 { 1474 int hwirq; 1475 1476 free_irq(gpmc->irq, gpmc); 1477 1478 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) 1479 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq)); 1480 1481 irq_domain_remove(gpmc_irq_domain); 1482 gpmc_irq_domain = NULL; 1483 1484 return 0; 1485 } 1486 1487 static void gpmc_mem_exit(void) 1488 { 1489 int cs; 1490 1491 for (cs = 0; cs < gpmc_cs_num; cs++) { 1492 if (!gpmc_cs_mem_enabled(cs)) 1493 continue; 1494 gpmc_cs_delete_mem(cs); 1495 } 1496 } 1497 1498 static void gpmc_mem_init(struct gpmc_device *gpmc) 1499 { 1500 int cs; 1501 1502 if (!gpmc->data) { 1503 /* All legacy devices have same data IO window */ 1504 gpmc_mem_root.start = GPMC_MEM_START; 1505 gpmc_mem_root.end = GPMC_MEM_END; 1506 } else { 1507 gpmc_mem_root.start = gpmc->data->start; 1508 gpmc_mem_root.end = gpmc->data->end; 1509 } 1510 1511 /* Reserve all regions that has been set up by bootloader */ 1512 for (cs = 0; cs < gpmc_cs_num; cs++) { 1513 u32 base, size; 1514 1515 if (!gpmc_cs_mem_enabled(cs)) 1516 continue; 1517 gpmc_cs_get_memconf(cs, &base, &size); 1518 if (gpmc_cs_insert_mem(cs, base, size)) { 1519 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", 1520 __func__, cs, base, base + size); 1521 gpmc_cs_disable_mem(cs); 1522 } 1523 } 1524 } 1525 1526 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) 1527 { 1528 u32 temp; 1529 int div; 1530 1531 div = gpmc_calc_divider(sync_clk); 1532 temp = gpmc_ps_to_ticks(time_ps); 1533 temp = (temp + div - 1) / div; 1534 return gpmc_ticks_to_ps(temp * div); 1535 } 1536 1537 /* XXX: can the cycles be avoided ? */ 1538 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, 1539 struct gpmc_device_timings *dev_t, 1540 bool mux) 1541 { 1542 u32 temp; 1543 1544 /* adv_rd_off */ 1545 temp = dev_t->t_avdp_r; 1546 /* XXX: mux check required ? */ 1547 if (mux) { 1548 /* XXX: t_avdp not to be required for sync, only added for tusb 1549 * this indirectly necessitates requirement of t_avdp_r and 1550 * t_avdp_w instead of having a single t_avdp 1551 */ 1552 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); 1553 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1554 } 1555 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1556 1557 /* oe_on */ 1558 temp = dev_t->t_oeasu; /* XXX: remove this ? */ 1559 if (mux) { 1560 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); 1561 temp = max_t(u32, temp, gpmc_t->adv_rd_off + 1562 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); 1563 } 1564 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1565 1566 /* access */ 1567 /* XXX: any scope for improvement ?, by combining oe_on 1568 * and clk_activation, need to check whether 1569 * access = clk_activation + round to sync clk ? 1570 */ 1571 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); 1572 temp += gpmc_t->clk_activation; 1573 if (dev_t->cyc_oe) 1574 temp = max_t(u32, temp, gpmc_t->oe_on + 1575 gpmc_ticks_to_ps(dev_t->cyc_oe)); 1576 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1577 1578 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1579 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1580 1581 /* rd_cycle */ 1582 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); 1583 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + 1584 gpmc_t->access; 1585 /* XXX: barter t_ce_rdyz with t_cez_r ? */ 1586 if (dev_t->t_ce_rdyz) 1587 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); 1588 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1589 1590 return 0; 1591 } 1592 1593 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, 1594 struct gpmc_device_timings *dev_t, 1595 bool mux) 1596 { 1597 u32 temp; 1598 1599 /* adv_wr_off */ 1600 temp = dev_t->t_avdp_w; 1601 if (mux) { 1602 temp = max_t(u32, temp, 1603 gpmc_t->clk_activation + dev_t->t_avdh); 1604 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1605 } 1606 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1607 1608 /* wr_data_mux_bus */ 1609 temp = max_t(u32, dev_t->t_weasu, 1610 gpmc_t->clk_activation + dev_t->t_rdyo); 1611 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, 1612 * and in that case remember to handle we_on properly 1613 */ 1614 if (mux) { 1615 temp = max_t(u32, temp, 1616 gpmc_t->adv_wr_off + dev_t->t_aavdh); 1617 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1618 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1619 } 1620 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1621 1622 /* we_on */ 1623 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1624 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1625 else 1626 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1627 1628 /* wr_access */ 1629 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ 1630 gpmc_t->wr_access = gpmc_t->access; 1631 1632 /* we_off */ 1633 temp = gpmc_t->we_on + dev_t->t_wpl; 1634 temp = max_t(u32, temp, 1635 gpmc_t->wr_access + gpmc_ticks_to_ps(1)); 1636 temp = max_t(u32, temp, 1637 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); 1638 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1639 1640 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1641 dev_t->t_wph); 1642 1643 /* wr_cycle */ 1644 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); 1645 temp += gpmc_t->wr_access; 1646 /* XXX: barter t_ce_rdyz with t_cez_w ? */ 1647 if (dev_t->t_ce_rdyz) 1648 temp = max_t(u32, temp, 1649 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); 1650 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1651 1652 return 0; 1653 } 1654 1655 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, 1656 struct gpmc_device_timings *dev_t, 1657 bool mux) 1658 { 1659 u32 temp; 1660 1661 /* adv_rd_off */ 1662 temp = dev_t->t_avdp_r; 1663 if (mux) 1664 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1665 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1666 1667 /* oe_on */ 1668 temp = dev_t->t_oeasu; 1669 if (mux) 1670 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh); 1671 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1672 1673 /* access */ 1674 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ 1675 gpmc_t->oe_on + dev_t->t_oe); 1676 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce); 1677 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa); 1678 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1679 1680 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1681 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1682 1683 /* rd_cycle */ 1684 temp = max_t(u32, dev_t->t_rd_cycle, 1685 gpmc_t->cs_rd_off + dev_t->t_cez_r); 1686 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); 1687 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1688 1689 return 0; 1690 } 1691 1692 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, 1693 struct gpmc_device_timings *dev_t, 1694 bool mux) 1695 { 1696 u32 temp; 1697 1698 /* adv_wr_off */ 1699 temp = dev_t->t_avdp_w; 1700 if (mux) 1701 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1702 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1703 1704 /* wr_data_mux_bus */ 1705 temp = dev_t->t_weasu; 1706 if (mux) { 1707 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); 1708 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1709 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1710 } 1711 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1712 1713 /* we_on */ 1714 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1715 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1716 else 1717 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1718 1719 /* we_off */ 1720 temp = gpmc_t->we_on + dev_t->t_wpl; 1721 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1722 1723 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1724 dev_t->t_wph); 1725 1726 /* wr_cycle */ 1727 temp = max_t(u32, dev_t->t_wr_cycle, 1728 gpmc_t->cs_wr_off + dev_t->t_cez_w); 1729 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1730 1731 return 0; 1732 } 1733 1734 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, 1735 struct gpmc_device_timings *dev_t) 1736 { 1737 u32 temp; 1738 1739 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * 1740 gpmc_get_fclk_period(); 1741 1742 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( 1743 dev_t->t_bacc, 1744 gpmc_t->sync_clk); 1745 1746 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); 1747 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); 1748 1749 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) 1750 return 0; 1751 1752 if (dev_t->ce_xdelay) 1753 gpmc_t->bool_timings.cs_extra_delay = true; 1754 if (dev_t->avd_xdelay) 1755 gpmc_t->bool_timings.adv_extra_delay = true; 1756 if (dev_t->oe_xdelay) 1757 gpmc_t->bool_timings.oe_extra_delay = true; 1758 if (dev_t->we_xdelay) 1759 gpmc_t->bool_timings.we_extra_delay = true; 1760 1761 return 0; 1762 } 1763 1764 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, 1765 struct gpmc_device_timings *dev_t, 1766 bool sync) 1767 { 1768 u32 temp; 1769 1770 /* cs_on */ 1771 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); 1772 1773 /* adv_on */ 1774 temp = dev_t->t_avdasu; 1775 if (dev_t->t_ce_avd) 1776 temp = max_t(u32, temp, 1777 gpmc_t->cs_on + dev_t->t_ce_avd); 1778 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); 1779 1780 if (sync) 1781 gpmc_calc_sync_common_timings(gpmc_t, dev_t); 1782 1783 return 0; 1784 } 1785 1786 /* 1787 * TODO: remove this function once all peripherals are confirmed to 1788 * work with generic timing. Simultaneously gpmc_cs_set_timings() 1789 * has to be modified to handle timings in ps instead of ns 1790 */ 1791 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) 1792 { 1793 t->cs_on /= 1000; 1794 t->cs_rd_off /= 1000; 1795 t->cs_wr_off /= 1000; 1796 t->adv_on /= 1000; 1797 t->adv_rd_off /= 1000; 1798 t->adv_wr_off /= 1000; 1799 t->we_on /= 1000; 1800 t->we_off /= 1000; 1801 t->oe_on /= 1000; 1802 t->oe_off /= 1000; 1803 t->page_burst_access /= 1000; 1804 t->access /= 1000; 1805 t->rd_cycle /= 1000; 1806 t->wr_cycle /= 1000; 1807 t->bus_turnaround /= 1000; 1808 t->cycle2cycle_delay /= 1000; 1809 t->wait_monitoring /= 1000; 1810 t->clk_activation /= 1000; 1811 t->wr_access /= 1000; 1812 t->wr_data_mux_bus /= 1000; 1813 } 1814 1815 int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 1816 struct gpmc_settings *gpmc_s, 1817 struct gpmc_device_timings *dev_t) 1818 { 1819 bool mux = false, sync = false; 1820 1821 if (gpmc_s) { 1822 mux = gpmc_s->mux_add_data ? true : false; 1823 sync = (gpmc_s->sync_read || gpmc_s->sync_write); 1824 } 1825 1826 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1827 1828 gpmc_calc_common_timings(gpmc_t, dev_t, sync); 1829 1830 if (gpmc_s && gpmc_s->sync_read) 1831 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); 1832 else 1833 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); 1834 1835 if (gpmc_s && gpmc_s->sync_write) 1836 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); 1837 else 1838 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); 1839 1840 /* TODO: remove, see function definition */ 1841 gpmc_convert_ps_to_ns(gpmc_t); 1842 1843 return 0; 1844 } 1845 1846 /** 1847 * gpmc_cs_program_settings - programs non-timing related settings 1848 * @cs: GPMC chip-select to program 1849 * @p: pointer to GPMC settings structure 1850 * 1851 * Programs non-timing related settings for a GPMC chip-select, such as 1852 * bus-width, burst configuration, etc. Function should be called once 1853 * for each chip-select that is being used and must be called before 1854 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 1855 * register will be initialised to zero by this function. Returns 0 on 1856 * success and appropriate negative error code on failure. 1857 */ 1858 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) 1859 { 1860 u32 config1; 1861 1862 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { 1863 pr_err("%s: invalid width %d!", __func__, p->device_width); 1864 return -EINVAL; 1865 } 1866 1867 /* Address-data multiplexing not supported for NAND devices */ 1868 if (p->device_nand && p->mux_add_data) { 1869 pr_err("%s: invalid configuration!\n", __func__); 1870 return -EINVAL; 1871 } 1872 1873 if ((p->mux_add_data > GPMC_MUX_AD) || 1874 ((p->mux_add_data == GPMC_MUX_AAD) && 1875 !(gpmc_capability & GPMC_HAS_MUX_AAD))) { 1876 pr_err("%s: invalid multiplex configuration!\n", __func__); 1877 return -EINVAL; 1878 } 1879 1880 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ 1881 if (p->burst_read || p->burst_write) { 1882 switch (p->burst_len) { 1883 case GPMC_BURST_4: 1884 case GPMC_BURST_8: 1885 case GPMC_BURST_16: 1886 break; 1887 default: 1888 pr_err("%s: invalid page/burst-length (%d)\n", 1889 __func__, p->burst_len); 1890 return -EINVAL; 1891 } 1892 } 1893 1894 if (p->wait_pin != GPMC_WAITPIN_INVALID && 1895 p->wait_pin > gpmc_nr_waitpins) { 1896 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); 1897 return -EINVAL; 1898 } 1899 1900 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); 1901 1902 if (p->sync_read) 1903 config1 |= GPMC_CONFIG1_READTYPE_SYNC; 1904 if (p->sync_write) 1905 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; 1906 if (p->wait_on_read) 1907 config1 |= GPMC_CONFIG1_WAIT_READ_MON; 1908 if (p->wait_on_write) 1909 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; 1910 if (p->wait_on_read || p->wait_on_write) 1911 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); 1912 if (p->device_nand) 1913 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); 1914 if (p->mux_add_data) 1915 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); 1916 if (p->burst_read) 1917 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; 1918 if (p->burst_write) 1919 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; 1920 if (p->burst_read || p->burst_write) { 1921 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); 1922 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; 1923 } 1924 1925 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); 1926 1927 if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) { 1928 config1 = gpmc_read_reg(GPMC_CONFIG); 1929 1930 if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW) 1931 config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); 1932 else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH) 1933 config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); 1934 1935 gpmc_write_reg(GPMC_CONFIG, config1); 1936 } 1937 1938 return 0; 1939 } 1940 1941 #ifdef CONFIG_OF 1942 static void gpmc_cs_set_name(int cs, const char *name) 1943 { 1944 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 1945 1946 gpmc->name = name; 1947 } 1948 1949 static const char *gpmc_cs_get_name(int cs) 1950 { 1951 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 1952 1953 return gpmc->name; 1954 } 1955 1956 /** 1957 * gpmc_cs_remap - remaps a chip-select physical base address 1958 * @cs: chip-select to remap 1959 * @base: physical base address to re-map chip-select to 1960 * 1961 * Re-maps a chip-select to a new physical base address specified by 1962 * "base". Returns 0 on success and appropriate negative error code 1963 * on failure. 1964 */ 1965 static int gpmc_cs_remap(int cs, u32 base) 1966 { 1967 int ret; 1968 u32 old_base, size; 1969 1970 if (cs >= gpmc_cs_num) { 1971 pr_err("%s: requested chip-select is disabled\n", __func__); 1972 return -ENODEV; 1973 } 1974 1975 /* 1976 * Make sure we ignore any device offsets from the GPMC partition 1977 * allocated for the chip select and that the new base confirms 1978 * to the GPMC 16MB minimum granularity. 1979 */ 1980 base &= ~(SZ_16M - 1); 1981 1982 gpmc_cs_get_memconf(cs, &old_base, &size); 1983 if (base == old_base) 1984 return 0; 1985 1986 ret = gpmc_cs_delete_mem(cs); 1987 if (ret < 0) 1988 return ret; 1989 1990 ret = gpmc_cs_insert_mem(cs, base, size); 1991 if (ret < 0) 1992 return ret; 1993 1994 ret = gpmc_cs_set_memconf(cs, base, size); 1995 1996 return ret; 1997 } 1998 1999 /** 2000 * gpmc_read_settings_dt - read gpmc settings from device-tree 2001 * @np: pointer to device-tree node for a gpmc child device 2002 * @p: pointer to gpmc settings structure 2003 * 2004 * Reads the GPMC settings for a GPMC child device from device-tree and 2005 * stores them in the GPMC settings structure passed. The GPMC settings 2006 * structure is initialised to zero by this function and so any 2007 * previously stored settings will be cleared. 2008 */ 2009 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 2010 { 2011 memset(p, 0, sizeof(struct gpmc_settings)); 2012 2013 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 2014 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 2015 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 2016 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 2017 2018 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { 2019 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); 2020 p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); 2021 p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); 2022 if (!p->burst_read && !p->burst_write) 2023 pr_warn("%s: page/burst-length set but not used!\n", 2024 __func__); 2025 } 2026 2027 p->wait_pin = GPMC_WAITPIN_INVALID; 2028 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; 2029 2030 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { 2031 if (!gpmc_is_valid_waitpin(p->wait_pin)) { 2032 pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin); 2033 p->wait_pin = GPMC_WAITPIN_INVALID; 2034 } 2035 2036 if (!of_property_read_u32(np, "ti,wait-pin-polarity", 2037 &p->wait_pin_polarity)) { 2038 if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH && 2039 p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) { 2040 pr_err("%s: Invalid wait-pin-polarity (%d)\n", 2041 __func__, p->wait_pin_polarity); 2042 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; 2043 } 2044 } 2045 2046 p->wait_on_read = of_property_read_bool(np, 2047 "gpmc,wait-on-read"); 2048 p->wait_on_write = of_property_read_bool(np, 2049 "gpmc,wait-on-write"); 2050 if (!p->wait_on_read && !p->wait_on_write) 2051 pr_debug("%s: rd/wr wait monitoring not enabled!\n", 2052 __func__); 2053 } 2054 } 2055 2056 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, 2057 struct gpmc_timings *gpmc_t) 2058 { 2059 struct gpmc_bool_timings *p; 2060 2061 if (!np || !gpmc_t) 2062 return; 2063 2064 memset(gpmc_t, 0, sizeof(*gpmc_t)); 2065 2066 /* minimum clock period for syncronous mode */ 2067 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); 2068 2069 /* chip select timtings */ 2070 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); 2071 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); 2072 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); 2073 2074 /* ADV signal timings */ 2075 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); 2076 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); 2077 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); 2078 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", 2079 &gpmc_t->adv_aad_mux_on); 2080 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", 2081 &gpmc_t->adv_aad_mux_rd_off); 2082 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", 2083 &gpmc_t->adv_aad_mux_wr_off); 2084 2085 /* WE signal timings */ 2086 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); 2087 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); 2088 2089 /* OE signal timings */ 2090 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); 2091 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); 2092 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", 2093 &gpmc_t->oe_aad_mux_on); 2094 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", 2095 &gpmc_t->oe_aad_mux_off); 2096 2097 /* access and cycle timings */ 2098 of_property_read_u32(np, "gpmc,page-burst-access-ns", 2099 &gpmc_t->page_burst_access); 2100 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); 2101 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); 2102 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); 2103 of_property_read_u32(np, "gpmc,bus-turnaround-ns", 2104 &gpmc_t->bus_turnaround); 2105 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", 2106 &gpmc_t->cycle2cycle_delay); 2107 of_property_read_u32(np, "gpmc,wait-monitoring-ns", 2108 &gpmc_t->wait_monitoring); 2109 of_property_read_u32(np, "gpmc,clk-activation-ns", 2110 &gpmc_t->clk_activation); 2111 2112 /* only applicable to OMAP3+ */ 2113 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); 2114 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", 2115 &gpmc_t->wr_data_mux_bus); 2116 2117 /* bool timing parameters */ 2118 p = &gpmc_t->bool_timings; 2119 2120 p->cycle2cyclediffcsen = 2121 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); 2122 p->cycle2cyclesamecsen = 2123 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); 2124 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); 2125 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); 2126 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); 2127 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); 2128 p->time_para_granularity = 2129 of_property_read_bool(np, "gpmc,time-para-granularity"); 2130 } 2131 2132 /** 2133 * gpmc_probe_generic_child - configures the gpmc for a child device 2134 * @pdev: pointer to gpmc platform device 2135 * @child: pointer to device-tree node for child device 2136 * 2137 * Allocates and configures a GPMC chip-select for a child device. 2138 * Returns 0 on success and appropriate negative error code on failure. 2139 */ 2140 static int gpmc_probe_generic_child(struct platform_device *pdev, 2141 struct device_node *child) 2142 { 2143 struct gpmc_settings gpmc_s; 2144 struct gpmc_timings gpmc_t; 2145 struct resource res; 2146 unsigned long base; 2147 const char *name; 2148 int ret, cs; 2149 u32 val; 2150 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2151 2152 if (of_property_read_u32(child, "reg", &cs) < 0) { 2153 dev_err(&pdev->dev, "%pOF has no 'reg' property\n", 2154 child); 2155 return -ENODEV; 2156 } 2157 2158 if (of_address_to_resource(child, 0, &res) < 0) { 2159 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n", 2160 child); 2161 return -ENODEV; 2162 } 2163 2164 /* 2165 * Check if we have multiple instances of the same device 2166 * on a single chip select. If so, use the already initialized 2167 * timings. 2168 */ 2169 name = gpmc_cs_get_name(cs); 2170 if (name && of_node_name_eq(child, name)) 2171 goto no_timings; 2172 2173 ret = gpmc_cs_request(cs, resource_size(&res), &base); 2174 if (ret < 0) { 2175 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); 2176 return ret; 2177 } 2178 gpmc_cs_set_name(cs, child->full_name); 2179 2180 gpmc_read_settings_dt(child, &gpmc_s); 2181 gpmc_read_timings_dt(child, &gpmc_t); 2182 2183 /* 2184 * For some GPMC devices we still need to rely on the bootloader 2185 * timings because the devices can be connected via FPGA. 2186 * REVISIT: Add timing support from slls644g.pdf. 2187 */ 2188 if (!gpmc_t.cs_rd_off) { 2189 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", 2190 cs); 2191 gpmc_cs_show_timings(cs, 2192 "please add GPMC bootloader timings to .dts"); 2193 goto no_timings; 2194 } 2195 2196 /* CS must be disabled while making changes to gpmc configuration */ 2197 gpmc_cs_disable_mem(cs); 2198 2199 /* 2200 * FIXME: gpmc_cs_request() will map the CS to an arbitrary 2201 * location in the gpmc address space. When booting with 2202 * device-tree we want the NOR flash to be mapped to the 2203 * location specified in the device-tree blob. So remap the 2204 * CS to this location. Once DT migration is complete should 2205 * just make gpmc_cs_request() map a specific address. 2206 */ 2207 ret = gpmc_cs_remap(cs, res.start); 2208 if (ret < 0) { 2209 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", 2210 cs, &res.start); 2211 if (res.start < GPMC_MEM_START) { 2212 dev_info(&pdev->dev, 2213 "GPMC CS %d start cannot be lesser than 0x%x\n", 2214 cs, GPMC_MEM_START); 2215 } else if (res.end > GPMC_MEM_END) { 2216 dev_info(&pdev->dev, 2217 "GPMC CS %d end cannot be greater than 0x%x\n", 2218 cs, GPMC_MEM_END); 2219 } 2220 goto err; 2221 } 2222 2223 if (of_match_node(omap_nand_ids, child)) { 2224 /* NAND specific setup */ 2225 val = 8; 2226 of_property_read_u32(child, "nand-bus-width", &val); 2227 switch (val) { 2228 case 8: 2229 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT; 2230 break; 2231 case 16: 2232 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT; 2233 break; 2234 default: 2235 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n", 2236 child); 2237 ret = -EINVAL; 2238 goto err; 2239 } 2240 2241 /* disable write protect */ 2242 gpmc_configure(GPMC_CONFIG_WP, 0); 2243 gpmc_s.device_nand = true; 2244 } else { 2245 ret = of_property_read_u32(child, "bank-width", 2246 &gpmc_s.device_width); 2247 if (ret < 0 && !gpmc_s.device_width) { 2248 dev_err(&pdev->dev, 2249 "%pOF has no 'gpmc,device-width' property\n", 2250 child); 2251 goto err; 2252 } 2253 } 2254 2255 /* Reserve wait pin if it is required and valid */ 2256 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { 2257 ret = gpmc_alloc_waitpin(gpmc, &gpmc_s); 2258 if (ret < 0) 2259 goto err; 2260 } 2261 2262 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); 2263 2264 ret = gpmc_cs_program_settings(cs, &gpmc_s); 2265 if (ret < 0) 2266 goto err_cs; 2267 2268 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 2269 if (ret) { 2270 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n", 2271 child); 2272 goto err_cs; 2273 } 2274 2275 /* Clear limited address i.e. enable A26-A11 */ 2276 val = gpmc_read_reg(GPMC_CONFIG); 2277 val &= ~GPMC_CONFIG_LIMITEDADDRESS; 2278 gpmc_write_reg(GPMC_CONFIG, val); 2279 2280 /* Enable CS region */ 2281 gpmc_cs_enable_mem(cs); 2282 2283 no_timings: 2284 2285 /* create platform device, NULL on error or when disabled */ 2286 if (!of_platform_device_create(child, NULL, &pdev->dev)) 2287 goto err_child_fail; 2288 2289 /* create children and other common bus children */ 2290 if (of_platform_default_populate(child, NULL, &pdev->dev)) 2291 goto err_child_fail; 2292 2293 return 0; 2294 2295 err_child_fail: 2296 2297 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child); 2298 ret = -ENODEV; 2299 2300 err_cs: 2301 gpmc_free_waitpin(gpmc, gpmc_s.wait_pin); 2302 err: 2303 gpmc_cs_free(cs); 2304 2305 return ret; 2306 } 2307 2308 static const struct of_device_id gpmc_dt_ids[]; 2309 2310 static int gpmc_probe_dt(struct platform_device *pdev) 2311 { 2312 int ret; 2313 const struct of_device_id *of_id = 2314 of_match_device(gpmc_dt_ids, &pdev->dev); 2315 2316 if (!of_id) 2317 return 0; 2318 2319 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", 2320 &gpmc_cs_num); 2321 if (ret < 0) { 2322 pr_err("%s: number of chip-selects not defined\n", __func__); 2323 return ret; 2324 } else if (gpmc_cs_num < 1) { 2325 pr_err("%s: all chip-selects are disabled\n", __func__); 2326 return -EINVAL; 2327 } else if (gpmc_cs_num > GPMC_CS_NUM) { 2328 pr_err("%s: number of supported chip-selects cannot be > %d\n", 2329 __func__, GPMC_CS_NUM); 2330 return -EINVAL; 2331 } 2332 2333 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 2334 &gpmc_nr_waitpins); 2335 if (ret < 0) { 2336 pr_err("%s: number of wait pins not found!\n", __func__); 2337 return ret; 2338 } 2339 2340 return 0; 2341 } 2342 2343 static void gpmc_probe_dt_children(struct platform_device *pdev) 2344 { 2345 int ret; 2346 struct device_node *child; 2347 2348 for_each_available_child_of_node(pdev->dev.of_node, child) { 2349 ret = gpmc_probe_generic_child(pdev, child); 2350 if (ret) { 2351 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n", 2352 child, ret); 2353 } 2354 } 2355 } 2356 #else 2357 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 2358 { 2359 memset(p, 0, sizeof(*p)); 2360 } 2361 static int gpmc_probe_dt(struct platform_device *pdev) 2362 { 2363 return 0; 2364 } 2365 2366 static void gpmc_probe_dt_children(struct platform_device *pdev) 2367 { 2368 } 2369 #endif /* CONFIG_OF */ 2370 2371 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 2372 { 2373 return GPIO_LINE_DIRECTION_IN; /* we're input only */ 2374 } 2375 2376 static int gpmc_gpio_direction_input(struct gpio_chip *chip, 2377 unsigned int offset) 2378 { 2379 return 0; /* we're input only */ 2380 } 2381 2382 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset) 2383 { 2384 u32 reg; 2385 2386 offset += 8; 2387 2388 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); 2389 2390 return !!reg; 2391 } 2392 2393 static int gpmc_gpio_init(struct gpmc_device *gpmc) 2394 { 2395 int ret; 2396 2397 gpmc->gpio_chip.parent = gpmc->dev; 2398 gpmc->gpio_chip.owner = THIS_MODULE; 2399 gpmc->gpio_chip.label = DEVICE_NAME; 2400 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; 2401 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; 2402 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; 2403 gpmc->gpio_chip.get = gpmc_gpio_get; 2404 gpmc->gpio_chip.base = -1; 2405 2406 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL); 2407 if (ret < 0) { 2408 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); 2409 return ret; 2410 } 2411 2412 return 0; 2413 } 2414 2415 static void omap3_gpmc_save_context(struct gpmc_device *gpmc) 2416 { 2417 struct omap3_gpmc_regs *gpmc_context; 2418 int i; 2419 2420 if (!gpmc || !gpmc_base) 2421 return; 2422 2423 gpmc_context = &gpmc->context; 2424 2425 gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); 2426 gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE); 2427 gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); 2428 gpmc_context->config = gpmc_read_reg(GPMC_CONFIG); 2429 gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 2430 gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 2431 gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 2432 for (i = 0; i < gpmc_cs_num; i++) { 2433 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 2434 if (gpmc_context->cs_context[i].is_valid) { 2435 gpmc_context->cs_context[i].config1 = 2436 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); 2437 gpmc_context->cs_context[i].config2 = 2438 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); 2439 gpmc_context->cs_context[i].config3 = 2440 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); 2441 gpmc_context->cs_context[i].config4 = 2442 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); 2443 gpmc_context->cs_context[i].config5 = 2444 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); 2445 gpmc_context->cs_context[i].config6 = 2446 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); 2447 gpmc_context->cs_context[i].config7 = 2448 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); 2449 } 2450 } 2451 } 2452 2453 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc) 2454 { 2455 struct omap3_gpmc_regs *gpmc_context; 2456 int i; 2457 2458 if (!gpmc || !gpmc_base) 2459 return; 2460 2461 gpmc_context = &gpmc->context; 2462 2463 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig); 2464 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable); 2465 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl); 2466 gpmc_write_reg(GPMC_CONFIG, gpmc_context->config); 2467 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1); 2468 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2); 2469 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control); 2470 for (i = 0; i < gpmc_cs_num; i++) { 2471 if (gpmc_context->cs_context[i].is_valid) { 2472 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 2473 gpmc_context->cs_context[i].config1); 2474 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, 2475 gpmc_context->cs_context[i].config2); 2476 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, 2477 gpmc_context->cs_context[i].config3); 2478 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, 2479 gpmc_context->cs_context[i].config4); 2480 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, 2481 gpmc_context->cs_context[i].config5); 2482 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, 2483 gpmc_context->cs_context[i].config6); 2484 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 2485 gpmc_context->cs_context[i].config7); 2486 } else { 2487 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0); 2488 } 2489 } 2490 } 2491 2492 static int omap_gpmc_context_notifier(struct notifier_block *nb, 2493 unsigned long cmd, void *v) 2494 { 2495 struct gpmc_device *gpmc; 2496 2497 gpmc = container_of(nb, struct gpmc_device, nb); 2498 if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev)) 2499 return NOTIFY_OK; 2500 2501 switch (cmd) { 2502 case CPU_CLUSTER_PM_ENTER: 2503 omap3_gpmc_save_context(gpmc); 2504 break; 2505 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 2506 break; 2507 case CPU_CLUSTER_PM_EXIT: 2508 omap3_gpmc_restore_context(gpmc); 2509 break; 2510 } 2511 2512 return NOTIFY_OK; 2513 } 2514 2515 static int gpmc_probe(struct platform_device *pdev) 2516 { 2517 int rc, i; 2518 u32 l; 2519 struct resource *res; 2520 struct gpmc_device *gpmc; 2521 2522 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); 2523 if (!gpmc) 2524 return -ENOMEM; 2525 2526 gpmc->dev = &pdev->dev; 2527 platform_set_drvdata(pdev, gpmc); 2528 2529 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 2530 if (!res) { 2531 /* legacy DT */ 2532 gpmc_base = devm_platform_ioremap_resource(pdev, 0); 2533 if (IS_ERR(gpmc_base)) 2534 return PTR_ERR(gpmc_base); 2535 } else { 2536 gpmc_base = devm_ioremap_resource(&pdev->dev, res); 2537 if (IS_ERR(gpmc_base)) 2538 return PTR_ERR(gpmc_base); 2539 2540 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data"); 2541 if (!res) { 2542 dev_err(&pdev->dev, "couldn't get data reg resource\n"); 2543 return -ENOENT; 2544 } 2545 2546 gpmc->data = res; 2547 } 2548 2549 gpmc->irq = platform_get_irq(pdev, 0); 2550 if (gpmc->irq < 0) 2551 return gpmc->irq; 2552 2553 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); 2554 if (IS_ERR(gpmc_l3_clk)) { 2555 dev_err(&pdev->dev, "Failed to get GPMC fck\n"); 2556 return PTR_ERR(gpmc_l3_clk); 2557 } 2558 2559 if (!clk_get_rate(gpmc_l3_clk)) { 2560 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); 2561 return -EINVAL; 2562 } 2563 2564 if (pdev->dev.of_node) { 2565 rc = gpmc_probe_dt(pdev); 2566 if (rc) 2567 return rc; 2568 } else { 2569 gpmc_cs_num = GPMC_CS_NUM; 2570 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 2571 } 2572 2573 gpmc->waitpins = devm_kzalloc(&pdev->dev, 2574 gpmc_nr_waitpins * sizeof(struct gpmc_waitpin), 2575 GFP_KERNEL); 2576 if (!gpmc->waitpins) 2577 return -ENOMEM; 2578 2579 for (i = 0; i < gpmc_nr_waitpins; i++) 2580 gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID; 2581 2582 pm_runtime_enable(&pdev->dev); 2583 pm_runtime_get_sync(&pdev->dev); 2584 2585 l = gpmc_read_reg(GPMC_REVISION); 2586 2587 /* 2588 * FIXME: Once device-tree migration is complete the below flags 2589 * should be populated based upon the device-tree compatible 2590 * string. For now just use the IP revision. OMAP3+ devices have 2591 * the wr_access and wr_data_mux_bus register fields. OMAP4+ 2592 * devices support the addr-addr-data multiplex protocol. 2593 * 2594 * GPMC IP revisions: 2595 * - OMAP24xx = 2.0 2596 * - OMAP3xxx = 5.0 2597 * - OMAP44xx/54xx/AM335x = 6.0 2598 */ 2599 if (GPMC_REVISION_MAJOR(l) > 0x4) 2600 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; 2601 if (GPMC_REVISION_MAJOR(l) > 0x5) 2602 gpmc_capability |= GPMC_HAS_MUX_AAD; 2603 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), 2604 GPMC_REVISION_MINOR(l)); 2605 2606 gpmc_mem_init(gpmc); 2607 rc = gpmc_gpio_init(gpmc); 2608 if (rc) 2609 goto gpio_init_failed; 2610 2611 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins; 2612 rc = gpmc_setup_irq(gpmc); 2613 if (rc) { 2614 dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); 2615 goto gpio_init_failed; 2616 } 2617 2618 gpmc_probe_dt_children(pdev); 2619 2620 gpmc->nb.notifier_call = omap_gpmc_context_notifier; 2621 cpu_pm_register_notifier(&gpmc->nb); 2622 2623 return 0; 2624 2625 gpio_init_failed: 2626 gpmc_mem_exit(); 2627 pm_runtime_put_sync(&pdev->dev); 2628 pm_runtime_disable(&pdev->dev); 2629 2630 return rc; 2631 } 2632 2633 static void gpmc_remove(struct platform_device *pdev) 2634 { 2635 int i; 2636 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2637 2638 cpu_pm_unregister_notifier(&gpmc->nb); 2639 for (i = 0; i < gpmc_nr_waitpins; i++) 2640 gpmc_free_waitpin(gpmc, i); 2641 gpmc_free_irq(gpmc); 2642 gpmc_mem_exit(); 2643 pm_runtime_put_sync(&pdev->dev); 2644 pm_runtime_disable(&pdev->dev); 2645 } 2646 2647 #ifdef CONFIG_PM_SLEEP 2648 static int gpmc_suspend(struct device *dev) 2649 { 2650 struct gpmc_device *gpmc = dev_get_drvdata(dev); 2651 2652 omap3_gpmc_save_context(gpmc); 2653 pm_runtime_put_sync(dev); 2654 gpmc->is_suspended = 1; 2655 2656 return 0; 2657 } 2658 2659 static int gpmc_resume(struct device *dev) 2660 { 2661 struct gpmc_device *gpmc = dev_get_drvdata(dev); 2662 2663 pm_runtime_get_sync(dev); 2664 omap3_gpmc_restore_context(gpmc); 2665 gpmc->is_suspended = 0; 2666 2667 return 0; 2668 } 2669 #endif 2670 2671 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); 2672 2673 #ifdef CONFIG_OF 2674 static const struct of_device_id gpmc_dt_ids[] = { 2675 { .compatible = "ti,omap2420-gpmc" }, 2676 { .compatible = "ti,omap2430-gpmc" }, 2677 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ 2678 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ 2679 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ 2680 { .compatible = "ti,am64-gpmc" }, 2681 { } 2682 }; 2683 MODULE_DEVICE_TABLE(of, gpmc_dt_ids); 2684 #endif 2685 2686 static struct platform_driver gpmc_driver = { 2687 .probe = gpmc_probe, 2688 .remove = gpmc_remove, 2689 .driver = { 2690 .name = DEVICE_NAME, 2691 .of_match_table = of_match_ptr(gpmc_dt_ids), 2692 .pm = &gpmc_pm_ops, 2693 }, 2694 }; 2695 2696 module_platform_driver(gpmc_driver); 2697 2698 MODULE_DESCRIPTION("Texas Instruments GPMC driver"); 2699 MODULE_LICENSE("GPL"); 2700