1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale vf610 GPIO support through PORT and GPIO
4 *
5 * Copyright (c) 2014 Toradex AG.
6 *
7 * Author: Stefan Agner <stefan@agner.ch>.
8 */
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21
22 #define VF610_GPIO_PER_PORT 32
23
24 struct fsl_gpio_soc_data {
25 /* SoCs has a Port Data Direction Register (PDDR) */
26 bool have_paddr;
27 bool have_dual_base;
28 };
29
30 struct vf610_gpio_port {
31 struct gpio_chip gc;
32 void __iomem *base;
33 void __iomem *gpio_base;
34 const struct fsl_gpio_soc_data *sdata;
35 u8 irqc[VF610_GPIO_PER_PORT];
36 struct clk *clk_port;
37 struct clk *clk_gpio;
38 int irq;
39 };
40
41 #define GPIO_PDOR 0x00
42 #define GPIO_PSOR 0x04
43 #define GPIO_PCOR 0x08
44 #define GPIO_PTOR 0x0c
45 #define GPIO_PDIR 0x10
46 #define GPIO_PDDR 0x14
47
48 #define PORT_PCR(n) ((n) * 0x4)
49 #define PORT_PCR_IRQC_OFFSET 16
50
51 #define PORT_ISFR 0xa0
52 #define PORT_DFER 0xc0
53 #define PORT_DFCR 0xc4
54 #define PORT_DFWR 0xc8
55
56 #define PORT_INT_OFF 0x0
57 #define PORT_INT_LOGIC_ZERO 0x8
58 #define PORT_INT_RISING_EDGE 0x9
59 #define PORT_INT_FALLING_EDGE 0xa
60 #define PORT_INT_EITHER_EDGE 0xb
61 #define PORT_INT_LOGIC_ONE 0xc
62
63 #define IMX8ULP_GPIO_BASE_OFF 0x40
64 #define IMX8ULP_BASE_OFF 0x80
65
66 static const struct fsl_gpio_soc_data vf610_data = {
67 .have_dual_base = true,
68 };
69
70 static const struct fsl_gpio_soc_data imx_data = {
71 .have_paddr = true,
72 .have_dual_base = true,
73 };
74
75 static const struct fsl_gpio_soc_data imx8ulp_data = {
76 .have_paddr = true,
77 };
78
79 static const struct of_device_id vf610_gpio_dt_ids[] = {
80 { .compatible = "fsl,vf610-gpio", .data = &vf610_data },
81 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
82 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
83 { /* sentinel */ }
84 };
85
vf610_gpio_writel(u32 val,void __iomem * reg)86 static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
87 {
88 writel_relaxed(val, reg);
89 }
90
vf610_gpio_readl(void __iomem * reg)91 static inline u32 vf610_gpio_readl(void __iomem *reg)
92 {
93 return readl_relaxed(reg);
94 }
95
vf610_gpio_irq_handler(struct irq_desc * desc)96 static void vf610_gpio_irq_handler(struct irq_desc *desc)
97 {
98 struct vf610_gpio_port *port =
99 gpiochip_get_data(irq_desc_get_handler_data(desc));
100 struct irq_chip *chip = irq_desc_get_chip(desc);
101 int pin;
102 unsigned long irq_isfr;
103
104 chained_irq_enter(chip, desc);
105
106 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
107
108 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
109 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
110
111 generic_handle_domain_irq(port->gc.irq.domain, pin);
112 }
113
114 chained_irq_exit(chip, desc);
115 }
116
vf610_gpio_irq_ack(struct irq_data * d)117 static void vf610_gpio_irq_ack(struct irq_data *d)
118 {
119 struct vf610_gpio_port *port =
120 gpiochip_get_data(irq_data_get_irq_chip_data(d));
121 int gpio = d->hwirq;
122
123 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
124 }
125
vf610_gpio_irq_set_type(struct irq_data * d,u32 type)126 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
127 {
128 struct vf610_gpio_port *port =
129 gpiochip_get_data(irq_data_get_irq_chip_data(d));
130 u8 irqc;
131
132 switch (type) {
133 case IRQ_TYPE_EDGE_RISING:
134 irqc = PORT_INT_RISING_EDGE;
135 break;
136 case IRQ_TYPE_EDGE_FALLING:
137 irqc = PORT_INT_FALLING_EDGE;
138 break;
139 case IRQ_TYPE_EDGE_BOTH:
140 irqc = PORT_INT_EITHER_EDGE;
141 break;
142 case IRQ_TYPE_LEVEL_LOW:
143 irqc = PORT_INT_LOGIC_ZERO;
144 break;
145 case IRQ_TYPE_LEVEL_HIGH:
146 irqc = PORT_INT_LOGIC_ONE;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 port->irqc[d->hwirq] = irqc;
153
154 if (type & IRQ_TYPE_LEVEL_MASK)
155 irq_set_handler_locked(d, handle_level_irq);
156 else
157 irq_set_handler_locked(d, handle_edge_irq);
158
159 return 0;
160 }
161
vf610_gpio_irq_mask(struct irq_data * d)162 static void vf610_gpio_irq_mask(struct irq_data *d)
163 {
164 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
165 struct vf610_gpio_port *port = gpiochip_get_data(gc);
166 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
167 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
168
169 vf610_gpio_writel(0, pcr_base);
170 gpiochip_disable_irq(gc, gpio_num);
171 }
172
vf610_gpio_irq_unmask(struct irq_data * d)173 static void vf610_gpio_irq_unmask(struct irq_data *d)
174 {
175 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
176 struct vf610_gpio_port *port = gpiochip_get_data(gc);
177 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
178 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
179
180 gpiochip_enable_irq(gc, gpio_num);
181 vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
182 pcr_base);
183 }
184
vf610_gpio_irq_set_wake(struct irq_data * d,u32 enable)185 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
186 {
187 struct vf610_gpio_port *port =
188 gpiochip_get_data(irq_data_get_irq_chip_data(d));
189
190 if (enable)
191 enable_irq_wake(port->irq);
192 else
193 disable_irq_wake(port->irq);
194
195 return 0;
196 }
197
198 static const struct irq_chip vf610_irqchip = {
199 .name = "gpio-vf610",
200 .irq_ack = vf610_gpio_irq_ack,
201 .irq_mask = vf610_gpio_irq_mask,
202 .irq_unmask = vf610_gpio_irq_unmask,
203 .irq_set_type = vf610_gpio_irq_set_type,
204 .irq_set_wake = vf610_gpio_irq_set_wake,
205 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
206 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
207 GPIOCHIP_IRQ_RESOURCE_HELPERS,
208 };
209
vf610_gpio_disable_clk(void * data)210 static void vf610_gpio_disable_clk(void *data)
211 {
212 clk_disable_unprepare(data);
213 }
214
vf610_gpio_probe(struct platform_device * pdev)215 static int vf610_gpio_probe(struct platform_device *pdev)
216 {
217 struct device *dev = &pdev->dev;
218 struct vf610_gpio_port *port;
219 struct gpio_chip *gc;
220 struct gpio_irq_chip *girq;
221 unsigned long flags;
222 int i;
223 int ret;
224 bool dual_base;
225
226 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
227 if (!port)
228 return -ENOMEM;
229
230 port->sdata = device_get_match_data(dev);
231
232 dual_base = port->sdata->have_dual_base;
233
234 /*
235 * Handle legacy compatible combinations which used two reg values
236 * for the i.MX8ULP and i.MX93.
237 */
238 if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
239 (device_is_compatible(dev, "fsl,imx93-gpio") ||
240 (device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
241 dual_base = true;
242
243 if (dual_base) {
244 port->base = devm_platform_ioremap_resource(pdev, 0);
245 if (IS_ERR(port->base))
246 return PTR_ERR(port->base);
247
248 port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
249 if (IS_ERR(port->gpio_base))
250 return PTR_ERR(port->gpio_base);
251 } else {
252 port->base = devm_platform_ioremap_resource(pdev, 0);
253 if (IS_ERR(port->base))
254 return PTR_ERR(port->base);
255
256 port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
257 port->base = port->base + IMX8ULP_BASE_OFF;
258 }
259
260 port->irq = platform_get_irq(pdev, 0);
261 if (port->irq < 0)
262 return port->irq;
263
264 port->clk_port = devm_clk_get(dev, "port");
265 ret = PTR_ERR_OR_ZERO(port->clk_port);
266 if (!ret) {
267 ret = clk_prepare_enable(port->clk_port);
268 if (ret)
269 return ret;
270 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
271 port->clk_port);
272 if (ret)
273 return ret;
274 } else if (ret == -EPROBE_DEFER) {
275 /*
276 * Percolate deferrals, for anything else,
277 * just live without the clocking.
278 */
279 return ret;
280 }
281
282 port->clk_gpio = devm_clk_get(dev, "gpio");
283 ret = PTR_ERR_OR_ZERO(port->clk_gpio);
284 if (!ret) {
285 ret = clk_prepare_enable(port->clk_gpio);
286 if (ret)
287 return ret;
288 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
289 port->clk_gpio);
290 if (ret)
291 return ret;
292 } else if (ret == -EPROBE_DEFER) {
293 return ret;
294 }
295
296 gc = &port->gc;
297 flags = BGPIOF_PINCTRL_BACKEND;
298 /*
299 * We only read the output register for current value on output
300 * lines if the direction register is available so we can switch
301 * direction.
302 */
303 if (port->sdata->have_paddr)
304 flags |= BGPIOF_READ_OUTPUT_REG_SET;
305 ret = bgpio_init(gc, dev, 4,
306 port->gpio_base + GPIO_PDIR,
307 port->gpio_base + GPIO_PDOR,
308 NULL,
309 port->sdata->have_paddr ? port->gpio_base + GPIO_PDDR : NULL,
310 NULL,
311 flags);
312 if (ret)
313 return dev_err_probe(dev, ret, "unable to init generic GPIO\n");
314 gc->label = dev_name(dev);
315 gc->base = -1;
316
317 /* Mask all GPIO interrupts */
318 for (i = 0; i < gc->ngpio; i++)
319 vf610_gpio_writel(0, port->base + PORT_PCR(i));
320
321 /* Clear the interrupt status register for all GPIO's */
322 vf610_gpio_writel(~0, port->base + PORT_ISFR);
323
324 girq = &gc->irq;
325 gpio_irq_chip_set_chip(girq, &vf610_irqchip);
326 girq->parent_handler = vf610_gpio_irq_handler;
327 girq->num_parents = 1;
328 girq->parents = devm_kcalloc(&pdev->dev, 1,
329 sizeof(*girq->parents),
330 GFP_KERNEL);
331 if (!girq->parents)
332 return -ENOMEM;
333 girq->parents[0] = port->irq;
334 girq->default_type = IRQ_TYPE_NONE;
335 girq->handler = handle_edge_irq;
336
337 return devm_gpiochip_add_data(dev, gc, port);
338 }
339
340 static struct platform_driver vf610_gpio_driver = {
341 .driver = {
342 .name = "gpio-vf610",
343 .of_match_table = vf610_gpio_dt_ids,
344 },
345 .probe = vf610_gpio_probe,
346 };
347
348 module_platform_driver(vf610_gpio_driver);
349 MODULE_DESCRIPTION("VF610 GPIO driver");
350 MODULE_LICENSE("GPL");
351