1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AppliedMicro X-Gene SoC GPIO-Standby Driver
4 *
5 * Copyright (c) 2014, Applied Micro Circuits Corporation
6 * Author: Tin Huynh <tnhuynh@apm.com>.
7 * Y Vo <yvo@apm.com>.
8 * Quan Nguyen <qnguyen@apm.com>.
9 */
10
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/types.h>
21
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/generic.h>
24
25 #include "gpiolib-acpi.h"
26
27 #define XGENE_DFLT_MAX_NGPIO 22
28 #define XGENE_DFLT_MAX_NIRQ 6
29 #define XGENE_DFLT_IRQ_START_PIN 8
30 #define GPIO_MASK(x) (1U << ((x) % 32))
31
32 #define MPA_GPIO_INT_LVL 0x0290
33 #define MPA_GPIO_OE_ADDR 0x029c
34 #define MPA_GPIO_OUT_ADDR 0x02a0
35 #define MPA_GPIO_IN_ADDR 0x02a4
36 #define MPA_GPIO_SEL_LO 0x0294
37
38 #define GPIO_INT_LEVEL_H 0x000001
39 #define GPIO_INT_LEVEL_L 0x000000
40
41 /**
42 * struct xgene_gpio_sb - GPIO-Standby private data structure.
43 * @chip: Generic GPIO chip data
44 * @regs: GPIO register base offset
45 * @irq_domain: GPIO interrupt domain
46 * @irq_start: GPIO pin that start support interrupt
47 * @nirq: Number of GPIO pins that supports interrupt
48 * @parent_irq_base: Start parent HWIRQ
49 */
50 struct xgene_gpio_sb {
51 struct gpio_generic_chip chip;
52 void __iomem *regs;
53 struct irq_domain *irq_domain;
54 u16 irq_start;
55 u16 nirq;
56 u16 parent_irq_base;
57 };
58
59 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
60 #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
61
xgene_gpio_set_bit(struct gpio_chip * gc,void __iomem * reg,u32 gpio,int val)62 static void xgene_gpio_set_bit(struct gpio_chip *gc,
63 void __iomem *reg, u32 gpio, int val)
64 {
65 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
66 u32 data;
67
68 data = gpio_generic_read_reg(chip, reg);
69 if (val)
70 data |= GPIO_MASK(gpio);
71 else
72 data &= ~GPIO_MASK(gpio);
73 gpio_generic_write_reg(chip, reg, data);
74 }
75
xgene_gpio_sb_irq_set_type(struct irq_data * d,unsigned int type)76 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
77 {
78 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
79 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
80 int lvl_type = GPIO_INT_LEVEL_H;
81
82 switch (type & IRQ_TYPE_SENSE_MASK) {
83 case IRQ_TYPE_EDGE_RISING:
84 case IRQ_TYPE_LEVEL_HIGH:
85 lvl_type = GPIO_INT_LEVEL_H;
86 break;
87 case IRQ_TYPE_EDGE_FALLING:
88 case IRQ_TYPE_LEVEL_LOW:
89 lvl_type = GPIO_INT_LEVEL_L;
90 break;
91 default:
92 break;
93 }
94
95 xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO,
96 gpio * 2, 1);
97 xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_INT_LVL,
98 d->hwirq, lvl_type);
99
100 /* Propagate IRQ type setting to parent */
101 if (type & IRQ_TYPE_EDGE_BOTH)
102 return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
103 else
104 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
105 }
106
xgene_gpio_sb_irq_mask(struct irq_data * d)107 static void xgene_gpio_sb_irq_mask(struct irq_data *d)
108 {
109 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
110
111 irq_chip_mask_parent(d);
112
113 gpiochip_disable_irq(&priv->chip.gc, d->hwirq);
114 }
115
xgene_gpio_sb_irq_unmask(struct irq_data * d)116 static void xgene_gpio_sb_irq_unmask(struct irq_data *d)
117 {
118 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
119
120 gpiochip_enable_irq(&priv->chip.gc, d->hwirq);
121
122 irq_chip_unmask_parent(d);
123 }
124
125 static const struct irq_chip xgene_gpio_sb_irq_chip = {
126 .name = "sbgpio",
127 .irq_eoi = irq_chip_eoi_parent,
128 .irq_mask = xgene_gpio_sb_irq_mask,
129 .irq_unmask = xgene_gpio_sb_irq_unmask,
130 .irq_set_type = xgene_gpio_sb_irq_set_type,
131 .flags = IRQCHIP_IMMUTABLE,
132 GPIOCHIP_IRQ_RESOURCE_HELPERS,
133 };
134
xgene_gpio_sb_to_irq(struct gpio_chip * gc,u32 gpio)135 static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
136 {
137 struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
138 struct irq_fwspec fwspec;
139
140 if ((gpio < priv->irq_start) ||
141 (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
142 return -ENXIO;
143
144 fwspec.fwnode = gc->parent->fwnode;
145 fwspec.param_count = 2;
146 fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
147 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
148 return irq_create_fwspec_mapping(&fwspec);
149 }
150
xgene_gpio_sb_domain_activate(struct irq_domain * d,struct irq_data * irq_data,bool reserve)151 static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
152 struct irq_data *irq_data,
153 bool reserve)
154 {
155 struct xgene_gpio_sb *priv = d->host_data;
156 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
157 int ret;
158
159 ret = gpiochip_lock_as_irq(&priv->chip.gc, gpio);
160 if (ret) {
161 dev_err(priv->chip.gc.parent,
162 "Unable to configure XGene GPIO standby pin %d as IRQ\n",
163 gpio);
164 return ret;
165 }
166
167 xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO,
168 gpio * 2, 1);
169 return 0;
170 }
171
xgene_gpio_sb_domain_deactivate(struct irq_domain * d,struct irq_data * irq_data)172 static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
173 struct irq_data *irq_data)
174 {
175 struct xgene_gpio_sb *priv = d->host_data;
176 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
177
178 gpiochip_unlock_as_irq(&priv->chip.gc, gpio);
179 xgene_gpio_set_bit(&priv->chip.gc, priv->regs + MPA_GPIO_SEL_LO,
180 gpio * 2, 0);
181 }
182
xgene_gpio_sb_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)183 static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
184 struct irq_fwspec *fwspec,
185 unsigned long *hwirq,
186 unsigned int *type)
187 {
188 struct xgene_gpio_sb *priv = d->host_data;
189
190 if ((fwspec->param_count != 2) ||
191 (fwspec->param[0] >= priv->nirq))
192 return -EINVAL;
193 *hwirq = fwspec->param[0];
194 *type = fwspec->param[1];
195 return 0;
196 }
197
xgene_gpio_sb_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)198 static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
199 unsigned int virq,
200 unsigned int nr_irqs, void *data)
201 {
202 struct irq_fwspec *fwspec = data;
203 struct irq_fwspec parent_fwspec;
204 struct xgene_gpio_sb *priv = domain->host_data;
205 irq_hw_number_t hwirq;
206 unsigned int i;
207
208 hwirq = fwspec->param[0];
209 for (i = 0; i < nr_irqs; i++)
210 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
211 &xgene_gpio_sb_irq_chip, priv);
212
213 parent_fwspec.fwnode = domain->parent->fwnode;
214 if (is_of_node(parent_fwspec.fwnode)) {
215 parent_fwspec.param_count = 3;
216 parent_fwspec.param[0] = 0;/* SPI */
217 /* Skip SGIs and PPIs*/
218 parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
219 parent_fwspec.param[2] = fwspec->param[1];
220 } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
221 parent_fwspec.param_count = 2;
222 parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
223 parent_fwspec.param[1] = fwspec->param[1];
224 } else
225 return -EINVAL;
226
227 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
228 &parent_fwspec);
229 }
230
231 static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
232 .translate = xgene_gpio_sb_domain_translate,
233 .alloc = xgene_gpio_sb_domain_alloc,
234 .free = irq_domain_free_irqs_common,
235 .activate = xgene_gpio_sb_domain_activate,
236 .deactivate = xgene_gpio_sb_domain_deactivate,
237 };
238
xgene_gpio_sb_probe(struct platform_device * pdev)239 static int xgene_gpio_sb_probe(struct platform_device *pdev)
240 {
241 struct gpio_generic_chip_config config;
242 struct xgene_gpio_sb *priv;
243 int ret;
244 void __iomem *regs;
245 struct irq_domain *parent_domain = NULL;
246 u32 val32;
247
248 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
249 if (!priv)
250 return -ENOMEM;
251
252 regs = devm_platform_ioremap_resource(pdev, 0);
253 if (IS_ERR(regs))
254 return PTR_ERR(regs);
255
256 priv->regs = regs;
257
258 ret = platform_get_irq(pdev, 0);
259 if (ret > 0) {
260 priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
261 parent_domain = irq_get_irq_data(ret)->domain;
262 }
263 if (!parent_domain) {
264 dev_err(&pdev->dev, "unable to obtain parent domain\n");
265 return -ENODEV;
266 }
267
268 config = (struct gpio_generic_chip_config) {
269 .dev = &pdev->dev,
270 .sz = 4,
271 .dat = regs + MPA_GPIO_IN_ADDR,
272 .set = regs + MPA_GPIO_OUT_ADDR,
273 .dirout = regs + MPA_GPIO_OE_ADDR,
274 };
275
276 ret = gpio_generic_chip_init(&priv->chip, &config);
277 if (ret)
278 return ret;
279
280 priv->chip.gc.to_irq = xgene_gpio_sb_to_irq;
281
282 /* Retrieve start irq pin, use default if property not found */
283 priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
284 if (!device_property_read_u32(&pdev->dev, "apm,irq-start", &val32))
285 priv->irq_start = val32;
286
287 /* Retrieve number irqs, use default if property not found */
288 priv->nirq = XGENE_DFLT_MAX_NIRQ;
289 if (!device_property_read_u32(&pdev->dev, "apm,nr-irqs", &val32))
290 priv->nirq = val32;
291
292 /* Retrieve number gpio, use default if property not found */
293 priv->chip.gc.ngpio = XGENE_DFLT_MAX_NGPIO;
294 if (!device_property_read_u32(&pdev->dev, "apm,nr-gpios", &val32))
295 priv->chip.gc.ngpio = val32;
296
297 dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
298 priv->chip.gc.ngpio, priv->nirq, priv->irq_start);
299
300 platform_set_drvdata(pdev, priv);
301
302 priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
303 0, priv->nirq, pdev->dev.fwnode,
304 &xgene_gpio_sb_domain_ops, priv);
305 if (!priv->irq_domain)
306 return -ENODEV;
307
308 priv->chip.gc.irq.domain = priv->irq_domain;
309
310 ret = devm_gpiochip_add_data(&pdev->dev, &priv->chip.gc, priv);
311 if (ret) {
312 dev_err(&pdev->dev,
313 "failed to register X-Gene GPIO Standby driver\n");
314 irq_domain_remove(priv->irq_domain);
315 return ret;
316 }
317
318 dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
319
320 /* Register interrupt handlers for GPIO signaled ACPI Events */
321 acpi_gpiochip_request_interrupts(&priv->chip.gc);
322
323 return ret;
324 }
325
xgene_gpio_sb_remove(struct platform_device * pdev)326 static void xgene_gpio_sb_remove(struct platform_device *pdev)
327 {
328 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
329
330 acpi_gpiochip_free_interrupts(&priv->chip.gc);
331
332 irq_domain_remove(priv->irq_domain);
333 }
334
335 static const struct of_device_id xgene_gpio_sb_of_match[] = {
336 { .compatible = "apm,xgene-gpio-sb" },
337 {}
338 };
339 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
340
341 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
342 { "APMC0D15" },
343 {}
344 };
345 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
346
347 static struct platform_driver xgene_gpio_sb_driver = {
348 .driver = {
349 .name = "xgene-gpio-sb",
350 .of_match_table = xgene_gpio_sb_of_match,
351 .acpi_match_table = xgene_gpio_sb_acpi_match,
352 },
353 .probe = xgene_gpio_sb_probe,
354 .remove = xgene_gpio_sb_remove,
355 };
356 module_platform_driver(xgene_gpio_sb_driver);
357
358 MODULE_AUTHOR("AppliedMicro");
359 MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
360 MODULE_LICENSE("GPL");
361