1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 *
5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/gpio/generic.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/property.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24
25 #define MPC8XXX_GPIO_PINS 32
26
27 #define GPIO_DIR 0x00
28 #define GPIO_ODR 0x04
29 #define GPIO_DAT 0x08
30 #define GPIO_IER 0x0c
31 #define GPIO_IMR 0x10
32 #define GPIO_ICR 0x14
33 #define GPIO_ICR2 0x18
34 #define GPIO_IBE 0x18
35
36 struct mpc8xxx_gpio_chip {
37 struct gpio_generic_chip chip;
38 void __iomem *regs;
39 raw_spinlock_t lock;
40
41 int (*direction_output)(struct gpio_chip *chip,
42 unsigned offset, int value);
43
44 struct irq_domain *irq;
45 int irqn;
46 };
47
48 /*
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
51 * This inline helper give the right bitmask for a certain line.
52 */
mpc_pin2mask(unsigned int offset)53 static inline u32 mpc_pin2mask(unsigned int offset)
54 {
55 return BIT(31 - offset);
56 }
57
58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
59 * defined as output cannot be determined by reading GPDAT register,
60 * so we use shadow data register instead. The status of input pins
61 * is determined by reading GPDAT register.
62 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
64 {
65 u32 val;
66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
67 u32 out_mask, out_shadow;
68
69 out_mask = gpio_generic_read_reg(&mpc8xxx_gc->chip,
70 mpc8xxx_gc->regs + GPIO_DIR);
71 val = gpio_generic_read_reg(&mpc8xxx_gc->chip,
72 mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
73 out_shadow = mpc8xxx_gc->chip.sdata & out_mask;
74
75 return !!((val | out_shadow) & mpc_pin2mask(gpio));
76 }
77
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)78 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
79 unsigned int gpio, int val)
80 {
81 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
82 /* GPIO 28..31 are input only on MPC5121 */
83 if (gpio >= 28)
84 return -EINVAL;
85
86 return mpc8xxx_gc->direction_output(gc, gpio, val);
87 }
88
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)89 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
90 unsigned int gpio, int val)
91 {
92 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
93 /* GPIO 0..3 are input only on MPC5125 */
94 if (gpio <= 3)
95 return -EINVAL;
96
97 return mpc8xxx_gc->direction_output(gc, gpio, val);
98 }
99
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)100 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
101 {
102 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
103
104 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
105 return irq_create_mapping(mpc8xxx_gc->irq, offset);
106 else
107 return -ENXIO;
108 }
109
mpc8xxx_gpio_irq_cascade(int irq,void * data)110 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
111 {
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
113 unsigned long mask;
114 int i;
115
116 mask = gpio_generic_read_reg(&mpc8xxx_gc->chip,
117 mpc8xxx_gc->regs + GPIO_IER) &
118 gpio_generic_read_reg(&mpc8xxx_gc->chip,
119 mpc8xxx_gc->regs + GPIO_IMR);
120 for_each_set_bit(i, &mask, 32)
121 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
122
123 return IRQ_HANDLED;
124 }
125
mpc8xxx_irq_unmask(struct irq_data * d)126 static void mpc8xxx_irq_unmask(struct irq_data *d)
127 {
128 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
129 irq_hw_number_t hwirq = irqd_to_hwirq(d);
130 struct gpio_chip *gc = &mpc8xxx_gc->chip.gc;
131 unsigned long flags;
132
133 gpiochip_enable_irq(gc, hwirq);
134
135 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
136
137 gpio_generic_write_reg(&mpc8xxx_gc->chip,
138 mpc8xxx_gc->regs + GPIO_IMR,
139 gpio_generic_read_reg(&mpc8xxx_gc->chip,
140 mpc8xxx_gc->regs + GPIO_IMR)
141 | mpc_pin2mask(irqd_to_hwirq(d)));
142
143 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
144 }
145
mpc8xxx_irq_mask(struct irq_data * d)146 static void mpc8xxx_irq_mask(struct irq_data *d)
147 {
148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
149 irq_hw_number_t hwirq = irqd_to_hwirq(d);
150 struct gpio_chip *gc = &mpc8xxx_gc->chip.gc;
151 unsigned long flags;
152
153 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
154
155 gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IMR,
156 gpio_generic_read_reg(&mpc8xxx_gc->chip,
157 mpc8xxx_gc->regs + GPIO_IMR)
158 & ~mpc_pin2mask(irqd_to_hwirq(d)));
159
160 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
161
162 gpiochip_disable_irq(gc, hwirq);
163 }
164
mpc8xxx_irq_ack(struct irq_data * d)165 static void mpc8xxx_irq_ack(struct irq_data *d)
166 {
167 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
168
169 gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IER,
170 mpc_pin2mask(irqd_to_hwirq(d)));
171 }
172
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)173 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
174 {
175 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
176 unsigned long flags;
177
178 switch (flow_type) {
179 case IRQ_TYPE_EDGE_FALLING:
180 case IRQ_TYPE_LEVEL_LOW:
181 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
182 gpio_generic_write_reg(&mpc8xxx_gc->chip,
183 mpc8xxx_gc->regs + GPIO_ICR,
184 gpio_generic_read_reg(&mpc8xxx_gc->chip,
185 mpc8xxx_gc->regs + GPIO_ICR)
186 | mpc_pin2mask(irqd_to_hwirq(d)));
187 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
188 break;
189
190 case IRQ_TYPE_EDGE_BOTH:
191 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
192 gpio_generic_write_reg(&mpc8xxx_gc->chip,
193 mpc8xxx_gc->regs + GPIO_ICR,
194 gpio_generic_read_reg(&mpc8xxx_gc->chip,
195 mpc8xxx_gc->regs + GPIO_ICR)
196 & ~mpc_pin2mask(irqd_to_hwirq(d)));
197 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
198 break;
199
200 default:
201 return -EINVAL;
202 }
203
204 return 0;
205 }
206
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)207 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
208 {
209 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
210 unsigned long gpio = irqd_to_hwirq(d);
211 void __iomem *reg;
212 unsigned int shift;
213 unsigned long flags;
214
215 if (gpio < 16) {
216 reg = mpc8xxx_gc->regs + GPIO_ICR;
217 shift = (15 - gpio) * 2;
218 } else {
219 reg = mpc8xxx_gc->regs + GPIO_ICR2;
220 shift = (15 - (gpio % 16)) * 2;
221 }
222
223 switch (flow_type) {
224 case IRQ_TYPE_EDGE_FALLING:
225 case IRQ_TYPE_LEVEL_LOW:
226 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
227 gpio_generic_write_reg(&mpc8xxx_gc->chip, reg,
228 (gpio_generic_read_reg(&mpc8xxx_gc->chip,
229 reg) & ~(3 << shift))
230 | (2 << shift));
231 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
232 break;
233
234 case IRQ_TYPE_EDGE_RISING:
235 case IRQ_TYPE_LEVEL_HIGH:
236 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
237 gpio_generic_write_reg(&mpc8xxx_gc->chip, reg,
238 (gpio_generic_read_reg(&mpc8xxx_gc->chip,
239 reg) & ~(3 << shift))
240 | (1 << shift));
241 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
242 break;
243
244 case IRQ_TYPE_EDGE_BOTH:
245 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
246 gpio_generic_write_reg(&mpc8xxx_gc->chip, reg,
247 (gpio_generic_read_reg(&mpc8xxx_gc->chip,
248 reg) & ~(3 << shift)));
249 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
250 break;
251
252 default:
253 return -EINVAL;
254 }
255
256 return 0;
257 }
258
259 static struct irq_chip mpc8xxx_irq_chip = {
260 .name = "mpc8xxx-gpio",
261 .irq_unmask = mpc8xxx_irq_unmask,
262 .irq_mask = mpc8xxx_irq_mask,
263 .irq_ack = mpc8xxx_irq_ack,
264 /* this might get overwritten in mpc8xxx_probe() */
265 .irq_set_type = mpc8xxx_irq_set_type,
266 .flags = IRQCHIP_IMMUTABLE,
267 GPIOCHIP_IRQ_RESOURCE_HELPERS,
268 };
269
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)270 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
271 irq_hw_number_t hwirq)
272 {
273 irq_set_chip_data(irq, h->host_data);
274 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
275
276 return 0;
277 }
278
279 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
280 .map = mpc8xxx_gpio_irq_map,
281 .xlate = irq_domain_xlate_twocell,
282 };
283
284 struct mpc8xxx_gpio_devtype {
285 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
286 int (*gpio_get)(struct gpio_chip *, unsigned int);
287 int (*irq_set_type)(struct irq_data *, unsigned int);
288 };
289
290 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
291 .gpio_dir_out = mpc5121_gpio_dir_out,
292 .irq_set_type = mpc512x_irq_set_type,
293 };
294
295 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
296 .gpio_dir_out = mpc5125_gpio_dir_out,
297 .irq_set_type = mpc512x_irq_set_type,
298 };
299
300 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
301 .gpio_get = mpc8572_gpio_get,
302 };
303
304 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
305 .irq_set_type = mpc8xxx_irq_set_type,
306 };
307
308 static const struct of_device_id mpc8xxx_gpio_ids[] = {
309 { .compatible = "fsl,mpc8314-gpio", },
310 { .compatible = "fsl,mpc8349-gpio", },
311 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
312 { .compatible = "fsl,mpc8610-gpio", },
313 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
314 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
315 { .compatible = "fsl,pq3-gpio", },
316 { .compatible = "fsl,ls1028a-gpio", },
317 { .compatible = "fsl,ls1088a-gpio", },
318 { .compatible = "fsl,qoriq-gpio", },
319 {}
320 };
321
mpc8xxx_probe(struct platform_device * pdev)322 static int mpc8xxx_probe(struct platform_device *pdev)
323 {
324 const struct mpc8xxx_gpio_devtype *devtype = NULL;
325 struct gpio_generic_chip_config config;
326 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
327 struct device *dev = &pdev->dev;
328 struct fwnode_handle *fwnode;
329 struct gpio_chip *gc;
330 int ret;
331
332 mpc8xxx_gc = devm_kzalloc(dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
333 if (!mpc8xxx_gc)
334 return -ENOMEM;
335
336 platform_set_drvdata(pdev, mpc8xxx_gc);
337
338 raw_spin_lock_init(&mpc8xxx_gc->lock);
339
340 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
341 if (IS_ERR(mpc8xxx_gc->regs))
342 return PTR_ERR(mpc8xxx_gc->regs);
343
344 gc = &mpc8xxx_gc->chip.gc;
345 gc->parent = dev;
346
347 config = (struct gpio_generic_chip_config) {
348 .dev = dev,
349 .sz = 4,
350 .dat = mpc8xxx_gc->regs + GPIO_DAT,
351 .dirout = mpc8xxx_gc->regs + GPIO_DIR,
352 .flags = GPIO_GENERIC_BIG_ENDIAN
353 };
354
355 if (device_property_read_bool(dev, "little-endian")) {
356 dev_dbg(dev, "GPIO registers are LITTLE endian\n");
357 } else {
358 config.flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
359 dev_dbg(dev, "GPIO registers are BIG endian\n");
360 }
361
362 ret = gpio_generic_chip_init(&mpc8xxx_gc->chip, &config);
363 if (ret)
364 return ret;
365
366 mpc8xxx_gc->direction_output = gc->direction_output;
367
368 devtype = device_get_match_data(dev);
369 if (!devtype)
370 devtype = &mpc8xxx_gpio_devtype_default;
371
372 /*
373 * It's assumed that only a single type of gpio controller is available
374 * on the current machine, so overwriting global data is fine.
375 */
376 if (devtype->irq_set_type)
377 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
378
379 if (devtype->gpio_dir_out)
380 gc->direction_output = devtype->gpio_dir_out;
381 if (devtype->gpio_get)
382 gc->get = devtype->gpio_get;
383
384 gc->to_irq = mpc8xxx_gpio_to_irq;
385
386 /*
387 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
388 * the input enable of each individual GPIO port. When an individual
389 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
390 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
391 * the port value to the GPIO Data Register.
392 */
393 fwnode = dev_fwnode(dev);
394 if (device_is_compatible(dev, "fsl,qoriq-gpio") ||
395 device_is_compatible(dev, "fsl,ls1028a-gpio") ||
396 device_is_compatible(dev, "fsl,ls1088a-gpio") ||
397 is_acpi_node(fwnode)) {
398 gpio_generic_write_reg(&mpc8xxx_gc->chip,
399 mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
400 /* Also, latch state of GPIOs configured as output by bootloader. */
401 mpc8xxx_gc->chip.sdata =
402 gpio_generic_read_reg(&mpc8xxx_gc->chip,
403 mpc8xxx_gc->regs + GPIO_DAT) &
404 gpio_generic_read_reg(&mpc8xxx_gc->chip,
405 mpc8xxx_gc->regs + GPIO_DIR);
406 }
407
408 ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc);
409 if (ret) {
410 dev_err(dev,
411 "GPIO chip registration failed with status %d\n", ret);
412 return ret;
413 }
414
415 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
416 if (mpc8xxx_gc->irqn < 0)
417 return mpc8xxx_gc->irqn;
418
419 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
420 MPC8XXX_GPIO_PINS,
421 &mpc8xxx_gpio_irq_ops,
422 mpc8xxx_gc);
423
424 if (!mpc8xxx_gc->irq)
425 return 0;
426
427 /* ack and mask all irqs */
428 gpio_generic_write_reg(&mpc8xxx_gc->chip,
429 mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
430 gpio_generic_write_reg(&mpc8xxx_gc->chip,
431 mpc8xxx_gc->regs + GPIO_IMR, 0);
432
433 ret = devm_request_irq(dev, mpc8xxx_gc->irqn,
434 mpc8xxx_gpio_irq_cascade,
435 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
436 mpc8xxx_gc);
437 if (ret) {
438 dev_err(dev, "failed to devm_request_irq(%d), ret = %d\n",
439 mpc8xxx_gc->irqn, ret);
440 goto err;
441 }
442
443 ret = devm_device_init_wakeup(dev);
444 if (ret)
445 return dev_err_probe(dev, ret, "Failed to init wakeup\n");
446
447 return 0;
448 err:
449 irq_domain_remove(mpc8xxx_gc->irq);
450 return ret;
451 }
452
mpc8xxx_remove(struct platform_device * pdev)453 static void mpc8xxx_remove(struct platform_device *pdev)
454 {
455 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
456
457 if (mpc8xxx_gc->irq) {
458 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
459 irq_domain_remove(mpc8xxx_gc->irq);
460 }
461 }
462
mpc8xxx_suspend(struct device * dev)463 static int mpc8xxx_suspend(struct device *dev)
464 {
465 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev);
466
467 if (mpc8xxx_gc->irqn && device_may_wakeup(dev))
468 enable_irq_wake(mpc8xxx_gc->irqn);
469
470 return 0;
471 }
472
mpc8xxx_resume(struct device * dev)473 static int mpc8xxx_resume(struct device *dev)
474 {
475 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev);
476
477 if (mpc8xxx_gc->irqn && device_may_wakeup(dev))
478 disable_irq_wake(mpc8xxx_gc->irqn);
479
480 return 0;
481 }
482
483 static DEFINE_RUNTIME_DEV_PM_OPS(mpc8xx_pm_ops,
484 mpc8xxx_suspend, mpc8xxx_resume, NULL);
485
486 #ifdef CONFIG_ACPI
487 static const struct acpi_device_id gpio_acpi_ids[] = {
488 {"NXP0031",},
489 { }
490 };
491 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
492 #endif
493
494 static struct platform_driver mpc8xxx_plat_driver = {
495 .probe = mpc8xxx_probe,
496 .remove = mpc8xxx_remove,
497 .driver = {
498 .name = "gpio-mpc8xxx",
499 .of_match_table = mpc8xxx_gpio_ids,
500 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
501 .pm = pm_ptr(&mpc8xx_pm_ops),
502 },
503 };
504
mpc8xxx_init(void)505 static int __init mpc8xxx_init(void)
506 {
507 return platform_driver_register(&mpc8xxx_plat_driver);
508 }
509
510 arch_initcall(mpc8xxx_init);
511