1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom Kona GPIO Driver
4 *
5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6 * Copyright (C) 2012-2014 Broadcom Corporation
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/irqdomain.h>
16 #include <linux/irqchip/chained_irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19
20 #define BCM_GPIO_PASSWD 0x00a5a501
21 #define GPIO_PER_BANK 32
22 #define GPIO_MAX_BANK_NUM 8
23
24 #define GPIO_BANK(gpio) ((gpio) >> 5)
25 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
26
27 /* There is a GPIO control register for each GPIO */
28 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
29
30 /* The remaining registers are per GPIO bank */
31 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
34 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
35 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
36 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
37 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
38 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
39
40 #define GPIO_GPPWR_OFFSET 0x00000520
41
42 #define GPIO_GPCTR0_DBR_SHIFT 5
43 #define GPIO_GPCTR0_DBR_MASK 0x000001e0
44
45 #define GPIO_GPCTR0_ITR_SHIFT 3
46 #define GPIO_GPCTR0_ITR_MASK 0x00000018
47 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
48 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
49 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
50
51 #define GPIO_GPCTR0_IOTR_MASK 0x00000001
52 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
53 #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
54
55 #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
56
57 #define LOCK_CODE 0xffffffff
58 #define UNLOCK_CODE 0x00000000
59
60 struct bcm_kona_gpio_bank {
61 int id;
62 int irq;
63 /*
64 * Used to keep track of lock/unlock operations for each GPIO in the
65 * bank.
66 *
67 * All GPIOs are locked by default (see bcm_kona_gpio_reset), and the
68 * unlock count for all GPIOs is 0 by default. Each unlock increments
69 * the counter, and each lock decrements the counter.
70 *
71 * The lock function only locks the GPIO once its unlock counter is
72 * down to 0. This is necessary because the GPIO is unlocked in two
73 * places in this driver: once for requested GPIOs, and once for
74 * requested IRQs. Since it is possible for a GPIO to be requested
75 * as both a GPIO and an IRQ, we need to ensure that we don't lock it
76 * too early.
77 */
78 u8 gpio_unlock_count[GPIO_PER_BANK];
79 /* Used in the interrupt handler */
80 struct bcm_kona_gpio *kona_gpio;
81 };
82
83 struct bcm_kona_gpio {
84 void __iomem *reg_base;
85 int num_bank;
86 raw_spinlock_t lock;
87 struct gpio_chip gpio_chip;
88 struct irq_domain *irq_domain;
89 struct bcm_kona_gpio_bank banks[] __counted_by(num_bank);
90 };
91
bcm_kona_gpio_write_lock_regs(void __iomem * reg_base,int bank_id,u32 lockcode)92 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
93 int bank_id, u32 lockcode)
94 {
95 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
96 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
97 }
98
bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio * kona_gpio,unsigned gpio)99 static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
100 unsigned gpio)
101 {
102 u32 val;
103 int bank_id = GPIO_BANK(gpio);
104 int bit = GPIO_BIT(gpio);
105 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];
106
107 if (bank->gpio_unlock_count[bit] == 0) {
108 dev_err(kona_gpio->gpio_chip.parent,
109 "Unbalanced locks for GPIO %u\n", gpio);
110 return;
111 }
112
113 if (--bank->gpio_unlock_count[bit] == 0) {
114 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
115
116 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
117 val |= BIT(bit);
118 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
119 }
120 }
121
bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio * kona_gpio,unsigned gpio)122 static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
123 unsigned gpio)
124 {
125 u32 val;
126 int bank_id = GPIO_BANK(gpio);
127 int bit = GPIO_BIT(gpio);
128 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];
129
130 if (bank->gpio_unlock_count[bit] == 0) {
131 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
132
133 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
134 val &= ~BIT(bit);
135 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
136 }
137
138 ++bank->gpio_unlock_count[bit];
139 }
140
bcm_kona_gpio_get_dir(struct gpio_chip * chip,unsigned gpio)141 static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
142 {
143 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
144 void __iomem *reg_base = kona_gpio->reg_base;
145 u32 val;
146
147 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
148 return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
149 }
150
bcm_kona_gpio_set(struct gpio_chip * chip,unsigned int gpio,int value)151 static int bcm_kona_gpio_set(struct gpio_chip *chip, unsigned int gpio,
152 int value)
153 {
154 struct bcm_kona_gpio *kona_gpio;
155 void __iomem *reg_base;
156 int bank_id = GPIO_BANK(gpio);
157 int bit = GPIO_BIT(gpio);
158 u32 val, reg_offset;
159
160 kona_gpio = gpiochip_get_data(chip);
161 reg_base = kona_gpio->reg_base;
162
163 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
164
165 /* this function only applies to output pin */
166 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
167 return 0;
168
169 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
170
171 val = readl(reg_base + reg_offset);
172 val |= BIT(bit);
173 writel(val, reg_base + reg_offset);
174
175 return 0;
176 }
177
bcm_kona_gpio_get(struct gpio_chip * chip,unsigned gpio)178 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
179 {
180 struct bcm_kona_gpio *kona_gpio;
181 void __iomem *reg_base;
182 int bank_id = GPIO_BANK(gpio);
183 int bit = GPIO_BIT(gpio);
184 u32 val, reg_offset;
185
186 kona_gpio = gpiochip_get_data(chip);
187 reg_base = kona_gpio->reg_base;
188
189 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
190
191 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
192 reg_offset = GPIO_IN_STATUS(bank_id);
193 else
194 reg_offset = GPIO_OUT_STATUS(bank_id);
195
196 /* read the GPIO bank status */
197 val = readl(reg_base + reg_offset);
198
199 /* return the specified bit status */
200 return !!(val & BIT(bit));
201 }
202
bcm_kona_gpio_request(struct gpio_chip * chip,unsigned gpio)203 static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
204 {
205 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
206
207 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
208 return 0;
209 }
210
bcm_kona_gpio_free(struct gpio_chip * chip,unsigned gpio)211 static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
212 {
213 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
214
215 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
216 }
217
bcm_kona_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)218 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
219 {
220 struct bcm_kona_gpio *kona_gpio;
221 void __iomem *reg_base;
222 u32 val;
223
224 kona_gpio = gpiochip_get_data(chip);
225 reg_base = kona_gpio->reg_base;
226
227 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
228
229 val = readl(reg_base + GPIO_CONTROL(gpio));
230 val &= ~GPIO_GPCTR0_IOTR_MASK;
231 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
232 writel(val, reg_base + GPIO_CONTROL(gpio));
233
234 return 0;
235 }
236
bcm_kona_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)237 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
238 unsigned gpio, int value)
239 {
240 struct bcm_kona_gpio *kona_gpio;
241 void __iomem *reg_base;
242 int bank_id = GPIO_BANK(gpio);
243 int bit = GPIO_BIT(gpio);
244 u32 val, reg_offset;
245
246 kona_gpio = gpiochip_get_data(chip);
247 reg_base = kona_gpio->reg_base;
248
249 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
250
251 val = readl(reg_base + GPIO_CONTROL(gpio));
252 val &= ~GPIO_GPCTR0_IOTR_MASK;
253 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
254 writel(val, reg_base + GPIO_CONTROL(gpio));
255 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
256
257 val = readl(reg_base + reg_offset);
258 val |= BIT(bit);
259 writel(val, reg_base + reg_offset);
260
261 return 0;
262 }
263
bcm_kona_gpio_to_irq(struct gpio_chip * chip,unsigned gpio)264 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
265 {
266 struct bcm_kona_gpio *kona_gpio;
267
268 kona_gpio = gpiochip_get_data(chip);
269 if (gpio >= kona_gpio->gpio_chip.ngpio)
270 return -ENXIO;
271 return irq_create_mapping(kona_gpio->irq_domain, gpio);
272 }
273
bcm_kona_gpio_set_debounce(struct gpio_chip * chip,unsigned gpio,unsigned debounce)274 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
275 unsigned debounce)
276 {
277 struct bcm_kona_gpio *kona_gpio;
278 void __iomem *reg_base;
279 u32 val, res;
280
281 kona_gpio = gpiochip_get_data(chip);
282 reg_base = kona_gpio->reg_base;
283 /* debounce must be 1-128ms (or 0) */
284 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
285 dev_err(chip->parent, "Debounce value %u not in range\n",
286 debounce);
287 return -EINVAL;
288 }
289
290 /* calculate debounce bit value */
291 if (debounce != 0) {
292 /* Convert to ms */
293 debounce /= 1000;
294 /* find the MSB */
295 res = fls(debounce) - 1;
296 /* Check if MSB-1 is set (round up or down) */
297 if (res > 0 && (debounce & BIT(res - 1)))
298 res++;
299 }
300
301 /* spin lock for read-modify-write of the GPIO register */
302 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
303
304 val = readl(reg_base + GPIO_CONTROL(gpio));
305 val &= ~GPIO_GPCTR0_DBR_MASK;
306
307 if (debounce == 0) {
308 /* disable debounce */
309 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
310 } else {
311 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
312 (res << GPIO_GPCTR0_DBR_SHIFT);
313 }
314
315 writel(val, reg_base + GPIO_CONTROL(gpio));
316
317 return 0;
318 }
319
bcm_kona_gpio_set_config(struct gpio_chip * chip,unsigned gpio,unsigned long config)320 static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
321 unsigned long config)
322 {
323 u32 debounce;
324
325 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
326 return -ENOTSUPP;
327
328 debounce = pinconf_to_config_argument(config);
329 return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
330 }
331
332 static const struct gpio_chip template_chip = {
333 .label = "bcm-kona-gpio",
334 .owner = THIS_MODULE,
335 .request = bcm_kona_gpio_request,
336 .free = bcm_kona_gpio_free,
337 .get_direction = bcm_kona_gpio_get_dir,
338 .direction_input = bcm_kona_gpio_direction_input,
339 .get = bcm_kona_gpio_get,
340 .direction_output = bcm_kona_gpio_direction_output,
341 .set = bcm_kona_gpio_set,
342 .set_config = bcm_kona_gpio_set_config,
343 .to_irq = bcm_kona_gpio_to_irq,
344 .base = 0,
345 };
346
bcm_kona_gpio_irq_ack(struct irq_data * d)347 static void bcm_kona_gpio_irq_ack(struct irq_data *d)
348 {
349 struct bcm_kona_gpio *kona_gpio;
350 void __iomem *reg_base;
351 unsigned gpio = d->hwirq;
352 int bank_id = GPIO_BANK(gpio);
353 int bit = GPIO_BIT(gpio);
354 u32 val;
355
356 kona_gpio = irq_data_get_irq_chip_data(d);
357 reg_base = kona_gpio->reg_base;
358
359 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
360
361 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
362 val |= BIT(bit);
363 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
364 }
365
bcm_kona_gpio_irq_mask(struct irq_data * d)366 static void bcm_kona_gpio_irq_mask(struct irq_data *d)
367 {
368 struct bcm_kona_gpio *kona_gpio;
369 void __iomem *reg_base;
370 unsigned gpio = d->hwirq;
371 int bank_id = GPIO_BANK(gpio);
372 int bit = GPIO_BIT(gpio);
373 u32 val;
374
375 kona_gpio = irq_data_get_irq_chip_data(d);
376 reg_base = kona_gpio->reg_base;
377
378 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
379
380 val = readl(reg_base + GPIO_INT_MASK(bank_id));
381 val |= BIT(bit);
382 writel(val, reg_base + GPIO_INT_MASK(bank_id));
383 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
384 }
385
bcm_kona_gpio_irq_unmask(struct irq_data * d)386 static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
387 {
388 struct bcm_kona_gpio *kona_gpio;
389 void __iomem *reg_base;
390 unsigned gpio = d->hwirq;
391 int bank_id = GPIO_BANK(gpio);
392 int bit = GPIO_BIT(gpio);
393 u32 val;
394
395 kona_gpio = irq_data_get_irq_chip_data(d);
396 reg_base = kona_gpio->reg_base;
397
398 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
399
400 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
401 val |= BIT(bit);
402 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
403 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
404 }
405
bcm_kona_gpio_irq_set_type(struct irq_data * d,unsigned int type)406 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
407 {
408 struct bcm_kona_gpio *kona_gpio;
409 void __iomem *reg_base;
410 unsigned gpio = d->hwirq;
411 u32 lvl_type;
412 u32 val;
413
414 kona_gpio = irq_data_get_irq_chip_data(d);
415 reg_base = kona_gpio->reg_base;
416 switch (type & IRQ_TYPE_SENSE_MASK) {
417 case IRQ_TYPE_EDGE_RISING:
418 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
419 break;
420
421 case IRQ_TYPE_EDGE_FALLING:
422 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
423 break;
424
425 case IRQ_TYPE_EDGE_BOTH:
426 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
427 break;
428
429 case IRQ_TYPE_LEVEL_HIGH:
430 case IRQ_TYPE_LEVEL_LOW:
431 /* BCM GPIO doesn't support level triggering */
432 default:
433 dev_err(kona_gpio->gpio_chip.parent,
434 "Invalid BCM GPIO irq type 0x%x\n", type);
435 return -EINVAL;
436 }
437
438 guard(raw_spinlock_irqsave)(&kona_gpio->lock);
439
440 val = readl(reg_base + GPIO_CONTROL(gpio));
441 val &= ~GPIO_GPCTR0_ITR_MASK;
442 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
443 writel(val, reg_base + GPIO_CONTROL(gpio));
444
445 return 0;
446 }
447
bcm_kona_gpio_irq_handler(struct irq_desc * desc)448 static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
449 {
450 void __iomem *reg_base;
451 int bit, bank_id;
452 unsigned long sta;
453 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
454 struct irq_chip *chip = irq_desc_get_chip(desc);
455
456 chained_irq_enter(chip, desc);
457
458 /*
459 * For bank interrupts, we can't use chip_data to store the kona_gpio
460 * pointer, since GIC needs it for its own purposes. Therefore, we get
461 * our pointer from the bank structure.
462 */
463 reg_base = bank->kona_gpio->reg_base;
464 bank_id = bank->id;
465
466 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
467 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
468 for_each_set_bit(bit, &sta, 32) {
469 int hwirq = GPIO_PER_BANK * bank_id + bit;
470 /*
471 * Clear interrupt before handler is called so we don't
472 * miss any interrupt occurred during executing them.
473 */
474 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
475 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
476 /* Invoke interrupt handler */
477 generic_handle_domain_irq(bank->kona_gpio->irq_domain,
478 hwirq);
479 }
480 }
481
482 chained_irq_exit(chip, desc);
483 }
484
bcm_kona_gpio_irq_reqres(struct irq_data * d)485 static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
486 {
487 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
488 unsigned int gpio = d->hwirq;
489
490 /*
491 * We need to unlock the GPIO before any other operations are performed
492 * on the relevant GPIO configuration registers
493 */
494 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
495
496 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, gpio);
497 }
498
bcm_kona_gpio_irq_relres(struct irq_data * d)499 static void bcm_kona_gpio_irq_relres(struct irq_data *d)
500 {
501 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
502 unsigned int gpio = d->hwirq;
503
504 /* Once we no longer use it, lock the GPIO again */
505 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
506
507 gpiochip_relres_irq(&kona_gpio->gpio_chip, gpio);
508 }
509
510 static struct irq_chip bcm_gpio_irq_chip = {
511 .name = "bcm-kona-gpio",
512 .irq_ack = bcm_kona_gpio_irq_ack,
513 .irq_mask = bcm_kona_gpio_irq_mask,
514 .irq_unmask = bcm_kona_gpio_irq_unmask,
515 .irq_set_type = bcm_kona_gpio_irq_set_type,
516 .irq_request_resources = bcm_kona_gpio_irq_reqres,
517 .irq_release_resources = bcm_kona_gpio_irq_relres,
518 .flags = IRQCHIP_IMMUTABLE,
519 };
520
521 static struct of_device_id const bcm_kona_gpio_of_match[] = {
522 { .compatible = "brcm,kona-gpio" },
523 {}
524 };
525
526 /*
527 * This lock class tells lockdep that GPIO irqs are in a different
528 * category than their parents, so it won't report false recursion.
529 */
530 static struct lock_class_key gpio_lock_class;
531 static struct lock_class_key gpio_request_class;
532
bcm_kona_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)533 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
534 irq_hw_number_t hwirq)
535 {
536 int ret;
537
538 ret = irq_set_chip_data(irq, d->host_data);
539 if (ret < 0)
540 return ret;
541 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
542 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
543 irq_set_noprobe(irq);
544
545 return 0;
546 }
547
bcm_kona_gpio_irq_unmap(struct irq_domain * d,unsigned int irq)548 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
549 {
550 irq_set_chip_and_handler(irq, NULL, NULL);
551 irq_set_chip_data(irq, NULL);
552 }
553
554 static const struct irq_domain_ops bcm_kona_irq_ops = {
555 .map = bcm_kona_gpio_irq_map,
556 .unmap = bcm_kona_gpio_irq_unmap,
557 .xlate = irq_domain_xlate_twocell,
558 };
559
bcm_kona_gpio_reset(struct bcm_kona_gpio * kona_gpio)560 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
561 {
562 void __iomem *reg_base;
563 int i;
564
565 reg_base = kona_gpio->reg_base;
566 /* disable interrupts and clear status */
567 for (i = 0; i < kona_gpio->num_bank; i++) {
568 /* Unlock the entire bank first */
569 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
570 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
571 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
572 /* Now re-lock the bank */
573 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
574 }
575 }
576
bcm_kona_gpio_probe(struct platform_device * pdev)577 static int bcm_kona_gpio_probe(struct platform_device *pdev)
578 {
579 struct device *dev = &pdev->dev;
580 struct bcm_kona_gpio_bank *bank;
581 struct bcm_kona_gpio *kona_gpio;
582 struct gpio_chip *chip;
583 int ret;
584 int i;
585
586 ret = platform_irq_count(pdev);
587 if (!ret) {
588 dev_err(dev, "Couldn't determine # GPIO banks\n");
589 return -ENOENT;
590 } else if (ret < 0) {
591 return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
592 }
593
594 kona_gpio = devm_kzalloc(dev, struct_size(kona_gpio, banks, ret), GFP_KERNEL);
595 if (!kona_gpio)
596 return -ENOMEM;
597
598 kona_gpio->num_bank = ret;
599
600 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
601 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
602 GPIO_MAX_BANK_NUM);
603 return -ENXIO;
604 }
605
606 kona_gpio->gpio_chip = template_chip;
607 chip = &kona_gpio->gpio_chip;
608 chip->parent = dev;
609 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
610
611 kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
612 chip->ngpio,
613 &bcm_kona_irq_ops,
614 kona_gpio);
615 if (!kona_gpio->irq_domain) {
616 dev_err(dev, "Couldn't allocate IRQ domain\n");
617 return -ENXIO;
618 }
619
620 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
621 if (IS_ERR(kona_gpio->reg_base)) {
622 ret = PTR_ERR(kona_gpio->reg_base);
623 goto err_irq_domain;
624 }
625
626 for (i = 0; i < kona_gpio->num_bank; i++) {
627 bank = &kona_gpio->banks[i];
628 bank->id = i;
629 bank->irq = platform_get_irq(pdev, i);
630 bank->kona_gpio = kona_gpio;
631 if (bank->irq < 0) {
632 dev_err(dev, "Couldn't get IRQ for bank %d\n", i);
633 ret = -ENOENT;
634 goto err_irq_domain;
635 }
636 }
637
638 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
639
640 bcm_kona_gpio_reset(kona_gpio);
641
642 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
643 if (ret < 0) {
644 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
645 goto err_irq_domain;
646 }
647 for (i = 0; i < kona_gpio->num_bank; i++) {
648 bank = &kona_gpio->banks[i];
649 irq_set_chained_handler_and_data(bank->irq,
650 bcm_kona_gpio_irq_handler,
651 bank);
652 }
653
654 raw_spin_lock_init(&kona_gpio->lock);
655
656 return 0;
657
658 err_irq_domain:
659 irq_domain_remove(kona_gpio->irq_domain);
660
661 return ret;
662 }
663
664 static struct platform_driver bcm_kona_gpio_driver = {
665 .driver = {
666 .name = "bcm-kona-gpio",
667 .of_match_table = bcm_kona_gpio_of_match,
668 },
669 .probe = bcm_kona_gpio_probe,
670 };
671 builtin_platform_driver(bcm_kona_gpio_driver);
672