1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl / GPIO driver for StarFive JH7100 SoC
4 *
5 * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
6 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
7 */
8
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/seq_file.h>
18 #include <linux/spinlock.h>
19
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24
25 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
26
27 #include "../core.h"
28 #include "../pinctrl-utils.h"
29 #include "../pinmux.h"
30 #include "../pinconf.h"
31
32 #define DRIVER_NAME "pinctrl-starfive"
33
34 /*
35 * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
36 * https://github.com/starfive-tech/JH7100_Docs
37 */
38 #define NR_GPIOS 64
39
40 /*
41 * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
42 * are enabled. If set to 0 the GPIO interrupts are disabled.
43 */
44 #define GPIOEN 0x000
45
46 /*
47 * The following 32-bit registers come in pairs, but only the offset of the
48 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
49 * the second GPIO 32-63.
50 */
51
52 /*
53 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
54 * interrupt is level-triggered.
55 */
56 #define GPIOIS 0x010
57
58 /*
59 * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on
60 * both positive and negative edges. If set to 0 the interrupt is triggered by a
61 * single edge.
62 */
63 #define GPIOIBE 0x018
64
65 /*
66 * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
67 * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
68 * interrupt is triggered on a falling edge (edge-triggered) or low level
69 * (level-triggered).
70 */
71 #define GPIOIEV 0x020
72
73 /*
74 * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
75 * the interrupt is disabled (masked). Note that the current documentation is
76 * wrong and says the exct opposite of this.
77 */
78 #define GPIOIE 0x028
79
80 /*
81 * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
82 * interrupt.
83 */
84 #define GPIOIC 0x030
85
86 /*
87 * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
88 */
89 #define GPIORIS 0x038
90
91 /*
92 * Interrupt Status after Masking. A 1 means the configured edge or level was
93 * detected and not masked.
94 */
95 #define GPIOMIS 0x040
96
97 /*
98 * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
99 * a digital 1 and if 0 the pin is a digital 0.
100 */
101 #define GPIODIN 0x048
102
103 /*
104 * From the data sheet section 12.2, there are 64 32-bit output data registers
105 * and 64 output enable registers. Output data and output enable registers for
106 * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
107 * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c. The stride
108 * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
109 * and GPOn_DOEN_CFG is 0x54 + 8n.
110 */
111 #define GPON_DOUT_CFG 0x050
112 #define GPON_DOEN_CFG 0x054
113
114 /*
115 * From Section 12.3, there are 75 input signal configuration registers which
116 * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
117 * GPI_USB_OVER_CURRENT_CFG 0x378
118 */
119 #define GPI_CFG_OFFSET 0x250
120
121 /*
122 * Pad Control Bits. There are 16 pad control bits for each pin located in 103
123 * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
124 * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
125 * bit of each register.
126 */
127 #define PAD_SLEW_RATE_MASK GENMASK(11, 9)
128 #define PAD_SLEW_RATE_POS 9
129 #define PAD_BIAS_STRONG_PULL_UP BIT(8)
130 #define PAD_INPUT_ENABLE BIT(7)
131 #define PAD_INPUT_SCHMITT_ENABLE BIT(6)
132 #define PAD_BIAS_DISABLE BIT(5)
133 #define PAD_BIAS_PULL_DOWN BIT(4)
134 #define PAD_BIAS_MASK \
135 (PAD_BIAS_STRONG_PULL_UP | \
136 PAD_BIAS_DISABLE | \
137 PAD_BIAS_PULL_DOWN)
138 #define PAD_DRIVE_STRENGTH_MASK GENMASK(3, 0)
139 #define PAD_DRIVE_STRENGTH_POS 0
140
141 /*
142 * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
143 * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
144 * PAD_GPIO pads. This is a global setting.
145 */
146 #define IO_PADSHARE_SEL 0x1a0
147
148 /*
149 * This just needs to be some number such that when
150 * sfp->gpio.pin_base = PAD_INVALID_GPIO then
151 * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
152 * That is it should underflow and return something >= NR_GPIOS.
153 */
154 #define PAD_INVALID_GPIO 0x10000
155
156 /*
157 * The packed pinmux values from the device tree look like this:
158 *
159 * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |
160 * | dout | doen | din | dout rev | doen rev | gpio nr |
161 *
162 * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
163 *
164 * | 31 | 30 - 8 | 7 - 0 |
165 * | dout/doen rev | unused | dout/doen |
166 */
starfive_pinmux_to_gpio(u32 v)167 static unsigned int starfive_pinmux_to_gpio(u32 v)
168 {
169 return v & (NR_GPIOS - 1);
170 }
171
starfive_pinmux_to_dout(u32 v)172 static u32 starfive_pinmux_to_dout(u32 v)
173 {
174 return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
175 }
176
starfive_pinmux_to_doen(u32 v)177 static u32 starfive_pinmux_to_doen(u32 v)
178 {
179 return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
180 }
181
starfive_pinmux_to_din(u32 v)182 static u32 starfive_pinmux_to_din(u32 v)
183 {
184 return (v >> 8) & GENMASK(7, 0);
185 }
186
187 /*
188 * The maximum GPIO output current depends on the chosen drive strength:
189 *
190 * DS: 0 1 2 3 4 5 6 7
191 * mA: 14.2 21.2 28.2 35.2 42.2 49.1 56.0 62.8
192 *
193 * After rounding that is 7*DS + 14 mA
194 */
starfive_drive_strength_to_max_mA(u16 ds)195 static u32 starfive_drive_strength_to_max_mA(u16 ds)
196 {
197 return 7 * ds + 14;
198 }
199
starfive_drive_strength_from_max_mA(u32 i)200 static u16 starfive_drive_strength_from_max_mA(u32 i)
201 {
202 return (clamp(i, 14U, 63U) - 14) / 7;
203 }
204
205 struct starfive_pinctrl {
206 struct gpio_chip gc;
207 struct pinctrl_gpio_range gpios;
208 raw_spinlock_t lock;
209 void __iomem *base;
210 void __iomem *padctl;
211 struct pinctrl_dev *pctl;
212 struct mutex mutex; /* serialize adding groups and functions */
213 };
214
starfive_pin_to_gpio(const struct starfive_pinctrl * sfp,unsigned int pin)215 static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
216 unsigned int pin)
217 {
218 return pin - sfp->gpios.pin_base;
219 }
220
starfive_gpio_to_pin(const struct starfive_pinctrl * sfp,unsigned int gpio)221 static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
222 unsigned int gpio)
223 {
224 return sfp->gpios.pin_base + gpio;
225 }
226
starfive_from_irq_data(struct irq_data * d)227 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
228 {
229 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
230
231 return container_of(gc, struct starfive_pinctrl, gc);
232 }
233
starfive_from_irq_desc(struct irq_desc * desc)234 static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
235 {
236 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
237
238 return container_of(gc, struct starfive_pinctrl, gc);
239 }
240
241 static const struct pinctrl_pin_desc starfive_pins[] = {
242 PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
243 PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
244 PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
245 PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
246 PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
247 PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
248 PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
249 PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
250 PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
251 PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
252 PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
253 PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
254 PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
255 PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
256 PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
257 PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
258 PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
259 PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
260 PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
261 PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
262 PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
263 PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
264 PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
265 PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
266 PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
267 PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
268 PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
269 PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
270 PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
271 PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
272 PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
273 PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
274 PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
275 PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
276 PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
277 PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
278 PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
279 PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
280 PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
281 PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
282 PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
283 PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
284 PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
285 PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
286 PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
287 PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
288 PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
289 PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
290 PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
291 PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
292 PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
293 PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
294 PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
295 PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
296 PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
297 PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
298 PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
299 PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
300 PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
301 PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
302 PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
303 PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
304 PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
305 PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
306 PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
307 PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
308 PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
309 PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
310 PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
311 PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
312 PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
313 PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
314 PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
315 PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
316 PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
317 PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
318 PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
319 PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
320 PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
321 PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
322 PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
323 PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
324 PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
325 PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
326 PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
327 PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
328 PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
329 PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
330 PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
331 PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
332 PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
333 PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
334 PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
335 PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
336 PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
337 PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
338 PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
339 PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
340 PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
341 PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
342 PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
343 PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
344 PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
345 PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
346 PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
347 PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
348 PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
349 PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
350 PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
351 PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
352 PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
353 PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
354 PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
355 PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
356 PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
357 PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
358 PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
359 PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
360 PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
361 PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
362 PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
363 PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
364 PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
365 PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
366 PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
367 PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
368 PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
369 PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
370 PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
371 PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
372 PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
373 PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
374 PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
375 PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
376 PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
377 PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
378 PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
379 PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
380 PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
381 PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
382 PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
383 PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
384 PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
385 PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
386 PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
387 PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
388 PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
389 PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
390 PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
391 PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
392 PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
393 PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
394 PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
395 PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
396 PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
397 PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
398 PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
399 PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
400 PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
401 PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
402 PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
403 PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
404 PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
405 PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
406 PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
407 PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
408 PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
409 PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
410 PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
411 PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
412 PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
413 PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
414 PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
415 PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
416 PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
417 PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
418 PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
419 PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
420 PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
421 PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
422 PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
423 PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
424 PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
425 PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
426 PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
427 PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
428 PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
429 PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
430 PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
431 PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
432 PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
433 PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
434 PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
435 PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
436 PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
437 PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
438 PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
439 PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
440 PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
441 PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
442 PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
443 PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
444 PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
445 PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
446 PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
447 PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
448 };
449
450 #ifdef CONFIG_DEBUG_FS
starfive_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)451 static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
452 struct seq_file *s,
453 unsigned int pin)
454 {
455 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
456 unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
457 void __iomem *reg;
458 u32 dout, doen;
459
460 if (gpio >= NR_GPIOS)
461 return;
462
463 reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
464 dout = readl_relaxed(reg + 0x000);
465 doen = readl_relaxed(reg + 0x004);
466
467 seq_printf(s, "dout=%lu%s doen=%lu%s",
468 dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
469 doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
470 }
471 #else
472 #define starfive_pin_dbg_show NULL
473 #endif
474
starfive_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** maps,unsigned int * num_maps)475 static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
476 struct device_node *np,
477 struct pinctrl_map **maps,
478 unsigned int *num_maps)
479 {
480 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
481 struct device *dev = sfp->gc.parent;
482 struct pinctrl_map *map;
483 const char **pgnames;
484 const char *grpname;
485 u32 *pinmux;
486 int ngroups;
487 int *pins;
488 int nmaps;
489 int ret;
490
491 nmaps = 0;
492 ngroups = 0;
493 for_each_available_child_of_node_scoped(np, child) {
494 int npinmux = of_property_count_u32_elems(child, "pinmux");
495 int npins = of_property_count_u32_elems(child, "pins");
496
497 if (npinmux > 0 && npins > 0) {
498 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
499 np, child);
500 return -EINVAL;
501 }
502 if (npinmux == 0 && npins == 0) {
503 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
504 np, child);
505 return -EINVAL;
506 }
507
508 if (npinmux > 0)
509 nmaps += 2;
510 else
511 nmaps += 1;
512 ngroups += 1;
513 }
514
515 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
516 if (!pgnames)
517 return -ENOMEM;
518
519 map = kzalloc_objs(*map, nmaps);
520 if (!map)
521 return -ENOMEM;
522
523 nmaps = 0;
524 ngroups = 0;
525 mutex_lock(&sfp->mutex);
526 for_each_available_child_of_node_scoped(np, child) {
527 int npins;
528 int i;
529
530 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
531 if (!grpname) {
532 ret = -ENOMEM;
533 goto free_map;
534 }
535
536 pgnames[ngroups++] = grpname;
537
538 if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
539 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
540 if (!pins) {
541 ret = -ENOMEM;
542 goto free_map;
543 }
544
545 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
546 if (!pinmux) {
547 ret = -ENOMEM;
548 goto free_map;
549 }
550
551 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
552 if (ret)
553 goto free_map;
554
555 for (i = 0; i < npins; i++) {
556 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
557
558 pins[i] = starfive_gpio_to_pin(sfp, gpio);
559 }
560
561 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
562 map[nmaps].data.mux.function = np->name;
563 map[nmaps].data.mux.group = grpname;
564 nmaps += 1;
565 } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
566 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
567 if (!pins) {
568 ret = -ENOMEM;
569 goto free_map;
570 }
571
572 pinmux = NULL;
573
574 for (i = 0; i < npins; i++) {
575 u32 v;
576
577 ret = of_property_read_u32_index(child, "pins", i, &v);
578 if (ret)
579 goto free_map;
580 pins[i] = v;
581 }
582 } else {
583 ret = -EINVAL;
584 goto free_map;
585 }
586
587 ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
588 if (ret < 0) {
589 dev_err(dev, "error adding group %s: %d\n", grpname, ret);
590 goto free_map;
591 }
592
593 ret = pinconf_generic_parse_dt_config(child, pctldev,
594 &map[nmaps].data.configs.configs,
595 &map[nmaps].data.configs.num_configs);
596 if (ret) {
597 dev_err(dev, "error parsing pin config of group %s: %d\n",
598 grpname, ret);
599 goto free_map;
600 }
601
602 /* don't create a map if there are no pinconf settings */
603 if (map[nmaps].data.configs.num_configs == 0)
604 continue;
605
606 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
607 map[nmaps].data.configs.group_or_pin = grpname;
608 nmaps += 1;
609 }
610
611 ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
612 if (ret < 0) {
613 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
614 goto free_map;
615 }
616
617 *maps = map;
618 *num_maps = nmaps;
619 mutex_unlock(&sfp->mutex);
620 return 0;
621
622 free_map:
623 pinctrl_utils_free_map(pctldev, map, nmaps);
624 mutex_unlock(&sfp->mutex);
625 return ret;
626 }
627
628 static const struct pinctrl_ops starfive_pinctrl_ops = {
629 .get_groups_count = pinctrl_generic_get_group_count,
630 .get_group_name = pinctrl_generic_get_group_name,
631 .get_group_pins = pinctrl_generic_get_group_pins,
632 .pin_dbg_show = starfive_pin_dbg_show,
633 .dt_node_to_map = starfive_dt_node_to_map,
634 .dt_free_map = pinctrl_utils_free_map,
635 };
636
starfive_set_mux(struct pinctrl_dev * pctldev,unsigned int fsel,unsigned int gsel)637 static int starfive_set_mux(struct pinctrl_dev *pctldev,
638 unsigned int fsel, unsigned int gsel)
639 {
640 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
641 struct device *dev = sfp->gc.parent;
642 const struct group_desc *group;
643 const u32 *pinmux;
644 unsigned int i;
645
646 group = pinctrl_generic_get_group(pctldev, gsel);
647 if (!group)
648 return -EINVAL;
649
650 pinmux = group->data;
651 for (i = 0; i < group->grp.npins; i++) {
652 u32 v = pinmux[i];
653 unsigned int gpio = starfive_pinmux_to_gpio(v);
654 u32 dout = starfive_pinmux_to_dout(v);
655 u32 doen = starfive_pinmux_to_doen(v);
656 u32 din = starfive_pinmux_to_din(v);
657 void __iomem *reg_dout;
658 void __iomem *reg_doen;
659 void __iomem *reg_din;
660 unsigned long flags;
661
662 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
663 gpio, dout, doen, din);
664
665 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
666 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
667 if (din != GPI_NONE)
668 reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
669 else
670 reg_din = NULL;
671
672 raw_spin_lock_irqsave(&sfp->lock, flags);
673 writel_relaxed(dout, reg_dout);
674 writel_relaxed(doen, reg_doen);
675 if (reg_din)
676 writel_relaxed(gpio + 2, reg_din);
677 raw_spin_unlock_irqrestore(&sfp->lock, flags);
678 }
679
680 return 0;
681 }
682
683 static const struct pinmux_ops starfive_pinmux_ops = {
684 .get_functions_count = pinmux_generic_get_function_count,
685 .get_function_name = pinmux_generic_get_function_name,
686 .get_function_groups = pinmux_generic_get_function_groups,
687 .set_mux = starfive_set_mux,
688 .strict = true,
689 };
690
starfive_padctl_get(struct starfive_pinctrl * sfp,unsigned int pin)691 static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
692 unsigned int pin)
693 {
694 void __iomem *reg = sfp->padctl + 4 * (pin / 2);
695 int shift = 16 * (pin % 2);
696
697 return readl_relaxed(reg) >> shift;
698 }
699
starfive_padctl_rmw(struct starfive_pinctrl * sfp,unsigned int pin,u16 _mask,u16 _value)700 static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
701 unsigned int pin,
702 u16 _mask, u16 _value)
703 {
704 void __iomem *reg = sfp->padctl + 4 * (pin / 2);
705 int shift = 16 * (pin % 2);
706 u32 mask = (u32)_mask << shift;
707 u32 value = (u32)_value << shift;
708 unsigned long flags;
709
710 dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
711
712 raw_spin_lock_irqsave(&sfp->lock, flags);
713 value |= readl_relaxed(reg) & ~mask;
714 writel_relaxed(value, reg);
715 raw_spin_unlock_irqrestore(&sfp->lock, flags);
716 }
717
718 #define PIN_CONFIG_STARFIVE_STRONG_PULL_UP (PIN_CONFIG_END + 1)
719
720 static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
721 { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
722 };
723
724 #ifdef CONFIG_DEBUG_FS
725 static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
726 PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
727 };
728
729 static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
730 ARRAY_SIZE(starfive_pinconf_custom_params));
731 #else
732 #define starfive_pinconf_custom_conf_items NULL
733 #endif
734
starfive_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)735 static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
736 unsigned int pin, unsigned long *config)
737 {
738 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
739 int param = pinconf_to_config_param(*config);
740 u16 value = starfive_padctl_get(sfp, pin);
741 bool enabled;
742 u32 arg;
743
744 switch (param) {
745 case PIN_CONFIG_BIAS_DISABLE:
746 enabled = value & PAD_BIAS_DISABLE;
747 arg = 0;
748 break;
749 case PIN_CONFIG_BIAS_PULL_DOWN:
750 enabled = value & PAD_BIAS_PULL_DOWN;
751 arg = 1;
752 break;
753 case PIN_CONFIG_BIAS_PULL_UP:
754 enabled = !(value & PAD_BIAS_MASK);
755 arg = 1;
756 break;
757 case PIN_CONFIG_DRIVE_STRENGTH:
758 enabled = value & PAD_DRIVE_STRENGTH_MASK;
759 arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
760 break;
761 case PIN_CONFIG_INPUT_ENABLE:
762 enabled = value & PAD_INPUT_ENABLE;
763 arg = enabled;
764 break;
765 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
766 enabled = value & PAD_INPUT_SCHMITT_ENABLE;
767 arg = enabled;
768 break;
769 case PIN_CONFIG_SLEW_RATE:
770 enabled = value & PAD_SLEW_RATE_MASK;
771 arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
772 break;
773 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
774 enabled = value & PAD_BIAS_STRONG_PULL_UP;
775 arg = enabled;
776 break;
777 default:
778 return -ENOTSUPP;
779 }
780
781 *config = pinconf_to_config_packed(param, arg);
782 return enabled ? 0 : -EINVAL;
783 }
784
starfive_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int gsel,unsigned long * config)785 static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
786 unsigned int gsel, unsigned long *config)
787 {
788 const struct group_desc *group;
789
790 group = pinctrl_generic_get_group(pctldev, gsel);
791 if (!group)
792 return -EINVAL;
793
794 return starfive_pinconf_get(pctldev, group->grp.pins[0], config);
795 }
796
starfive_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int gsel,unsigned long * configs,unsigned int num_configs)797 static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
798 unsigned int gsel,
799 unsigned long *configs,
800 unsigned int num_configs)
801 {
802 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
803 const struct group_desc *group;
804 u16 mask, value;
805 int i;
806
807 group = pinctrl_generic_get_group(pctldev, gsel);
808 if (!group)
809 return -EINVAL;
810
811 mask = 0;
812 value = 0;
813 for (i = 0; i < num_configs; i++) {
814 int param = pinconf_to_config_param(configs[i]);
815 u32 arg = pinconf_to_config_argument(configs[i]);
816
817 switch (param) {
818 case PIN_CONFIG_BIAS_DISABLE:
819 mask |= PAD_BIAS_MASK;
820 value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
821 break;
822 case PIN_CONFIG_BIAS_PULL_DOWN:
823 if (arg == 0)
824 return -ENOTSUPP;
825 mask |= PAD_BIAS_MASK;
826 value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
827 break;
828 case PIN_CONFIG_BIAS_PULL_UP:
829 if (arg == 0)
830 return -ENOTSUPP;
831 mask |= PAD_BIAS_MASK;
832 value = value & ~PAD_BIAS_MASK;
833 break;
834 case PIN_CONFIG_DRIVE_STRENGTH:
835 mask |= PAD_DRIVE_STRENGTH_MASK;
836 value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
837 starfive_drive_strength_from_max_mA(arg);
838 break;
839 case PIN_CONFIG_INPUT_ENABLE:
840 mask |= PAD_INPUT_ENABLE;
841 if (arg)
842 value |= PAD_INPUT_ENABLE;
843 else
844 value &= ~PAD_INPUT_ENABLE;
845 break;
846 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
847 mask |= PAD_INPUT_SCHMITT_ENABLE;
848 if (arg)
849 value |= PAD_INPUT_SCHMITT_ENABLE;
850 else
851 value &= ~PAD_INPUT_SCHMITT_ENABLE;
852 break;
853 case PIN_CONFIG_SLEW_RATE:
854 mask |= PAD_SLEW_RATE_MASK;
855 value = (value & ~PAD_SLEW_RATE_MASK) |
856 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
857 break;
858 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
859 if (arg) {
860 mask |= PAD_BIAS_MASK;
861 value = (value & ~PAD_BIAS_MASK) |
862 PAD_BIAS_STRONG_PULL_UP;
863 } else {
864 mask |= PAD_BIAS_STRONG_PULL_UP;
865 value = value & ~PAD_BIAS_STRONG_PULL_UP;
866 }
867 break;
868 default:
869 return -ENOTSUPP;
870 }
871 }
872
873 for (i = 0; i < group->grp.npins; i++)
874 starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value);
875
876 return 0;
877 }
878
879 #ifdef CONFIG_DEBUG_FS
starfive_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)880 static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
881 struct seq_file *s, unsigned int pin)
882 {
883 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
884 u16 value = starfive_padctl_get(sfp, pin);
885
886 seq_printf(s, " (0x%03x)", value);
887 }
888 #else
889 #define starfive_pinconf_dbg_show NULL
890 #endif
891
892 static const struct pinconf_ops starfive_pinconf_ops = {
893 .pin_config_get = starfive_pinconf_get,
894 .pin_config_group_get = starfive_pinconf_group_get,
895 .pin_config_group_set = starfive_pinconf_group_set,
896 .pin_config_dbg_show = starfive_pinconf_dbg_show,
897 .is_generic = true,
898 };
899
900 static const struct pinctrl_desc starfive_desc = {
901 .name = DRIVER_NAME,
902 .pins = starfive_pins,
903 .npins = ARRAY_SIZE(starfive_pins),
904 .pctlops = &starfive_pinctrl_ops,
905 .pmxops = &starfive_pinmux_ops,
906 .confops = &starfive_pinconf_ops,
907 .owner = THIS_MODULE,
908 .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
909 .custom_params = starfive_pinconf_custom_params,
910 .custom_conf_items = starfive_pinconf_custom_conf_items,
911 };
912
starfive_gpio_get_direction(struct gpio_chip * gc,unsigned int gpio)913 static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
914 {
915 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
916 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
917
918 if (readl_relaxed(doen) == GPO_ENABLE)
919 return GPIO_LINE_DIRECTION_OUT;
920
921 return GPIO_LINE_DIRECTION_IN;
922 }
923
starfive_gpio_direction_input(struct gpio_chip * gc,unsigned int gpio)924 static int starfive_gpio_direction_input(struct gpio_chip *gc,
925 unsigned int gpio)
926 {
927 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
928 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
929 unsigned long flags;
930
931 /* enable input and schmitt trigger */
932 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
933 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
934 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
935
936 raw_spin_lock_irqsave(&sfp->lock, flags);
937 writel_relaxed(GPO_DISABLE, doen);
938 raw_spin_unlock_irqrestore(&sfp->lock, flags);
939 return 0;
940 }
941
starfive_gpio_direction_output(struct gpio_chip * gc,unsigned int gpio,int value)942 static int starfive_gpio_direction_output(struct gpio_chip *gc,
943 unsigned int gpio, int value)
944 {
945 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
946 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
947 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
948 unsigned long flags;
949
950 raw_spin_lock_irqsave(&sfp->lock, flags);
951 writel_relaxed(value, dout);
952 writel_relaxed(GPO_ENABLE, doen);
953 raw_spin_unlock_irqrestore(&sfp->lock, flags);
954
955 /* disable input, schmitt trigger and bias */
956 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
957 PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
958 PAD_BIAS_DISABLE);
959
960 return 0;
961 }
962
starfive_gpio_get(struct gpio_chip * gc,unsigned int gpio)963 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
964 {
965 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
966 void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
967
968 return !!(readl_relaxed(din) & BIT(gpio % 32));
969 }
970
starfive_gpio_set(struct gpio_chip * gc,unsigned int gpio,int value)971 static int starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
972 int value)
973 {
974 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
975 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
976 unsigned long flags;
977
978 raw_spin_lock_irqsave(&sfp->lock, flags);
979 writel_relaxed(value, dout);
980 raw_spin_unlock_irqrestore(&sfp->lock, flags);
981
982 return 0;
983 }
984
starfive_gpio_set_config(struct gpio_chip * gc,unsigned int gpio,unsigned long config)985 static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
986 unsigned long config)
987 {
988 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
989 u32 arg = pinconf_to_config_argument(config);
990 u16 value;
991 u16 mask;
992
993 switch (pinconf_to_config_param(config)) {
994 case PIN_CONFIG_BIAS_DISABLE:
995 mask = PAD_BIAS_MASK;
996 value = PAD_BIAS_DISABLE;
997 break;
998 case PIN_CONFIG_BIAS_PULL_DOWN:
999 if (arg == 0)
1000 return -ENOTSUPP;
1001 mask = PAD_BIAS_MASK;
1002 value = PAD_BIAS_PULL_DOWN;
1003 break;
1004 case PIN_CONFIG_BIAS_PULL_UP:
1005 if (arg == 0)
1006 return -ENOTSUPP;
1007 mask = PAD_BIAS_MASK;
1008 value = 0;
1009 break;
1010 case PIN_CONFIG_DRIVE_PUSH_PULL:
1011 return 0;
1012 case PIN_CONFIG_INPUT_ENABLE:
1013 mask = PAD_INPUT_ENABLE;
1014 value = arg ? PAD_INPUT_ENABLE : 0;
1015 break;
1016 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1017 mask = PAD_INPUT_SCHMITT_ENABLE;
1018 value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
1019 break;
1020 default:
1021 return -ENOTSUPP;
1022 }
1023
1024 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1025 return 0;
1026 }
1027
starfive_gpio_add_pin_ranges(struct gpio_chip * gc)1028 static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
1029 {
1030 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1031
1032 sfp->gpios.name = sfp->gc.label;
1033 sfp->gpios.base = sfp->gc.base;
1034 /*
1035 * sfp->gpios.pin_base depends on the chosen signal group
1036 * and is set in starfive_probe()
1037 */
1038 sfp->gpios.npins = NR_GPIOS;
1039 sfp->gpios.gc = &sfp->gc;
1040 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1041 return 0;
1042 }
1043
starfive_irq_ack(struct irq_data * d)1044 static void starfive_irq_ack(struct irq_data *d)
1045 {
1046 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1047 irq_hw_number_t gpio = irqd_to_hwirq(d);
1048 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1049 u32 mask = BIT(gpio % 32);
1050 unsigned long flags;
1051
1052 raw_spin_lock_irqsave(&sfp->lock, flags);
1053 writel_relaxed(mask, ic);
1054 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1055 }
1056
starfive_irq_mask(struct irq_data * d)1057 static void starfive_irq_mask(struct irq_data *d)
1058 {
1059 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1060 irq_hw_number_t gpio = irqd_to_hwirq(d);
1061 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1062 u32 mask = BIT(gpio % 32);
1063 unsigned long flags;
1064 u32 value;
1065
1066 raw_spin_lock_irqsave(&sfp->lock, flags);
1067 value = readl_relaxed(ie) & ~mask;
1068 writel_relaxed(value, ie);
1069 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1070
1071 gpiochip_disable_irq(&sfp->gc, gpio);
1072 }
1073
starfive_irq_mask_ack(struct irq_data * d)1074 static void starfive_irq_mask_ack(struct irq_data *d)
1075 {
1076 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1077 irq_hw_number_t gpio = irqd_to_hwirq(d);
1078 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1079 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1080 u32 mask = BIT(gpio % 32);
1081 unsigned long flags;
1082 u32 value;
1083
1084 raw_spin_lock_irqsave(&sfp->lock, flags);
1085 value = readl_relaxed(ie) & ~mask;
1086 writel_relaxed(value, ie);
1087 writel_relaxed(mask, ic);
1088 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1089 }
1090
starfive_irq_unmask(struct irq_data * d)1091 static void starfive_irq_unmask(struct irq_data *d)
1092 {
1093 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1094 irq_hw_number_t gpio = irqd_to_hwirq(d);
1095 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1096 u32 mask = BIT(gpio % 32);
1097 unsigned long flags;
1098 u32 value;
1099
1100 gpiochip_enable_irq(&sfp->gc, gpio);
1101
1102 raw_spin_lock_irqsave(&sfp->lock, flags);
1103 value = readl_relaxed(ie) | mask;
1104 writel_relaxed(value, ie);
1105 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1106 }
1107
starfive_irq_set_type(struct irq_data * d,unsigned int trigger)1108 static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
1109 {
1110 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1111 irq_hw_number_t gpio = irqd_to_hwirq(d);
1112 void __iomem *base = sfp->base + 4 * (gpio / 32);
1113 u32 mask = BIT(gpio % 32);
1114 u32 irq_type, edge_both, polarity;
1115 unsigned long flags;
1116
1117 switch (trigger) {
1118 case IRQ_TYPE_EDGE_RISING:
1119 irq_type = mask; /* 1: edge triggered */
1120 edge_both = 0; /* 0: single edge */
1121 polarity = mask; /* 1: rising edge */
1122 break;
1123 case IRQ_TYPE_EDGE_FALLING:
1124 irq_type = mask; /* 1: edge triggered */
1125 edge_both = 0; /* 0: single edge */
1126 polarity = 0; /* 0: falling edge */
1127 break;
1128 case IRQ_TYPE_EDGE_BOTH:
1129 irq_type = mask; /* 1: edge triggered */
1130 edge_both = mask; /* 1: both edges */
1131 polarity = 0; /* 0: ignored */
1132 break;
1133 case IRQ_TYPE_LEVEL_HIGH:
1134 irq_type = 0; /* 0: level triggered */
1135 edge_both = 0; /* 0: ignored */
1136 polarity = mask; /* 1: high level */
1137 break;
1138 case IRQ_TYPE_LEVEL_LOW:
1139 irq_type = 0; /* 0: level triggered */
1140 edge_both = 0; /* 0: ignored */
1141 polarity = 0; /* 0: low level */
1142 break;
1143 default:
1144 return -EINVAL;
1145 }
1146
1147 if (trigger & IRQ_TYPE_EDGE_BOTH)
1148 irq_set_handler_locked(d, handle_edge_irq);
1149 else
1150 irq_set_handler_locked(d, handle_level_irq);
1151
1152 raw_spin_lock_irqsave(&sfp->lock, flags);
1153 irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
1154 writel_relaxed(irq_type, base + GPIOIS);
1155 edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
1156 writel_relaxed(edge_both, base + GPIOIBE);
1157 polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
1158 writel_relaxed(polarity, base + GPIOIEV);
1159 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1160 return 0;
1161 }
1162
1163 static const struct irq_chip starfive_irq_chip = {
1164 .name = "StarFive GPIO",
1165 .irq_ack = starfive_irq_ack,
1166 .irq_mask = starfive_irq_mask,
1167 .irq_mask_ack = starfive_irq_mask_ack,
1168 .irq_unmask = starfive_irq_unmask,
1169 .irq_set_type = starfive_irq_set_type,
1170 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1171 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1172 };
1173
starfive_gpio_irq_handler(struct irq_desc * desc)1174 static void starfive_gpio_irq_handler(struct irq_desc *desc)
1175 {
1176 struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1177 struct irq_chip *chip = irq_desc_get_chip(desc);
1178 unsigned long mis;
1179 unsigned int pin;
1180
1181 chained_irq_enter(chip, desc);
1182
1183 mis = readl_relaxed(sfp->base + GPIOMIS + 0);
1184 for_each_set_bit(pin, &mis, 32)
1185 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1186
1187 mis = readl_relaxed(sfp->base + GPIOMIS + 4);
1188 for_each_set_bit(pin, &mis, 32)
1189 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
1190
1191 chained_irq_exit(chip, desc);
1192 }
1193
starfive_gpio_init_hw(struct gpio_chip * gc)1194 static int starfive_gpio_init_hw(struct gpio_chip *gc)
1195 {
1196 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1197
1198 /* mask all GPIO interrupts */
1199 writel(0, sfp->base + GPIOIE + 0);
1200 writel(0, sfp->base + GPIOIE + 4);
1201 /* clear edge interrupt flags */
1202 writel(~0U, sfp->base + GPIOIC + 0);
1203 writel(~0U, sfp->base + GPIOIC + 4);
1204 /* enable GPIO interrupts */
1205 writel(1, sfp->base + GPIOEN);
1206 return 0;
1207 }
1208
starfive_disable_clock(void * data)1209 static void starfive_disable_clock(void *data)
1210 {
1211 clk_disable_unprepare(data);
1212 }
1213
starfive_probe(struct platform_device * pdev)1214 static int starfive_probe(struct platform_device *pdev)
1215 {
1216 struct device *dev = &pdev->dev;
1217 struct starfive_pinctrl *sfp;
1218 struct reset_control *rst;
1219 struct clk *clk;
1220 u32 value;
1221 int ret;
1222
1223 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1224 if (!sfp)
1225 return -ENOMEM;
1226
1227 sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
1228 if (IS_ERR(sfp->base))
1229 return PTR_ERR(sfp->base);
1230
1231 sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
1232 if (IS_ERR(sfp->padctl))
1233 return PTR_ERR(sfp->padctl);
1234
1235 clk = devm_clk_get(dev, NULL);
1236 if (IS_ERR(clk))
1237 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1238
1239 rst = devm_reset_control_get_exclusive(dev, NULL);
1240 if (IS_ERR(rst))
1241 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1242
1243 ret = clk_prepare_enable(clk);
1244 if (ret)
1245 return dev_err_probe(dev, ret, "could not enable clock\n");
1246
1247 ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
1248 if (ret)
1249 return ret;
1250
1251 /*
1252 * We don't want to assert reset and risk undoing pin muxing for the
1253 * early boot serial console, but let's make sure the reset line is
1254 * deasserted in case someone runs a really minimal bootloader.
1255 */
1256 ret = reset_control_deassert(rst);
1257 if (ret)
1258 return dev_err_probe(dev, ret, "could not deassert reset\n");
1259
1260 platform_set_drvdata(pdev, sfp);
1261 sfp->gc.parent = dev;
1262 raw_spin_lock_init(&sfp->lock);
1263 mutex_init(&sfp->mutex);
1264
1265 ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
1266 if (ret)
1267 return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
1268
1269 if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
1270 if (value > 6)
1271 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1272 writel(value, sfp->padctl + IO_PADSHARE_SEL);
1273 }
1274
1275 value = readl(sfp->padctl + IO_PADSHARE_SEL);
1276 switch (value) {
1277 case 0:
1278 sfp->gpios.pin_base = PAD_INVALID_GPIO;
1279 goto out_pinctrl_enable;
1280 case 1:
1281 sfp->gpios.pin_base = PAD_GPIO(0);
1282 break;
1283 case 2:
1284 sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
1285 break;
1286 case 3:
1287 sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
1288 break;
1289 case 4: case 5: case 6:
1290 sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
1291 break;
1292 default:
1293 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1294 }
1295
1296 sfp->gc.label = dev_name(dev);
1297 sfp->gc.owner = THIS_MODULE;
1298 sfp->gc.request = pinctrl_gpio_request;
1299 sfp->gc.free = pinctrl_gpio_free;
1300 sfp->gc.get_direction = starfive_gpio_get_direction;
1301 sfp->gc.direction_input = starfive_gpio_direction_input;
1302 sfp->gc.direction_output = starfive_gpio_direction_output;
1303 sfp->gc.get = starfive_gpio_get;
1304 sfp->gc.set = starfive_gpio_set;
1305 sfp->gc.set_config = starfive_gpio_set_config;
1306 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1307 sfp->gc.base = -1;
1308 sfp->gc.ngpio = NR_GPIOS;
1309
1310 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
1311 sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
1312 sfp->gc.irq.num_parents = 1;
1313 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1314 sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
1315 if (!sfp->gc.irq.parents)
1316 return -ENOMEM;
1317 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1318 sfp->gc.irq.handler = handle_bad_irq;
1319 sfp->gc.irq.init_hw = starfive_gpio_init_hw;
1320
1321 ret = platform_get_irq(pdev, 0);
1322 if (ret < 0)
1323 return ret;
1324 sfp->gc.irq.parents[0] = ret;
1325
1326 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1327 if (ret)
1328 return dev_err_probe(dev, ret, "could not register gpiochip\n");
1329
1330 irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1331
1332 out_pinctrl_enable:
1333 return pinctrl_enable(sfp->pctl);
1334 }
1335
1336 static const struct of_device_id starfive_of_match[] = {
1337 { .compatible = "starfive,jh7100-pinctrl" },
1338 { /* sentinel */ }
1339 };
1340 MODULE_DEVICE_TABLE(of, starfive_of_match);
1341
1342 static struct platform_driver starfive_pinctrl_driver = {
1343 .probe = starfive_probe,
1344 .driver = {
1345 .name = DRIVER_NAME,
1346 .of_match_table = starfive_of_match,
1347 },
1348 };
1349 module_platform_driver(starfive_pinctrl_driver);
1350
1351 MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
1352 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1353 MODULE_LICENSE("GPL v2");
1354