1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2025 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 39 #include <linux/unaligned.h> 40 41 #include "bcmgenet.h" 42 43 /* Default highest priority queue for multi queue support */ 44 #define GENET_Q1_PRIORITY 0 45 #define GENET_Q0_PRIORITY 1 46 47 #define GENET_Q0_RX_BD_CNT \ 48 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 49 #define GENET_Q0_TX_BD_CNT \ 50 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 51 52 #define RX_BUF_LENGTH 2048 53 #define SKB_ALIGNMENT 32 54 55 /* Tx/Rx DMA register offset, skip 256 descriptors */ 56 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 57 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 58 59 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 60 TOTAL_DESC * DMA_DESC_SIZE) 61 62 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65 /* Forward declarations */ 66 static void bcmgenet_set_rx_mode(struct net_device *dev); 67 68 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 69 { 70 /* MIPS chips strapped for BE will automagically configure the 71 * peripheral registers for CPU-native byte order. 72 */ 73 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 74 __raw_writel(value, offset); 75 else 76 writel_relaxed(value, offset); 77 } 78 79 static inline u32 bcmgenet_readl(void __iomem *offset) 80 { 81 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 82 return __raw_readl(offset); 83 else 84 return readl_relaxed(offset); 85 } 86 87 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 88 void __iomem *d, u32 value) 89 { 90 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 91 } 92 93 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 94 void __iomem *d, 95 dma_addr_t addr) 96 { 97 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 98 99 /* Register writes to GISB bus can take couple hundred nanoseconds 100 * and are done for each packet, save these expensive writes unless 101 * the platform is explicitly configured for 64-bits/LPAE. 102 */ 103 #ifdef CONFIG_PHYS_ADDR_T_64BIT 104 if (bcmgenet_has_40bits(priv)) 105 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 106 #endif 107 } 108 109 /* Combined address + length/status setter */ 110 static inline void dmadesc_set(struct bcmgenet_priv *priv, 111 void __iomem *d, dma_addr_t addr, u32 val) 112 { 113 dmadesc_set_addr(priv, d, addr); 114 dmadesc_set_length_status(priv, d, val); 115 } 116 117 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 118 119 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 120 NETIF_MSG_LINK) 121 122 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 123 { 124 if (GENET_IS_V1(priv)) 125 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 126 else 127 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 128 } 129 130 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 131 { 132 if (GENET_IS_V1(priv)) 133 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 134 else 135 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 136 } 137 138 /* These macros are defined to deal with register map change 139 * between GENET1.1 and GENET2. Only those currently being used 140 * by driver are defined. 141 */ 142 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 143 { 144 if (GENET_IS_V1(priv)) 145 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 146 else 147 return bcmgenet_readl(priv->base + 148 priv->hw_params->tbuf_offset + TBUF_CTRL); 149 } 150 151 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152 { 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 155 else 156 bcmgenet_writel(val, priv->base + 157 priv->hw_params->tbuf_offset + TBUF_CTRL); 158 } 159 160 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 161 { 162 if (GENET_IS_V1(priv)) 163 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 164 else 165 return bcmgenet_readl(priv->base + 166 priv->hw_params->tbuf_offset + TBUF_BP_MC); 167 } 168 169 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 170 { 171 if (GENET_IS_V1(priv)) 172 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 173 else 174 bcmgenet_writel(val, priv->base + 175 priv->hw_params->tbuf_offset + TBUF_BP_MC); 176 } 177 178 /* RX/TX DMA register accessors */ 179 enum dma_reg { 180 DMA_RING_CFG = 0, 181 DMA_CTRL, 182 DMA_STATUS, 183 DMA_SCB_BURST_SIZE, 184 DMA_ARB_CTRL, 185 DMA_PRIORITY_0, 186 DMA_PRIORITY_1, 187 DMA_PRIORITY_2, 188 DMA_INDEX2RING_0, 189 DMA_INDEX2RING_1, 190 DMA_INDEX2RING_2, 191 DMA_INDEX2RING_3, 192 DMA_INDEX2RING_4, 193 DMA_INDEX2RING_5, 194 DMA_INDEX2RING_6, 195 DMA_INDEX2RING_7, 196 DMA_RING0_TIMEOUT, 197 DMA_RING1_TIMEOUT, 198 DMA_RING2_TIMEOUT, 199 DMA_RING3_TIMEOUT, 200 DMA_RING4_TIMEOUT, 201 DMA_RING5_TIMEOUT, 202 DMA_RING6_TIMEOUT, 203 DMA_RING7_TIMEOUT, 204 DMA_RING8_TIMEOUT, 205 DMA_RING9_TIMEOUT, 206 DMA_RING10_TIMEOUT, 207 DMA_RING11_TIMEOUT, 208 DMA_RING12_TIMEOUT, 209 DMA_RING13_TIMEOUT, 210 DMA_RING14_TIMEOUT, 211 DMA_RING15_TIMEOUT, 212 DMA_RING16_TIMEOUT, 213 }; 214 215 static const u8 bcmgenet_dma_regs_v3plus[] = { 216 [DMA_RING_CFG] = 0x00, 217 [DMA_CTRL] = 0x04, 218 [DMA_STATUS] = 0x08, 219 [DMA_SCB_BURST_SIZE] = 0x0C, 220 [DMA_ARB_CTRL] = 0x2C, 221 [DMA_PRIORITY_0] = 0x30, 222 [DMA_PRIORITY_1] = 0x34, 223 [DMA_PRIORITY_2] = 0x38, 224 [DMA_RING0_TIMEOUT] = 0x2C, 225 [DMA_RING1_TIMEOUT] = 0x30, 226 [DMA_RING2_TIMEOUT] = 0x34, 227 [DMA_RING3_TIMEOUT] = 0x38, 228 [DMA_RING4_TIMEOUT] = 0x3c, 229 [DMA_RING5_TIMEOUT] = 0x40, 230 [DMA_RING6_TIMEOUT] = 0x44, 231 [DMA_RING7_TIMEOUT] = 0x48, 232 [DMA_RING8_TIMEOUT] = 0x4c, 233 [DMA_RING9_TIMEOUT] = 0x50, 234 [DMA_RING10_TIMEOUT] = 0x54, 235 [DMA_RING11_TIMEOUT] = 0x58, 236 [DMA_RING12_TIMEOUT] = 0x5c, 237 [DMA_RING13_TIMEOUT] = 0x60, 238 [DMA_RING14_TIMEOUT] = 0x64, 239 [DMA_RING15_TIMEOUT] = 0x68, 240 [DMA_RING16_TIMEOUT] = 0x6C, 241 [DMA_INDEX2RING_0] = 0x70, 242 [DMA_INDEX2RING_1] = 0x74, 243 [DMA_INDEX2RING_2] = 0x78, 244 [DMA_INDEX2RING_3] = 0x7C, 245 [DMA_INDEX2RING_4] = 0x80, 246 [DMA_INDEX2RING_5] = 0x84, 247 [DMA_INDEX2RING_6] = 0x88, 248 [DMA_INDEX2RING_7] = 0x8C, 249 }; 250 251 static const u8 bcmgenet_dma_regs_v2[] = { 252 [DMA_RING_CFG] = 0x00, 253 [DMA_CTRL] = 0x04, 254 [DMA_STATUS] = 0x08, 255 [DMA_SCB_BURST_SIZE] = 0x0C, 256 [DMA_ARB_CTRL] = 0x30, 257 [DMA_PRIORITY_0] = 0x34, 258 [DMA_PRIORITY_1] = 0x38, 259 [DMA_PRIORITY_2] = 0x3C, 260 [DMA_RING0_TIMEOUT] = 0x2C, 261 [DMA_RING1_TIMEOUT] = 0x30, 262 [DMA_RING2_TIMEOUT] = 0x34, 263 [DMA_RING3_TIMEOUT] = 0x38, 264 [DMA_RING4_TIMEOUT] = 0x3c, 265 [DMA_RING5_TIMEOUT] = 0x40, 266 [DMA_RING6_TIMEOUT] = 0x44, 267 [DMA_RING7_TIMEOUT] = 0x48, 268 [DMA_RING8_TIMEOUT] = 0x4c, 269 [DMA_RING9_TIMEOUT] = 0x50, 270 [DMA_RING10_TIMEOUT] = 0x54, 271 [DMA_RING11_TIMEOUT] = 0x58, 272 [DMA_RING12_TIMEOUT] = 0x5c, 273 [DMA_RING13_TIMEOUT] = 0x60, 274 [DMA_RING14_TIMEOUT] = 0x64, 275 [DMA_RING15_TIMEOUT] = 0x68, 276 [DMA_RING16_TIMEOUT] = 0x6C, 277 }; 278 279 static const u8 bcmgenet_dma_regs_v1[] = { 280 [DMA_CTRL] = 0x00, 281 [DMA_STATUS] = 0x04, 282 [DMA_SCB_BURST_SIZE] = 0x0C, 283 [DMA_ARB_CTRL] = 0x30, 284 [DMA_PRIORITY_0] = 0x34, 285 [DMA_PRIORITY_1] = 0x38, 286 [DMA_PRIORITY_2] = 0x3C, 287 [DMA_RING0_TIMEOUT] = 0x2C, 288 [DMA_RING1_TIMEOUT] = 0x30, 289 [DMA_RING2_TIMEOUT] = 0x34, 290 [DMA_RING3_TIMEOUT] = 0x38, 291 [DMA_RING4_TIMEOUT] = 0x3c, 292 [DMA_RING5_TIMEOUT] = 0x40, 293 [DMA_RING6_TIMEOUT] = 0x44, 294 [DMA_RING7_TIMEOUT] = 0x48, 295 [DMA_RING8_TIMEOUT] = 0x4c, 296 [DMA_RING9_TIMEOUT] = 0x50, 297 [DMA_RING10_TIMEOUT] = 0x54, 298 [DMA_RING11_TIMEOUT] = 0x58, 299 [DMA_RING12_TIMEOUT] = 0x5c, 300 [DMA_RING13_TIMEOUT] = 0x60, 301 [DMA_RING14_TIMEOUT] = 0x64, 302 [DMA_RING15_TIMEOUT] = 0x68, 303 [DMA_RING16_TIMEOUT] = 0x6C, 304 }; 305 306 /* Set at runtime once bcmgenet version is known */ 307 static const u8 *bcmgenet_dma_regs; 308 309 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 310 { 311 return netdev_priv(dev_get_drvdata(dev)); 312 } 313 314 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 315 enum dma_reg r) 316 { 317 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 318 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 319 } 320 321 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 322 u32 val, enum dma_reg r) 323 { 324 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 325 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 326 } 327 328 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 329 enum dma_reg r) 330 { 331 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 332 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 333 } 334 335 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 336 u32 val, enum dma_reg r) 337 { 338 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340 } 341 342 /* RDMA/TDMA ring registers and accessors 343 * we merge the common fields and just prefix with T/D the registers 344 * having different meaning depending on the direction 345 */ 346 enum dma_ring_reg { 347 TDMA_READ_PTR = 0, 348 RDMA_WRITE_PTR = TDMA_READ_PTR, 349 TDMA_READ_PTR_HI, 350 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 351 TDMA_CONS_INDEX, 352 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 353 TDMA_PROD_INDEX, 354 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 355 DMA_RING_BUF_SIZE, 356 DMA_START_ADDR, 357 DMA_START_ADDR_HI, 358 DMA_END_ADDR, 359 DMA_END_ADDR_HI, 360 DMA_MBUF_DONE_THRESH, 361 TDMA_FLOW_PERIOD, 362 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 363 TDMA_WRITE_PTR, 364 RDMA_READ_PTR = TDMA_WRITE_PTR, 365 TDMA_WRITE_PTR_HI, 366 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 367 }; 368 369 /* GENET v4 supports 40-bits pointer addressing 370 * for obvious reasons the LO and HI word parts 371 * are contiguous, but this offsets the other 372 * registers. 373 */ 374 static const u8 genet_dma_ring_regs_v4[] = { 375 [TDMA_READ_PTR] = 0x00, 376 [TDMA_READ_PTR_HI] = 0x04, 377 [TDMA_CONS_INDEX] = 0x08, 378 [TDMA_PROD_INDEX] = 0x0C, 379 [DMA_RING_BUF_SIZE] = 0x10, 380 [DMA_START_ADDR] = 0x14, 381 [DMA_START_ADDR_HI] = 0x18, 382 [DMA_END_ADDR] = 0x1C, 383 [DMA_END_ADDR_HI] = 0x20, 384 [DMA_MBUF_DONE_THRESH] = 0x24, 385 [TDMA_FLOW_PERIOD] = 0x28, 386 [TDMA_WRITE_PTR] = 0x2C, 387 [TDMA_WRITE_PTR_HI] = 0x30, 388 }; 389 390 static const u8 genet_dma_ring_regs_v123[] = { 391 [TDMA_READ_PTR] = 0x00, 392 [TDMA_CONS_INDEX] = 0x04, 393 [TDMA_PROD_INDEX] = 0x08, 394 [DMA_RING_BUF_SIZE] = 0x0C, 395 [DMA_START_ADDR] = 0x10, 396 [DMA_END_ADDR] = 0x14, 397 [DMA_MBUF_DONE_THRESH] = 0x18, 398 [TDMA_FLOW_PERIOD] = 0x1C, 399 [TDMA_WRITE_PTR] = 0x20, 400 }; 401 402 /* Set at runtime once GENET version is known */ 403 static const u8 *genet_dma_ring_regs; 404 405 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 406 unsigned int ring, 407 enum dma_ring_reg r) 408 { 409 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 410 (DMA_RING_SIZE * ring) + 411 genet_dma_ring_regs[r]); 412 } 413 414 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 415 unsigned int ring, u32 val, 416 enum dma_ring_reg r) 417 { 418 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 419 (DMA_RING_SIZE * ring) + 420 genet_dma_ring_regs[r]); 421 } 422 423 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 424 unsigned int ring, 425 enum dma_ring_reg r) 426 { 427 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 428 (DMA_RING_SIZE * ring) + 429 genet_dma_ring_regs[r]); 430 } 431 432 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 433 unsigned int ring, u32 val, 434 enum dma_ring_reg r) 435 { 436 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 437 (DMA_RING_SIZE * ring) + 438 genet_dma_ring_regs[r]); 439 } 440 441 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 442 { 443 u32 offset; 444 u32 reg; 445 446 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 447 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 448 reg |= (1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)) | 449 RBUF_HFB_EN; 450 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 451 } else { 452 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 453 reg = bcmgenet_hfb_reg_readl(priv, offset); 454 reg |= (1 << (f_index % 32)); 455 bcmgenet_hfb_reg_writel(priv, reg, offset); 456 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 457 reg |= RBUF_HFB_EN; 458 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 459 } 460 } 461 462 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 463 { 464 u32 offset, reg, reg1; 465 466 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 467 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 468 reg &= ~(1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)); 469 if (!(reg & RBUF_HFB_FILTER_EN_MASK)) 470 reg &= ~RBUF_HFB_EN; 471 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 472 } else { 473 offset = HFB_FLT_ENABLE_V3PLUS; 474 reg = bcmgenet_hfb_reg_readl(priv, offset); 475 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 476 if (f_index < 32) { 477 reg1 &= ~(1 << (f_index % 32)); 478 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 479 } else { 480 reg &= ~(1 << (f_index % 32)); 481 bcmgenet_hfb_reg_writel(priv, reg, offset); 482 } 483 if (!reg && !reg1) { 484 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 485 reg &= ~RBUF_HFB_EN; 486 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 487 } 488 } 489 } 490 491 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 492 u32 f_index, u32 rx_queue) 493 { 494 u32 offset; 495 u32 reg; 496 497 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 498 return; 499 500 offset = f_index / 8; 501 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 502 reg &= ~(0xF << (4 * (f_index % 8))); 503 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 504 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 505 } 506 507 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 508 u32 f_index, u32 f_length) 509 { 510 u32 offset; 511 u32 reg; 512 513 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 514 offset = HFB_FLT_LEN_V2; 515 else 516 offset = HFB_FLT_LEN_V3PLUS; 517 518 offset += sizeof(u32) * 519 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4); 520 reg = bcmgenet_hfb_reg_readl(priv, offset); 521 reg &= ~(0xFF << (8 * (f_index % 4))); 522 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 523 bcmgenet_hfb_reg_writel(priv, reg, offset); 524 } 525 526 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 527 { 528 while (size) { 529 switch (*(unsigned char *)mask++) { 530 case 0x00: 531 case 0x0f: 532 case 0xf0: 533 case 0xff: 534 size--; 535 continue; 536 default: 537 return -EINVAL; 538 } 539 } 540 541 return 0; 542 } 543 544 #define VALIDATE_MASK(x) \ 545 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 546 547 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 548 u32 offset, void *val, void *mask, 549 size_t size) 550 { 551 u32 index, tmp; 552 553 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 554 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 555 556 while (size--) { 557 if (offset++ & 1) { 558 tmp &= ~0x300FF; 559 tmp |= (*(unsigned char *)val++); 560 switch ((*(unsigned char *)mask++)) { 561 case 0xFF: 562 tmp |= 0x30000; 563 break; 564 case 0xF0: 565 tmp |= 0x20000; 566 break; 567 case 0x0F: 568 tmp |= 0x10000; 569 break; 570 } 571 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 572 if (size) 573 tmp = bcmgenet_hfb_readl(priv, 574 index * sizeof(u32)); 575 } else { 576 tmp &= ~0xCFF00; 577 tmp |= (*(unsigned char *)val++) << 8; 578 switch ((*(unsigned char *)mask++)) { 579 case 0xFF: 580 tmp |= 0xC0000; 581 break; 582 case 0xF0: 583 tmp |= 0x80000; 584 break; 585 case 0x0F: 586 tmp |= 0x40000; 587 break; 588 } 589 if (!size) 590 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 591 } 592 } 593 594 return 0; 595 } 596 597 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 598 struct bcmgenet_rxnfc_rule *rule) 599 { 600 struct ethtool_rx_flow_spec *fs = &rule->fs; 601 u32 offset = 0, f_length = 0, f, q; 602 u8 val_8, mask_8; 603 __be16 val_16; 604 u16 mask_16; 605 size_t size; 606 607 f = fs->location + 1; 608 if (fs->flow_type & FLOW_MAC_EXT) { 609 bcmgenet_hfb_insert_data(priv, f, 0, 610 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 611 sizeof(fs->h_ext.h_dest)); 612 } 613 614 if (fs->flow_type & FLOW_EXT) { 615 if (fs->m_ext.vlan_etype || 616 fs->m_ext.vlan_tci) { 617 bcmgenet_hfb_insert_data(priv, f, 12, 618 &fs->h_ext.vlan_etype, 619 &fs->m_ext.vlan_etype, 620 sizeof(fs->h_ext.vlan_etype)); 621 bcmgenet_hfb_insert_data(priv, f, 14, 622 &fs->h_ext.vlan_tci, 623 &fs->m_ext.vlan_tci, 624 sizeof(fs->h_ext.vlan_tci)); 625 offset += VLAN_HLEN; 626 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 627 } 628 } 629 630 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 631 case ETHER_FLOW: 632 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 633 bcmgenet_hfb_insert_data(priv, f, 0, 634 &fs->h_u.ether_spec.h_dest, 635 &fs->m_u.ether_spec.h_dest, 636 sizeof(fs->h_u.ether_spec.h_dest)); 637 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 638 &fs->h_u.ether_spec.h_source, 639 &fs->m_u.ether_spec.h_source, 640 sizeof(fs->h_u.ether_spec.h_source)); 641 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 642 &fs->h_u.ether_spec.h_proto, 643 &fs->m_u.ether_spec.h_proto, 644 sizeof(fs->h_u.ether_spec.h_proto)); 645 break; 646 case IP_USER_FLOW: 647 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 648 /* Specify IP Ether Type */ 649 val_16 = htons(ETH_P_IP); 650 mask_16 = 0xFFFF; 651 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 652 &val_16, &mask_16, sizeof(val_16)); 653 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 654 &fs->h_u.usr_ip4_spec.tos, 655 &fs->m_u.usr_ip4_spec.tos, 656 sizeof(fs->h_u.usr_ip4_spec.tos)); 657 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 658 &fs->h_u.usr_ip4_spec.proto, 659 &fs->m_u.usr_ip4_spec.proto, 660 sizeof(fs->h_u.usr_ip4_spec.proto)); 661 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 662 &fs->h_u.usr_ip4_spec.ip4src, 663 &fs->m_u.usr_ip4_spec.ip4src, 664 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 665 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 666 &fs->h_u.usr_ip4_spec.ip4dst, 667 &fs->m_u.usr_ip4_spec.ip4dst, 668 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 669 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 670 break; 671 672 /* Only supports 20 byte IPv4 header */ 673 val_8 = 0x45; 674 mask_8 = 0xFF; 675 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 676 &val_8, &mask_8, 677 sizeof(val_8)); 678 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 679 bcmgenet_hfb_insert_data(priv, f, 680 ETH_HLEN + 20 + offset, 681 &fs->h_u.usr_ip4_spec.l4_4_bytes, 682 &fs->m_u.usr_ip4_spec.l4_4_bytes, 683 size); 684 f_length += DIV_ROUND_UP(size, 2); 685 break; 686 } 687 688 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 689 if (fs->ring_cookie == RX_CLS_FLOW_WAKE) 690 q = 0; 691 else if (fs->ring_cookie == RX_CLS_FLOW_DISC) 692 q = priv->hw_params->rx_queues + 1; 693 else 694 /* Other Rx rings are direct mapped here */ 695 q = fs->ring_cookie; 696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, q); 697 bcmgenet_hfb_enable_filter(priv, f); 698 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 699 } 700 701 /* bcmgenet_hfb_clear 702 * 703 * Clear Hardware Filter Block and disable all filtering. 704 */ 705 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 706 { 707 u32 base, i; 708 709 bcmgenet_hfb_set_filter_length(priv, f_index, 0); 710 base = f_index * priv->hw_params->hfb_filter_size; 711 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 712 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 713 } 714 715 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 716 { 717 u32 i; 718 719 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 720 721 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) { 722 bcmgenet_hfb_reg_writel(priv, 0, 723 HFB_FLT_ENABLE_V3PLUS); 724 bcmgenet_hfb_reg_writel(priv, 0, 725 HFB_FLT_ENABLE_V3PLUS + 4); 726 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 727 bcmgenet_rdma_writel(priv, 0, i); 728 } 729 730 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 731 bcmgenet_hfb_clear_filter(priv, i); 732 733 /* Enable filter 0 to send default flow to ring 0 */ 734 bcmgenet_hfb_set_filter_length(priv, 0, 4); 735 bcmgenet_hfb_enable_filter(priv, 0); 736 } 737 738 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 739 { 740 int i; 741 742 INIT_LIST_HEAD(&priv->rxnfc_list); 743 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 744 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 745 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 746 } 747 748 bcmgenet_hfb_clear(priv); 749 } 750 751 static int bcmgenet_begin(struct net_device *dev) 752 { 753 struct bcmgenet_priv *priv = netdev_priv(dev); 754 755 /* Turn on the clock */ 756 return clk_prepare_enable(priv->clk); 757 } 758 759 static void bcmgenet_complete(struct net_device *dev) 760 { 761 struct bcmgenet_priv *priv = netdev_priv(dev); 762 763 /* Turn off the clock */ 764 clk_disable_unprepare(priv->clk); 765 } 766 767 static int bcmgenet_get_link_ksettings(struct net_device *dev, 768 struct ethtool_link_ksettings *cmd) 769 { 770 if (!netif_running(dev)) 771 return -EINVAL; 772 773 if (!dev->phydev) 774 return -ENODEV; 775 776 phy_ethtool_ksettings_get(dev->phydev, cmd); 777 778 return 0; 779 } 780 781 static int bcmgenet_set_link_ksettings(struct net_device *dev, 782 const struct ethtool_link_ksettings *cmd) 783 { 784 if (!netif_running(dev)) 785 return -EINVAL; 786 787 if (!dev->phydev) 788 return -ENODEV; 789 790 return phy_ethtool_ksettings_set(dev->phydev, cmd); 791 } 792 793 static int bcmgenet_set_features(struct net_device *dev, 794 netdev_features_t features) 795 { 796 struct bcmgenet_priv *priv = netdev_priv(dev); 797 u32 reg; 798 int ret; 799 800 ret = clk_prepare_enable(priv->clk); 801 if (ret) 802 return ret; 803 804 /* Make sure we reflect the value of CRC_CMD_FWD */ 805 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 806 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 807 808 clk_disable_unprepare(priv->clk); 809 810 return ret; 811 } 812 813 static u32 bcmgenet_get_msglevel(struct net_device *dev) 814 { 815 struct bcmgenet_priv *priv = netdev_priv(dev); 816 817 return priv->msg_enable; 818 } 819 820 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 821 { 822 struct bcmgenet_priv *priv = netdev_priv(dev); 823 824 priv->msg_enable = level; 825 } 826 827 static int bcmgenet_get_coalesce(struct net_device *dev, 828 struct ethtool_coalesce *ec, 829 struct kernel_ethtool_coalesce *kernel_coal, 830 struct netlink_ext_ack *extack) 831 { 832 struct bcmgenet_priv *priv = netdev_priv(dev); 833 struct bcmgenet_rx_ring *ring; 834 unsigned int i; 835 836 ec->tx_max_coalesced_frames = 837 bcmgenet_tdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 838 ec->rx_max_coalesced_frames = 839 bcmgenet_rdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 840 ec->rx_coalesce_usecs = 841 bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT) * 8192 / 1000; 842 843 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 844 ring = &priv->rx_rings[i]; 845 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 846 } 847 848 return 0; 849 } 850 851 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 852 u32 usecs, u32 pkts) 853 { 854 struct bcmgenet_priv *priv = ring->priv; 855 unsigned int i = ring->index; 856 u32 reg; 857 858 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 859 860 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 861 reg &= ~DMA_TIMEOUT_MASK; 862 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 863 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 864 } 865 866 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 867 struct ethtool_coalesce *ec) 868 { 869 struct dim_cq_moder moder; 870 u32 usecs, pkts; 871 872 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 873 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 874 usecs = ring->rx_coalesce_usecs; 875 pkts = ring->rx_max_coalesced_frames; 876 877 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 878 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 879 usecs = moder.usec; 880 pkts = moder.pkts; 881 } 882 883 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 884 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 885 } 886 887 static int bcmgenet_set_coalesce(struct net_device *dev, 888 struct ethtool_coalesce *ec, 889 struct kernel_ethtool_coalesce *kernel_coal, 890 struct netlink_ext_ack *extack) 891 { 892 struct bcmgenet_priv *priv = netdev_priv(dev); 893 unsigned int i; 894 895 /* Base system clock is 125Mhz, DMA timeout is this reference clock 896 * divided by 1024, which yields roughly 8.192us, our maximum value 897 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 898 */ 899 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 900 ec->tx_max_coalesced_frames == 0 || 901 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 902 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 903 return -EINVAL; 904 905 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 906 return -EINVAL; 907 908 /* GENET TDMA hardware does not support a configurable timeout, but will 909 * always generate an interrupt either after MBDONE packets have been 910 * transmitted, or when the ring is empty. 911 */ 912 913 /* Program all TX queues with the same values, as there is no 914 * ethtool knob to do coalescing on a per-queue basis 915 */ 916 for (i = 0; i <= priv->hw_params->tx_queues; i++) 917 bcmgenet_tdma_ring_writel(priv, i, 918 ec->tx_max_coalesced_frames, 919 DMA_MBUF_DONE_THRESH); 920 921 for (i = 0; i <= priv->hw_params->rx_queues; i++) 922 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 923 924 return 0; 925 } 926 927 static void bcmgenet_get_pauseparam(struct net_device *dev, 928 struct ethtool_pauseparam *epause) 929 { 930 struct bcmgenet_priv *priv; 931 u32 umac_cmd; 932 933 priv = netdev_priv(dev); 934 935 epause->autoneg = priv->autoneg_pause; 936 937 if (netif_carrier_ok(dev)) { 938 /* report active state when link is up */ 939 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD); 940 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE); 941 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE); 942 } else { 943 /* otherwise report stored settings */ 944 epause->tx_pause = priv->tx_pause; 945 epause->rx_pause = priv->rx_pause; 946 } 947 } 948 949 static int bcmgenet_set_pauseparam(struct net_device *dev, 950 struct ethtool_pauseparam *epause) 951 { 952 struct bcmgenet_priv *priv = netdev_priv(dev); 953 954 if (!dev->phydev) 955 return -ENODEV; 956 957 if (!phy_validate_pause(dev->phydev, epause)) 958 return -EINVAL; 959 960 priv->autoneg_pause = !!epause->autoneg; 961 priv->tx_pause = !!epause->tx_pause; 962 priv->rx_pause = !!epause->rx_pause; 963 964 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 965 966 return 0; 967 } 968 969 /* standard ethtool support functions. */ 970 enum bcmgenet_stat_type { 971 BCMGENET_STAT_RTNL = -1, 972 BCMGENET_STAT_MIB_RX, 973 BCMGENET_STAT_MIB_TX, 974 BCMGENET_STAT_RUNT, 975 BCMGENET_STAT_MISC, 976 BCMGENET_STAT_SOFT, 977 BCMGENET_STAT_SOFT64, 978 }; 979 980 struct bcmgenet_stats { 981 char stat_string[ETH_GSTRING_LEN]; 982 int stat_sizeof; 983 int stat_offset; 984 enum bcmgenet_stat_type type; 985 /* reg offset from UMAC base for misc counters */ 986 u16 reg_offset; 987 /* sync for u64 stats counters */ 988 int syncp_offset; 989 }; 990 991 #define STAT_RTNL(m) { \ 992 .stat_string = __stringify(m), \ 993 .stat_sizeof = sizeof(((struct rtnl_link_stats64 *)0)->m), \ 994 .stat_offset = offsetof(struct rtnl_link_stats64, m), \ 995 .type = BCMGENET_STAT_RTNL, \ 996 } 997 998 #define STAT_GENET_MIB(str, m, _type) { \ 999 .stat_string = str, \ 1000 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1001 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1002 .type = _type, \ 1003 } 1004 1005 #define STAT_GENET_SOFT_MIB64(str, s, m) { \ 1006 .stat_string = str, \ 1007 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->s.m), \ 1008 .stat_offset = offsetof(struct bcmgenet_priv, s.m), \ 1009 .type = BCMGENET_STAT_SOFT64, \ 1010 .syncp_offset = offsetof(struct bcmgenet_priv, s.syncp), \ 1011 } 1012 1013 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 1014 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 1015 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 1016 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 1017 1018 #define STAT_GENET_MISC(str, m, offset) { \ 1019 .stat_string = str, \ 1020 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1021 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1022 .type = BCMGENET_STAT_MISC, \ 1023 .reg_offset = offset, \ 1024 } 1025 1026 #define STAT_GENET_Q(num) \ 1027 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_packets", \ 1028 tx_rings[num].stats64, packets), \ 1029 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_bytes", \ 1030 tx_rings[num].stats64, bytes), \ 1031 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_errors", \ 1032 tx_rings[num].stats64, errors), \ 1033 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_dropped", \ 1034 tx_rings[num].stats64, dropped), \ 1035 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_bytes", \ 1036 rx_rings[num].stats64, bytes), \ 1037 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_packets", \ 1038 rx_rings[num].stats64, packets), \ 1039 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_errors", \ 1040 rx_rings[num].stats64, errors), \ 1041 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_dropped", \ 1042 rx_rings[num].stats64, dropped), \ 1043 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_multicast", \ 1044 rx_rings[num].stats64, multicast), \ 1045 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_missed", \ 1046 rx_rings[num].stats64, missed), \ 1047 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_length_errors", \ 1048 rx_rings[num].stats64, length_errors), \ 1049 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_over_errors", \ 1050 rx_rings[num].stats64, over_errors), \ 1051 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_crc_errors", \ 1052 rx_rings[num].stats64, crc_errors), \ 1053 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_frame_errors", \ 1054 rx_rings[num].stats64, frame_errors), \ 1055 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_fragmented_errors", \ 1056 rx_rings[num].stats64, fragmented_errors), \ 1057 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_broadcast", \ 1058 rx_rings[num].stats64, broadcast) 1059 1060 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 1061 * between the end of TX stats and the beginning of the RX RUNT 1062 */ 1063 #define BCMGENET_STAT_OFFSET 0xc 1064 1065 /* Hardware counters must be kept in sync because the order/offset 1066 * is important here (order in structure declaration = order in hardware) 1067 */ 1068 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1069 /* general stats */ 1070 STAT_RTNL(rx_packets), 1071 STAT_RTNL(tx_packets), 1072 STAT_RTNL(rx_bytes), 1073 STAT_RTNL(tx_bytes), 1074 STAT_RTNL(rx_errors), 1075 STAT_RTNL(tx_errors), 1076 STAT_RTNL(rx_dropped), 1077 STAT_RTNL(tx_dropped), 1078 STAT_RTNL(multicast), 1079 STAT_RTNL(rx_missed_errors), 1080 STAT_RTNL(rx_length_errors), 1081 STAT_RTNL(rx_over_errors), 1082 STAT_RTNL(rx_crc_errors), 1083 STAT_RTNL(rx_frame_errors), 1084 /* UniMAC RSV counters */ 1085 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1086 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1087 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1088 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1089 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1090 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1091 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1092 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1093 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1094 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1095 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1096 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1097 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1098 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1099 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1100 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1101 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1102 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1103 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1104 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1105 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1106 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1107 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1108 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1109 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1110 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1111 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1112 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1113 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1114 /* UniMAC TSV counters */ 1115 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1116 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1117 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1118 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1119 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1120 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1121 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1122 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1123 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1124 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1125 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1126 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1127 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1128 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1129 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1130 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1131 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1132 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1133 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1134 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1135 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1136 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1137 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1138 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1139 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1140 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1141 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1142 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1143 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1144 /* UniMAC RUNT counters */ 1145 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1146 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1147 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1148 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1149 /* Misc UniMAC counters */ 1150 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1151 UMAC_RBUF_OVFL_CNT_V1), 1152 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1153 UMAC_RBUF_ERR_CNT_V1), 1154 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1155 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1156 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1157 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1158 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1159 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1160 mib.tx_realloc_tsb_failed), 1161 /* Per TX queues */ 1162 STAT_GENET_Q(0), 1163 STAT_GENET_Q(1), 1164 STAT_GENET_Q(2), 1165 STAT_GENET_Q(3), 1166 STAT_GENET_Q(4), 1167 }; 1168 1169 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1170 1171 #define BCMGENET_STATS64_ADD(stats, m, v) \ 1172 do { \ 1173 u64_stats_update_begin(&stats->syncp); \ 1174 u64_stats_add(&stats->m, v); \ 1175 u64_stats_update_end(&stats->syncp); \ 1176 } while (0) 1177 1178 #define BCMGENET_STATS64_INC(stats, m) \ 1179 do { \ 1180 u64_stats_update_begin(&stats->syncp); \ 1181 u64_stats_inc(&stats->m); \ 1182 u64_stats_update_end(&stats->syncp); \ 1183 } while (0) 1184 1185 static void bcmgenet_get_drvinfo(struct net_device *dev, 1186 struct ethtool_drvinfo *info) 1187 { 1188 strscpy(info->driver, "bcmgenet", sizeof(info->driver)); 1189 } 1190 1191 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1192 { 1193 switch (string_set) { 1194 case ETH_SS_STATS: 1195 return BCMGENET_STATS_LEN; 1196 default: 1197 return -EOPNOTSUPP; 1198 } 1199 } 1200 1201 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1202 u8 *data) 1203 { 1204 const char *str; 1205 int i; 1206 1207 switch (stringset) { 1208 case ETH_SS_STATS: 1209 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1210 str = bcmgenet_gstrings_stats[i].stat_string; 1211 ethtool_puts(&data, str); 1212 } 1213 break; 1214 } 1215 } 1216 1217 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1218 { 1219 u16 new_offset; 1220 u32 val; 1221 1222 switch (offset) { 1223 case UMAC_RBUF_OVFL_CNT_V1: 1224 if (GENET_IS_V2(priv)) 1225 new_offset = RBUF_OVFL_CNT_V2; 1226 else 1227 new_offset = RBUF_OVFL_CNT_V3PLUS; 1228 1229 val = bcmgenet_rbuf_readl(priv, new_offset); 1230 /* clear if overflowed */ 1231 if (val == ~0) 1232 bcmgenet_rbuf_writel(priv, 0, new_offset); 1233 break; 1234 case UMAC_RBUF_ERR_CNT_V1: 1235 if (GENET_IS_V2(priv)) 1236 new_offset = RBUF_ERR_CNT_V2; 1237 else 1238 new_offset = RBUF_ERR_CNT_V3PLUS; 1239 1240 val = bcmgenet_rbuf_readl(priv, new_offset); 1241 /* clear if overflowed */ 1242 if (val == ~0) 1243 bcmgenet_rbuf_writel(priv, 0, new_offset); 1244 break; 1245 default: 1246 val = bcmgenet_umac_readl(priv, offset); 1247 /* clear if overflowed */ 1248 if (val == ~0) 1249 bcmgenet_umac_writel(priv, 0, offset); 1250 break; 1251 } 1252 1253 return val; 1254 } 1255 1256 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1257 { 1258 int i, j = 0; 1259 1260 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1261 const struct bcmgenet_stats *s; 1262 u8 offset = 0; 1263 u32 val = 0; 1264 char *p; 1265 1266 s = &bcmgenet_gstrings_stats[i]; 1267 switch (s->type) { 1268 case BCMGENET_STAT_RTNL: 1269 case BCMGENET_STAT_SOFT: 1270 case BCMGENET_STAT_SOFT64: 1271 continue; 1272 case BCMGENET_STAT_RUNT: 1273 offset += BCMGENET_STAT_OFFSET; 1274 fallthrough; 1275 case BCMGENET_STAT_MIB_TX: 1276 offset += BCMGENET_STAT_OFFSET; 1277 fallthrough; 1278 case BCMGENET_STAT_MIB_RX: 1279 val = bcmgenet_umac_readl(priv, 1280 UMAC_MIB_START + j + offset); 1281 offset = 0; /* Reset Offset */ 1282 break; 1283 case BCMGENET_STAT_MISC: 1284 if (GENET_IS_V1(priv)) { 1285 val = bcmgenet_umac_readl(priv, s->reg_offset); 1286 /* clear if overflowed */ 1287 if (val == ~0) 1288 bcmgenet_umac_writel(priv, 0, 1289 s->reg_offset); 1290 } else { 1291 val = bcmgenet_update_stat_misc(priv, 1292 s->reg_offset); 1293 } 1294 break; 1295 } 1296 1297 j += s->stat_sizeof; 1298 p = (char *)priv + s->stat_offset; 1299 *(u32 *)p = val; 1300 } 1301 } 1302 1303 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1304 struct ethtool_stats *stats, 1305 u64 *data) 1306 { 1307 struct bcmgenet_priv *priv = netdev_priv(dev); 1308 struct rtnl_link_stats64 stats64; 1309 struct u64_stats_sync *syncp; 1310 unsigned int start; 1311 int i; 1312 1313 if (netif_running(dev)) 1314 bcmgenet_update_mib_counters(priv); 1315 1316 dev_get_stats(dev, &stats64); 1317 1318 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1319 const struct bcmgenet_stats *s; 1320 char *p; 1321 1322 s = &bcmgenet_gstrings_stats[i]; 1323 p = (char *)priv; 1324 1325 if (s->type == BCMGENET_STAT_SOFT64) { 1326 syncp = (struct u64_stats_sync *)(p + s->syncp_offset); 1327 do { 1328 start = u64_stats_fetch_begin(syncp); 1329 data[i] = u64_stats_read((u64_stats_t *)(p + s->stat_offset)); 1330 } while (u64_stats_fetch_retry(syncp, start)); 1331 } else { 1332 if (s->type == BCMGENET_STAT_RTNL) 1333 p = (char *)&stats64; 1334 1335 p += s->stat_offset; 1336 if (sizeof(unsigned long) != sizeof(u32) && 1337 s->stat_sizeof == sizeof(unsigned long)) 1338 data[i] = *(unsigned long *)p; 1339 else 1340 data[i] = *(u32 *)p; 1341 } 1342 } 1343 } 1344 1345 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable, 1346 bool tx_lpi_enabled) 1347 { 1348 struct bcmgenet_priv *priv = netdev_priv(dev); 1349 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1350 u32 reg; 1351 1352 if (enable && !priv->clk_eee_enabled) { 1353 clk_prepare_enable(priv->clk_eee); 1354 priv->clk_eee_enabled = true; 1355 } 1356 1357 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1358 if (enable) 1359 reg |= EEE_EN; 1360 else 1361 reg &= ~EEE_EN; 1362 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1363 1364 /* Enable EEE and switch to a 27Mhz clock automatically */ 1365 reg = bcmgenet_readl(priv->base + off); 1366 if (tx_lpi_enabled) 1367 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1368 else 1369 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1370 bcmgenet_writel(reg, priv->base + off); 1371 1372 /* Do the same for thing for RBUF */ 1373 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1374 if (enable) 1375 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1376 else 1377 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1378 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1379 1380 if (!enable && priv->clk_eee_enabled) { 1381 clk_disable_unprepare(priv->clk_eee); 1382 priv->clk_eee_enabled = false; 1383 } 1384 1385 priv->eee.eee_enabled = enable; 1386 priv->eee.tx_lpi_enabled = tx_lpi_enabled; 1387 } 1388 1389 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e) 1390 { 1391 struct bcmgenet_priv *priv = netdev_priv(dev); 1392 struct ethtool_keee *p = &priv->eee; 1393 1394 if (GENET_IS_V1(priv)) 1395 return -EOPNOTSUPP; 1396 1397 if (!dev->phydev) 1398 return -ENODEV; 1399 1400 e->tx_lpi_enabled = p->tx_lpi_enabled; 1401 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1402 1403 return phy_ethtool_get_eee(dev->phydev, e); 1404 } 1405 1406 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e) 1407 { 1408 struct bcmgenet_priv *priv = netdev_priv(dev); 1409 struct ethtool_keee *p = &priv->eee; 1410 bool active; 1411 1412 if (GENET_IS_V1(priv)) 1413 return -EOPNOTSUPP; 1414 1415 if (!dev->phydev) 1416 return -ENODEV; 1417 1418 p->eee_enabled = e->eee_enabled; 1419 1420 if (!p->eee_enabled) { 1421 bcmgenet_eee_enable_set(dev, false, false); 1422 } else { 1423 active = phy_init_eee(dev->phydev, false) >= 0; 1424 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1425 bcmgenet_eee_enable_set(dev, active, e->tx_lpi_enabled); 1426 } 1427 1428 return phy_ethtool_set_eee(dev->phydev, e); 1429 } 1430 1431 static int bcmgenet_validate_flow(struct net_device *dev, 1432 struct ethtool_rxnfc *cmd) 1433 { 1434 struct ethtool_usrip4_spec *l4_mask; 1435 struct ethhdr *eth_mask; 1436 1437 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES && 1438 cmd->fs.location != RX_CLS_LOC_ANY) { 1439 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1440 cmd->fs.location); 1441 return -EINVAL; 1442 } 1443 1444 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1445 case IP_USER_FLOW: 1446 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1447 /* don't allow mask which isn't valid */ 1448 if (VALIDATE_MASK(l4_mask->ip4src) || 1449 VALIDATE_MASK(l4_mask->ip4dst) || 1450 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1451 VALIDATE_MASK(l4_mask->proto) || 1452 VALIDATE_MASK(l4_mask->ip_ver) || 1453 VALIDATE_MASK(l4_mask->tos)) { 1454 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1455 return -EINVAL; 1456 } 1457 break; 1458 case ETHER_FLOW: 1459 eth_mask = &cmd->fs.m_u.ether_spec; 1460 /* don't allow mask which isn't valid */ 1461 if (VALIDATE_MASK(eth_mask->h_dest) || 1462 VALIDATE_MASK(eth_mask->h_source) || 1463 VALIDATE_MASK(eth_mask->h_proto)) { 1464 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1465 return -EINVAL; 1466 } 1467 break; 1468 default: 1469 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1470 cmd->fs.flow_type); 1471 return -EINVAL; 1472 } 1473 1474 if ((cmd->fs.flow_type & FLOW_EXT)) { 1475 /* don't allow mask which isn't valid */ 1476 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1477 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1478 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1479 return -EINVAL; 1480 } 1481 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1482 netdev_err(dev, "rxnfc: user-def not supported\n"); 1483 return -EINVAL; 1484 } 1485 } 1486 1487 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1488 /* don't allow mask which isn't valid */ 1489 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1490 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1491 return -EINVAL; 1492 } 1493 } 1494 1495 return 0; 1496 } 1497 1498 static int bcmgenet_insert_flow(struct net_device *dev, 1499 struct ethtool_rxnfc *cmd) 1500 { 1501 struct bcmgenet_priv *priv = netdev_priv(dev); 1502 struct bcmgenet_rxnfc_rule *loc_rule; 1503 int err, i; 1504 1505 if (priv->hw_params->hfb_filter_size < 128) { 1506 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1507 return -EINVAL; 1508 } 1509 1510 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1511 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE && 1512 cmd->fs.ring_cookie != RX_CLS_FLOW_DISC) { 1513 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1514 cmd->fs.ring_cookie); 1515 return -EINVAL; 1516 } 1517 1518 err = bcmgenet_validate_flow(dev, cmd); 1519 if (err) 1520 return err; 1521 1522 if (cmd->fs.location == RX_CLS_LOC_ANY) { 1523 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) { 1524 cmd->fs.location = loc_rule->fs.location; 1525 err = memcmp(&loc_rule->fs, &cmd->fs, 1526 sizeof(struct ethtool_rx_flow_spec)); 1527 if (!err) 1528 /* rule exists so return current location */ 1529 return 0; 1530 } 1531 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1532 loc_rule = &priv->rxnfc_rules[i]; 1533 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1534 cmd->fs.location = i; 1535 break; 1536 } 1537 } 1538 if (i == MAX_NUM_OF_FS_RULES) { 1539 cmd->fs.location = RX_CLS_LOC_ANY; 1540 return -ENOSPC; 1541 } 1542 } else { 1543 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1544 } 1545 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1546 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1547 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1548 list_del(&loc_rule->list); 1549 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1550 } 1551 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1552 memcpy(&loc_rule->fs, &cmd->fs, 1553 sizeof(struct ethtool_rx_flow_spec)); 1554 1555 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1556 1557 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1558 1559 return 0; 1560 } 1561 1562 static int bcmgenet_delete_flow(struct net_device *dev, 1563 struct ethtool_rxnfc *cmd) 1564 { 1565 struct bcmgenet_priv *priv = netdev_priv(dev); 1566 struct bcmgenet_rxnfc_rule *rule; 1567 int err = 0; 1568 1569 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1570 return -EINVAL; 1571 1572 rule = &priv->rxnfc_rules[cmd->fs.location]; 1573 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1574 err = -ENOENT; 1575 goto out; 1576 } 1577 1578 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1579 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1580 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1581 list_del(&rule->list); 1582 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1583 } 1584 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1585 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1586 1587 out: 1588 return err; 1589 } 1590 1591 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1592 { 1593 struct bcmgenet_priv *priv = netdev_priv(dev); 1594 int err = 0; 1595 1596 switch (cmd->cmd) { 1597 case ETHTOOL_SRXCLSRLINS: 1598 err = bcmgenet_insert_flow(dev, cmd); 1599 break; 1600 case ETHTOOL_SRXCLSRLDEL: 1601 err = bcmgenet_delete_flow(dev, cmd); 1602 break; 1603 default: 1604 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1605 cmd->cmd); 1606 return -EINVAL; 1607 } 1608 1609 return err; 1610 } 1611 1612 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1613 int loc) 1614 { 1615 struct bcmgenet_priv *priv = netdev_priv(dev); 1616 struct bcmgenet_rxnfc_rule *rule; 1617 int err = 0; 1618 1619 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1620 return -EINVAL; 1621 1622 rule = &priv->rxnfc_rules[loc]; 1623 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1624 err = -ENOENT; 1625 else 1626 memcpy(&cmd->fs, &rule->fs, 1627 sizeof(struct ethtool_rx_flow_spec)); 1628 1629 return err; 1630 } 1631 1632 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1633 { 1634 struct list_head *pos; 1635 int res = 0; 1636 1637 list_for_each(pos, &priv->rxnfc_list) 1638 res++; 1639 1640 return res; 1641 } 1642 1643 static u32 bcmgenet_get_rx_ring_count(struct net_device *dev) 1644 { 1645 struct bcmgenet_priv *priv = netdev_priv(dev); 1646 1647 return priv->hw_params->rx_queues ?: 1; 1648 } 1649 1650 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1651 u32 *rule_locs) 1652 { 1653 struct bcmgenet_priv *priv = netdev_priv(dev); 1654 struct bcmgenet_rxnfc_rule *rule; 1655 int err = 0; 1656 int i = 0; 1657 1658 switch (cmd->cmd) { 1659 case ETHTOOL_GRXCLSRLCNT: 1660 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1661 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL; 1662 break; 1663 case ETHTOOL_GRXCLSRULE: 1664 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1665 break; 1666 case ETHTOOL_GRXCLSRLALL: 1667 list_for_each_entry(rule, &priv->rxnfc_list, list) 1668 if (i < cmd->rule_cnt) 1669 rule_locs[i++] = rule->fs.location; 1670 cmd->rule_cnt = i; 1671 cmd->data = MAX_NUM_OF_FS_RULES; 1672 break; 1673 default: 1674 err = -EOPNOTSUPP; 1675 break; 1676 } 1677 1678 return err; 1679 } 1680 1681 /* standard ethtool support functions. */ 1682 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1683 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1684 ETHTOOL_COALESCE_MAX_FRAMES | 1685 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1686 .begin = bcmgenet_begin, 1687 .complete = bcmgenet_complete, 1688 .get_strings = bcmgenet_get_strings, 1689 .get_sset_count = bcmgenet_get_sset_count, 1690 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1691 .get_drvinfo = bcmgenet_get_drvinfo, 1692 .get_link = ethtool_op_get_link, 1693 .get_msglevel = bcmgenet_get_msglevel, 1694 .set_msglevel = bcmgenet_set_msglevel, 1695 .get_wol = bcmgenet_get_wol, 1696 .set_wol = bcmgenet_set_wol, 1697 .get_eee = bcmgenet_get_eee, 1698 .set_eee = bcmgenet_set_eee, 1699 .nway_reset = phy_ethtool_nway_reset, 1700 .get_coalesce = bcmgenet_get_coalesce, 1701 .set_coalesce = bcmgenet_set_coalesce, 1702 .get_link_ksettings = bcmgenet_get_link_ksettings, 1703 .set_link_ksettings = bcmgenet_set_link_ksettings, 1704 .get_ts_info = ethtool_op_get_ts_info, 1705 .get_rxnfc = bcmgenet_get_rxnfc, 1706 .set_rxnfc = bcmgenet_set_rxnfc, 1707 .get_rx_ring_count = bcmgenet_get_rx_ring_count, 1708 .get_pauseparam = bcmgenet_get_pauseparam, 1709 .set_pauseparam = bcmgenet_set_pauseparam, 1710 }; 1711 1712 /* Power down the unimac, based on mode. */ 1713 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1714 enum bcmgenet_power_mode mode) 1715 { 1716 int ret = 0; 1717 u32 reg; 1718 1719 switch (mode) { 1720 case GENET_POWER_CABLE_SENSE: 1721 phy_detach(priv->dev->phydev); 1722 break; 1723 1724 case GENET_POWER_WOL_MAGIC: 1725 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1726 break; 1727 1728 case GENET_POWER_PASSIVE: 1729 /* Power down LED */ 1730 if (bcmgenet_has_ext(priv)) { 1731 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1732 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) 1733 reg |= EXT_PWR_DOWN_PHY_EN | 1734 EXT_PWR_DOWN_PHY_RD | 1735 EXT_PWR_DOWN_PHY_SD | 1736 EXT_PWR_DOWN_PHY_RX | 1737 EXT_PWR_DOWN_PHY_TX | 1738 EXT_IDDQ_GLBL_PWR; 1739 else 1740 reg |= EXT_PWR_DOWN_PHY; 1741 1742 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1743 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1744 1745 bcmgenet_phy_power_set(priv->dev, false); 1746 } 1747 break; 1748 default: 1749 break; 1750 } 1751 1752 return ret; 1753 } 1754 1755 static int bcmgenet_power_up(struct bcmgenet_priv *priv, 1756 enum bcmgenet_power_mode mode) 1757 { 1758 int ret = 0; 1759 u32 reg; 1760 1761 if (!bcmgenet_has_ext(priv)) 1762 return ret; 1763 1764 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1765 1766 switch (mode) { 1767 case GENET_POWER_PASSIVE: 1768 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1769 EXT_ENERGY_DET_MASK); 1770 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) { 1771 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1772 EXT_PWR_DOWN_PHY_RD | 1773 EXT_PWR_DOWN_PHY_SD | 1774 EXT_PWR_DOWN_PHY_RX | 1775 EXT_PWR_DOWN_PHY_TX | 1776 EXT_IDDQ_GLBL_PWR); 1777 reg |= EXT_PHY_RESET; 1778 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1779 mdelay(1); 1780 1781 reg &= ~EXT_PHY_RESET; 1782 } else { 1783 reg &= ~EXT_PWR_DOWN_PHY; 1784 reg |= EXT_PWR_DN_EN_LD; 1785 } 1786 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1787 bcmgenet_phy_power_set(priv->dev, true); 1788 break; 1789 1790 case GENET_POWER_CABLE_SENSE: 1791 /* enable APD */ 1792 if (!GENET_IS_V5(priv)) { 1793 reg |= EXT_PWR_DN_EN_LD; 1794 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1795 } 1796 break; 1797 case GENET_POWER_WOL_MAGIC: 1798 ret = bcmgenet_wol_power_up_cfg(priv, mode); 1799 break; 1800 default: 1801 break; 1802 } 1803 1804 return ret; 1805 } 1806 1807 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1808 struct bcmgenet_tx_ring *ring) 1809 { 1810 struct enet_cb *tx_cb_ptr; 1811 1812 tx_cb_ptr = ring->cbs; 1813 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1814 1815 /* Advancing local write pointer */ 1816 if (ring->write_ptr == ring->end_ptr) 1817 ring->write_ptr = ring->cb_ptr; 1818 else 1819 ring->write_ptr++; 1820 1821 return tx_cb_ptr; 1822 } 1823 1824 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1825 struct bcmgenet_tx_ring *ring) 1826 { 1827 struct enet_cb *tx_cb_ptr; 1828 1829 tx_cb_ptr = ring->cbs; 1830 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1831 1832 /* Rewinding local write pointer */ 1833 if (ring->write_ptr == ring->cb_ptr) 1834 ring->write_ptr = ring->end_ptr; 1835 else 1836 ring->write_ptr--; 1837 1838 return tx_cb_ptr; 1839 } 1840 1841 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1842 { 1843 bcmgenet_intrl2_1_writel(ring->priv, 1844 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1845 INTRL2_CPU_MASK_SET); 1846 } 1847 1848 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1849 { 1850 bcmgenet_intrl2_1_writel(ring->priv, 1851 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1852 INTRL2_CPU_MASK_CLEAR); 1853 } 1854 1855 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1856 { 1857 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1858 INTRL2_CPU_MASK_CLEAR); 1859 } 1860 1861 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1862 { 1863 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1864 INTRL2_CPU_MASK_SET); 1865 } 1866 1867 /* Simple helper to free a transmit control block's resources 1868 * Returns an skb when the last transmit control block associated with the 1869 * skb is freed. The skb should be freed by the caller if necessary. 1870 */ 1871 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1872 struct enet_cb *cb) 1873 { 1874 struct sk_buff *skb; 1875 1876 skb = cb->skb; 1877 1878 if (skb) { 1879 cb->skb = NULL; 1880 if (cb == GENET_CB(skb)->first_cb) 1881 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1882 dma_unmap_len(cb, dma_len), 1883 DMA_TO_DEVICE); 1884 else 1885 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1886 dma_unmap_len(cb, dma_len), 1887 DMA_TO_DEVICE); 1888 dma_unmap_addr_set(cb, dma_addr, 0); 1889 1890 if (cb == GENET_CB(skb)->last_cb) 1891 return skb; 1892 1893 } else if (dma_unmap_addr(cb, dma_addr)) { 1894 dma_unmap_page(dev, 1895 dma_unmap_addr(cb, dma_addr), 1896 dma_unmap_len(cb, dma_len), 1897 DMA_TO_DEVICE); 1898 dma_unmap_addr_set(cb, dma_addr, 0); 1899 } 1900 1901 return NULL; 1902 } 1903 1904 /* Simple helper to free a receive control block's resources */ 1905 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1906 struct enet_cb *cb) 1907 { 1908 struct sk_buff *skb; 1909 1910 skb = cb->skb; 1911 cb->skb = NULL; 1912 1913 if (dma_unmap_addr(cb, dma_addr)) { 1914 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1915 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1916 dma_unmap_addr_set(cb, dma_addr, 0); 1917 } 1918 1919 return skb; 1920 } 1921 1922 /* Unlocked version of the reclaim routine */ 1923 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1924 struct bcmgenet_tx_ring *ring) 1925 { 1926 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 1927 struct bcmgenet_priv *priv = netdev_priv(dev); 1928 unsigned int txbds_processed = 0; 1929 unsigned int bytes_compl = 0; 1930 unsigned int pkts_compl = 0; 1931 unsigned int txbds_ready; 1932 unsigned int c_index; 1933 struct sk_buff *skb; 1934 1935 /* Clear status before servicing to reduce spurious interrupts */ 1936 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_CLEAR); 1937 1938 /* Compute how many buffers are transmitted since last xmit call */ 1939 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1940 & DMA_C_INDEX_MASK; 1941 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1942 1943 netif_dbg(priv, tx_done, dev, 1944 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1945 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1946 1947 /* Reclaim transmitted buffers */ 1948 while (txbds_processed < txbds_ready) { 1949 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1950 &priv->tx_cbs[ring->clean_ptr]); 1951 if (skb) { 1952 pkts_compl++; 1953 bytes_compl += GENET_CB(skb)->bytes_sent; 1954 dev_consume_skb_any(skb); 1955 } 1956 1957 txbds_processed++; 1958 if (likely(ring->clean_ptr < ring->end_ptr)) 1959 ring->clean_ptr++; 1960 else 1961 ring->clean_ptr = ring->cb_ptr; 1962 } 1963 1964 ring->free_bds += txbds_processed; 1965 ring->c_index = c_index; 1966 1967 u64_stats_update_begin(&stats->syncp); 1968 u64_stats_add(&stats->packets, pkts_compl); 1969 u64_stats_add(&stats->bytes, bytes_compl); 1970 u64_stats_update_end(&stats->syncp); 1971 1972 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->index), 1973 pkts_compl, bytes_compl); 1974 1975 return txbds_processed; 1976 } 1977 1978 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1979 struct bcmgenet_tx_ring *ring, 1980 bool all) 1981 { 1982 struct bcmgenet_priv *priv = netdev_priv(dev); 1983 struct device *kdev = &priv->pdev->dev; 1984 unsigned int released, drop, wr_ptr; 1985 struct enet_cb *cb_ptr; 1986 struct sk_buff *skb; 1987 1988 spin_lock_bh(&ring->lock); 1989 released = __bcmgenet_tx_reclaim(dev, ring); 1990 if (all) { 1991 skb = NULL; 1992 drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK; 1993 released += drop; 1994 ring->prod_index = ring->c_index & DMA_C_INDEX_MASK; 1995 while (drop--) { 1996 cb_ptr = bcmgenet_put_txcb(priv, ring); 1997 skb = cb_ptr->skb; 1998 bcmgenet_free_tx_cb(kdev, cb_ptr); 1999 if (skb && cb_ptr == GENET_CB(skb)->first_cb) { 2000 dev_consume_skb_any(skb); 2001 skb = NULL; 2002 } 2003 } 2004 if (skb) 2005 dev_consume_skb_any(skb); 2006 bcmgenet_tdma_ring_writel(priv, ring->index, 2007 ring->prod_index, TDMA_PROD_INDEX); 2008 wr_ptr = ring->write_ptr * WORDS_PER_BD(priv); 2009 bcmgenet_tdma_ring_writel(priv, ring->index, wr_ptr, 2010 TDMA_WRITE_PTR); 2011 } 2012 spin_unlock_bh(&ring->lock); 2013 2014 return released; 2015 } 2016 2017 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 2018 { 2019 struct bcmgenet_tx_ring *ring = 2020 container_of(napi, struct bcmgenet_tx_ring, napi); 2021 unsigned int work_done = 0; 2022 struct netdev_queue *txq; 2023 2024 spin_lock(&ring->lock); 2025 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 2026 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 2027 txq = netdev_get_tx_queue(ring->priv->dev, ring->index); 2028 netif_tx_wake_queue(txq); 2029 } 2030 spin_unlock(&ring->lock); 2031 2032 if (work_done == 0) { 2033 napi_complete(napi); 2034 bcmgenet_tx_ring_int_enable(ring); 2035 2036 return 0; 2037 } 2038 2039 return budget; 2040 } 2041 2042 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 2043 { 2044 struct bcmgenet_priv *priv = netdev_priv(dev); 2045 int i = 0; 2046 2047 do { 2048 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i++], true); 2049 } while (i <= priv->hw_params->tx_queues && netif_is_multiqueue(dev)); 2050 } 2051 2052 /* Reallocate the SKB to put enough headroom in front of it and insert 2053 * the transmit checksum offsets in the descriptors 2054 */ 2055 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 2056 struct sk_buff *skb, 2057 struct bcmgenet_tx_ring *ring) 2058 { 2059 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 2060 struct bcmgenet_priv *priv = netdev_priv(dev); 2061 struct status_64 *status = NULL; 2062 struct sk_buff *new_skb; 2063 u16 offset; 2064 u8 ip_proto; 2065 __be16 ip_ver; 2066 u32 tx_csum_info; 2067 2068 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 2069 /* If 64 byte status block enabled, must make sure skb has 2070 * enough headroom for us to insert 64B status block. 2071 */ 2072 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 2073 if (!new_skb) { 2074 dev_kfree_skb_any(skb); 2075 priv->mib.tx_realloc_tsb_failed++; 2076 BCMGENET_STATS64_INC(stats, dropped); 2077 return NULL; 2078 } 2079 dev_consume_skb_any(skb); 2080 skb = new_skb; 2081 priv->mib.tx_realloc_tsb++; 2082 } 2083 2084 skb_push(skb, sizeof(*status)); 2085 status = (struct status_64 *)skb->data; 2086 2087 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2088 ip_ver = skb->protocol; 2089 switch (ip_ver) { 2090 case htons(ETH_P_IP): 2091 ip_proto = ip_hdr(skb)->protocol; 2092 break; 2093 case htons(ETH_P_IPV6): 2094 ip_proto = ipv6_hdr(skb)->nexthdr; 2095 break; 2096 default: 2097 /* don't use UDP flag */ 2098 ip_proto = 0; 2099 break; 2100 } 2101 2102 offset = skb_checksum_start_offset(skb) - sizeof(*status); 2103 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 2104 (offset + skb->csum_offset) | 2105 STATUS_TX_CSUM_LV; 2106 2107 /* Set the special UDP flag for UDP */ 2108 if (ip_proto == IPPROTO_UDP) 2109 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 2110 2111 status->tx_csum_info = tx_csum_info; 2112 } 2113 2114 return skb; 2115 } 2116 2117 static void bcmgenet_hide_tsb(struct sk_buff *skb) 2118 { 2119 __skb_pull(skb, sizeof(struct status_64)); 2120 } 2121 2122 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2123 { 2124 struct bcmgenet_priv *priv = netdev_priv(dev); 2125 struct device *kdev = &priv->pdev->dev; 2126 struct bcmgenet_tx_ring *ring = NULL; 2127 struct enet_cb *tx_cb_ptr; 2128 struct netdev_queue *txq; 2129 int nr_frags, index; 2130 dma_addr_t mapping; 2131 unsigned int size; 2132 skb_frag_t *frag; 2133 u32 len_stat; 2134 int ret; 2135 int i; 2136 2137 index = skb_get_queue_mapping(skb); 2138 /* Mapping strategy: 2139 * queue_mapping = 0, unclassified, packet xmited through ring 0 2140 * queue_mapping = 1, goes to ring 1. (highest priority queue) 2141 * queue_mapping = 2, goes to ring 2. 2142 * queue_mapping = 3, goes to ring 3. 2143 * queue_mapping = 4, goes to ring 4. 2144 */ 2145 ring = &priv->tx_rings[index]; 2146 txq = netdev_get_tx_queue(dev, index); 2147 2148 nr_frags = skb_shinfo(skb)->nr_frags; 2149 2150 spin_lock(&ring->lock); 2151 if (ring->free_bds <= (nr_frags + 1)) { 2152 if (!netif_tx_queue_stopped(txq)) 2153 netif_tx_stop_queue(txq); 2154 ret = NETDEV_TX_BUSY; 2155 goto out; 2156 } 2157 2158 /* Retain how many bytes will be sent on the wire, without TSB inserted 2159 * by transmit checksum offload 2160 */ 2161 GENET_CB(skb)->bytes_sent = skb->len; 2162 2163 /* add the Transmit Status Block */ 2164 skb = bcmgenet_add_tsb(dev, skb, ring); 2165 if (!skb) { 2166 ret = NETDEV_TX_OK; 2167 goto out; 2168 } 2169 2170 for (i = 0; i <= nr_frags; i++) { 2171 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2172 2173 BUG_ON(!tx_cb_ptr); 2174 2175 if (!i) { 2176 /* Transmit single SKB or head of fragment list */ 2177 GENET_CB(skb)->first_cb = tx_cb_ptr; 2178 size = skb_headlen(skb); 2179 mapping = dma_map_single(kdev, skb->data, size, 2180 DMA_TO_DEVICE); 2181 } else { 2182 /* xmit fragment */ 2183 frag = &skb_shinfo(skb)->frags[i - 1]; 2184 size = skb_frag_size(frag); 2185 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2186 DMA_TO_DEVICE); 2187 } 2188 2189 ret = dma_mapping_error(kdev, mapping); 2190 if (ret) { 2191 priv->mib.tx_dma_failed++; 2192 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2193 ret = NETDEV_TX_OK; 2194 goto out_unmap_frags; 2195 } 2196 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2197 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2198 2199 tx_cb_ptr->skb = skb; 2200 2201 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2202 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2203 2204 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2205 * will need to restore software padding of "runt" packets 2206 */ 2207 len_stat |= DMA_TX_APPEND_CRC; 2208 2209 if (!i) { 2210 len_stat |= DMA_SOP; 2211 if (skb->ip_summed == CHECKSUM_PARTIAL) 2212 len_stat |= DMA_TX_DO_CSUM; 2213 } 2214 if (i == nr_frags) 2215 len_stat |= DMA_EOP; 2216 2217 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2218 } 2219 2220 GENET_CB(skb)->last_cb = tx_cb_ptr; 2221 2222 bcmgenet_hide_tsb(skb); 2223 skb_tx_timestamp(skb); 2224 2225 /* Decrement total BD count and advance our write pointer */ 2226 ring->free_bds -= nr_frags + 1; 2227 ring->prod_index += nr_frags + 1; 2228 ring->prod_index &= DMA_P_INDEX_MASK; 2229 2230 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2231 2232 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2233 netif_tx_stop_queue(txq); 2234 2235 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2236 /* Packets are ready, update producer index */ 2237 bcmgenet_tdma_ring_writel(priv, ring->index, 2238 ring->prod_index, TDMA_PROD_INDEX); 2239 out: 2240 spin_unlock(&ring->lock); 2241 2242 return ret; 2243 2244 out_unmap_frags: 2245 /* Back up for failed control block mapping */ 2246 bcmgenet_put_txcb(priv, ring); 2247 2248 /* Unmap successfully mapped control blocks */ 2249 while (i-- > 0) { 2250 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2251 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2252 } 2253 2254 dev_kfree_skb(skb); 2255 goto out; 2256 } 2257 2258 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2259 struct enet_cb *cb) 2260 { 2261 struct device *kdev = &priv->pdev->dev; 2262 struct sk_buff *skb; 2263 struct sk_buff *rx_skb; 2264 dma_addr_t mapping; 2265 2266 /* Allocate a new Rx skb */ 2267 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2268 GFP_ATOMIC | __GFP_NOWARN); 2269 if (!skb) { 2270 priv->mib.alloc_rx_buff_failed++; 2271 netif_err(priv, rx_err, priv->dev, 2272 "%s: Rx skb allocation failed\n", __func__); 2273 return NULL; 2274 } 2275 2276 /* DMA-map the new Rx skb */ 2277 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2278 DMA_FROM_DEVICE); 2279 if (dma_mapping_error(kdev, mapping)) { 2280 priv->mib.rx_dma_failed++; 2281 dev_kfree_skb_any(skb); 2282 netif_err(priv, rx_err, priv->dev, 2283 "%s: Rx skb DMA mapping failed\n", __func__); 2284 return NULL; 2285 } 2286 2287 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2288 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2289 2290 /* Put the new Rx skb on the ring */ 2291 cb->skb = skb; 2292 dma_unmap_addr_set(cb, dma_addr, mapping); 2293 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2294 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2295 2296 /* Return the current Rx skb to caller */ 2297 return rx_skb; 2298 } 2299 2300 /* bcmgenet_desc_rx - descriptor based rx process. 2301 * this could be called from bottom half, or from NAPI polling method. 2302 */ 2303 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2304 unsigned int budget) 2305 { 2306 struct bcmgenet_rx_stats64 *stats = &ring->stats64; 2307 struct bcmgenet_priv *priv = ring->priv; 2308 struct net_device *dev = priv->dev; 2309 struct enet_cb *cb; 2310 struct sk_buff *skb; 2311 u32 dma_length_status; 2312 unsigned long dma_flag; 2313 int len; 2314 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2315 unsigned int bytes_processed = 0; 2316 unsigned int p_index, mask; 2317 unsigned int discards; 2318 2319 /* Clear status before servicing to reduce spurious interrupts */ 2320 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2321 bcmgenet_intrl2_1_writel(priv, mask, INTRL2_CPU_CLEAR); 2322 2323 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2324 2325 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2326 DMA_P_INDEX_DISCARD_CNT_MASK; 2327 if (discards > ring->old_discards) { 2328 discards = discards - ring->old_discards; 2329 BCMGENET_STATS64_ADD(stats, missed, discards); 2330 ring->old_discards += discards; 2331 2332 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2333 if (ring->old_discards >= 0xC000) { 2334 ring->old_discards = 0; 2335 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2336 RDMA_PROD_INDEX); 2337 } 2338 } 2339 2340 p_index &= DMA_P_INDEX_MASK; 2341 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2342 2343 netif_dbg(priv, rx_status, dev, 2344 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2345 2346 while ((rxpktprocessed < rxpkttoprocess) && 2347 (rxpktprocessed < budget)) { 2348 struct status_64 *status; 2349 __be16 rx_csum; 2350 2351 cb = &priv->rx_cbs[ring->read_ptr]; 2352 skb = bcmgenet_rx_refill(priv, cb); 2353 2354 if (unlikely(!skb)) { 2355 BCMGENET_STATS64_INC(stats, dropped); 2356 goto next; 2357 } 2358 2359 status = (struct status_64 *)skb->data; 2360 dma_length_status = status->length_status; 2361 if (dev->features & NETIF_F_RXCSUM) { 2362 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2363 if (rx_csum) { 2364 skb->csum = (__force __wsum)ntohs(rx_csum); 2365 skb->ip_summed = CHECKSUM_COMPLETE; 2366 } 2367 } 2368 2369 /* DMA flags and length are still valid no matter how 2370 * we got the Receive Status Vector (64B RSB or register) 2371 */ 2372 dma_flag = dma_length_status & 0xffff; 2373 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2374 2375 netif_dbg(priv, rx_status, dev, 2376 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2377 __func__, p_index, ring->c_index, 2378 ring->read_ptr, dma_length_status); 2379 2380 if (unlikely(len > RX_BUF_LENGTH)) { 2381 netif_err(priv, rx_status, dev, "oversized packet\n"); 2382 BCMGENET_STATS64_INC(stats, length_errors); 2383 dev_kfree_skb_any(skb); 2384 goto next; 2385 } 2386 2387 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2388 netif_err(priv, rx_status, dev, 2389 "dropping fragmented packet!\n"); 2390 BCMGENET_STATS64_INC(stats, fragmented_errors); 2391 dev_kfree_skb_any(skb); 2392 goto next; 2393 } 2394 2395 /* report errors */ 2396 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2397 DMA_RX_OV | 2398 DMA_RX_NO | 2399 DMA_RX_LG | 2400 DMA_RX_RXER))) { 2401 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2402 (unsigned int)dma_flag); 2403 u64_stats_update_begin(&stats->syncp); 2404 if (dma_flag & DMA_RX_CRC_ERROR) 2405 u64_stats_inc(&stats->crc_errors); 2406 if (dma_flag & DMA_RX_OV) 2407 u64_stats_inc(&stats->over_errors); 2408 if (dma_flag & DMA_RX_NO) 2409 u64_stats_inc(&stats->frame_errors); 2410 if (dma_flag & DMA_RX_LG) 2411 u64_stats_inc(&stats->length_errors); 2412 if ((dma_flag & (DMA_RX_CRC_ERROR | 2413 DMA_RX_OV | 2414 DMA_RX_NO | 2415 DMA_RX_LG | 2416 DMA_RX_RXER)) == DMA_RX_RXER) 2417 u64_stats_inc(&stats->errors); 2418 u64_stats_update_end(&stats->syncp); 2419 dev_kfree_skb_any(skb); 2420 goto next; 2421 } /* error packet */ 2422 2423 skb_put(skb, len); 2424 2425 /* remove RSB and hardware 2bytes added for IP alignment */ 2426 skb_pull(skb, 66); 2427 len -= 66; 2428 2429 if (priv->crc_fwd_en) { 2430 skb_trim(skb, len - ETH_FCS_LEN); 2431 len -= ETH_FCS_LEN; 2432 } 2433 2434 bytes_processed += len; 2435 2436 /*Finish setting up the received SKB and send it to the kernel*/ 2437 skb->protocol = eth_type_trans(skb, priv->dev); 2438 2439 u64_stats_update_begin(&stats->syncp); 2440 u64_stats_inc(&stats->packets); 2441 u64_stats_add(&stats->bytes, len); 2442 if (dma_flag & DMA_RX_MULT) 2443 u64_stats_inc(&stats->multicast); 2444 else if (dma_flag & DMA_RX_BRDCAST) 2445 u64_stats_inc(&stats->broadcast); 2446 u64_stats_update_end(&stats->syncp); 2447 2448 /* Notify kernel */ 2449 napi_gro_receive(&ring->napi, skb); 2450 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2451 2452 next: 2453 rxpktprocessed++; 2454 if (likely(ring->read_ptr < ring->end_ptr)) 2455 ring->read_ptr++; 2456 else 2457 ring->read_ptr = ring->cb_ptr; 2458 2459 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2460 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2461 } 2462 2463 ring->dim.bytes = bytes_processed; 2464 ring->dim.packets = rxpktprocessed; 2465 2466 return rxpktprocessed; 2467 } 2468 2469 /* Rx NAPI polling method */ 2470 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2471 { 2472 struct bcmgenet_rx_ring *ring = container_of(napi, 2473 struct bcmgenet_rx_ring, napi); 2474 struct dim_sample dim_sample = {}; 2475 unsigned int work_done; 2476 2477 work_done = bcmgenet_desc_rx(ring, budget); 2478 2479 if (work_done < budget && napi_complete_done(napi, work_done)) 2480 bcmgenet_rx_ring_int_enable(ring); 2481 2482 if (ring->dim.use_dim) { 2483 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2484 ring->dim.bytes, &dim_sample); 2485 net_dim(&ring->dim.dim, &dim_sample); 2486 } 2487 2488 return work_done; 2489 } 2490 2491 static void bcmgenet_dim_work(struct work_struct *work) 2492 { 2493 struct dim *dim = container_of(work, struct dim, work); 2494 struct bcmgenet_net_dim *ndim = 2495 container_of(dim, struct bcmgenet_net_dim, dim); 2496 struct bcmgenet_rx_ring *ring = 2497 container_of(ndim, struct bcmgenet_rx_ring, dim); 2498 struct dim_cq_moder cur_profile = 2499 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2500 2501 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2502 dim->state = DIM_START_MEASURE; 2503 } 2504 2505 /* Assign skb to RX DMA descriptor. */ 2506 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2507 struct bcmgenet_rx_ring *ring) 2508 { 2509 struct enet_cb *cb; 2510 struct sk_buff *skb; 2511 int i; 2512 2513 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2514 2515 /* loop here for each buffer needing assign */ 2516 for (i = 0; i < ring->size; i++) { 2517 cb = ring->cbs + i; 2518 skb = bcmgenet_rx_refill(priv, cb); 2519 if (skb) 2520 dev_consume_skb_any(skb); 2521 if (!cb->skb) 2522 return -ENOMEM; 2523 } 2524 2525 return 0; 2526 } 2527 2528 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2529 { 2530 struct sk_buff *skb; 2531 struct enet_cb *cb; 2532 int i; 2533 2534 for (i = 0; i < priv->num_rx_bds; i++) { 2535 cb = &priv->rx_cbs[i]; 2536 2537 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2538 if (skb) 2539 dev_consume_skb_any(skb); 2540 } 2541 } 2542 2543 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2544 { 2545 u32 reg; 2546 2547 spin_lock_bh(&priv->reg_lock); 2548 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2549 if (reg & CMD_SW_RESET) { 2550 spin_unlock_bh(&priv->reg_lock); 2551 return; 2552 } 2553 if (enable) 2554 reg |= mask; 2555 else 2556 reg &= ~mask; 2557 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2558 spin_unlock_bh(&priv->reg_lock); 2559 2560 /* UniMAC stops on a packet boundary, wait for a full-size packet 2561 * to be processed 2562 */ 2563 if (enable == 0) 2564 usleep_range(1000, 2000); 2565 } 2566 2567 static void reset_umac(struct bcmgenet_priv *priv) 2568 { 2569 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2570 bcmgenet_rbuf_ctrl_set(priv, 0); 2571 udelay(10); 2572 2573 /* issue soft reset and disable MAC while updating its registers */ 2574 spin_lock_bh(&priv->reg_lock); 2575 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2576 udelay(2); 2577 spin_unlock_bh(&priv->reg_lock); 2578 } 2579 2580 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2581 { 2582 /* Mask all interrupts.*/ 2583 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2584 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2585 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2586 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2587 } 2588 2589 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2590 { 2591 u32 int0_enable = 0; 2592 2593 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2594 * and MoCA PHY 2595 */ 2596 if (priv->internal_phy) { 2597 int0_enable |= UMAC_IRQ_LINK_EVENT; 2598 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2599 int0_enable |= UMAC_IRQ_PHY_DET_R; 2600 } else if (priv->ext_phy) { 2601 int0_enable |= UMAC_IRQ_LINK_EVENT; 2602 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2603 if (bcmgenet_has_moca_link_det(priv)) 2604 int0_enable |= UMAC_IRQ_LINK_EVENT; 2605 } 2606 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2607 } 2608 2609 static void init_umac(struct bcmgenet_priv *priv) 2610 { 2611 struct device *kdev = &priv->pdev->dev; 2612 u32 reg; 2613 u32 int0_enable = 0; 2614 2615 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2616 2617 reset_umac(priv); 2618 2619 /* clear tx/rx counter */ 2620 bcmgenet_umac_writel(priv, 2621 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2622 UMAC_MIB_CTRL); 2623 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2624 2625 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2626 2627 /* init tx registers, enable TSB */ 2628 reg = bcmgenet_tbuf_ctrl_get(priv); 2629 reg |= TBUF_64B_EN; 2630 bcmgenet_tbuf_ctrl_set(priv, reg); 2631 2632 /* init rx registers, enable ip header optimization and RSB */ 2633 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2634 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2635 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2636 2637 /* enable rx checksumming */ 2638 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2639 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2640 /* If UniMAC forwards CRC, we need to skip over it to get 2641 * a valid CHK bit to be set in the per-packet status word 2642 */ 2643 if (priv->crc_fwd_en) 2644 reg |= RBUF_SKIP_FCS; 2645 else 2646 reg &= ~RBUF_SKIP_FCS; 2647 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2648 2649 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2650 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2651 2652 bcmgenet_intr_disable(priv); 2653 2654 /* Configure backpressure vectors for MoCA */ 2655 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2656 reg = bcmgenet_bp_mc_get(priv); 2657 reg |= BIT(priv->hw_params->bp_in_en_shift); 2658 2659 /* bp_mask: back pressure mask */ 2660 if (netif_is_multiqueue(priv->dev)) 2661 reg |= priv->hw_params->bp_in_mask; 2662 else 2663 reg &= ~priv->hw_params->bp_in_mask; 2664 bcmgenet_bp_mc_set(priv, reg); 2665 } 2666 2667 /* Enable MDIO interrupts on GENET v3+ */ 2668 if (bcmgenet_has_mdio_intr(priv)) 2669 int0_enable |= UMAC_IRQ_MDIO_EVENT; 2670 2671 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2672 2673 dev_dbg(kdev, "done init umac\n"); 2674 } 2675 2676 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2677 void (*cb)(struct work_struct *work)) 2678 { 2679 struct bcmgenet_net_dim *dim = &ring->dim; 2680 2681 INIT_WORK(&dim->dim.work, cb); 2682 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2683 dim->event_ctr = 0; 2684 dim->packets = 0; 2685 dim->bytes = 0; 2686 } 2687 2688 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2689 { 2690 struct bcmgenet_net_dim *dim = &ring->dim; 2691 struct dim_cq_moder moder; 2692 u32 usecs, pkts; 2693 2694 usecs = ring->rx_coalesce_usecs; 2695 pkts = ring->rx_max_coalesced_frames; 2696 2697 /* If DIM was enabled, re-apply default parameters */ 2698 if (dim->use_dim) { 2699 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2700 usecs = moder.usec; 2701 pkts = moder.pkts; 2702 } 2703 2704 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2705 } 2706 2707 /* Initialize a Tx ring along with corresponding hardware registers */ 2708 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2709 unsigned int index, unsigned int size, 2710 unsigned int start_ptr, unsigned int end_ptr) 2711 { 2712 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2713 u32 words_per_bd = WORDS_PER_BD(priv); 2714 u32 flow_period_val = 0; 2715 2716 spin_lock_init(&ring->lock); 2717 ring->priv = priv; 2718 ring->index = index; 2719 ring->cbs = priv->tx_cbs + start_ptr; 2720 ring->size = size; 2721 ring->clean_ptr = start_ptr; 2722 ring->c_index = 0; 2723 ring->free_bds = size; 2724 ring->write_ptr = start_ptr; 2725 ring->cb_ptr = start_ptr; 2726 ring->end_ptr = end_ptr - 1; 2727 ring->prod_index = 0; 2728 2729 /* Set flow period for ring != 0 */ 2730 if (index) 2731 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2732 2733 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2734 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2735 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2736 /* Disable rate control for now */ 2737 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2738 TDMA_FLOW_PERIOD); 2739 bcmgenet_tdma_ring_writel(priv, index, 2740 ((size << DMA_RING_SIZE_SHIFT) | 2741 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2742 2743 /* Set start and end address, read and write pointers */ 2744 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2745 DMA_START_ADDR); 2746 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2747 TDMA_READ_PTR); 2748 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2749 TDMA_WRITE_PTR); 2750 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2751 DMA_END_ADDR); 2752 2753 /* Initialize Tx NAPI */ 2754 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll); 2755 } 2756 2757 /* Initialize a RDMA ring */ 2758 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2759 unsigned int index, unsigned int size, 2760 unsigned int start_ptr, unsigned int end_ptr) 2761 { 2762 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2763 u32 words_per_bd = WORDS_PER_BD(priv); 2764 int ret; 2765 2766 ring->priv = priv; 2767 ring->index = index; 2768 ring->cbs = priv->rx_cbs + start_ptr; 2769 ring->size = size; 2770 ring->c_index = 0; 2771 ring->read_ptr = start_ptr; 2772 ring->cb_ptr = start_ptr; 2773 ring->end_ptr = end_ptr - 1; 2774 2775 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2776 if (ret) 2777 return ret; 2778 2779 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2780 bcmgenet_init_rx_coalesce(ring); 2781 2782 /* Initialize Rx NAPI */ 2783 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll); 2784 2785 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2786 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2787 bcmgenet_rdma_ring_writel(priv, index, 2788 ((size << DMA_RING_SIZE_SHIFT) | 2789 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2790 bcmgenet_rdma_ring_writel(priv, index, 2791 (DMA_FC_THRESH_LO << 2792 DMA_XOFF_THRESHOLD_SHIFT) | 2793 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2794 2795 /* Set start and end address, read and write pointers */ 2796 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2797 DMA_START_ADDR); 2798 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2799 RDMA_READ_PTR); 2800 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2801 RDMA_WRITE_PTR); 2802 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2803 DMA_END_ADDR); 2804 2805 return ret; 2806 } 2807 2808 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2809 { 2810 unsigned int i; 2811 struct bcmgenet_tx_ring *ring; 2812 2813 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2814 ring = &priv->tx_rings[i]; 2815 napi_enable(&ring->napi); 2816 bcmgenet_tx_ring_int_enable(ring); 2817 } 2818 } 2819 2820 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2821 { 2822 unsigned int i; 2823 struct bcmgenet_tx_ring *ring; 2824 2825 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2826 ring = &priv->tx_rings[i]; 2827 napi_disable(&ring->napi); 2828 } 2829 } 2830 2831 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2832 { 2833 unsigned int i; 2834 struct bcmgenet_tx_ring *ring; 2835 2836 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2837 ring = &priv->tx_rings[i]; 2838 netif_napi_del(&ring->napi); 2839 } 2840 } 2841 2842 static int bcmgenet_tdma_disable(struct bcmgenet_priv *priv) 2843 { 2844 int timeout = 0; 2845 u32 reg, mask; 2846 2847 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2848 mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2849 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2850 reg &= ~mask; 2851 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2852 2853 /* Check DMA status register to confirm DMA is disabled */ 2854 while (timeout++ < DMA_TIMEOUT_VAL) { 2855 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2856 if ((reg & mask) == mask) 2857 return 0; 2858 2859 udelay(1); 2860 } 2861 2862 return -ETIMEDOUT; 2863 } 2864 2865 static int bcmgenet_rdma_disable(struct bcmgenet_priv *priv) 2866 { 2867 int timeout = 0; 2868 u32 reg, mask; 2869 2870 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2871 mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 2872 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2873 reg &= ~mask; 2874 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2875 2876 /* Check DMA status register to confirm DMA is disabled */ 2877 while (timeout++ < DMA_TIMEOUT_VAL) { 2878 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2879 if ((reg & mask) == mask) 2880 return 0; 2881 2882 udelay(1); 2883 } 2884 2885 return -ETIMEDOUT; 2886 } 2887 2888 /* Initialize Tx queues 2889 * 2890 * Queues 1-4 are priority-based, each one has 32 descriptors, 2891 * with queue 1 being the highest priority queue. 2892 * 2893 * Queue 0 is the default Tx queue with 2894 * GENET_Q0_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2895 * 2896 * The transmit control block pool is then partitioned as follows: 2897 * - Tx queue 0 uses tx_cbs[0..127] 2898 * - Tx queue 1 uses tx_cbs[128..159] 2899 * - Tx queue 2 uses tx_cbs[160..191] 2900 * - Tx queue 3 uses tx_cbs[192..223] 2901 * - Tx queue 4 uses tx_cbs[224..255] 2902 */ 2903 static void bcmgenet_init_tx_queues(struct net_device *dev) 2904 { 2905 struct bcmgenet_priv *priv = netdev_priv(dev); 2906 unsigned int start = 0, end = GENET_Q0_TX_BD_CNT; 2907 u32 i, ring_mask, dma_priority[3] = {0, 0, 0}; 2908 2909 /* Enable strict priority arbiter mode */ 2910 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2911 2912 /* Initialize Tx priority queues */ 2913 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 2914 bcmgenet_init_tx_ring(priv, i, end - start, start, end); 2915 start = end; 2916 end += priv->hw_params->tx_bds_per_q; 2917 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2918 (i ? GENET_Q1_PRIORITY : GENET_Q0_PRIORITY) 2919 << DMA_PRIO_REG_SHIFT(i); 2920 } 2921 2922 /* Set Tx queue priorities */ 2923 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2924 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2925 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2926 2927 /* Configure Tx queues as descriptor rings */ 2928 ring_mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2929 bcmgenet_tdma_writel(priv, ring_mask, DMA_RING_CFG); 2930 2931 /* Enable Tx rings */ 2932 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 2933 bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL); 2934 } 2935 2936 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2937 { 2938 unsigned int i; 2939 struct bcmgenet_rx_ring *ring; 2940 2941 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2942 ring = &priv->rx_rings[i]; 2943 napi_enable(&ring->napi); 2944 bcmgenet_rx_ring_int_enable(ring); 2945 } 2946 } 2947 2948 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2949 { 2950 unsigned int i; 2951 struct bcmgenet_rx_ring *ring; 2952 2953 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2954 ring = &priv->rx_rings[i]; 2955 napi_disable(&ring->napi); 2956 cancel_work_sync(&ring->dim.dim.work); 2957 } 2958 } 2959 2960 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2961 { 2962 unsigned int i; 2963 struct bcmgenet_rx_ring *ring; 2964 2965 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2966 ring = &priv->rx_rings[i]; 2967 netif_napi_del(&ring->napi); 2968 } 2969 } 2970 2971 /* Initialize Rx queues 2972 * 2973 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2974 * used to direct traffic to these queues. 2975 * 2976 * Queue 0 is also the default Rx queue with GENET_Q0_RX_BD_CNT descriptors. 2977 */ 2978 static int bcmgenet_init_rx_queues(struct net_device *dev) 2979 { 2980 struct bcmgenet_priv *priv = netdev_priv(dev); 2981 unsigned int start = 0, end = GENET_Q0_RX_BD_CNT; 2982 u32 i, ring_mask; 2983 int ret; 2984 2985 /* Initialize Rx priority queues */ 2986 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 2987 ret = bcmgenet_init_rx_ring(priv, i, end - start, start, end); 2988 if (ret) 2989 return ret; 2990 2991 start = end; 2992 end += priv->hw_params->rx_bds_per_q; 2993 } 2994 2995 /* Configure Rx queues as descriptor rings */ 2996 ring_mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 2997 bcmgenet_rdma_writel(priv, ring_mask, DMA_RING_CFG); 2998 2999 /* Enable Rx rings */ 3000 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 3001 bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL); 3002 3003 return 0; 3004 } 3005 3006 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 3007 { 3008 int ret = 0; 3009 3010 /* Disable TDMA to stop add more frames in TX DMA */ 3011 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) { 3012 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 3013 ret = -ETIMEDOUT; 3014 } 3015 3016 /* Wait 10ms for packet drain in both tx and rx dma */ 3017 usleep_range(10000, 20000); 3018 3019 /* Disable RDMA */ 3020 if (-ETIMEDOUT == bcmgenet_rdma_disable(priv)) { 3021 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 3022 ret = -ETIMEDOUT; 3023 } 3024 3025 return ret; 3026 } 3027 3028 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 3029 { 3030 struct netdev_queue *txq; 3031 int i; 3032 3033 bcmgenet_fini_rx_napi(priv); 3034 bcmgenet_fini_tx_napi(priv); 3035 3036 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 3037 txq = netdev_get_tx_queue(priv->dev, i); 3038 netdev_tx_reset_queue(txq); 3039 } 3040 3041 bcmgenet_free_rx_buffers(priv); 3042 kfree(priv->rx_cbs); 3043 kfree(priv->tx_cbs); 3044 } 3045 3046 /* init_edma: Initialize DMA control register */ 3047 static int bcmgenet_init_dma(struct bcmgenet_priv *priv, bool flush_rx) 3048 { 3049 struct enet_cb *cb; 3050 unsigned int i; 3051 int ret; 3052 u32 reg; 3053 3054 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3055 3056 /* Disable TX DMA */ 3057 ret = bcmgenet_tdma_disable(priv); 3058 if (ret) { 3059 netdev_err(priv->dev, "failed to halt Tx DMA\n"); 3060 return ret; 3061 } 3062 3063 /* Disable RX DMA */ 3064 ret = bcmgenet_rdma_disable(priv); 3065 if (ret) { 3066 netdev_err(priv->dev, "failed to halt Rx DMA\n"); 3067 return ret; 3068 } 3069 3070 /* Flush TX queues */ 3071 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3072 udelay(10); 3073 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3074 3075 if (flush_rx) { 3076 reg = bcmgenet_rbuf_ctrl_get(priv); 3077 bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0)); 3078 udelay(10); 3079 bcmgenet_rbuf_ctrl_set(priv, reg); 3080 udelay(10); 3081 } 3082 3083 /* Initialize common Rx ring structures */ 3084 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3085 priv->num_rx_bds = TOTAL_DESC; 3086 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3087 GFP_KERNEL); 3088 if (!priv->rx_cbs) 3089 return -ENOMEM; 3090 3091 for (i = 0; i < priv->num_rx_bds; i++) { 3092 cb = priv->rx_cbs + i; 3093 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3094 } 3095 3096 /* Initialize common TX ring structures */ 3097 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3098 priv->num_tx_bds = TOTAL_DESC; 3099 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3100 GFP_KERNEL); 3101 if (!priv->tx_cbs) { 3102 kfree(priv->rx_cbs); 3103 return -ENOMEM; 3104 } 3105 3106 for (i = 0; i < priv->num_tx_bds; i++) { 3107 cb = priv->tx_cbs + i; 3108 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3109 } 3110 3111 /* Init rDma */ 3112 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3113 DMA_SCB_BURST_SIZE); 3114 3115 /* Initialize Rx queues */ 3116 ret = bcmgenet_init_rx_queues(priv->dev); 3117 if (ret) { 3118 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3119 bcmgenet_free_rx_buffers(priv); 3120 kfree(priv->rx_cbs); 3121 kfree(priv->tx_cbs); 3122 return ret; 3123 } 3124 3125 /* Init tDma */ 3126 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3127 DMA_SCB_BURST_SIZE); 3128 3129 /* Initialize Tx queues */ 3130 bcmgenet_init_tx_queues(priv->dev); 3131 3132 /* Enable RX/TX DMA */ 3133 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3134 reg |= DMA_EN; 3135 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3136 3137 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3138 reg |= DMA_EN; 3139 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3140 3141 return 0; 3142 } 3143 3144 /* Interrupt bottom half */ 3145 static void bcmgenet_irq_task(struct work_struct *work) 3146 { 3147 unsigned int status; 3148 struct bcmgenet_priv *priv = container_of( 3149 work, struct bcmgenet_priv, bcmgenet_irq_work); 3150 3151 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3152 3153 spin_lock_irq(&priv->lock); 3154 status = priv->irq0_stat; 3155 priv->irq0_stat = 0; 3156 spin_unlock_irq(&priv->lock); 3157 3158 if (status & UMAC_IRQ_PHY_DET_R && 3159 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3160 phy_init_hw(priv->dev->phydev); 3161 genphy_config_aneg(priv->dev->phydev); 3162 } 3163 3164 /* Link UP/DOWN event */ 3165 if (status & UMAC_IRQ_LINK_EVENT) 3166 phy_mac_interrupt(priv->dev->phydev); 3167 3168 } 3169 3170 /* bcmgenet_isr1: handle Rx and Tx queues */ 3171 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3172 { 3173 struct bcmgenet_priv *priv = dev_id; 3174 struct bcmgenet_rx_ring *rx_ring; 3175 struct bcmgenet_tx_ring *tx_ring; 3176 unsigned int index, status; 3177 3178 /* Read irq status */ 3179 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3180 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3181 3182 /* clear interrupts */ 3183 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3184 3185 netif_dbg(priv, intr, priv->dev, 3186 "%s: IRQ=0x%x\n", __func__, status); 3187 3188 /* Check Rx priority queue interrupts */ 3189 for (index = 0; index <= priv->hw_params->rx_queues; index++) { 3190 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3191 continue; 3192 3193 rx_ring = &priv->rx_rings[index]; 3194 rx_ring->dim.event_ctr++; 3195 3196 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3197 bcmgenet_rx_ring_int_disable(rx_ring); 3198 __napi_schedule_irqoff(&rx_ring->napi); 3199 } 3200 } 3201 3202 /* Check Tx priority queue interrupts */ 3203 for (index = 0; index <= priv->hw_params->tx_queues; index++) { 3204 if (!(status & BIT(index))) 3205 continue; 3206 3207 tx_ring = &priv->tx_rings[index]; 3208 3209 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3210 bcmgenet_tx_ring_int_disable(tx_ring); 3211 __napi_schedule_irqoff(&tx_ring->napi); 3212 } 3213 } 3214 3215 return IRQ_HANDLED; 3216 } 3217 3218 /* bcmgenet_isr0: handle other stuff */ 3219 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3220 { 3221 struct bcmgenet_priv *priv = dev_id; 3222 unsigned int status; 3223 unsigned long flags; 3224 3225 /* Read irq status */ 3226 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3227 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3228 3229 /* clear interrupts */ 3230 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3231 3232 netif_dbg(priv, intr, priv->dev, 3233 "IRQ=0x%x\n", status); 3234 3235 if (bcmgenet_has_mdio_intr(priv) && status & UMAC_IRQ_MDIO_EVENT) 3236 wake_up(&priv->wq); 3237 3238 /* all other interested interrupts handled in bottom half */ 3239 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3240 if (status) { 3241 /* Save irq status for bottom-half processing. */ 3242 spin_lock_irqsave(&priv->lock, flags); 3243 priv->irq0_stat |= status; 3244 spin_unlock_irqrestore(&priv->lock, flags); 3245 3246 schedule_work(&priv->bcmgenet_irq_work); 3247 } 3248 3249 return IRQ_HANDLED; 3250 } 3251 3252 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3253 { 3254 /* Acknowledge the interrupt */ 3255 return IRQ_HANDLED; 3256 } 3257 3258 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3259 { 3260 u32 reg; 3261 3262 reg = bcmgenet_rbuf_ctrl_get(priv); 3263 reg |= BIT(1); 3264 bcmgenet_rbuf_ctrl_set(priv, reg); 3265 udelay(10); 3266 3267 reg &= ~BIT(1); 3268 bcmgenet_rbuf_ctrl_set(priv, reg); 3269 udelay(10); 3270 } 3271 3272 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3273 const unsigned char *addr) 3274 { 3275 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3276 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3277 } 3278 3279 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3280 unsigned char *addr) 3281 { 3282 u32 addr_tmp; 3283 3284 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3285 put_unaligned_be32(addr_tmp, &addr[0]); 3286 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3287 put_unaligned_be16(addr_tmp, &addr[4]); 3288 } 3289 3290 static void bcmgenet_netif_start(struct net_device *dev) 3291 { 3292 struct bcmgenet_priv *priv = netdev_priv(dev); 3293 3294 /* Start the network engine */ 3295 netif_addr_lock_bh(dev); 3296 bcmgenet_set_rx_mode(dev); 3297 netif_addr_unlock_bh(dev); 3298 bcmgenet_enable_rx_napi(priv); 3299 3300 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3301 3302 bcmgenet_enable_tx_napi(priv); 3303 3304 /* Monitor link interrupts now */ 3305 bcmgenet_link_intr_enable(priv); 3306 3307 phy_start(dev->phydev); 3308 } 3309 3310 static int bcmgenet_open(struct net_device *dev) 3311 { 3312 struct bcmgenet_priv *priv = netdev_priv(dev); 3313 int ret; 3314 3315 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3316 3317 /* Turn on the clock */ 3318 clk_prepare_enable(priv->clk); 3319 3320 /* If this is an internal GPHY, power it back on now, before UniMAC is 3321 * brought out of reset as absolutely no UniMAC activity is allowed 3322 */ 3323 if (priv->internal_phy) 3324 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3325 3326 /* take MAC out of reset */ 3327 bcmgenet_umac_reset(priv); 3328 3329 init_umac(priv); 3330 3331 /* Apply features again in case we changed them while interface was 3332 * down 3333 */ 3334 bcmgenet_set_features(dev, dev->features); 3335 3336 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3337 3338 /* HFB init */ 3339 bcmgenet_hfb_init(priv); 3340 3341 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3342 ret = bcmgenet_init_dma(priv, true); 3343 if (ret) { 3344 netdev_err(dev, "failed to initialize DMA\n"); 3345 goto err_clk_disable; 3346 } 3347 3348 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3349 dev->name, priv); 3350 if (ret < 0) { 3351 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3352 goto err_fini_dma; 3353 } 3354 3355 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3356 dev->name, priv); 3357 if (ret < 0) { 3358 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3359 goto err_irq0; 3360 } 3361 3362 ret = bcmgenet_mii_probe(dev); 3363 if (ret) { 3364 netdev_err(dev, "failed to connect to PHY\n"); 3365 goto err_irq1; 3366 } 3367 3368 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 3369 3370 bcmgenet_netif_start(dev); 3371 3372 netif_tx_start_all_queues(dev); 3373 3374 return 0; 3375 3376 err_irq1: 3377 free_irq(priv->irq1, priv); 3378 err_irq0: 3379 free_irq(priv->irq0, priv); 3380 err_fini_dma: 3381 bcmgenet_dma_teardown(priv); 3382 bcmgenet_fini_dma(priv); 3383 err_clk_disable: 3384 if (priv->internal_phy) 3385 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3386 clk_disable_unprepare(priv->clk); 3387 return ret; 3388 } 3389 3390 static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) 3391 { 3392 struct bcmgenet_priv *priv = netdev_priv(dev); 3393 3394 netif_tx_disable(dev); 3395 3396 /* Disable MAC receive */ 3397 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 3398 umac_enable_set(priv, CMD_RX_EN, false); 3399 3400 if (stop_phy) 3401 phy_stop(dev->phydev); 3402 3403 bcmgenet_dma_teardown(priv); 3404 3405 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3406 umac_enable_set(priv, CMD_TX_EN, false); 3407 3408 bcmgenet_disable_tx_napi(priv); 3409 bcmgenet_disable_rx_napi(priv); 3410 bcmgenet_intr_disable(priv); 3411 3412 /* Wait for pending work items to complete. Since interrupts are 3413 * disabled no new work will be scheduled. 3414 */ 3415 cancel_work_sync(&priv->bcmgenet_irq_work); 3416 3417 /* tx reclaim */ 3418 bcmgenet_tx_reclaim_all(dev); 3419 bcmgenet_fini_dma(priv); 3420 } 3421 3422 static int bcmgenet_close(struct net_device *dev) 3423 { 3424 struct bcmgenet_priv *priv = netdev_priv(dev); 3425 int ret = 0; 3426 3427 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3428 3429 bcmgenet_netif_stop(dev, false); 3430 3431 /* Really kill the PHY state machine and disconnect from it */ 3432 phy_disconnect(dev->phydev); 3433 3434 free_irq(priv->irq0, priv); 3435 free_irq(priv->irq1, priv); 3436 3437 if (priv->internal_phy) 3438 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3439 3440 clk_disable_unprepare(priv->clk); 3441 3442 return ret; 3443 } 3444 3445 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3446 { 3447 struct bcmgenet_priv *priv = ring->priv; 3448 u32 p_index, c_index, intsts, intmsk; 3449 struct netdev_queue *txq; 3450 unsigned int free_bds; 3451 bool txq_stopped; 3452 3453 if (!netif_msg_tx_err(priv)) 3454 return; 3455 3456 txq = netdev_get_tx_queue(priv->dev, ring->index); 3457 3458 spin_lock(&ring->lock); 3459 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3460 intmsk = 1 << ring->index; 3461 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3462 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3463 txq_stopped = netif_tx_queue_stopped(txq); 3464 free_bds = ring->free_bds; 3465 spin_unlock(&ring->lock); 3466 3467 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3468 "TX queue status: %s, interrupts: %s\n" 3469 "(sw)free_bds: %d (sw)size: %d\n" 3470 "(sw)p_index: %d (hw)p_index: %d\n" 3471 "(sw)c_index: %d (hw)c_index: %d\n" 3472 "(sw)clean_p: %d (sw)write_p: %d\n" 3473 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3474 ring->index, ring->index, 3475 txq_stopped ? "stopped" : "active", 3476 intsts & intmsk ? "enabled" : "disabled", 3477 free_bds, ring->size, 3478 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3479 ring->c_index, c_index & DMA_C_INDEX_MASK, 3480 ring->clean_ptr, ring->write_ptr, 3481 ring->cb_ptr, ring->end_ptr); 3482 } 3483 3484 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3485 { 3486 struct bcmgenet_priv *priv = netdev_priv(dev); 3487 u32 int1_enable = 0; 3488 unsigned int q; 3489 3490 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3491 3492 for (q = 0; q <= priv->hw_params->tx_queues; q++) 3493 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3494 3495 bcmgenet_tx_reclaim_all(dev); 3496 3497 for (q = 0; q <= priv->hw_params->tx_queues; q++) 3498 int1_enable |= (1 << q); 3499 3500 /* Re-enable TX interrupts if disabled */ 3501 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3502 3503 netif_trans_update(dev); 3504 3505 BCMGENET_STATS64_INC((&priv->tx_rings[txqueue].stats64), errors); 3506 3507 netif_tx_wake_all_queues(dev); 3508 } 3509 3510 #define MAX_MDF_FILTER 17 3511 3512 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3513 const unsigned char *addr, 3514 int *i) 3515 { 3516 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3517 UMAC_MDF_ADDR + (*i * 4)); 3518 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3519 addr[4] << 8 | addr[5], 3520 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3521 *i += 2; 3522 } 3523 3524 static void bcmgenet_set_rx_mode(struct net_device *dev) 3525 { 3526 struct bcmgenet_priv *priv = netdev_priv(dev); 3527 struct netdev_hw_addr *ha; 3528 int i, nfilter; 3529 u32 reg; 3530 3531 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3532 3533 /* Number of filters needed */ 3534 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3535 3536 /* 3537 * Turn on promicuous mode for three scenarios 3538 * 1. IFF_PROMISC flag is set 3539 * 2. IFF_ALLMULTI flag is set 3540 * 3. The number of filters needed exceeds the number filters 3541 * supported by the hardware. 3542 */ 3543 spin_lock(&priv->reg_lock); 3544 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3545 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3546 (nfilter > MAX_MDF_FILTER)) { 3547 reg |= CMD_PROMISC; 3548 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3549 spin_unlock(&priv->reg_lock); 3550 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3551 return; 3552 } else { 3553 reg &= ~CMD_PROMISC; 3554 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3555 spin_unlock(&priv->reg_lock); 3556 } 3557 3558 /* update MDF filter */ 3559 i = 0; 3560 /* Broadcast */ 3561 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3562 /* my own address.*/ 3563 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3564 3565 /* Unicast */ 3566 netdev_for_each_uc_addr(ha, dev) 3567 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3568 3569 /* Multicast */ 3570 netdev_for_each_mc_addr(ha, dev) 3571 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3572 3573 /* Enable filters */ 3574 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3575 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3576 } 3577 3578 /* Set the hardware MAC address. */ 3579 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3580 { 3581 struct sockaddr *addr = p; 3582 3583 /* Setting the MAC address at the hardware level is not possible 3584 * without disabling the UniMAC RX/TX enable bits. 3585 */ 3586 if (netif_running(dev)) 3587 return -EBUSY; 3588 3589 eth_hw_addr_set(dev, addr->sa_data); 3590 3591 return 0; 3592 } 3593 3594 static void bcmgenet_get_stats64(struct net_device *dev, 3595 struct rtnl_link_stats64 *stats) 3596 { 3597 struct bcmgenet_priv *priv = netdev_priv(dev); 3598 struct bcmgenet_tx_stats64 *tx_stats; 3599 struct bcmgenet_rx_stats64 *rx_stats; 3600 u64 rx_length_errors, rx_over_errors; 3601 u64 rx_missed, rx_fragmented_errors; 3602 u64 rx_crc_errors, rx_frame_errors; 3603 u64 tx_errors, tx_dropped; 3604 u64 rx_errors, rx_dropped; 3605 u64 tx_bytes, tx_packets; 3606 u64 rx_bytes, rx_packets; 3607 unsigned int start; 3608 unsigned int q; 3609 u64 multicast; 3610 3611 for (q = 0; q <= priv->hw_params->tx_queues; q++) { 3612 tx_stats = &priv->tx_rings[q].stats64; 3613 do { 3614 start = u64_stats_fetch_begin(&tx_stats->syncp); 3615 tx_bytes = u64_stats_read(&tx_stats->bytes); 3616 tx_packets = u64_stats_read(&tx_stats->packets); 3617 tx_errors = u64_stats_read(&tx_stats->errors); 3618 tx_dropped = u64_stats_read(&tx_stats->dropped); 3619 } while (u64_stats_fetch_retry(&tx_stats->syncp, start)); 3620 3621 stats->tx_bytes += tx_bytes; 3622 stats->tx_packets += tx_packets; 3623 stats->tx_errors += tx_errors; 3624 stats->tx_dropped += tx_dropped; 3625 } 3626 3627 for (q = 0; q <= priv->hw_params->rx_queues; q++) { 3628 rx_stats = &priv->rx_rings[q].stats64; 3629 do { 3630 start = u64_stats_fetch_begin(&rx_stats->syncp); 3631 rx_bytes = u64_stats_read(&rx_stats->bytes); 3632 rx_packets = u64_stats_read(&rx_stats->packets); 3633 rx_errors = u64_stats_read(&rx_stats->errors); 3634 rx_dropped = u64_stats_read(&rx_stats->dropped); 3635 rx_missed = u64_stats_read(&rx_stats->missed); 3636 rx_length_errors = u64_stats_read(&rx_stats->length_errors); 3637 rx_over_errors = u64_stats_read(&rx_stats->over_errors); 3638 rx_crc_errors = u64_stats_read(&rx_stats->crc_errors); 3639 rx_frame_errors = u64_stats_read(&rx_stats->frame_errors); 3640 rx_fragmented_errors = u64_stats_read(&rx_stats->fragmented_errors); 3641 multicast = u64_stats_read(&rx_stats->multicast); 3642 } while (u64_stats_fetch_retry(&rx_stats->syncp, start)); 3643 3644 rx_errors += rx_length_errors; 3645 rx_errors += rx_crc_errors; 3646 rx_errors += rx_frame_errors; 3647 rx_errors += rx_fragmented_errors; 3648 3649 stats->rx_bytes += rx_bytes; 3650 stats->rx_packets += rx_packets; 3651 stats->rx_errors += rx_errors; 3652 stats->rx_dropped += rx_dropped; 3653 stats->rx_missed_errors += rx_missed; 3654 stats->rx_length_errors += rx_length_errors; 3655 stats->rx_over_errors += rx_over_errors; 3656 stats->rx_crc_errors += rx_crc_errors; 3657 stats->rx_frame_errors += rx_frame_errors; 3658 stats->multicast += multicast; 3659 } 3660 } 3661 3662 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3663 { 3664 struct bcmgenet_priv *priv = netdev_priv(dev); 3665 3666 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3667 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3668 return -EOPNOTSUPP; 3669 3670 if (new_carrier) 3671 netif_carrier_on(dev); 3672 else 3673 netif_carrier_off(dev); 3674 3675 return 0; 3676 } 3677 3678 static const struct net_device_ops bcmgenet_netdev_ops = { 3679 .ndo_open = bcmgenet_open, 3680 .ndo_stop = bcmgenet_close, 3681 .ndo_start_xmit = bcmgenet_xmit, 3682 .ndo_tx_timeout = bcmgenet_timeout, 3683 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3684 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3685 .ndo_eth_ioctl = phy_do_ioctl_running, 3686 .ndo_set_features = bcmgenet_set_features, 3687 .ndo_get_stats64 = bcmgenet_get_stats64, 3688 .ndo_change_carrier = bcmgenet_change_carrier, 3689 }; 3690 3691 /* GENET hardware parameters/characteristics */ 3692 static const struct bcmgenet_hw_params bcmgenet_hw_params_v1 = { 3693 .tx_queues = 0, 3694 .tx_bds_per_q = 0, 3695 .rx_queues = 0, 3696 .rx_bds_per_q = 0, 3697 .bp_in_en_shift = 16, 3698 .bp_in_mask = 0xffff, 3699 .hfb_filter_cnt = 16, 3700 .hfb_filter_size = 64, 3701 .qtag_mask = 0x1F, 3702 .hfb_offset = 0x1000, 3703 .hfb_reg_offset = GENET_RBUF_OFF + RBUF_HFB_CTRL_V1, 3704 .rdma_offset = 0x2000, 3705 .tdma_offset = 0x3000, 3706 .words_per_bd = 2, 3707 }; 3708 3709 static const struct bcmgenet_hw_params bcmgenet_hw_params_v2 = { 3710 .tx_queues = 4, 3711 .tx_bds_per_q = 32, 3712 .rx_queues = 0, 3713 .rx_bds_per_q = 0, 3714 .bp_in_en_shift = 16, 3715 .bp_in_mask = 0xffff, 3716 .hfb_filter_cnt = 16, 3717 .hfb_filter_size = 64, 3718 .qtag_mask = 0x1F, 3719 .tbuf_offset = 0x0600, 3720 .hfb_offset = 0x1000, 3721 .hfb_reg_offset = 0x2000, 3722 .rdma_offset = 0x3000, 3723 .tdma_offset = 0x4000, 3724 .words_per_bd = 2, 3725 }; 3726 3727 static const struct bcmgenet_hw_params bcmgenet_hw_params_v3 = { 3728 .tx_queues = 4, 3729 .tx_bds_per_q = 32, 3730 .rx_queues = 0, 3731 .rx_bds_per_q = 0, 3732 .bp_in_en_shift = 17, 3733 .bp_in_mask = 0x1ffff, 3734 .hfb_filter_cnt = 48, 3735 .hfb_filter_size = 128, 3736 .qtag_mask = 0x3F, 3737 .tbuf_offset = 0x0600, 3738 .hfb_offset = 0x8000, 3739 .hfb_reg_offset = 0xfc00, 3740 .rdma_offset = 0x10000, 3741 .tdma_offset = 0x11000, 3742 .words_per_bd = 2, 3743 }; 3744 3745 static const struct bcmgenet_hw_params bcmgenet_hw_params_v4 = { 3746 .tx_queues = 4, 3747 .tx_bds_per_q = 32, 3748 .rx_queues = 0, 3749 .rx_bds_per_q = 0, 3750 .bp_in_en_shift = 17, 3751 .bp_in_mask = 0x1ffff, 3752 .hfb_filter_cnt = 48, 3753 .hfb_filter_size = 128, 3754 .qtag_mask = 0x3F, 3755 .tbuf_offset = 0x0600, 3756 .hfb_offset = 0x8000, 3757 .hfb_reg_offset = 0xfc00, 3758 .rdma_offset = 0x2000, 3759 .tdma_offset = 0x4000, 3760 .words_per_bd = 3, 3761 }; 3762 3763 /* Infer hardware parameters from the detected GENET version */ 3764 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3765 { 3766 const struct bcmgenet_hw_params *params; 3767 u32 reg; 3768 u8 major; 3769 u16 gphy_rev; 3770 3771 /* default to latest values */ 3772 params = &bcmgenet_hw_params_v4; 3773 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3774 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3775 if (GENET_IS_V3(priv)) { 3776 params = &bcmgenet_hw_params_v3; 3777 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3778 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3779 } else if (GENET_IS_V2(priv)) { 3780 params = &bcmgenet_hw_params_v2; 3781 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3782 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3783 } else if (GENET_IS_V1(priv)) { 3784 params = &bcmgenet_hw_params_v1; 3785 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3786 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3787 } 3788 priv->hw_params = params; 3789 3790 /* Read GENET HW version */ 3791 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3792 major = (reg >> 24 & 0x0f); 3793 if (major == 6 || major == 7) 3794 major = 5; 3795 else if (major == 5) 3796 major = 4; 3797 else if (major == 0) 3798 major = 1; 3799 if (major != priv->version) { 3800 dev_err(&priv->pdev->dev, 3801 "GENET version mismatch, got: %d, configured for: %d\n", 3802 major, priv->version); 3803 } 3804 3805 /* Print the GENET core version */ 3806 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3807 major, (reg >> 16) & 0x0f, reg & 0xffff); 3808 3809 /* Store the integrated PHY revision for the MDIO probing function 3810 * to pass this information to the PHY driver. The PHY driver expects 3811 * to find the PHY major revision in bits 15:8 while the GENET register 3812 * stores that information in bits 7:0, account for that. 3813 * 3814 * On newer chips, starting with PHY revision G0, a new scheme is 3815 * deployed similar to the Starfighter 2 switch with GPHY major 3816 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3817 * is reserved as well as special value 0x01ff, we have a small 3818 * heuristic to check for the new GPHY revision and re-arrange things 3819 * so the GPHY driver is happy. 3820 */ 3821 gphy_rev = reg & 0xffff; 3822 3823 if (GENET_IS_V5(priv)) { 3824 /* The EPHY revision should come from the MDIO registers of 3825 * the PHY not from GENET. 3826 */ 3827 if (gphy_rev != 0) { 3828 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3829 gphy_rev); 3830 } 3831 /* This is reserved so should require special treatment */ 3832 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3833 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3834 return; 3835 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3836 } else if ((gphy_rev & 0xf0) != 0) { 3837 priv->gphy_rev = gphy_rev << 8; 3838 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3839 } else if ((gphy_rev & 0xff00) != 0) { 3840 priv->gphy_rev = gphy_rev; 3841 } 3842 3843 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3844 if (!bcmgenet_has_40bits(priv)) 3845 pr_warn("GENET does not support 40-bits PA\n"); 3846 #endif 3847 3848 pr_debug("Configuration for version: %d\n" 3849 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3850 "BP << en: %2d, BP msk: 0x%05x\n" 3851 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3852 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3853 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3854 "Words/BD: %d\n", 3855 priv->version, 3856 params->tx_queues, params->tx_bds_per_q, 3857 params->rx_queues, params->rx_bds_per_q, 3858 params->bp_in_en_shift, params->bp_in_mask, 3859 params->hfb_filter_cnt, params->qtag_mask, 3860 params->tbuf_offset, params->hfb_offset, 3861 params->hfb_reg_offset, 3862 params->rdma_offset, params->tdma_offset, 3863 params->words_per_bd); 3864 } 3865 3866 struct bcmgenet_plat_data { 3867 enum bcmgenet_version version; 3868 u32 dma_max_burst_length; 3869 u32 flags; 3870 }; 3871 3872 static const struct bcmgenet_plat_data v1_plat_data = { 3873 .version = GENET_V1, 3874 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3875 }; 3876 3877 static const struct bcmgenet_plat_data v2_plat_data = { 3878 .version = GENET_V2, 3879 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3880 .flags = GENET_HAS_EXT, 3881 }; 3882 3883 static const struct bcmgenet_plat_data v3_plat_data = { 3884 .version = GENET_V3, 3885 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3886 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3887 GENET_HAS_MOCA_LINK_DET, 3888 }; 3889 3890 static const struct bcmgenet_plat_data v4_plat_data = { 3891 .version = GENET_V4, 3892 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3893 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3894 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3895 }; 3896 3897 static const struct bcmgenet_plat_data v5_plat_data = { 3898 .version = GENET_V5, 3899 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3900 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3901 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3902 }; 3903 3904 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3905 .version = GENET_V5, 3906 .dma_max_burst_length = 0x08, 3907 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3908 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3909 }; 3910 3911 static const struct bcmgenet_plat_data bcm7712_plat_data = { 3912 .version = GENET_V5, 3913 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3914 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3915 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET | 3916 GENET_HAS_EPHY_16NM, 3917 }; 3918 3919 static const struct of_device_id bcmgenet_match[] = { 3920 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3921 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3922 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3923 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3924 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3925 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3926 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data }, 3927 { }, 3928 }; 3929 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3930 3931 static int bcmgenet_probe(struct platform_device *pdev) 3932 { 3933 const struct bcmgenet_plat_data *pdata; 3934 struct bcmgenet_priv *priv; 3935 struct net_device *dev; 3936 unsigned int i; 3937 int err = -EIO; 3938 3939 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3940 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3941 GENET_MAX_MQ_CNT + 1); 3942 if (!dev) { 3943 dev_err(&pdev->dev, "can't allocate net device\n"); 3944 return -ENOMEM; 3945 } 3946 3947 priv = netdev_priv(dev); 3948 priv->irq0 = platform_get_irq(pdev, 0); 3949 if (priv->irq0 < 0) { 3950 err = priv->irq0; 3951 goto err; 3952 } 3953 priv->irq1 = platform_get_irq(pdev, 1); 3954 if (priv->irq1 < 0) { 3955 err = priv->irq1; 3956 goto err; 3957 } 3958 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3959 if (priv->wol_irq == -EPROBE_DEFER) { 3960 err = priv->wol_irq; 3961 goto err; 3962 } 3963 3964 priv->base = devm_platform_ioremap_resource(pdev, 0); 3965 if (IS_ERR(priv->base)) { 3966 err = PTR_ERR(priv->base); 3967 goto err; 3968 } 3969 3970 spin_lock_init(&priv->reg_lock); 3971 spin_lock_init(&priv->lock); 3972 3973 /* Set default pause parameters */ 3974 priv->autoneg_pause = 1; 3975 priv->tx_pause = 1; 3976 priv->rx_pause = 1; 3977 3978 SET_NETDEV_DEV(dev, &pdev->dev); 3979 dev_set_drvdata(&pdev->dev, dev); 3980 dev->watchdog_timeo = 2 * HZ; 3981 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3982 dev->netdev_ops = &bcmgenet_netdev_ops; 3983 3984 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3985 3986 /* Set default features */ 3987 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3988 NETIF_F_RXCSUM; 3989 dev->hw_features |= dev->features; 3990 dev->vlan_features |= dev->features; 3991 3992 netdev_sw_irq_coalesce_default_on(dev); 3993 3994 /* Request the WOL interrupt and advertise suspend if available */ 3995 priv->wol_irq_disabled = true; 3996 if (priv->wol_irq > 0) { 3997 err = devm_request_irq(&pdev->dev, priv->wol_irq, 3998 bcmgenet_wol_isr, 0, dev->name, priv); 3999 if (!err) 4000 device_set_wakeup_capable(&pdev->dev, 1); 4001 } 4002 4003 /* Set the needed headroom to account for any possible 4004 * features enabling/disabling at runtime 4005 */ 4006 dev->needed_headroom += 64; 4007 4008 priv->dev = dev; 4009 priv->pdev = pdev; 4010 4011 pdata = device_get_match_data(&pdev->dev); 4012 if (pdata) { 4013 priv->version = pdata->version; 4014 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4015 priv->flags = pdata->flags; 4016 } 4017 4018 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4019 if (IS_ERR(priv->clk)) { 4020 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4021 err = PTR_ERR(priv->clk); 4022 goto err; 4023 } 4024 4025 err = clk_prepare_enable(priv->clk); 4026 if (err) 4027 goto err; 4028 4029 bcmgenet_set_hw_params(priv); 4030 4031 err = -EIO; 4032 if (bcmgenet_has_40bits(priv)) 4033 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4034 if (err) 4035 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4036 if (err) 4037 goto err_clk_disable; 4038 4039 /* Mii wait queue */ 4040 init_waitqueue_head(&priv->wq); 4041 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4042 priv->rx_buf_len = RX_BUF_LENGTH; 4043 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4044 4045 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4046 if (IS_ERR(priv->clk_wol)) { 4047 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4048 err = PTR_ERR(priv->clk_wol); 4049 goto err_clk_disable; 4050 } 4051 4052 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4053 if (IS_ERR(priv->clk_eee)) { 4054 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4055 err = PTR_ERR(priv->clk_eee); 4056 goto err_clk_disable; 4057 } 4058 4059 /* If this is an internal GPHY, power it on now, before UniMAC is 4060 * brought out of reset as absolutely no UniMAC activity is allowed 4061 */ 4062 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4063 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4064 4065 if (device_get_ethdev_address(&pdev->dev, dev)) 4066 if (has_acpi_companion(&pdev->dev)) { 4067 u8 addr[ETH_ALEN]; 4068 4069 bcmgenet_get_hw_addr(priv, addr); 4070 eth_hw_addr_set(dev, addr); 4071 } 4072 4073 if (!is_valid_ether_addr(dev->dev_addr)) { 4074 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4075 eth_hw_addr_random(dev); 4076 } 4077 4078 reset_umac(priv); 4079 4080 err = bcmgenet_mii_init(dev); 4081 if (err) 4082 goto err_clk_disable; 4083 4084 /* setup number of real queues + 1 */ 4085 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4086 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4087 4088 /* Set default coalescing parameters */ 4089 for (i = 0; i <= priv->hw_params->rx_queues; i++) 4090 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4091 4092 /* Initialize u64 stats seq counter for 32bit machines */ 4093 for (i = 0; i <= priv->hw_params->rx_queues; i++) 4094 u64_stats_init(&priv->rx_rings[i].stats64.syncp); 4095 for (i = 0; i <= priv->hw_params->tx_queues; i++) 4096 u64_stats_init(&priv->tx_rings[i].stats64.syncp); 4097 4098 /* libphy will determine the link state */ 4099 netif_carrier_off(dev); 4100 4101 /* Turn off the main clock, WOL clock is handled separately */ 4102 clk_disable_unprepare(priv->clk); 4103 4104 err = register_netdev(dev); 4105 if (err) { 4106 bcmgenet_mii_exit(dev); 4107 goto err; 4108 } 4109 4110 return err; 4111 4112 err_clk_disable: 4113 clk_disable_unprepare(priv->clk); 4114 err: 4115 free_netdev(dev); 4116 return err; 4117 } 4118 4119 static void bcmgenet_remove(struct platform_device *pdev) 4120 { 4121 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4122 4123 dev_set_drvdata(&pdev->dev, NULL); 4124 unregister_netdev(priv->dev); 4125 bcmgenet_mii_exit(priv->dev); 4126 free_netdev(priv->dev); 4127 } 4128 4129 static void bcmgenet_shutdown(struct platform_device *pdev) 4130 { 4131 bcmgenet_remove(pdev); 4132 } 4133 4134 #ifdef CONFIG_PM_SLEEP 4135 static int bcmgenet_resume_noirq(struct device *d) 4136 { 4137 struct net_device *dev = dev_get_drvdata(d); 4138 struct bcmgenet_priv *priv = netdev_priv(dev); 4139 int ret; 4140 u32 reg; 4141 4142 if (!netif_running(dev)) 4143 return 0; 4144 4145 /* Turn on the clock */ 4146 ret = clk_prepare_enable(priv->clk); 4147 if (ret) 4148 return ret; 4149 4150 if (device_may_wakeup(d) && priv->wolopts) { 4151 /* Account for Wake-on-LAN events and clear those events 4152 * (Some devices need more time between enabling the clocks 4153 * and the interrupt register reflecting the wake event so 4154 * read the register twice) 4155 */ 4156 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4157 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4158 if (reg & UMAC_IRQ_WAKE_EVENT) 4159 pm_wakeup_event(&priv->pdev->dev, 0); 4160 4161 /* From WOL-enabled suspend, switch to regular clock */ 4162 if (!bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC)) 4163 return 0; 4164 4165 /* Failed so fall through to reset MAC */ 4166 } 4167 4168 /* If this is an internal GPHY, power it back on now, before UniMAC is 4169 * brought out of reset as absolutely no UniMAC activity is allowed 4170 */ 4171 if (priv->internal_phy) 4172 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4173 4174 /* take MAC out of reset */ 4175 bcmgenet_umac_reset(priv); 4176 4177 return 0; 4178 } 4179 4180 static int bcmgenet_resume(struct device *d) 4181 { 4182 struct net_device *dev = dev_get_drvdata(d); 4183 struct bcmgenet_priv *priv = netdev_priv(dev); 4184 struct bcmgenet_rxnfc_rule *rule; 4185 int ret; 4186 u32 reg; 4187 4188 if (!netif_running(dev)) 4189 return 0; 4190 4191 if (device_may_wakeup(d) && priv->wolopts) { 4192 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 4193 if (reg & CMD_RX_EN) { 4194 /* Successfully exited WoL, just resume data flows */ 4195 list_for_each_entry(rule, &priv->rxnfc_list, list) 4196 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4197 bcmgenet_hfb_enable_filter(priv, 4198 rule->fs.location + 1); 4199 bcmgenet_hfb_enable_filter(priv, 0); 4200 bcmgenet_set_rx_mode(dev); 4201 bcmgenet_enable_rx_napi(priv); 4202 4203 /* Reinitialize Tx flows */ 4204 bcmgenet_tdma_disable(priv); 4205 bcmgenet_init_tx_queues(priv->dev); 4206 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 4207 reg |= DMA_EN; 4208 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 4209 bcmgenet_enable_tx_napi(priv); 4210 4211 bcmgenet_link_intr_enable(priv); 4212 phy_start_machine(dev->phydev); 4213 4214 netif_device_attach(dev); 4215 enable_irq(priv->irq1); 4216 return 0; 4217 } 4218 /* MAC was reset so complete bcmgenet_netif_stop() */ 4219 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, false); 4220 bcmgenet_rdma_disable(priv); 4221 bcmgenet_intr_disable(priv); 4222 bcmgenet_fini_dma(priv); 4223 enable_irq(priv->irq1); 4224 } 4225 4226 init_umac(priv); 4227 4228 phy_init_hw(dev->phydev); 4229 4230 /* Speed settings must be restored */ 4231 genphy_config_aneg(dev->phydev); 4232 bcmgenet_mii_config(priv->dev, false); 4233 4234 /* Restore enabled features */ 4235 bcmgenet_set_features(dev, dev->features); 4236 4237 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4238 4239 /* Restore hardware filters */ 4240 bcmgenet_hfb_clear(priv); 4241 list_for_each_entry(rule, &priv->rxnfc_list, list) 4242 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 4243 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 4244 4245 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4246 ret = bcmgenet_init_dma(priv, false); 4247 if (ret) { 4248 netdev_err(dev, "failed to initialize DMA\n"); 4249 goto out_clk_disable; 4250 } 4251 4252 if (!device_may_wakeup(d)) 4253 phy_resume(dev->phydev); 4254 4255 bcmgenet_netif_start(dev); 4256 4257 netif_device_attach(dev); 4258 4259 return 0; 4260 4261 out_clk_disable: 4262 if (priv->internal_phy) 4263 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4264 clk_disable_unprepare(priv->clk); 4265 return ret; 4266 } 4267 4268 static int bcmgenet_suspend(struct device *d) 4269 { 4270 struct net_device *dev = dev_get_drvdata(d); 4271 struct bcmgenet_priv *priv = netdev_priv(dev); 4272 struct bcmgenet_rxnfc_rule *rule; 4273 u32 reg, hfb_enable = 0; 4274 4275 if (!netif_running(dev)) 4276 return 0; 4277 4278 netif_device_detach(dev); 4279 4280 if (device_may_wakeup(d) && priv->wolopts) { 4281 netif_tx_disable(dev); 4282 4283 /* Suspend non-wake Rx data flows */ 4284 if (priv->wolopts & WAKE_FILTER) 4285 list_for_each_entry(rule, &priv->rxnfc_list, list) 4286 if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE && 4287 rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4288 hfb_enable |= 1 << rule->fs.location; 4289 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 4290 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 4291 reg &= ~RBUF_HFB_FILTER_EN_MASK; 4292 reg |= hfb_enable << (RBUF_HFB_FILTER_EN_SHIFT + 1); 4293 } else { 4294 bcmgenet_hfb_reg_writel(priv, hfb_enable << 1, 4295 HFB_FLT_ENABLE_V3PLUS + 4); 4296 } 4297 if (!hfb_enable) 4298 reg &= ~RBUF_HFB_EN; 4299 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 4300 4301 /* Clear any old filter matches so only new matches wake */ 4302 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 4303 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 4304 4305 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) 4306 netdev_warn(priv->dev, 4307 "Timed out while disabling TX DMA\n"); 4308 4309 bcmgenet_disable_tx_napi(priv); 4310 bcmgenet_disable_rx_napi(priv); 4311 disable_irq(priv->irq1); 4312 bcmgenet_tx_reclaim_all(dev); 4313 bcmgenet_fini_tx_napi(priv); 4314 } else { 4315 /* Teardown the interface */ 4316 bcmgenet_netif_stop(dev, true); 4317 } 4318 4319 return 0; 4320 } 4321 4322 static int bcmgenet_suspend_noirq(struct device *d) 4323 { 4324 struct net_device *dev = dev_get_drvdata(d); 4325 struct bcmgenet_priv *priv = netdev_priv(dev); 4326 int ret = 0; 4327 4328 if (!netif_running(dev)) 4329 return 0; 4330 4331 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4332 if (device_may_wakeup(d) && priv->wolopts) 4333 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4334 else if (priv->internal_phy) 4335 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4336 4337 /* Let the framework handle resumption and leave the clocks on */ 4338 if (ret) 4339 return ret; 4340 4341 /* Turn off the clocks */ 4342 clk_disable_unprepare(priv->clk); 4343 4344 return 0; 4345 } 4346 #else 4347 #define bcmgenet_suspend NULL 4348 #define bcmgenet_suspend_noirq NULL 4349 #define bcmgenet_resume NULL 4350 #define bcmgenet_resume_noirq NULL 4351 #endif /* CONFIG_PM_SLEEP */ 4352 4353 static const struct dev_pm_ops bcmgenet_pm_ops = { 4354 .suspend = bcmgenet_suspend, 4355 .suspend_noirq = bcmgenet_suspend_noirq, 4356 .resume = bcmgenet_resume, 4357 .resume_noirq = bcmgenet_resume_noirq, 4358 }; 4359 4360 static const struct acpi_device_id genet_acpi_match[] = { 4361 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4362 { }, 4363 }; 4364 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4365 4366 static struct platform_driver bcmgenet_driver = { 4367 .probe = bcmgenet_probe, 4368 .remove = bcmgenet_remove, 4369 .shutdown = bcmgenet_shutdown, 4370 .driver = { 4371 .name = "bcmgenet", 4372 .of_match_table = bcmgenet_match, 4373 .pm = &bcmgenet_pm_ops, 4374 .acpi_match_table = genet_acpi_match, 4375 }, 4376 }; 4377 module_platform_driver(bcmgenet_driver); 4378 4379 MODULE_AUTHOR("Broadcom Corporation"); 4380 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4381 MODULE_ALIAS("platform:bcmgenet"); 4382 MODULE_LICENSE("GPL"); 4383 MODULE_SOFTDEP("pre: mdio-bcm-unimac"); 4384