xref: /linux/include/dt-bindings/reset/qcom,ipq5424-gcc.h (revision 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H
8 #define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H
9 
10 #define GCC_QUPV3_BCR				0
11 #define GCC_QUPV3_I2C0_BCR			1
12 #define GCC_QUPV3_UART0_BCR			2
13 #define GCC_QUPV3_I2C1_BCR			3
14 #define GCC_QUPV3_UART1_BCR			4
15 #define GCC_QUPV3_SPI0_BCR			5
16 #define GCC_QUPV3_SPI1_BCR			6
17 #define GCC_IMEM_BCR				7
18 #define GCC_TME_BCR				8
19 #define GCC_DDRSS_BCR				9
20 #define GCC_PRNG_BCR				10
21 #define GCC_BOOT_ROM_BCR			11
22 #define GCC_NSS_BCR				12
23 #define GCC_MDIO_BCR				13
24 #define GCC_UNIPHY0_BCR				14
25 #define GCC_UNIPHY1_BCR				15
26 #define GCC_UNIPHY2_BCR				16
27 #define GCC_WCSS_BCR				17
28 #define GCC_SEC_CTRL_BCR			19
29 #define GCC_TME_SEC_BUS_BCR			20
30 #define GCC_ADSS_BCR				21
31 #define GCC_LPASS_BCR				22
32 #define GCC_PCIE0_BCR				23
33 #define GCC_PCIE0_LINK_DOWN_BCR			24
34 #define GCC_PCIE0PHY_PHY_BCR			25
35 #define GCC_PCIE0_PHY_BCR			26
36 #define GCC_PCIE1_BCR				27
37 #define GCC_PCIE1_LINK_DOWN_BCR			28
38 #define GCC_PCIE1PHY_PHY_BCR			29
39 #define GCC_PCIE1_PHY_BCR			30
40 #define GCC_PCIE2_BCR				31
41 #define GCC_PCIE2_LINK_DOWN_BCR			32
42 #define GCC_PCIE2PHY_PHY_BCR			33
43 #define GCC_PCIE2_PHY_BCR			34
44 #define GCC_PCIE3_BCR				35
45 #define GCC_PCIE3_LINK_DOWN_BCR			36
46 #define GCC_PCIE3PHY_PHY_BCR			37
47 #define GCC_PCIE3_PHY_BCR			38
48 #define GCC_USB_BCR				39
49 #define GCC_QUSB2_0_PHY_BCR			40
50 #define GCC_USB0_PHY_BCR			41
51 #define GCC_USB3PHY_0_PHY_BCR			42
52 #define GCC_QDSS_BCR				43
53 #define GCC_SNOC_BCR				44
54 #define GCC_ANOC_BCR				45
55 #define GCC_PCNOC_BCR				46
56 #define GCC_PCNOC_BUS_TIMEOUT0_BCR		47
57 #define GCC_PCNOC_BUS_TIMEOUT1_BCR		48
58 #define GCC_PCNOC_BUS_TIMEOUT2_BCR		49
59 #define GCC_PCNOC_BUS_TIMEOUT3_BCR		50
60 #define GCC_PCNOC_BUS_TIMEOUT4_BCR		51
61 #define GCC_PCNOC_BUS_TIMEOUT5_BCR		52
62 #define GCC_PCNOC_BUS_TIMEOUT6_BCR		53
63 #define GCC_PCNOC_BUS_TIMEOUT7_BCR		54
64 #define GCC_PCNOC_BUS_TIMEOUT8_BCR		55
65 #define GCC_PCNOC_BUS_TIMEOUT9_BCR		56
66 #define GCC_QPIC_BCR				57
67 #define GCC_SDCC_BCR				58
68 #define GCC_DCC_BCR				59
69 #define GCC_SPDM_BCR				60
70 #define GCC_MPM_BCR				61
71 #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	62
72 #define GCC_RBCPR_BCR				63
73 #define GCC_CMN_BLK_BCR				64
74 #define GCC_TCSR_BCR				65
75 #define GCC_TLMM_BCR				66
76 #define GCC_QUPV3_AHB_MST_ARES			67
77 #define GCC_QUPV3_CORE_ARES			68
78 #define GCC_QUPV3_2X_CORE_ARES			69
79 #define GCC_QUPV3_SLEEP_ARES			70
80 #define GCC_QUPV3_AHB_SLV_ARES			71
81 #define GCC_QUPV3_I2C0_ARES			72
82 #define GCC_QUPV3_UART0_ARES			73
83 #define GCC_QUPV3_I2C1_ARES			74
84 #define GCC_QUPV3_UART1_ARES			75
85 #define GCC_QUPV3_SPI0_ARES			76
86 #define GCC_QUPV3_SPI1_ARES			77
87 #define GCC_DEBUG_ARES				78
88 #define GCC_GP1_ARES				79
89 #define GCC_GP2_ARES				80
90 #define GCC_GP3_ARES				81
91 #define GCC_IMEM_AXI_ARES			82
92 #define GCC_IMEM_CFG_AHB_ARES			83
93 #define GCC_TME_ARES				84
94 #define GCC_TME_TS_ARES				85
95 #define GCC_TME_SLOW_ARES			86
96 #define GCC_TME_RTC_TOGGLE_ARES			87
97 #define GCC_TIC_ARES				88
98 #define GCC_PRNG_AHB_ARES			89
99 #define GCC_BOOT_ROM_AHB_ARES			90
100 #define GCC_NSSNOC_ATB_ARES			91
101 #define GCC_NSS_TS_ARES				92
102 #define GCC_NSSNOC_QOSGEN_REF_ARES		93
103 #define GCC_NSSNOC_TIMEOUT_REF_ARES		94
104 #define GCC_NSSNOC_MEMNOC_ARES			95
105 #define GCC_NSSNOC_SNOC_ARES			96
106 #define GCC_NSSCFG_ARES				97
107 #define GCC_NSSNOC_NSSCC_ARES			98
108 #define GCC_NSSCC_ARES				99
109 #define GCC_MDIO_AHB_ARES			100
110 #define GCC_UNIPHY0_SYS_ARES			101
111 #define GCC_UNIPHY0_AHB_ARES			102
112 #define GCC_UNIPHY1_SYS_ARES			103
113 #define GCC_UNIPHY1_AHB_ARES			104
114 #define GCC_UNIPHY2_SYS_ARES			105
115 #define GCC_UNIPHY2_AHB_ARES			106
116 #define GCC_NSSNOC_XO_DCD_ARES			107
117 #define GCC_NSSNOC_SNOC_1_ARES			108
118 #define GCC_NSSNOC_PCNOC_1_ARES			109
119 #define GCC_NSSNOC_MEMNOC_1_ARES		110
120 #define GCC_DDRSS_ATB_ARES			111
121 #define GCC_DDRSS_AHB_ARES			112
122 #define GCC_GEMNOC_AHB_ARES			113
123 #define GCC_GEMNOC_Q6_AXI_ARES			114
124 #define GCC_GEMNOC_NSSNOC_ARES			115
125 #define GCC_GEMNOC_SNOC_ARES			116
126 #define GCC_GEMNOC_APSS_ARES			117
127 #define GCC_GEMNOC_QOSGEN_EXTREF_ARES		118
128 #define GCC_GEMNOC_TS_ARES			119
129 #define GCC_DDRSS_SMS_SLOW_ARES			120
130 #define GCC_GEMNOC_CNOC_ARES			121
131 #define GCC_GEMNOC_XO_DBG_ARES			122
132 #define GCC_GEMNOC_ANOC_ARES			123
133 #define GCC_DDRSS_LLCC_ATB_ARES			124
134 #define GCC_LLCC_TPDM_CFG_ARES			125
135 #define GCC_TME_BUS_ARES			126
136 #define GCC_SEC_CTRL_ACC_ARES			127
137 #define GCC_SEC_CTRL_ARES			128
138 #define GCC_SEC_CTRL_SENSE_ARES			129
139 #define GCC_SEC_CTRL_AHB_ARES			130
140 #define GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES	131
141 #define GCC_ADSS_PWM_ARES			132
142 #define GCC_TME_ATB_ARES			133
143 #define GCC_TME_DBGAPB_ARES			134
144 #define GCC_TME_DEBUG_ARES			135
145 #define GCC_TME_AT_ARES				136
146 #define GCC_TME_APB_ARES			137
147 #define GCC_TME_DMI_DBG_HS_ARES			138
148 #define GCC_APSS_AHB_ARES			139
149 #define GCC_APSS_AXI_ARES			140
150 #define GCC_CPUSS_TRIG_ARES			141
151 #define GCC_APSS_DBG_ARES			142
152 #define GCC_APSS_TS_ARES			143
153 #define GCC_APSS_ATB_ARES			144
154 #define GCC_Q6_AXIM_ARES			145
155 #define GCC_Q6_AXIS_ARES			146
156 #define GCC_Q6_AHB_ARES				147
157 #define GCC_Q6_AHB_S_ARES			148
158 #define GCC_Q6SS_ATBM_ARES			149
159 #define GCC_Q6_TSCTR_1TO2_ARES			150
160 #define GCC_Q6SS_PCLKDBG_ARES			151
161 #define GCC_Q6SS_TRIG_ARES			152
162 #define GCC_Q6SS_BOOT_CBCR_ARES			153
163 #define GCC_WCSS_DBG_IFC_APB_ARES		154
164 #define GCC_WCSS_DBG_IFC_ATB_ARES		155
165 #define GCC_WCSS_DBG_IFC_NTS_ARES		156
166 #define GCC_WCSS_DBG_IFC_DAPBUS_ARES		157
167 #define GCC_WCSS_DBG_IFC_APB_BDG_ARES		158
168 #define GCC_WCSS_DBG_IFC_NTS_BDG_ARES		159
169 #define GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES	160
170 #define GCC_WCSS_ECAHB_ARES			161
171 #define GCC_WCSS_ACMT_ARES			162
172 #define GCC_WCSS_AHB_S_ARES			163
173 #define GCC_WCSS_AXI_M_ARES			164
174 #define GCC_PCNOC_WAPSS_ARES			165
175 #define GCC_SNOC_WAPSS_ARES			166
176 #define GCC_LPASS_SWAY_ARES			167
177 #define GCC_LPASS_CORE_AXIM_ARES		168
178 #define GCC_PCIE0_AHB_ARES			169
179 #define GCC_PCIE0_AXI_M_ARES			170
180 #define GCC_PCIE0_AXI_S_ARES			171
181 #define GCC_PCIE0_AXI_S_BRIDGE_ARES		172
182 #define GCC_PCIE0_PIPE_ARES			173
183 #define GCC_PCIE0_AUX_ARES			174
184 #define GCC_PCIE1_AHB_ARES			175
185 #define GCC_PCIE1_AXI_M_ARES			176
186 #define GCC_PCIE1_AXI_S_ARES			177
187 #define GCC_PCIE1_AXI_S_BRIDGE_ARES		178
188 #define GCC_PCIE1_PIPE_ARES			179
189 #define GCC_PCIE1_AUX_ARES			180
190 #define GCC_PCIE2_AHB_ARES			181
191 #define GCC_PCIE2_AXI_M_ARES			182
192 #define GCC_PCIE2_AXI_S_ARES			183
193 #define GCC_PCIE2_AXI_S_BRIDGE_ARES		184
194 #define GCC_PCIE2_PIPE_ARES			185
195 #define GCC_PCIE2_AUX_ARES			186
196 #define GCC_PCIE3_AHB_ARES			187
197 #define GCC_PCIE3_AXI_M_ARES			188
198 #define GCC_PCIE3_AXI_S_ARES			189
199 #define GCC_PCIE3_AXI_S_BRIDGE_ARES		190
200 #define GCC_PCIE3_PIPE_ARES			191
201 #define GCC_PCIE3_AUX_ARES			192
202 #define GCC_USB0_MASTER_ARES			193
203 #define GCC_USB0_AUX_ARES			194
204 #define GCC_USB0_MOCK_UTMI_ARES			195
205 #define GCC_USB0_PIPE_ARES			196
206 #define GCC_USB0_SLEEP_ARES			197
207 #define GCC_USB0_PHY_CFG_AHB_ARES		198
208 #define GCC_QDSS_AT_ARES			199
209 #define GCC_QDSS_STM_ARES			200
210 #define GCC_QDSS_TRACECLKIN_ARES		201
211 #define GCC_QDSS_TSCTR_DIV2_ARES		202
212 #define GCC_QDSS_TSCTR_DIV3_ARES		203
213 #define GCC_QDSS_TSCTR_DIV4_ARES		204
214 #define GCC_QDSS_TSCTR_DIV8_ARES		205
215 #define GCC_QDSS_TSCTR_DIV16_ARES		206
216 #define GCC_QDSS_DAP_ARES			207
217 #define GCC_QDSS_APB2JTAG_ARES			208
218 #define GCC_QDSS_ETR_USB_ARES			209
219 #define GCC_QDSS_DAP_AHB_ARES			210
220 #define GCC_QDSS_CFG_AHB_ARES			211
221 #define GCC_QDSS_EUD_AT_ARES			212
222 #define GCC_QDSS_TS_ARES			213
223 #define GCC_QDSS_USB_ARES			214
224 #define GCC_SYS_NOC_AXI_ARES			215
225 #define GCC_SNOC_QOSGEN_EXTREF_ARES		216
226 #define GCC_CNOC_LPASS_CFG_ARES			217
227 #define GCC_SYS_NOC_AT_ARES			218
228 #define GCC_SNOC_PCNOC_AHB_ARES			219
229 #define GCC_SNOC_TME_ARES			220
230 #define GCC_SNOC_XO_DCD_ARES			221
231 #define GCC_SNOC_TS_ARES			222
232 #define GCC_ANOC0_AXI_ARES			223
233 #define GCC_ANOC_PCIE0_1LANE_M_ARES		224
234 #define GCC_ANOC_PCIE2_2LANE_M_ARES		225
235 #define GCC_ANOC_PCIE1_1LANE_M_ARES		226
236 #define GCC_ANOC_PCIE3_2LANE_M_ARES		227
237 #define GCC_ANOC_PCNOC_AHB_ARES			228
238 #define GCC_ANOC_QOSGEN_EXTREF_ARES		229
239 #define GCC_ANOC_XO_DCD_ARES			230
240 #define GCC_SNOC_XO_DBG_ARES			231
241 #define GCC_AGGRNOC_ATB_ARES			232
242 #define GCC_AGGRNOC_TS_ARES			233
243 #define GCC_USB0_EUD_AT_ARES			234
244 #define GCC_PCNOC_TIC_ARES			235
245 #define GCC_PCNOC_AHB_ARES			236
246 #define GCC_PCNOC_XO_DBG_ARES			237
247 #define GCC_SNOC_LPASS_ARES			238
248 #define GCC_PCNOC_AT_ARES			239
249 #define GCC_PCNOC_XO_DCD_ARES			240
250 #define GCC_PCNOC_TS_ARES			241
251 #define GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES		242
252 #define GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES		243
253 #define GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES		244
254 #define GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES		245
255 #define GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES		246
256 #define GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES		247
257 #define GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES		248
258 #define GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES		249
259 #define GCC_Q6_AXIM_RESET			250
260 #define GCC_Q6_AXIS_RESET			251
261 #define GCC_Q6_AHB_S_RESET			252
262 #define GCC_Q6_AHB_RESET			253
263 #define GCC_Q6SS_DBG_RESET			254
264 #define GCC_WCSS_ECAHB_RESET			255
265 #define GCC_WCSS_DBG_BDG_RESET			256
266 #define GCC_WCSS_DBG_RESET			257
267 #define GCC_WCSS_AXI_M_RESET			258
268 #define GCC_WCSS_AHB_S_RESET			259
269 #define GCC_WCSS_ACMT_RESET			260
270 #define GCC_WCSSAON_RESET			261
271 #define GCC_PCIE0_PIPE_RESET			262
272 #define GCC_PCIE0_CORE_STICKY_RESET		263
273 #define GCC_PCIE0_AXI_S_STICKY_RESET		264
274 #define GCC_PCIE0_AXI_S_RESET			265
275 #define GCC_PCIE0_AXI_M_STICKY_RESET		266
276 #define GCC_PCIE0_AXI_M_RESET			267
277 #define GCC_PCIE0_AUX_RESET			268
278 #define GCC_PCIE0_AHB_RESET			269
279 #define GCC_PCIE1_PIPE_RESET			270
280 #define GCC_PCIE1_CORE_STICKY_RESET		271
281 #define GCC_PCIE1_AXI_S_STICKY_RESET		272
282 #define GCC_PCIE1_AXI_S_RESET			273
283 #define GCC_PCIE1_AXI_M_STICKY_RESET		274
284 #define GCC_PCIE1_AXI_M_RESET			275
285 #define GCC_PCIE1_AUX_RESET			276
286 #define GCC_PCIE1_AHB_RESET			277
287 #define GCC_PCIE2_PIPE_RESET			278
288 #define GCC_PCIE2_CORE_STICKY_RESET		279
289 #define GCC_PCIE2_AXI_S_STICKY_RESET		280
290 #define GCC_PCIE2_AXI_S_RESET			281
291 #define GCC_PCIE2_AXI_M_STICKY_RESET		282
292 #define GCC_PCIE2_AXI_M_RESET			283
293 #define GCC_PCIE2_AUX_RESET			284
294 #define GCC_PCIE2_AHB_RESET			285
295 #define GCC_PCIE3_PIPE_RESET			286
296 #define GCC_PCIE3_CORE_STICKY_RESET		287
297 #define GCC_PCIE3_AXI_S_STICKY_RESET		288
298 #define GCC_PCIE3_AXI_S_RESET			289
299 #define GCC_PCIE3_AXI_M_STICKY_RESET		290
300 #define GCC_PCIE3_AXI_M_RESET			291
301 #define GCC_PCIE3_AUX_RESET			292
302 #define GCC_PCIE3_AHB_RESET			293
303 #define GCC_NSS_PARTIAL_RESET			294
304 #define GCC_UNIPHY0_XPCS_ARES			295
305 #define GCC_UNIPHY1_XPCS_ARES			296
306 #define GCC_UNIPHY2_XPCS_ARES			297
307 #define GCC_USB1_BCR				298
308 #define GCC_QUSB2_1_PHY_BCR			299
309 
310 #endif
311