1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Renesas R-Car I2C unit
4 *
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
7 *
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 *
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 */
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/i2c.h>
24 #include <linux/i2c-smbus.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32
33 /* register offsets */
34 #define ICSCR 0x00 /* slave ctrl */
35 #define ICMCR 0x04 /* master ctrl */
36 #define ICSSR 0x08 /* slave status */
37 #define ICMSR 0x0C /* master status */
38 #define ICSIER 0x10 /* slave irq enable */
39 #define ICMIER 0x14 /* master irq enable */
40 #define ICCCR 0x18 /* clock dividers */
41 #define ICSAR 0x1C /* slave address */
42 #define ICMAR 0x20 /* master address */
43 #define ICRXTX 0x24 /* data port */
44 #define ICCCR2 0x28 /* Clock control 2 */
45 #define ICMPR 0x2C /* SCL mask control */
46 #define ICHPR 0x30 /* SCL HIGH control */
47 #define ICLPR 0x34 /* SCL LOW control */
48 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
49 #define ICDMAER 0x3c /* DMA enable (Gen3) */
50
51 /* ICSCR */
52 #define SDBS BIT(3) /* slave data buffer select */
53 #define SIE BIT(2) /* slave interface enable */
54 #define GCAE BIT(1) /* general call address enable */
55 #define FNA BIT(0) /* forced non acknowledgment */
56
57 /* ICMCR */
58 #define MDBS BIT(7) /* non-fifo mode switch */
59 #define FSCL BIT(6) /* override SCL pin */
60 #define FSDA BIT(5) /* override SDA pin */
61 #define OBPC BIT(4) /* override pins */
62 #define MIE BIT(3) /* master if enable */
63 #define TSBE BIT(2)
64 #define FSB BIT(1) /* force stop bit */
65 #define ESG BIT(0) /* enable start bit gen */
66
67 /* ICSSR (also for ICSIER) */
68 #define GCAR BIT(6) /* general call received */
69 #define STM BIT(5) /* slave transmit mode */
70 #define SSR BIT(4) /* stop received */
71 #define SDE BIT(3) /* slave data empty */
72 #define SDT BIT(2) /* slave data transmitted */
73 #define SDR BIT(1) /* slave data received */
74 #define SAR BIT(0) /* slave addr received */
75
76 /* ICMSR (also for ICMIE) */
77 #define MNR BIT(6) /* nack received */
78 #define MAL BIT(5) /* arbitration lost */
79 #define MST BIT(4) /* sent a stop */
80 #define MDE BIT(3)
81 #define MDT BIT(2)
82 #define MDR BIT(1)
83 #define MAT BIT(0) /* slave addr xfer done */
84
85 /* ICDMAER */
86 #define RSDMAE BIT(3) /* DMA Slave Received Enable */
87 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */
88 #define RMDMAE BIT(1) /* DMA Master Received Enable */
89 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */
90
91 /* ICCCR2 */
92 #define FMPE BIT(7) /* Fast Mode Plus Enable */
93 #define CDFD BIT(2) /* CDF Disable */
94 #define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */
95 #define SME BIT(0) /* SCL Mask Enable */
96
97 /* ICFBSCR */
98 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
99
100 #define RCAR_MIN_DMA_LEN 8
101
102 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */
103 #define RCAR_SCLD_RATIO 5
104 #define RCAR_SCHD_RATIO 4
105 /*
106 * SMD should be smaller than SCLD/SCHD and is always around 20 in the docs.
107 * Thus, we simply use 20 which works for low and high speeds.
108 */
109 #define RCAR_DEFAULT_SMD 20
110
111 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
112 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
113 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
114
115 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
116 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
117 #define RCAR_IRQ_STOP (MST)
118
119 #define ID_LAST_MSG BIT(0)
120 #define ID_REP_AFTER_RD BIT(1)
121 #define ID_DONE BIT(2)
122 #define ID_ARBLOST BIT(3)
123 #define ID_NACK BIT(4)
124 #define ID_EPROTO BIT(5)
125 /* persistent flags */
126 #define ID_P_FMPLUS BIT(27)
127 #define ID_P_NOT_ATOMIC BIT(28)
128 #define ID_P_HOST_NOTIFY BIT(29)
129 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */
130 #define ID_P_PM_BLOCKED BIT(31)
131 #define ID_P_MASK GENMASK(31, 27)
132
133 #define ID_SLAVE_NACK BIT(0)
134
135 enum rcar_i2c_type {
136 I2C_RCAR_GEN1,
137 I2C_RCAR_GEN2,
138 I2C_RCAR_GEN3,
139 I2C_RCAR_GEN4,
140 };
141
142 struct rcar_i2c_priv {
143 u32 flags;
144 void __iomem *io;
145 struct i2c_adapter adap;
146 struct i2c_msg *msg;
147 int msgs_left;
148 struct clk *clk;
149
150 wait_queue_head_t wait;
151
152 int pos;
153 u32 icccr;
154 u16 schd;
155 u16 scld;
156 u8 smd;
157 u8 recovery_icmcr; /* protected by adapter lock */
158 enum rcar_i2c_type devtype;
159 struct i2c_client *slave;
160
161 struct resource *res;
162 struct dma_chan *dma_tx;
163 struct dma_chan *dma_rx;
164 struct scatterlist sg;
165 enum dma_data_direction dma_direction;
166
167 struct reset_control *rstc;
168 int irq;
169
170 struct i2c_client *host_notify_client;
171 u8 slave_flags;
172 };
173
174 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
175 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
176
rcar_i2c_write(struct rcar_i2c_priv * priv,int reg,u32 val)177 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
178 {
179 writel(val, priv->io + reg);
180 }
181
rcar_i2c_read(struct rcar_i2c_priv * priv,int reg)182 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
183 {
184 return readl(priv->io + reg);
185 }
186
rcar_i2c_clear_irq(struct rcar_i2c_priv * priv,u32 val)187 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val)
188 {
189 writel(~val & 0x7f, priv->io + ICMSR);
190 }
191
rcar_i2c_get_scl(struct i2c_adapter * adap)192 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
193 {
194 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
195
196 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
197 }
198
rcar_i2c_set_scl(struct i2c_adapter * adap,int val)199 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
200 {
201 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
202
203 if (val)
204 priv->recovery_icmcr |= FSCL;
205 else
206 priv->recovery_icmcr &= ~FSCL;
207
208 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
209 }
210
rcar_i2c_set_sda(struct i2c_adapter * adap,int val)211 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
212 {
213 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
214
215 if (val)
216 priv->recovery_icmcr |= FSDA;
217 else
218 priv->recovery_icmcr &= ~FSDA;
219
220 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
221 }
222
rcar_i2c_get_bus_free(struct i2c_adapter * adap)223 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
224 {
225 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
226
227 return !(rcar_i2c_read(priv, ICMCR) & FSDA);
228 }
229
230 static struct i2c_bus_recovery_info rcar_i2c_bri = {
231 .get_scl = rcar_i2c_get_scl,
232 .set_scl = rcar_i2c_set_scl,
233 .set_sda = rcar_i2c_set_sda,
234 .get_bus_free = rcar_i2c_get_bus_free,
235 .recover_bus = i2c_generic_scl_recovery,
236 };
237
rcar_i2c_init(struct rcar_i2c_priv * priv)238 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
239 {
240 /* reset master mode */
241 rcar_i2c_write(priv, ICMIER, 0);
242 rcar_i2c_write(priv, ICMCR, MDBS);
243 rcar_i2c_write(priv, ICMSR, 0);
244 /* start clock */
245 if (priv->devtype < I2C_RCAR_GEN3) {
246 rcar_i2c_write(priv, ICCCR, priv->icccr);
247 } else {
248 u32 icccr2 = CDFD | HLSE | SME;
249
250 if (priv->flags & ID_P_FMPLUS)
251 icccr2 |= FMPE;
252
253 rcar_i2c_write(priv, ICCCR2, icccr2);
254 rcar_i2c_write(priv, ICCCR, priv->icccr);
255 rcar_i2c_write(priv, ICMPR, priv->smd);
256 rcar_i2c_write(priv, ICHPR, priv->schd);
257 rcar_i2c_write(priv, ICLPR, priv->scld);
258 rcar_i2c_write(priv, ICFBSCR, TCYC17);
259 }
260 }
261
rcar_i2c_reset_slave(struct rcar_i2c_priv * priv)262 static void rcar_i2c_reset_slave(struct rcar_i2c_priv *priv)
263 {
264 rcar_i2c_write(priv, ICSIER, 0);
265 rcar_i2c_write(priv, ICSSR, 0);
266 rcar_i2c_write(priv, ICSCR, SDBS);
267 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
268 }
269
rcar_i2c_bus_barrier(struct rcar_i2c_priv * priv)270 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
271 {
272 int ret;
273 u32 val;
274
275 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
276 priv->adap.timeout);
277 if (ret) {
278 /* Waiting did not help, try to recover */
279 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
280 ret = i2c_recover_bus(&priv->adap);
281 }
282
283 return ret;
284 }
285
rcar_i2c_clock_calculate(struct rcar_i2c_priv * priv)286 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
287 {
288 u32 cdf, round, ick, sum, scl, cdf_width;
289 unsigned long rate;
290 struct device *dev = rcar_i2c_priv_to_dev(priv);
291 struct i2c_timings t = {
292 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ,
293 .scl_fall_ns = 35,
294 .scl_rise_ns = 200,
295 .scl_int_delay_ns = 50,
296 };
297
298 /* Fall back to previously used values if not supplied */
299 i2c_parse_fw_timings(dev, &t, false);
300 priv->smd = RCAR_DEFAULT_SMD;
301
302 /*
303 * calculate SCL clock
304 * see
305 * ICCCR (and ICCCR2 for Gen3+)
306 *
307 * ick = clkp / (1 + CDF)
308 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
309 *
310 * for Gen3+:
311 * SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp])
312 *
313 * ick : I2C internal clock < 20 MHz
314 * ticf : I2C SCL falling time
315 * tr : I2C SCL rising time
316 * intd : LSI internal delay
317 * clkp : peripheral_clk
318 * F[] : integer up-valuation
319 */
320 rate = clk_get_rate(priv->clk);
321 cdf = rate / 20000000;
322 cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3;
323 if (cdf >= 1U << cdf_width)
324 goto err_no_val;
325
326 if (t.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ && priv->devtype >= I2C_RCAR_GEN4)
327 priv->flags |= ID_P_FMPLUS;
328 else
329 priv->flags &= ~ID_P_FMPLUS;
330
331 /* On Gen3+, we use cdf only for the filters, not as a SCL divider */
332 ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1);
333
334 /*
335 * It is impossible to calculate a large scale number on u32. Separate it.
336 *
337 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
338 * = F[sum * ick / 1000000000]
339 * = F[(ick / 1000000) * sum / 1000]
340 */
341 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
342 round = DIV_ROUND_CLOSEST(ick, 1000000);
343 round = DIV_ROUND_CLOSEST(round * sum, 1000);
344
345 if (priv->devtype < I2C_RCAR_GEN3) {
346 u32 scgd;
347 /*
348 * SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick])
349 * 20 + 8 * SCGD + F[...] = ick / SCL
350 * SCGD = ((ick / SCL) - 20 - F[...]) / 8
351 * Result (= SCL) should be less than bus_speed for hardware safety
352 */
353 scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1);
354 scgd = DIV_ROUND_UP(scgd - 20 - round, 8);
355 scl = ick / (20 + 8 * scgd + round);
356
357 if (scgd > 0x3f)
358 goto err_no_val;
359
360 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n",
361 scl, t.bus_freq_hz, rate, round, cdf, scgd);
362
363 priv->icccr = scgd << cdf_width | cdf;
364 } else {
365 u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO;
366 /*
367 * SCLD/SCHD ratio and SMD default value are explained above
368 * where they are defined. With these definitions, we can compute
369 * x as a base value for the SCLD/SCHD ratio:
370 *
371 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp])
372 * SCL = clkp / (8 + 2 * SMD + RCAR_SCLD_RATIO * x
373 * + RCAR_SCHD_RATIO * x + F[...])
374 *
375 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO
376 *
377 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...])
378 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL
379 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio
380 */
381 x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1);
382 x = DIV_ROUND_UP(x - 8 - 2 * priv->smd - round, sum_ratio);
383 scl = rate / (8 + 2 * priv->smd + sum_ratio * x + round);
384
385 if (x == 0 || x * RCAR_SCLD_RATIO > 0xffff)
386 goto err_no_val;
387
388 priv->icccr = cdf;
389 priv->schd = RCAR_SCHD_RATIO * x;
390 priv->scld = RCAR_SCLD_RATIO * x;
391 if (priv->smd >= priv->schd)
392 priv->smd = priv->schd - 1;
393
394 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u SMD %u\n",
395 scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld, priv->smd);
396 }
397
398 return 0;
399
400 err_no_val:
401 dev_err(dev, "it is impossible to calculate best SCL\n");
402 return -EINVAL;
403 }
404
405 /*
406 * We don't have a test case but the HW engineers say that the write order of
407 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR
408 * handling is outside of this function. First messages clear ICMSR before this
409 * function, interrupt handlers clear the relevant bits after this function.
410 */
rcar_i2c_prepare_msg(struct rcar_i2c_priv * priv)411 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
412 {
413 int read = !!rcar_i2c_is_recv(priv);
414 bool rep_start = !(priv->flags & ID_REP_AFTER_RD);
415
416 priv->pos = 0;
417 priv->flags &= ID_P_MASK;
418
419 if (priv->msgs_left == 1)
420 priv->flags |= ID_LAST_MSG;
421
422 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
423 if (priv->flags & ID_P_NOT_ATOMIC)
424 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
425
426 if (rep_start)
427 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
428 }
429
rcar_i2c_first_msg(struct rcar_i2c_priv * priv,struct i2c_msg * msgs,int num)430 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv,
431 struct i2c_msg *msgs, int num)
432 {
433 priv->msg = msgs;
434 priv->msgs_left = num;
435 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */
436 rcar_i2c_prepare_msg(priv);
437 }
438
rcar_i2c_next_msg(struct rcar_i2c_priv * priv)439 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
440 {
441 priv->msg++;
442 priv->msgs_left--;
443 rcar_i2c_prepare_msg(priv);
444 /* ICMSR handling must come afterwards in the irq handler */
445 }
446
rcar_i2c_cleanup_dma(struct rcar_i2c_priv * priv,bool terminate)447 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)
448 {
449 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
450 ? priv->dma_rx : priv->dma_tx;
451
452 /* only allowed from thread context! */
453 if (terminate)
454 dmaengine_terminate_sync(chan);
455
456 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
457 sg_dma_len(&priv->sg), priv->dma_direction);
458
459 /* Gen3+ can only do one RXDMA per transfer and we just completed it */
460 if (priv->devtype >= I2C_RCAR_GEN3 &&
461 priv->dma_direction == DMA_FROM_DEVICE)
462 priv->flags |= ID_P_NO_RXDMA;
463
464 priv->dma_direction = DMA_NONE;
465
466 /* Disable DMA Master Received/Transmitted, must be last! */
467 rcar_i2c_write(priv, ICDMAER, 0);
468 }
469
rcar_i2c_dma_callback(void * data)470 static void rcar_i2c_dma_callback(void *data)
471 {
472 struct rcar_i2c_priv *priv = data;
473
474 priv->pos += sg_dma_len(&priv->sg);
475
476 rcar_i2c_cleanup_dma(priv, false);
477 }
478
rcar_i2c_dma(struct rcar_i2c_priv * priv)479 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
480 {
481 struct device *dev = rcar_i2c_priv_to_dev(priv);
482 struct i2c_msg *msg = priv->msg;
483 bool read = msg->flags & I2C_M_RD;
484 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
485 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
486 struct dma_async_tx_descriptor *txdesc;
487 dma_addr_t dma_addr;
488 dma_cookie_t cookie;
489 unsigned char *buf;
490 int len;
491
492 /* Do various checks to see if DMA is feasible at all */
493 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
494 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
495 return false;
496
497 if (read) {
498 /*
499 * The last two bytes needs to be fetched using PIO in
500 * order for the STOP phase to work.
501 */
502 buf = priv->msg->buf;
503 len = priv->msg->len - 2;
504 } else {
505 /*
506 * First byte in message was sent using PIO.
507 */
508 buf = priv->msg->buf + 1;
509 len = priv->msg->len - 1;
510 }
511
512 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
513 if (dma_mapping_error(chan->device->dev, dma_addr)) {
514 dev_dbg(dev, "dma map failed, using PIO\n");
515 return false;
516 }
517
518 sg_dma_len(&priv->sg) = len;
519 sg_dma_address(&priv->sg) = dma_addr;
520
521 priv->dma_direction = dir;
522
523 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
524 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
525 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
526 if (!txdesc) {
527 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
528 rcar_i2c_cleanup_dma(priv, false);
529 return false;
530 }
531
532 txdesc->callback = rcar_i2c_dma_callback;
533 txdesc->callback_param = priv;
534
535 cookie = dmaengine_submit(txdesc);
536 if (dma_submit_error(cookie)) {
537 dev_dbg(dev, "submitting dma failed, using PIO\n");
538 rcar_i2c_cleanup_dma(priv, false);
539 return false;
540 }
541
542 /* Enable DMA Master Received/Transmitted */
543 if (read)
544 rcar_i2c_write(priv, ICDMAER, RMDMAE);
545 else
546 rcar_i2c_write(priv, ICDMAER, TMDMAE);
547
548 dma_async_issue_pending(chan);
549 return true;
550 }
551
rcar_i2c_irq_send(struct rcar_i2c_priv * priv,u32 msr)552 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
553 {
554 struct i2c_msg *msg = priv->msg;
555 u32 irqs_to_clear = MDE;
556
557 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
558 if (WARN(!(msr & MDE), "spurious irq"))
559 return;
560
561 if (msr & MAT)
562 irqs_to_clear |= MAT;
563
564 /* Check if DMA can be enabled and take over */
565 if (priv->pos == 1 && rcar_i2c_dma(priv))
566 return;
567
568 if (priv->pos < msg->len) {
569 /*
570 * Prepare next data to ICRXTX register.
571 * This data will go to _SHIFT_ register.
572 *
573 * *
574 * [ICRXTX] -> [SHIFT] -> [I2C bus]
575 */
576 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
577 priv->pos++;
578 } else {
579 /*
580 * The last data was pushed to ICRXTX on _PREV_ empty irq.
581 * It is on _SHIFT_ register, and will sent to I2C bus.
582 *
583 * *
584 * [ICRXTX] -> [SHIFT] -> [I2C bus]
585 */
586
587 if (priv->flags & ID_LAST_MSG)
588 /*
589 * If current msg is the _LAST_ msg,
590 * prepare stop condition here.
591 * ID_DONE will be set on STOP irq.
592 */
593 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
594 else
595 rcar_i2c_next_msg(priv);
596 }
597
598 rcar_i2c_clear_irq(priv, irqs_to_clear);
599 }
600
rcar_i2c_irq_recv(struct rcar_i2c_priv * priv,u32 msr)601 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
602 {
603 struct i2c_msg *msg = priv->msg;
604 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN;
605 u32 irqs_to_clear = MDR;
606
607 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
608 if (!(msr & MDR))
609 return;
610
611 if (msr & MAT) {
612 irqs_to_clear |= MAT;
613 /*
614 * Address transfer phase finished, but no data at this point.
615 * Try to use DMA to receive data.
616 */
617 rcar_i2c_dma(priv);
618 } else if (priv->pos < msg->len) {
619 /* get received data */
620 u8 data = rcar_i2c_read(priv, ICRXTX);
621
622 msg->buf[priv->pos] = data;
623 if (recv_len_init) {
624 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) {
625 priv->flags |= ID_DONE | ID_EPROTO;
626 return;
627 }
628 msg->len += msg->buf[0];
629 /* Enough data for DMA? */
630 if (rcar_i2c_dma(priv))
631 return;
632 /* new length after RECV_LEN now properly initialized */
633 recv_len_init = false;
634 }
635 priv->pos++;
636 }
637
638 /*
639 * If next received data is the _LAST_ and we are not waiting for a new
640 * length because of RECV_LEN, then go to a new phase.
641 */
642 if (priv->pos + 1 == msg->len && !recv_len_init) {
643 if (priv->flags & ID_LAST_MSG) {
644 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
645 } else {
646 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
647 priv->flags |= ID_REP_AFTER_RD;
648 }
649 }
650
651 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
652 rcar_i2c_next_msg(priv);
653
654 rcar_i2c_clear_irq(priv, irqs_to_clear);
655 }
656
rcar_i2c_slave_irq(struct rcar_i2c_priv * priv)657 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
658 {
659 u32 ssr_raw, ssr_filtered;
660 u8 value;
661 int ret;
662
663 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
664 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
665
666 if (!ssr_filtered)
667 return false;
668
669 /* address detected */
670 if (ssr_filtered & SAR) {
671 /* read or write request */
672 if (ssr_raw & STM) {
673 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
674 rcar_i2c_write(priv, ICRXTX, value);
675 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
676 } else {
677 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
678 if (ret)
679 priv->slave_flags |= ID_SLAVE_NACK;
680
681 rcar_i2c_read(priv, ICRXTX); /* dummy read */
682 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
683 }
684
685 /* Clear SSR, too, because of old STOPs to other clients than us */
686 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
687 }
688
689 /* master sent stop */
690 if (ssr_filtered & SSR) {
691 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
692 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
693 priv->slave_flags &= ~ID_SLAVE_NACK;
694 rcar_i2c_write(priv, ICSIER, SAR);
695 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
696 }
697
698 /* master wants to write to us */
699 if (ssr_filtered & SDR) {
700 value = rcar_i2c_read(priv, ICRXTX);
701 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
702 if (ret)
703 priv->slave_flags |= ID_SLAVE_NACK;
704
705 /* Send NACK in case of error, but it will come 1 byte late :( */
706 rcar_i2c_write(priv, ICSCR, SIE | SDBS |
707 (priv->slave_flags & ID_SLAVE_NACK ? FNA : 0));
708 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
709 }
710
711 /* master wants to read from us */
712 if (ssr_filtered & SDE) {
713 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
714 rcar_i2c_write(priv, ICRXTX, value);
715 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
716 }
717
718 return true;
719 }
720
721 /*
722 * This driver has a lock-free design because there are IP cores (at least
723 * R-Car Gen2) which have an inherent race condition in their hardware design.
724 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
725 * the interrupt was generated, otherwise an unwanted repeated message gets
726 * generated. It turned out that taking a spinlock at the beginning of the ISR
727 * was already causing repeated messages. Thus, this driver was converted to
728 * the now lockless behaviour. Please keep this in mind when hacking the driver.
729 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
730 * likely affected. Therefore, we have different interrupt handler entries.
731 */
rcar_i2c_irq(int irq,struct rcar_i2c_priv * priv,u32 msr)732 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
733 {
734 if (!msr) {
735 if (rcar_i2c_slave_irq(priv))
736 return IRQ_HANDLED;
737
738 return IRQ_NONE;
739 }
740
741 /* Arbitration lost */
742 if (msr & MAL) {
743 priv->flags |= ID_DONE | ID_ARBLOST;
744 goto out;
745 }
746
747 /* Nack */
748 if (msr & MNR) {
749 /* HW automatically sends STOP after received NACK */
750 if (priv->flags & ID_P_NOT_ATOMIC)
751 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
752 priv->flags |= ID_NACK;
753 goto out;
754 }
755
756 /* Stop */
757 if (msr & MST) {
758 priv->msgs_left--; /* The last message also made it */
759 priv->flags |= ID_DONE;
760 goto out;
761 }
762
763 if (rcar_i2c_is_recv(priv))
764 rcar_i2c_irq_recv(priv, msr);
765 else
766 rcar_i2c_irq_send(priv, msr);
767
768 out:
769 if (priv->flags & ID_DONE) {
770 rcar_i2c_write(priv, ICMIER, 0);
771 rcar_i2c_write(priv, ICMSR, 0);
772 if (priv->flags & ID_P_NOT_ATOMIC)
773 wake_up(&priv->wait);
774 }
775
776 return IRQ_HANDLED;
777 }
778
rcar_i2c_gen2_irq(int irq,void * ptr)779 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
780 {
781 struct rcar_i2c_priv *priv = ptr;
782 u32 msr;
783
784 /* Clear START or STOP immediately, except for REPSTART after read */
785 if (likely(!(priv->flags & ID_REP_AFTER_RD)))
786 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
787
788 /* Only handle interrupts that are currently enabled */
789 msr = rcar_i2c_read(priv, ICMSR);
790 if (priv->flags & ID_P_NOT_ATOMIC)
791 msr &= rcar_i2c_read(priv, ICMIER);
792
793 return rcar_i2c_irq(irq, priv, msr);
794 }
795
rcar_i2c_gen3_irq(int irq,void * ptr)796 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
797 {
798 struct rcar_i2c_priv *priv = ptr;
799 u32 msr;
800
801 /* Only handle interrupts that are currently enabled */
802 msr = rcar_i2c_read(priv, ICMSR);
803 if (priv->flags & ID_P_NOT_ATOMIC)
804 msr &= rcar_i2c_read(priv, ICMIER);
805
806 /*
807 * Clear START or STOP immediately, except for REPSTART after read or
808 * if a spurious interrupt was detected.
809 */
810 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr))
811 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
812
813 return rcar_i2c_irq(irq, priv, msr);
814 }
815
rcar_i2c_request_dma_chan(struct device * dev,enum dma_transfer_direction dir,dma_addr_t port_addr)816 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
817 enum dma_transfer_direction dir,
818 dma_addr_t port_addr)
819 {
820 struct dma_chan *chan;
821 struct dma_slave_config cfg;
822 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
823 int ret;
824
825 chan = dma_request_chan(dev, chan_name);
826 if (IS_ERR(chan)) {
827 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
828 chan_name, PTR_ERR(chan));
829 return chan;
830 }
831
832 memset(&cfg, 0, sizeof(cfg));
833 cfg.direction = dir;
834 if (dir == DMA_MEM_TO_DEV) {
835 cfg.dst_addr = port_addr;
836 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
837 } else {
838 cfg.src_addr = port_addr;
839 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
840 }
841
842 ret = dmaengine_slave_config(chan, &cfg);
843 if (ret) {
844 dev_dbg(dev, "slave_config failed for %s (%d)\n",
845 chan_name, ret);
846 dma_release_channel(chan);
847 return ERR_PTR(ret);
848 }
849
850 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
851 return chan;
852 }
853
rcar_i2c_request_dma(struct rcar_i2c_priv * priv,struct i2c_msg * msg)854 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
855 struct i2c_msg *msg)
856 {
857 struct device *dev = rcar_i2c_priv_to_dev(priv);
858 bool read;
859 struct dma_chan *chan;
860 enum dma_transfer_direction dir;
861
862 read = msg->flags & I2C_M_RD;
863
864 chan = read ? priv->dma_rx : priv->dma_tx;
865 if (PTR_ERR(chan) != -EPROBE_DEFER)
866 return;
867
868 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
869 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
870
871 if (read)
872 priv->dma_rx = chan;
873 else
874 priv->dma_tx = chan;
875 }
876
rcar_i2c_release_dma(struct rcar_i2c_priv * priv)877 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
878 {
879 if (!IS_ERR(priv->dma_tx)) {
880 dma_release_channel(priv->dma_tx);
881 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
882 }
883
884 if (!IS_ERR(priv->dma_rx)) {
885 dma_release_channel(priv->dma_rx);
886 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
887 }
888 }
889
890 /* I2C is a special case, we need to poll the status of a reset */
rcar_i2c_do_reset(struct rcar_i2c_priv * priv)891 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
892 {
893 int ret;
894
895 /* Don't reset if a slave instance is currently running */
896 if (priv->slave)
897 return -EISCONN;
898
899 ret = reset_control_reset(priv->rstc);
900 if (ret)
901 return ret;
902
903 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
904 100, false, priv->rstc);
905 }
906
rcar_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)907 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
908 struct i2c_msg *msgs,
909 int num)
910 {
911 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
912 struct device *dev = rcar_i2c_priv_to_dev(priv);
913 int i, ret;
914 long time_left;
915
916 priv->flags |= ID_P_NOT_ATOMIC;
917
918 pm_runtime_get_sync(dev);
919
920 /* Check bus state before init otherwise bus busy info will be lost */
921 ret = rcar_i2c_bus_barrier(priv);
922 if (ret < 0)
923 goto out;
924
925 /* Gen3+ needs a reset. That also allows RXDMA once */
926 if (priv->devtype >= I2C_RCAR_GEN3) {
927 ret = rcar_i2c_do_reset(priv);
928 if (ret)
929 goto out;
930 priv->flags &= ~ID_P_NO_RXDMA;
931 }
932
933 rcar_i2c_init(priv);
934
935 for (i = 0; i < num; i++)
936 rcar_i2c_request_dma(priv, msgs + i);
937
938 rcar_i2c_first_msg(priv, msgs, num);
939
940 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
941 num * adap->timeout);
942
943 /* cleanup DMA if it couldn't complete properly due to an error */
944 if (priv->dma_direction != DMA_NONE)
945 rcar_i2c_cleanup_dma(priv, true);
946
947 if (!time_left) {
948 rcar_i2c_init(priv);
949 ret = -ETIMEDOUT;
950 } else if (priv->flags & ID_NACK) {
951 ret = -ENXIO;
952 } else if (priv->flags & ID_ARBLOST) {
953 ret = -EAGAIN;
954 } else if (priv->flags & ID_EPROTO) {
955 ret = -EPROTO;
956 } else {
957 ret = num - priv->msgs_left; /* The number of transfer */
958 }
959 out:
960 pm_runtime_put(dev);
961
962 if (ret < 0 && ret != -ENXIO)
963 dev_err(dev, "error %d : %x\n", ret, priv->flags);
964
965 return ret;
966 }
967
rcar_i2c_master_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)968 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap,
969 struct i2c_msg *msgs,
970 int num)
971 {
972 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
973 struct device *dev = rcar_i2c_priv_to_dev(priv);
974 unsigned long j;
975 bool time_left;
976 int ret;
977
978 priv->flags &= ~ID_P_NOT_ATOMIC;
979
980 pm_runtime_get_sync(dev);
981
982 /* Check bus state before init otherwise bus busy info will be lost */
983 ret = rcar_i2c_bus_barrier(priv);
984 if (ret < 0)
985 goto out;
986
987 rcar_i2c_init(priv);
988 rcar_i2c_first_msg(priv, msgs, num);
989
990 j = jiffies + num * adap->timeout;
991 do {
992 u32 msr = rcar_i2c_read(priv, ICMSR);
993
994 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP;
995
996 if (msr) {
997 if (priv->devtype < I2C_RCAR_GEN3)
998 rcar_i2c_gen2_irq(0, priv);
999 else
1000 rcar_i2c_gen3_irq(0, priv);
1001 }
1002
1003 time_left = time_before_eq(jiffies, j);
1004 } while (!(priv->flags & ID_DONE) && time_left);
1005
1006 if (!time_left) {
1007 rcar_i2c_init(priv);
1008 ret = -ETIMEDOUT;
1009 } else if (priv->flags & ID_NACK) {
1010 ret = -ENXIO;
1011 } else if (priv->flags & ID_ARBLOST) {
1012 ret = -EAGAIN;
1013 } else if (priv->flags & ID_EPROTO) {
1014 ret = -EPROTO;
1015 } else {
1016 ret = num - priv->msgs_left; /* The number of transfer */
1017 }
1018 out:
1019 pm_runtime_put(dev);
1020
1021 if (ret < 0 && ret != -ENXIO)
1022 dev_err(dev, "error %d : %x\n", ret, priv->flags);
1023
1024 return ret;
1025 }
1026
rcar_reg_slave(struct i2c_client * slave)1027 static int rcar_reg_slave(struct i2c_client *slave)
1028 {
1029 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
1030
1031 if (priv->slave)
1032 return -EBUSY;
1033
1034 if (slave->flags & I2C_CLIENT_TEN)
1035 return -EAFNOSUPPORT;
1036
1037 /* Keep device active for slave address detection logic */
1038 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
1039
1040 priv->slave = slave;
1041 rcar_i2c_write(priv, ICSAR, slave->addr);
1042 rcar_i2c_write(priv, ICSSR, 0);
1043 rcar_i2c_write(priv, ICSIER, SAR);
1044 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
1045
1046 return 0;
1047 }
1048
rcar_unreg_slave(struct i2c_client * slave)1049 static int rcar_unreg_slave(struct i2c_client *slave)
1050 {
1051 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
1052
1053 WARN_ON(!priv->slave);
1054
1055 /* ensure no irq is running before clearing ptr */
1056 disable_irq(priv->irq);
1057 rcar_i2c_reset_slave(priv);
1058 enable_irq(priv->irq);
1059
1060 priv->slave = NULL;
1061
1062 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
1063
1064 return 0;
1065 }
1066
rcar_i2c_func(struct i2c_adapter * adap)1067 static u32 rcar_i2c_func(struct i2c_adapter *adap)
1068 {
1069 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
1070
1071 /*
1072 * This HW can't do:
1073 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
1074 * I2C_M_NOSTART (automatically sends address after START)
1075 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
1076 */
1077 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
1078 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1079
1080 if (priv->flags & ID_P_HOST_NOTIFY)
1081 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
1082
1083 return func;
1084 }
1085
1086 static const struct i2c_algorithm rcar_i2c_algo = {
1087 .master_xfer = rcar_i2c_master_xfer,
1088 .master_xfer_atomic = rcar_i2c_master_xfer_atomic,
1089 .functionality = rcar_i2c_func,
1090 .reg_slave = rcar_reg_slave,
1091 .unreg_slave = rcar_unreg_slave,
1092 };
1093
1094 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
1095 .flags = I2C_AQ_NO_ZERO_LEN,
1096 };
1097
1098 static const struct of_device_id rcar_i2c_dt_ids[] = {
1099 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
1100 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
1101 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
1102 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
1103 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
1104 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
1105 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
1106 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
1107 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
1108 /* S4 has no FM+ bit */
1109 { .compatible = "renesas,i2c-r8a779f0", .data = (void *)I2C_RCAR_GEN3 },
1110 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
1111 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
1112 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
1113 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 },
1114 {},
1115 };
1116 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
1117
rcar_i2c_probe(struct platform_device * pdev)1118 static int rcar_i2c_probe(struct platform_device *pdev)
1119 {
1120 struct rcar_i2c_priv *priv;
1121 struct i2c_adapter *adap;
1122 struct device *dev = &pdev->dev;
1123 unsigned long irqflags = 0;
1124 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
1125 int ret;
1126
1127 /* Otherwise logic will break because some bytes must always use PIO */
1128 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
1129
1130 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
1131 if (!priv)
1132 return -ENOMEM;
1133
1134 priv->clk = devm_clk_get(dev, NULL);
1135 if (IS_ERR(priv->clk)) {
1136 dev_err(dev, "cannot get clock\n");
1137 return PTR_ERR(priv->clk);
1138 }
1139
1140 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
1141 if (IS_ERR(priv->io))
1142 return PTR_ERR(priv->io);
1143
1144 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
1145 init_waitqueue_head(&priv->wait);
1146
1147 adap = &priv->adap;
1148 adap->nr = pdev->id;
1149 adap->algo = &rcar_i2c_algo;
1150 adap->class = I2C_CLASS_DEPRECATED;
1151 adap->retries = 3;
1152 adap->dev.parent = dev;
1153 adap->dev.of_node = dev->of_node;
1154 adap->bus_recovery_info = &rcar_i2c_bri;
1155 adap->quirks = &rcar_i2c_quirks;
1156 i2c_set_adapdata(adap, priv);
1157 strscpy(adap->name, pdev->name, sizeof(adap->name));
1158
1159 /* Init DMA */
1160 sg_init_table(&priv->sg, 1);
1161 priv->dma_direction = DMA_NONE;
1162 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
1163
1164 /* Activate device for clock calculation */
1165 pm_runtime_enable(dev);
1166 pm_runtime_get_sync(dev);
1167 ret = rcar_i2c_clock_calculate(priv);
1168 if (ret < 0) {
1169 pm_runtime_put(dev);
1170 goto out_pm_disable;
1171 }
1172
1173 /* Bring hardware to known state */
1174 rcar_i2c_init(priv);
1175 rcar_i2c_reset_slave(priv);
1176
1177 /* Stay always active when multi-master to keep arbitration working */
1178 if (of_property_read_bool(dev->of_node, "multi-master"))
1179 priv->flags |= ID_P_PM_BLOCKED;
1180 else
1181 pm_runtime_put(dev);
1182
1183 if (of_property_read_bool(dev->of_node, "smbus"))
1184 priv->flags |= ID_P_HOST_NOTIFY;
1185
1186 if (priv->devtype < I2C_RCAR_GEN3) {
1187 irqflags |= IRQF_NO_THREAD;
1188 irqhandler = rcar_i2c_gen2_irq;
1189 } else {
1190 /* R-Car Gen3+ needs a reset before every transfer */
1191 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1192 if (IS_ERR(priv->rstc)) {
1193 ret = PTR_ERR(priv->rstc);
1194 goto out_pm_put;
1195 }
1196
1197 ret = reset_control_status(priv->rstc);
1198 if (ret < 0)
1199 goto out_pm_put;
1200
1201 /* hard reset disturbs HostNotify local target, so disable it */
1202 priv->flags &= ~ID_P_HOST_NOTIFY;
1203 }
1204
1205 ret = platform_get_irq(pdev, 0);
1206 if (ret < 0)
1207 goto out_pm_put;
1208 priv->irq = ret;
1209 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
1210 if (ret < 0) {
1211 dev_err(dev, "cannot get irq %d\n", priv->irq);
1212 goto out_pm_put;
1213 }
1214
1215 platform_set_drvdata(pdev, priv);
1216
1217 ret = i2c_add_numbered_adapter(adap);
1218 if (ret < 0)
1219 goto out_pm_put;
1220
1221 if (priv->flags & ID_P_HOST_NOTIFY) {
1222 priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
1223 if (IS_ERR(priv->host_notify_client)) {
1224 ret = PTR_ERR(priv->host_notify_client);
1225 goto out_del_device;
1226 }
1227 }
1228
1229 dev_info(dev, "probed\n");
1230
1231 return 0;
1232
1233 out_del_device:
1234 i2c_del_adapter(&priv->adap);
1235 out_pm_put:
1236 if (priv->flags & ID_P_PM_BLOCKED)
1237 pm_runtime_put(dev);
1238 out_pm_disable:
1239 pm_runtime_disable(dev);
1240 return ret;
1241 }
1242
rcar_i2c_remove(struct platform_device * pdev)1243 static void rcar_i2c_remove(struct platform_device *pdev)
1244 {
1245 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1246 struct device *dev = &pdev->dev;
1247
1248 if (priv->host_notify_client)
1249 i2c_free_slave_host_notify_device(priv->host_notify_client);
1250 i2c_del_adapter(&priv->adap);
1251 rcar_i2c_release_dma(priv);
1252 if (priv->flags & ID_P_PM_BLOCKED)
1253 pm_runtime_put(dev);
1254 pm_runtime_disable(dev);
1255 }
1256
rcar_i2c_suspend(struct device * dev)1257 static int rcar_i2c_suspend(struct device *dev)
1258 {
1259 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1260
1261 i2c_mark_adapter_suspended(&priv->adap);
1262 return 0;
1263 }
1264
rcar_i2c_resume(struct device * dev)1265 static int rcar_i2c_resume(struct device *dev)
1266 {
1267 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1268
1269 i2c_mark_adapter_resumed(&priv->adap);
1270 return 0;
1271 }
1272
1273 static const struct dev_pm_ops rcar_i2c_pm_ops = {
1274 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1275 };
1276
1277 static struct platform_driver rcar_i2c_driver = {
1278 .driver = {
1279 .name = "i2c-rcar",
1280 .of_match_table = rcar_i2c_dt_ids,
1281 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops),
1282 },
1283 .probe = rcar_i2c_probe,
1284 .remove = rcar_i2c_remove,
1285 };
1286
1287 module_platform_driver(rcar_i2c_driver);
1288
1289 MODULE_LICENSE("GPL v2");
1290 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1291 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
1292