1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * Guangjie Song <guangjie.song@mediatek.com> 5 * Copyright (c) 2025 Collabora Ltd. 6 * Laura Nao <laura.nao@collabora.com> 7 */ 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h> 9 10 #include <linux/clk-provider.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 18 static const struct mtk_gate_regs mm10_cg_regs = { 19 .set_ofs = 0x104, 20 .clr_ofs = 0x108, 21 .sta_ofs = 0x100, 22 }; 23 24 static const struct mtk_gate_regs mm10_hwv_regs = { 25 .set_ofs = 0x0010, 26 .clr_ofs = 0x0014, 27 .sta_ofs = 0x2c08, 28 }; 29 30 static const struct mtk_gate_regs mm11_cg_regs = { 31 .set_ofs = 0x114, 32 .clr_ofs = 0x118, 33 .sta_ofs = 0x110, 34 }; 35 36 static const struct mtk_gate_regs mm11_hwv_regs = { 37 .set_ofs = 0x0018, 38 .clr_ofs = 0x001c, 39 .sta_ofs = 0x2c0c, 40 }; 41 42 #define GATE_MM10(_id, _name, _parent, _shift) {\ 43 .id = _id, \ 44 .name = _name, \ 45 .parent_name = _parent, \ 46 .regs = &mm10_cg_regs, \ 47 .shift = _shift, \ 48 .flags = CLK_OPS_PARENT_ENABLE, \ 49 .ops = &mtk_clk_gate_ops_setclr,\ 50 } 51 52 #define GATE_HWV_MM10(_id, _name, _parent, _shift) { \ 53 .id = _id, \ 54 .name = _name, \ 55 .parent_name = _parent, \ 56 .regs = &mm10_cg_regs, \ 57 .hwv_regs = &mm10_hwv_regs, \ 58 .shift = _shift, \ 59 .ops = &mtk_clk_gate_hwv_ops_setclr, \ 60 .flags = CLK_OPS_PARENT_ENABLE, \ 61 } 62 63 #define GATE_MM11(_id, _name, _parent, _shift) {\ 64 .id = _id, \ 65 .name = _name, \ 66 .parent_name = _parent, \ 67 .regs = &mm11_cg_regs, \ 68 .shift = _shift, \ 69 .flags = CLK_OPS_PARENT_ENABLE, \ 70 .ops = &mtk_clk_gate_ops_setclr,\ 71 } 72 73 #define GATE_HWV_MM11(_id, _name, _parent, _shift) { \ 74 .id = _id, \ 75 .name = _name, \ 76 .parent_name = _parent, \ 77 .regs = &mm11_cg_regs, \ 78 .hwv_regs = &mm11_hwv_regs, \ 79 .shift = _shift, \ 80 .ops = &mtk_clk_gate_hwv_ops_setclr, \ 81 } 82 83 static const struct mtk_gate mm1_clks[] = { 84 /* MM10 */ 85 GATE_HWV_MM10(CLK_MM1_DISPSYS1_CONFIG, "mm1_dispsys1_config", "disp", 0), 86 GATE_HWV_MM10(CLK_MM1_DISPSYS1_S_CONFIG, "mm1_dispsys1_s_config", "disp", 1), 87 GATE_HWV_MM10(CLK_MM1_DISP_MUTEX0, "mm1_disp_mutex0", "disp", 2), 88 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC20, "mm1_disp_dli_async20", "disp", 3), 89 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC21, "mm1_disp_dli_async21", "disp", 4), 90 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC22, "mm1_disp_dli_async22", "disp", 5), 91 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC23, "mm1_disp_dli_async23", "disp", 6), 92 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC24, "mm1_disp_dli_async24", "disp", 7), 93 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC25, "mm1_disp_dli_async25", "disp", 8), 94 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC26, "mm1_disp_dli_async26", "disp", 9), 95 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC27, "mm1_disp_dli_async27", "disp", 10), 96 GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC28, "mm1_disp_dli_async28", "disp", 11), 97 GATE_HWV_MM10(CLK_MM1_DISP_RELAY0, "mm1_disp_relay0", "disp", 12), 98 GATE_HWV_MM10(CLK_MM1_DISP_RELAY1, "mm1_disp_relay1", "disp", 13), 99 GATE_HWV_MM10(CLK_MM1_DISP_RELAY2, "mm1_disp_relay2", "disp", 14), 100 GATE_HWV_MM10(CLK_MM1_DISP_RELAY3, "mm1_disp_relay3", "disp", 15), 101 GATE_HWV_MM10(CLK_MM1_DISP_DP_INTF0, "mm1_DP_CLK", "disp", 16), 102 GATE_HWV_MM10(CLK_MM1_DISP_DP_INTF1, "mm1_disp_dp_intf1", "disp", 17), 103 GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP0, "mm1_disp_dsc_wrap0", "disp", 18), 104 GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP1, "mm1_disp_dsc_wrap1", "disp", 19), 105 GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP2, "mm1_disp_dsc_wrap2", "disp", 20), 106 GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP3, "mm1_disp_dsc_wrap3", "disp", 21), 107 GATE_HWV_MM10(CLK_MM1_DISP_DSI0, "mm1_CLK0", "disp", 22), 108 GATE_HWV_MM10(CLK_MM1_DISP_DSI1, "mm1_CLK1", "disp", 23), 109 GATE_HWV_MM10(CLK_MM1_DISP_DSI2, "mm1_CLK2", "disp", 24), 110 GATE_HWV_MM10(CLK_MM1_DISP_DVO0, "mm1_disp_dvo0", "disp", 25), 111 GATE_HWV_MM10(CLK_MM1_DISP_GDMA0, "mm1_disp_gdma0", "disp", 26), 112 GATE_HWV_MM10(CLK_MM1_DISP_MERGE0, "mm1_disp_merge0", "disp", 27), 113 GATE_HWV_MM10(CLK_MM1_DISP_MERGE1, "mm1_disp_merge1", "disp", 28), 114 GATE_HWV_MM10(CLK_MM1_DISP_MERGE2, "mm1_disp_merge2", "disp", 29), 115 GATE_HWV_MM10(CLK_MM1_DISP_ODDMR0, "mm1_disp_oddmr0", "disp", 30), 116 GATE_HWV_MM10(CLK_MM1_DISP_POSTALIGN0, "mm1_disp_postalign0", "disp", 31), 117 /* MM11 */ 118 GATE_HWV_MM11(CLK_MM1_DISP_DITHER2, "mm1_disp_dither2", "disp", 0), 119 GATE_HWV_MM11(CLK_MM1_DISP_R2Y0, "mm1_disp_r2y0", "disp", 1), 120 GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER0, "mm1_disp_splitter0", "disp", 2), 121 GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER1, "mm1_disp_splitter1", "disp", 3), 122 GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER2, "mm1_disp_splitter2", "disp", 4), 123 GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER3, "mm1_disp_splitter3", "disp", 5), 124 GATE_HWV_MM11(CLK_MM1_DISP_VDCM0, "mm1_disp_vdcm0", "disp", 6), 125 GATE_HWV_MM11(CLK_MM1_DISP_WDMA1, "mm1_disp_wdma1", "disp", 7), 126 GATE_HWV_MM11(CLK_MM1_DISP_WDMA2, "mm1_disp_wdma2", "disp", 8), 127 GATE_HWV_MM11(CLK_MM1_DISP_WDMA3, "mm1_disp_wdma3", "disp", 9), 128 GATE_HWV_MM11(CLK_MM1_DISP_WDMA4, "mm1_disp_wdma4", "disp", 10), 129 GATE_HWV_MM11(CLK_MM1_MDP_RDMA1, "mm1_mdp_rdma1", "disp", 11), 130 GATE_HWV_MM11(CLK_MM1_SMI_LARB0, "mm1_smi_larb0", "disp", 12), 131 GATE_HWV_MM11(CLK_MM1_MOD1, "mm1_mod1", "clk26m", 13), 132 GATE_HWV_MM11(CLK_MM1_MOD2, "mm1_mod2", "clk26m", 14), 133 GATE_HWV_MM11(CLK_MM1_MOD3, "mm1_mod3", "clk26m", 15), 134 GATE_HWV_MM11(CLK_MM1_MOD4, "mm1_mod4", "dp0", 16), 135 GATE_HWV_MM11(CLK_MM1_MOD5, "mm1_mod5", "dp1", 17), 136 GATE_HWV_MM11(CLK_MM1_MOD6, "mm1_mod6", "dp1", 18), 137 GATE_HWV_MM11(CLK_MM1_CG0, "mm1_cg0", "disp", 20), 138 GATE_HWV_MM11(CLK_MM1_CG1, "mm1_cg1", "disp", 21), 139 GATE_HWV_MM11(CLK_MM1_CG2, "mm1_cg2", "disp", 22), 140 GATE_HWV_MM11(CLK_MM1_CG3, "mm1_cg3", "disp", 23), 141 GATE_HWV_MM11(CLK_MM1_CG4, "mm1_cg4", "disp", 24), 142 GATE_HWV_MM11(CLK_MM1_CG5, "mm1_cg5", "disp", 25), 143 GATE_HWV_MM11(CLK_MM1_CG6, "mm1_cg6", "disp", 26), 144 GATE_HWV_MM11(CLK_MM1_CG7, "mm1_cg7", "disp", 27), 145 GATE_HWV_MM11(CLK_MM1_F26M, "mm1_f26m_ck", "clk26m", 28), 146 }; 147 148 static const struct mtk_clk_desc mm1_mcd = { 149 .clks = mm1_clks, 150 .num_clks = ARRAY_SIZE(mm1_clks), 151 }; 152 153 static const struct platform_device_id clk_mt8196_disp1_id_table[] = { 154 { .name = "clk-mt8196-disp1", .driver_data = (kernel_ulong_t)&mm1_mcd }, 155 { /* sentinel */ } 156 }; 157 MODULE_DEVICE_TABLE(platform, clk_mt8196_disp1_id_table); 158 159 static struct platform_driver clk_mt8196_disp1_drv = { 160 .probe = mtk_clk_pdev_probe, 161 .remove = mtk_clk_pdev_remove, 162 .driver = { 163 .name = "clk-mt8196-disp1", 164 }, 165 .id_table = clk_mt8196_disp1_id_table, 166 }; 167 module_platform_driver(clk_mt8196_disp1_drv); 168 169 MODULE_DESCRIPTION("MediaTek MT8196 disp1 clocks driver"); 170 MODULE_LICENSE("GPL"); 171