1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_transform.h" 27 #include "reg_helper.h" 28 #include "opp.h" 29 #include "basics/conversion.h" 30 #include "dc.h" 31 32 #define REG(reg) \ 33 (xfm_dce->regs->reg) 34 35 #undef FN 36 #define FN(reg_name, field_name) \ 37 xfm_dce->xfm_shift->field_name, xfm_dce->xfm_mask->field_name 38 39 #define CTX \ 40 xfm_dce->base.ctx 41 #define DC_LOGGER \ 42 xfm_dce->base.ctx->logger 43 44 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19)) 45 #define GAMUT_MATRIX_SIZE 12 46 #define SCL_PHASES 16 47 48 enum dcp_out_trunc_round_mode { 49 DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE, 50 DCP_OUT_TRUNC_ROUND_MODE_ROUND 51 }; 52 53 enum dcp_out_trunc_round_depth { 54 DCP_OUT_TRUNC_ROUND_DEPTH_14BIT, 55 DCP_OUT_TRUNC_ROUND_DEPTH_13BIT, 56 DCP_OUT_TRUNC_ROUND_DEPTH_12BIT, 57 DCP_OUT_TRUNC_ROUND_DEPTH_11BIT, 58 DCP_OUT_TRUNC_ROUND_DEPTH_10BIT, 59 DCP_OUT_TRUNC_ROUND_DEPTH_9BIT, 60 DCP_OUT_TRUNC_ROUND_DEPTH_8BIT 61 }; 62 63 /* defines the various methods of bit reduction available for use */ 64 enum dcp_bit_depth_reduction_mode { 65 DCP_BIT_DEPTH_REDUCTION_MODE_DITHER, 66 DCP_BIT_DEPTH_REDUCTION_MODE_ROUND, 67 DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE, 68 DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED, 69 DCP_BIT_DEPTH_REDUCTION_MODE_INVALID 70 }; 71 72 enum dcp_spatial_dither_mode { 73 DCP_SPATIAL_DITHER_MODE_AAAA, 74 DCP_SPATIAL_DITHER_MODE_A_AA_A, 75 DCP_SPATIAL_DITHER_MODE_AABBAABB, 76 DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC, 77 DCP_SPATIAL_DITHER_MODE_INVALID 78 }; 79 80 enum dcp_spatial_dither_depth { 81 DCP_SPATIAL_DITHER_DEPTH_30BPP, 82 DCP_SPATIAL_DITHER_DEPTH_24BPP 83 }; 84 85 enum csc_color_mode { 86 /* 00 - BITS2:0 Bypass */ 87 CSC_COLOR_MODE_GRAPHICS_BYPASS, 88 /* 01 - hard coded coefficient TV RGB */ 89 CSC_COLOR_MODE_GRAPHICS_PREDEFINED, 90 /* 04 - programmable OUTPUT CSC coefficient */ 91 CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC, 92 }; 93 94 enum grph_color_adjust_option { 95 GRPH_COLOR_MATRIX_HW_DEFAULT = 1, 96 GRPH_COLOR_MATRIX_SW 97 }; 98 99 static const struct out_csc_color_matrix global_color_matrix[] = { 100 { COLOR_SPACE_SRGB, 101 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, 102 { COLOR_SPACE_SRGB_LIMITED, 103 { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} }, 104 { COLOR_SPACE_YCBCR601, 105 { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47, 106 0xF6B9, 0xE00, 0x1000} }, 107 { COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA, 108 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, 109 /* TODO: correct values below */ 110 { COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, 111 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, 112 { COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, 113 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, 114 { COLOR_SPACE_2020_RGB_FULLRANGE, 115 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, 116 { COLOR_SPACE_2020_RGB_LIMITEDRANGE, 117 { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} }, 118 { COLOR_SPACE_2020_YCBCR_LIMITED, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 119 0x15B2, 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} }, 120 { COLOR_SPACE_2020_YCBCR_FULL, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 0x15B2, 121 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} } 122 }; 123 124 static bool setup_scaling_configuration( 125 struct dce_transform *xfm_dce, 126 const struct scaler_data *data) 127 { 128 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); 129 130 if (data->taps.h_taps + data->taps.v_taps <= 2) { 131 /* Set bypass */ 132 if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0) 133 REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0); 134 else 135 REG_UPDATE(SCL_MODE, SCL_MODE, 0); 136 return false; 137 } 138 139 REG_SET_2(SCL_TAP_CONTROL, 0, 140 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, 141 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); 142 143 if (data->format <= PIXEL_FORMAT_GRPH_END) 144 REG_UPDATE(SCL_MODE, SCL_MODE, 1); 145 else 146 REG_UPDATE(SCL_MODE, SCL_MODE, 2); 147 148 if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0) 149 REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1); 150 151 /* 1 - Replace out of bound pixels with edge */ 152 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); 153 154 return true; 155 } 156 157 #if defined(CONFIG_DRM_AMD_DC_SI) 158 static bool dce60_setup_scaling_configuration( 159 struct dce_transform *xfm_dce, 160 const struct scaler_data *data) 161 { 162 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); 163 164 if (data->taps.h_taps + data->taps.v_taps <= 2) { 165 /* Disable scaler functionality */ 166 REG_WRITE(SCL_SCALER_ENABLE, 0); 167 168 /* Clear registers that can cause glitches even when the scaler is off */ 169 REG_WRITE(SCL_TAP_CONTROL, 0); 170 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); 171 REG_WRITE(SCL_F_SHARP_CONTROL, 0); 172 return false; 173 } 174 175 REG_SET_2(SCL_TAP_CONTROL, 0, 176 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, 177 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); 178 179 REG_WRITE(SCL_SCALER_ENABLE, 1); 180 181 /* DCE6 has no SCL_BOUNDARY_MODE bit, skip replace out of bound pixels */ 182 183 return true; 184 } 185 #endif 186 187 static void program_overscan( 188 struct dce_transform *xfm_dce, 189 const struct scaler_data *data) 190 { 191 int overscan_right = data->h_active 192 - data->recout.x - data->recout.width; 193 int overscan_bottom = data->v_active 194 - data->recout.y - data->recout.height; 195 196 if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 197 overscan_bottom += 2; 198 overscan_right += 2; 199 } 200 201 if (overscan_right < 0) { 202 BREAK_TO_DEBUGGER(); 203 overscan_right = 0; 204 } 205 if (overscan_bottom < 0) { 206 BREAK_TO_DEBUGGER(); 207 overscan_bottom = 0; 208 } 209 210 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, 211 EXT_OVERSCAN_LEFT, data->recout.x, 212 EXT_OVERSCAN_RIGHT, overscan_right); 213 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, 214 EXT_OVERSCAN_TOP, data->recout.y, 215 EXT_OVERSCAN_BOTTOM, overscan_bottom); 216 } 217 218 static void program_multi_taps_filter( 219 struct dce_transform *xfm_dce, 220 int taps, 221 const uint16_t *coeffs, 222 enum ram_filter_type filter_type) 223 { 224 int phase, pair; 225 int array_idx = 0; 226 int taps_pairs = (taps + 1) / 2; 227 int phases_to_program = SCL_PHASES / 2 + 1; 228 229 uint32_t power_ctl = 0; 230 231 if (!coeffs) 232 return; 233 234 /*We need to disable power gating on coeff memory to do programming*/ 235 if (REG(DCFE_MEM_PWR_CTRL)) { 236 power_ctl = REG_READ(DCFE_MEM_PWR_CTRL); 237 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); 238 239 REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10); 240 } 241 for (phase = 0; phase < phases_to_program; phase++) { 242 /*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror 243 phase 0 is unique and phase N/2 is unique if N is even*/ 244 for (pair = 0; pair < taps_pairs; pair++) { 245 uint16_t odd_coeff = 0; 246 uint16_t even_coeff = coeffs[array_idx]; 247 248 REG_SET_3(SCL_COEF_RAM_SELECT, 0, 249 SCL_C_RAM_FILTER_TYPE, filter_type, 250 SCL_C_RAM_PHASE, phase, 251 SCL_C_RAM_TAP_PAIR_IDX, pair); 252 253 if (taps % 2 && pair == taps_pairs - 1) 254 array_idx++; 255 else { 256 odd_coeff = coeffs[array_idx + 1]; 257 array_idx += 2; 258 } 259 260 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, 261 SCL_C_RAM_EVEN_TAP_COEF_EN, 1, 262 SCL_C_RAM_EVEN_TAP_COEF, even_coeff, 263 SCL_C_RAM_ODD_TAP_COEF_EN, 1, 264 SCL_C_RAM_ODD_TAP_COEF, odd_coeff); 265 } 266 } 267 268 /*We need to restore power gating on coeff memory to initial state*/ 269 if (REG(DCFE_MEM_PWR_CTRL)) 270 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl); 271 } 272 273 static void program_viewport( 274 struct dce_transform *xfm_dce, 275 const struct rect *view_port) 276 { 277 REG_SET_2(VIEWPORT_START, 0, 278 VIEWPORT_X_START, view_port->x, 279 VIEWPORT_Y_START, view_port->y); 280 281 REG_SET_2(VIEWPORT_SIZE, 0, 282 VIEWPORT_HEIGHT, view_port->height, 283 VIEWPORT_WIDTH, view_port->width); 284 285 /* TODO: add stereo support */ 286 } 287 288 static void calculate_inits( 289 struct dce_transform *xfm_dce, 290 const struct scaler_data *data, 291 struct scl_ratios_inits *inits) 292 { 293 (void)xfm_dce; 294 struct fixed31_32 h_init; 295 struct fixed31_32 v_init; 296 297 inits->h_int_scale_ratio = 298 dc_fixpt_u2d19(data->ratios.horz) << 5; 299 inits->v_int_scale_ratio = 300 dc_fixpt_u2d19(data->ratios.vert) << 5; 301 302 h_init = 303 dc_fixpt_div_int( 304 dc_fixpt_add( 305 data->ratios.horz, 306 dc_fixpt_from_int(data->taps.h_taps + 1)), 307 2); 308 inits->h_init.integer = dc_fixpt_floor(h_init); 309 inits->h_init.fraction = dc_fixpt_u0d19(h_init) << 5; 310 311 v_init = 312 dc_fixpt_div_int( 313 dc_fixpt_add( 314 data->ratios.vert, 315 dc_fixpt_from_int(data->taps.v_taps + 1)), 316 2); 317 inits->v_init.integer = dc_fixpt_floor(v_init); 318 inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5; 319 } 320 321 #if defined(CONFIG_DRM_AMD_DC_SI) 322 static void dce60_calculate_inits( 323 struct dce_transform *xfm_dce, 324 const struct scaler_data *data, 325 struct sclh_ratios_inits *inits) 326 { 327 struct fixed31_32 v_init; 328 329 inits->h_int_scale_ratio = 330 dc_fixpt_u2d19(data->ratios.horz) << 5; 331 inits->v_int_scale_ratio = 332 dc_fixpt_u2d19(data->ratios.vert) << 5; 333 334 /* DCE6 h_init_luma setting inspired by DCE110 */ 335 inits->h_init_luma.integer = 1; 336 337 /* DCE6 h_init_chroma setting inspired by DCE110 */ 338 inits->h_init_chroma.integer = 1; 339 340 v_init = 341 dc_fixpt_div_int( 342 dc_fixpt_add( 343 data->ratios.vert, 344 dc_fixpt_from_int(data->taps.v_taps + 1)), 345 2); 346 inits->v_init.integer = dc_fixpt_floor(v_init); 347 inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5; 348 } 349 #endif 350 351 static void program_scl_ratios_inits( 352 struct dce_transform *xfm_dce, 353 struct scl_ratios_inits *inits) 354 { 355 356 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, 357 SCL_H_SCALE_RATIO, inits->h_int_scale_ratio); 358 359 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, 360 SCL_V_SCALE_RATIO, inits->v_int_scale_ratio); 361 362 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, 363 SCL_H_INIT_INT, inits->h_init.integer, 364 SCL_H_INIT_FRAC, inits->h_init.fraction); 365 366 REG_SET_2(SCL_VERT_FILTER_INIT, 0, 367 SCL_V_INIT_INT, inits->v_init.integer, 368 SCL_V_INIT_FRAC, inits->v_init.fraction); 369 370 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); 371 } 372 373 #if defined(CONFIG_DRM_AMD_DC_SI) 374 static void dce60_program_scl_ratios_inits( 375 struct dce_transform *xfm_dce, 376 struct sclh_ratios_inits *inits) 377 { 378 379 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, 380 SCL_H_SCALE_RATIO, inits->h_int_scale_ratio); 381 382 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, 383 SCL_V_SCALE_RATIO, inits->v_int_scale_ratio); 384 385 /* DCE6 has SCL_HORZ_FILTER_INIT_RGB_LUMA register */ 386 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0, 387 SCL_H_INIT_INT_RGB_Y, inits->h_init_luma.integer, 388 SCL_H_INIT_FRAC_RGB_Y, inits->h_init_luma.fraction); 389 390 /* DCE6 has SCL_HORZ_FILTER_INIT_CHROMA register */ 391 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0, 392 SCL_H_INIT_INT_CBCR, inits->h_init_chroma.integer, 393 SCL_H_INIT_FRAC_CBCR, inits->h_init_chroma.fraction); 394 395 REG_SET_2(SCL_VERT_FILTER_INIT, 0, 396 SCL_V_INIT_INT, inits->v_init.integer, 397 SCL_V_INIT_FRAC, inits->v_init.fraction); 398 399 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); 400 } 401 #endif 402 403 static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio) 404 { 405 if (taps == 4) 406 return get_filter_4tap_16p(ratio); 407 else if (taps == 3) 408 return get_filter_3tap_16p(ratio); 409 else if (taps == 2) 410 return get_filter_2tap_16p(); 411 else if (taps == 1) 412 return NULL; 413 else { 414 /* should never happen, bug */ 415 BREAK_TO_DEBUGGER(); 416 return NULL; 417 } 418 } 419 420 static void dce_transform_set_scaler( 421 struct transform *xfm, 422 const struct scaler_data *data) 423 { 424 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 425 bool is_scaling_required; 426 bool filter_updated = false; 427 const uint16_t *coeffs_v, *coeffs_h; 428 429 /*Use all three pieces of memory always*/ 430 REG_SET_2(LB_MEMORY_CTRL, 0, 431 LB_MEMORY_CONFIG, 0, 432 LB_MEMORY_SIZE, xfm_dce->lb_memory_size); 433 434 /* Clear SCL_F_SHARP_CONTROL value to 0 */ 435 REG_WRITE(SCL_F_SHARP_CONTROL, 0); 436 437 /* 1. Program overscan */ 438 program_overscan(xfm_dce, data); 439 440 /* 2. Program taps and configuration */ 441 is_scaling_required = setup_scaling_configuration(xfm_dce, data); 442 443 if (is_scaling_required) { 444 /* 3. Calculate and program ratio, filter initialization */ 445 struct scl_ratios_inits inits = { 0 }; 446 447 calculate_inits(xfm_dce, data, &inits); 448 449 program_scl_ratios_inits(xfm_dce, &inits); 450 451 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); 452 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); 453 454 if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) { 455 /* 4. Program vertical filters */ 456 if (xfm_dce->filter_v == NULL) 457 REG_SET(SCL_VERT_FILTER_CONTROL, 0, 458 SCL_V_2TAP_HARDCODE_COEF_EN, 0); 459 program_multi_taps_filter( 460 xfm_dce, 461 data->taps.v_taps, 462 coeffs_v, 463 FILTER_TYPE_RGB_Y_VERTICAL); 464 program_multi_taps_filter( 465 xfm_dce, 466 data->taps.v_taps, 467 coeffs_v, 468 FILTER_TYPE_ALPHA_VERTICAL); 469 470 /* 5. Program horizontal filters */ 471 if (xfm_dce->filter_h == NULL) 472 REG_SET(SCL_HORZ_FILTER_CONTROL, 0, 473 SCL_H_2TAP_HARDCODE_COEF_EN, 0); 474 program_multi_taps_filter( 475 xfm_dce, 476 data->taps.h_taps, 477 coeffs_h, 478 FILTER_TYPE_RGB_Y_HORIZONTAL); 479 program_multi_taps_filter( 480 xfm_dce, 481 data->taps.h_taps, 482 coeffs_h, 483 FILTER_TYPE_ALPHA_HORIZONTAL); 484 485 xfm_dce->filter_v = coeffs_v; 486 xfm_dce->filter_h = coeffs_h; 487 filter_updated = true; 488 } 489 } 490 491 /* 6. Program the viewport */ 492 program_viewport(xfm_dce, &data->viewport); 493 494 /* 7. Set bit to flip to new coefficient memory */ 495 if (filter_updated) 496 REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1); 497 498 REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); 499 } 500 501 #if defined(CONFIG_DRM_AMD_DC_SI) 502 static void dce60_transform_set_scaler( 503 struct transform *xfm, 504 const struct scaler_data *data) 505 { 506 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 507 bool is_scaling_required; 508 const uint16_t *coeffs_v, *coeffs_h; 509 510 /*Use whole line buffer memory always*/ 511 REG_SET(DC_LB_MEMORY_SPLIT, 0, 512 DC_LB_MEMORY_CONFIG, 0); 513 514 REG_SET(DC_LB_MEM_SIZE, 0, 515 DC_LB_MEM_SIZE, xfm_dce->lb_memory_size); 516 517 REG_WRITE(SCL_UPDATE, 0x00010000); 518 519 /* Clear SCL_F_SHARP_CONTROL value to 0 */ 520 REG_WRITE(SCL_F_SHARP_CONTROL, 0); 521 522 /* 1. Program overscan */ 523 program_overscan(xfm_dce, data); 524 525 /* 2. Program taps and configuration */ 526 is_scaling_required = dce60_setup_scaling_configuration(xfm_dce, data); 527 528 if (is_scaling_required) { 529 /* 3. Calculate and program ratio, DCE6 filter initialization */ 530 struct sclh_ratios_inits inits = { 0 }; 531 532 /* DCE6 has specific calculate_inits() function */ 533 dce60_calculate_inits(xfm_dce, data, &inits); 534 535 /* DCE6 has specific program_scl_ratios_inits() function */ 536 dce60_program_scl_ratios_inits(xfm_dce, &inits); 537 538 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); 539 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); 540 541 if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) { 542 /* 4. Program vertical filters */ 543 if (xfm_dce->filter_v == NULL) 544 REG_WRITE(SCL_VERT_FILTER_CONTROL, 0); 545 program_multi_taps_filter( 546 xfm_dce, 547 data->taps.v_taps, 548 coeffs_v, 549 FILTER_TYPE_RGB_Y_VERTICAL); 550 program_multi_taps_filter( 551 xfm_dce, 552 data->taps.v_taps, 553 coeffs_v, 554 FILTER_TYPE_ALPHA_VERTICAL); 555 556 /* 5. Program horizontal filters */ 557 if (xfm_dce->filter_h == NULL) 558 REG_WRITE(SCL_HORZ_FILTER_CONTROL, 0); 559 program_multi_taps_filter( 560 xfm_dce, 561 data->taps.h_taps, 562 coeffs_h, 563 FILTER_TYPE_RGB_Y_HORIZONTAL); 564 program_multi_taps_filter( 565 xfm_dce, 566 data->taps.h_taps, 567 coeffs_h, 568 FILTER_TYPE_ALPHA_HORIZONTAL); 569 570 xfm_dce->filter_v = coeffs_v; 571 xfm_dce->filter_h = coeffs_h; 572 } 573 } 574 575 /* 6. Program the viewport */ 576 program_viewport(xfm_dce, &data->viewport); 577 578 /* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient memory */ 579 580 /* DCE6 DATA_FORMAT register does not support ALPHA_EN */ 581 582 REG_WRITE(SCL_UPDATE, 0); 583 } 584 #endif 585 586 /***************************************************************************** 587 * set_clamp 588 * 589 * @param depth : bit depth to set the clamp to (should match denorm) 590 * 591 * @brief 592 * Programs clamp according to panel bit depth. 593 * 594 *******************************************************************************/ 595 static void set_clamp( 596 struct dce_transform *xfm_dce, 597 enum dc_color_depth depth) 598 { 599 int clamp_max = 0; 600 601 /* At the clamp block the data will be MSB aligned, so we set the max 602 * clamp accordingly. 603 * For example, the max value for 6 bits MSB aligned (14 bit bus) would 604 * be "11 1111 0000 0000" in binary, so 0x3F00. 605 */ 606 switch (depth) { 607 case COLOR_DEPTH_666: 608 /* 6bit MSB aligned on 14 bit bus '11 1111 0000 0000' */ 609 clamp_max = 0x3F00; 610 break; 611 case COLOR_DEPTH_888: 612 /* 8bit MSB aligned on 14 bit bus '11 1111 1100 0000' */ 613 clamp_max = 0x3FC0; 614 break; 615 case COLOR_DEPTH_101010: 616 /* 10bit MSB aligned on 14 bit bus '11 1111 1111 0000' */ 617 clamp_max = 0x3FF0; 618 break; 619 case COLOR_DEPTH_121212: 620 /* 12bit MSB aligned on 14 bit bus '11 1111 1111 1100' */ 621 clamp_max = 0x3FFC; 622 break; 623 default: 624 clamp_max = 0x3FC0; 625 BREAK_TO_DEBUGGER(); /* Invalid clamp bit depth */ 626 } 627 REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0, 628 OUT_CLAMP_MIN_B_CB, 0, 629 OUT_CLAMP_MAX_B_CB, clamp_max); 630 631 REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0, 632 OUT_CLAMP_MIN_G_Y, 0, 633 OUT_CLAMP_MAX_G_Y, clamp_max); 634 635 REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0, 636 OUT_CLAMP_MIN_R_CR, 0, 637 OUT_CLAMP_MAX_R_CR, clamp_max); 638 } 639 640 /******************************************************************************* 641 * set_round 642 * 643 * @brief 644 * Programs Round/Truncate 645 * 646 * @param [in] mode :round or truncate 647 * @param [in] depth :bit depth to round/truncate to 648 OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode 649 POSSIBLE VALUES: 650 00 - truncate to u0.12 651 01 - truncate to u0.11 652 02 - truncate to u0.10 653 03 - truncate to u0.9 654 04 - truncate to u0.8 655 05 - reserved 656 06 - truncate to u0.14 657 07 - truncate to u0.13 set_reg_field_value( 658 value, 659 clamp_max, 660 OUT_CLAMP_CONTROL_R_CR, 661 OUT_CLAMP_MAX_R_CR); 662 08 - round to u0.12 663 09 - round to u0.11 664 10 - round to u0.10 665 11 - round to u0.9 666 12 - round to u0.8 667 13 - reserved 668 14 - round to u0.14 669 15 - round to u0.13 670 671 ******************************************************************************/ 672 static void set_round( 673 struct dce_transform *xfm_dce, 674 enum dcp_out_trunc_round_mode mode, 675 enum dcp_out_trunc_round_depth depth) 676 { 677 int depth_bits = 0; 678 int mode_bit = 0; 679 680 /* set up bit depth */ 681 switch (depth) { 682 case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT: 683 depth_bits = 6; 684 break; 685 case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT: 686 depth_bits = 7; 687 break; 688 case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT: 689 depth_bits = 0; 690 break; 691 case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT: 692 depth_bits = 1; 693 break; 694 case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT: 695 depth_bits = 2; 696 break; 697 case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT: 698 depth_bits = 3; 699 break; 700 case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT: 701 depth_bits = 4; 702 break; 703 default: 704 depth_bits = 4; 705 BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_depth */ 706 } 707 708 /* set up round or truncate */ 709 switch (mode) { 710 case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE: 711 mode_bit = 0; 712 break; 713 case DCP_OUT_TRUNC_ROUND_MODE_ROUND: 714 mode_bit = 1; 715 break; 716 default: 717 BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_mode */ 718 } 719 720 depth_bits |= mode_bit << 3; 721 722 REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits); 723 } 724 725 /***************************************************************************** 726 * set_dither 727 * 728 * @brief 729 * Programs Dither 730 * 731 * @param [in] dither_enable : enable dither 732 * @param [in] dither_mode : dither mode to set 733 * @param [in] dither_depth : bit depth to dither to 734 * @param [in] frame_random_enable : enable frame random 735 * @param [in] rgb_random_enable : enable rgb random 736 * @param [in] highpass_random_enable : enable highpass random 737 * 738 ******************************************************************************/ 739 740 static void set_dither( 741 struct dce_transform *xfm_dce, 742 bool dither_enable, 743 enum dcp_spatial_dither_mode dither_mode, 744 enum dcp_spatial_dither_depth dither_depth, 745 bool frame_random_enable, 746 bool rgb_random_enable, 747 bool highpass_random_enable) 748 { 749 int dither_depth_bits = 0; 750 int dither_mode_bits = 0; 751 752 switch (dither_mode) { 753 case DCP_SPATIAL_DITHER_MODE_AAAA: 754 dither_mode_bits = 0; 755 break; 756 case DCP_SPATIAL_DITHER_MODE_A_AA_A: 757 dither_mode_bits = 1; 758 break; 759 case DCP_SPATIAL_DITHER_MODE_AABBAABB: 760 dither_mode_bits = 2; 761 break; 762 case DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC: 763 dither_mode_bits = 3; 764 break; 765 default: 766 /* Invalid dcp_spatial_dither_mode */ 767 BREAK_TO_DEBUGGER(); 768 } 769 770 switch (dither_depth) { 771 case DCP_SPATIAL_DITHER_DEPTH_30BPP: 772 dither_depth_bits = 0; 773 break; 774 case DCP_SPATIAL_DITHER_DEPTH_24BPP: 775 dither_depth_bits = 1; 776 break; 777 default: 778 /* Invalid dcp_spatial_dither_depth */ 779 BREAK_TO_DEBUGGER(); 780 } 781 782 /* write the register */ 783 REG_SET_6(DCP_SPATIAL_DITHER_CNTL, 0, 784 DCP_SPATIAL_DITHER_EN, dither_enable, 785 DCP_SPATIAL_DITHER_MODE, dither_mode_bits, 786 DCP_SPATIAL_DITHER_DEPTH, dither_depth_bits, 787 DCP_FRAME_RANDOM_ENABLE, frame_random_enable, 788 DCP_RGB_RANDOM_ENABLE, rgb_random_enable, 789 DCP_HIGHPASS_RANDOM_ENABLE, highpass_random_enable); 790 } 791 792 /***************************************************************************** 793 * dce_transform_bit_depth_reduction_program 794 * 795 * @brief 796 * Programs the DCP bit depth reduction registers (Clamp, Round/Truncate, 797 * Dither) for dce 798 * 799 * @param depth : bit depth to set the clamp to (should match denorm) 800 * 801 ******************************************************************************/ 802 static void program_bit_depth_reduction( 803 struct dce_transform *xfm_dce, 804 enum dc_color_depth depth, 805 const struct bit_depth_reduction_params *bit_depth_params) 806 { 807 enum dcp_out_trunc_round_depth trunc_round_depth; 808 enum dcp_out_trunc_round_mode trunc_mode; 809 bool spatial_dither_enable; 810 811 ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ 812 813 spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED != 0; 814 /* Default to 12 bit truncation without rounding */ 815 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; 816 trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; 817 818 if (bit_depth_params->flags.TRUNCATE_ENABLED) { 819 /* Don't enable dithering if truncation is enabled */ 820 spatial_dither_enable = false; 821 trunc_mode = bit_depth_params->flags.TRUNCATE_MODE ? 822 DCP_OUT_TRUNC_ROUND_MODE_ROUND : 823 DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; 824 825 if (bit_depth_params->flags.TRUNCATE_DEPTH == 0 || 826 bit_depth_params->flags.TRUNCATE_DEPTH == 1) 827 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_8BIT; 828 else if (bit_depth_params->flags.TRUNCATE_DEPTH == 2) 829 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_10BIT; 830 else { 831 /* 832 * Invalid truncate/round depth. Setting here to 12bit 833 * to prevent use-before-initialize errors. 834 */ 835 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; 836 BREAK_TO_DEBUGGER(); 837 } 838 } 839 840 set_clamp(xfm_dce, depth); 841 set_round(xfm_dce, trunc_mode, trunc_round_depth); 842 set_dither(xfm_dce, 843 spatial_dither_enable, 844 DCP_SPATIAL_DITHER_MODE_A_AA_A, 845 DCP_SPATIAL_DITHER_DEPTH_30BPP, 846 bit_depth_params->flags.FRAME_RANDOM != 0, 847 bit_depth_params->flags.RGB_RANDOM != 0, 848 bit_depth_params->flags.HIGHPASS_RANDOM != 0); 849 } 850 851 #if defined(CONFIG_DRM_AMD_DC_SI) 852 /***************************************************************************** 853 * dce60_transform_bit_depth_reduction program 854 * 855 * @brief 856 * Programs the DCP bit depth reduction registers (Clamp, Round/Truncate, 857 * Dither) for dce 858 * 859 * @param depth : bit depth to set the clamp to (should match denorm) 860 * 861 ******************************************************************************/ 862 static void dce60_program_bit_depth_reduction( 863 struct dce_transform *xfm_dce, 864 enum dc_color_depth depth, 865 const struct bit_depth_reduction_params *bit_depth_params) 866 { 867 enum dcp_out_trunc_round_depth trunc_round_depth; 868 enum dcp_out_trunc_round_mode trunc_mode; 869 bool spatial_dither_enable; 870 871 ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ 872 873 spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED; 874 /* Default to 12 bit truncation without rounding */ 875 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; 876 trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; 877 878 if (bit_depth_params->flags.TRUNCATE_ENABLED) { 879 /* Don't enable dithering if truncation is enabled */ 880 spatial_dither_enable = false; 881 trunc_mode = bit_depth_params->flags.TRUNCATE_MODE ? 882 DCP_OUT_TRUNC_ROUND_MODE_ROUND : 883 DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; 884 885 if (bit_depth_params->flags.TRUNCATE_DEPTH == 0 || 886 bit_depth_params->flags.TRUNCATE_DEPTH == 1) 887 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_8BIT; 888 else if (bit_depth_params->flags.TRUNCATE_DEPTH == 2) 889 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_10BIT; 890 else { 891 /* 892 * Invalid truncate/round depth. Setting here to 12bit 893 * to prevent use-before-initialize errors. 894 */ 895 trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; 896 BREAK_TO_DEBUGGER(); 897 } 898 } 899 900 /* DCE6 has no OUT_CLAMP_CONTROL_* registers - set_clamp() is skipped */ 901 set_round(xfm_dce, trunc_mode, trunc_round_depth); 902 set_dither(xfm_dce, 903 spatial_dither_enable, 904 DCP_SPATIAL_DITHER_MODE_A_AA_A, 905 DCP_SPATIAL_DITHER_DEPTH_30BPP, 906 bit_depth_params->flags.FRAME_RANDOM, 907 bit_depth_params->flags.RGB_RANDOM, 908 bit_depth_params->flags.HIGHPASS_RANDOM); 909 } 910 #endif 911 912 static int dce_transform_get_max_num_of_supported_lines( 913 struct dce_transform *xfm_dce, 914 enum lb_pixel_depth depth, 915 int pixel_width) 916 { 917 int pixels_per_entries = 0; 918 int max_pixels_supports = 0; 919 920 ASSERT(pixel_width); 921 922 /* Find number of pixels that can fit into a single LB entry and 923 * take floor of the value since we cannot store a single pixel 924 * across multiple entries. */ 925 switch (depth) { 926 case LB_PIXEL_DEPTH_18BPP: 927 pixels_per_entries = xfm_dce->lb_bits_per_entry / 18; 928 break; 929 930 case LB_PIXEL_DEPTH_24BPP: 931 pixels_per_entries = xfm_dce->lb_bits_per_entry / 24; 932 break; 933 934 case LB_PIXEL_DEPTH_30BPP: 935 pixels_per_entries = xfm_dce->lb_bits_per_entry / 30; 936 break; 937 938 case LB_PIXEL_DEPTH_36BPP: 939 pixels_per_entries = xfm_dce->lb_bits_per_entry / 36; 940 break; 941 942 default: 943 DC_LOG_WARNING("%s: Invalid LB pixel depth", 944 __func__); 945 BREAK_TO_DEBUGGER(); 946 break; 947 } 948 949 ASSERT(pixels_per_entries); 950 951 max_pixels_supports = 952 pixels_per_entries * 953 xfm_dce->lb_memory_size; 954 955 return (max_pixels_supports / pixel_width); 956 } 957 958 static void set_denormalization( 959 struct dce_transform *xfm_dce, 960 enum dc_color_depth depth) 961 { 962 int denorm_mode = 0; 963 964 switch (depth) { 965 case COLOR_DEPTH_666: 966 /* 63/64 for 6 bit output color depth */ 967 denorm_mode = 1; 968 break; 969 case COLOR_DEPTH_888: 970 /* Unity for 8 bit output color depth 971 * because prescale is disabled by default */ 972 denorm_mode = 0; 973 break; 974 case COLOR_DEPTH_101010: 975 /* 1023/1024 for 10 bit output color depth */ 976 denorm_mode = 3; 977 break; 978 case COLOR_DEPTH_121212: 979 /* 4095/4096 for 12 bit output color depth */ 980 denorm_mode = 5; 981 break; 982 case COLOR_DEPTH_141414: 983 case COLOR_DEPTH_161616: 984 default: 985 /* not valid used case! */ 986 break; 987 } 988 989 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode); 990 } 991 992 static void dce_transform_set_pixel_storage_depth( 993 struct transform *xfm, 994 enum lb_pixel_depth depth, 995 const struct bit_depth_reduction_params *bit_depth_params) 996 { 997 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 998 int pixel_depth, expan_mode; 999 enum dc_color_depth color_depth; 1000 1001 switch (depth) { 1002 case LB_PIXEL_DEPTH_18BPP: 1003 color_depth = COLOR_DEPTH_666; 1004 pixel_depth = 2; 1005 expan_mode = 1; 1006 break; 1007 case LB_PIXEL_DEPTH_24BPP: 1008 color_depth = COLOR_DEPTH_888; 1009 pixel_depth = 1; 1010 expan_mode = 1; 1011 break; 1012 case LB_PIXEL_DEPTH_30BPP: 1013 color_depth = COLOR_DEPTH_101010; 1014 pixel_depth = 0; 1015 expan_mode = 1; 1016 break; 1017 case LB_PIXEL_DEPTH_36BPP: 1018 color_depth = COLOR_DEPTH_121212; 1019 pixel_depth = 3; 1020 expan_mode = 0; 1021 break; 1022 default: 1023 color_depth = COLOR_DEPTH_101010; 1024 pixel_depth = 0; 1025 expan_mode = 1; 1026 DC_LOG_DC("The pixel depth %d is not valid, set COLOR_DEPTH_101010 instead.", depth); 1027 break; 1028 } 1029 1030 set_denormalization(xfm_dce, color_depth); 1031 program_bit_depth_reduction(xfm_dce, color_depth, bit_depth_params); 1032 1033 REG_UPDATE_2(LB_DATA_FORMAT, 1034 PIXEL_DEPTH, pixel_depth, 1035 PIXEL_EXPAN_MODE, expan_mode); 1036 1037 if (!(xfm_dce->lb_pixel_depth_supported & depth)) { 1038 /*we should use unsupported capabilities 1039 * unless it is required by w/a*/ 1040 DC_LOG_DC("%s: Capability not supported", __func__); 1041 } 1042 } 1043 1044 #if defined(CONFIG_DRM_AMD_DC_SI) 1045 static void dce60_transform_set_pixel_storage_depth( 1046 struct transform *xfm, 1047 enum lb_pixel_depth depth, 1048 const struct bit_depth_reduction_params *bit_depth_params) 1049 { 1050 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1051 enum dc_color_depth color_depth; 1052 1053 switch (depth) { 1054 case LB_PIXEL_DEPTH_18BPP: 1055 color_depth = COLOR_DEPTH_666; 1056 break; 1057 case LB_PIXEL_DEPTH_24BPP: 1058 color_depth = COLOR_DEPTH_888; 1059 break; 1060 case LB_PIXEL_DEPTH_30BPP: 1061 color_depth = COLOR_DEPTH_101010; 1062 break; 1063 case LB_PIXEL_DEPTH_36BPP: 1064 color_depth = COLOR_DEPTH_121212; 1065 break; 1066 default: 1067 color_depth = COLOR_DEPTH_101010; 1068 BREAK_TO_DEBUGGER(); 1069 break; 1070 } 1071 1072 set_denormalization(xfm_dce, color_depth); 1073 dce60_program_bit_depth_reduction(xfm_dce, color_depth, bit_depth_params); 1074 1075 /* DATA_FORMAT in DCE6 does not have PIXEL_DEPTH and PIXEL_EXPAN_MODE masks */ 1076 1077 if (!(xfm_dce->lb_pixel_depth_supported & depth)) { 1078 /*we should use unsupported capabilities 1079 * unless it is required by w/a*/ 1080 DC_LOG_WARNING("%s: Capability not supported", 1081 __func__); 1082 } 1083 } 1084 #endif 1085 1086 static void program_gamut_remap( 1087 struct dce_transform *xfm_dce, 1088 const uint16_t *reg_val) 1089 { 1090 if (reg_val) { 1091 REG_SET_2(GAMUT_REMAP_C11_C12, 0, 1092 GAMUT_REMAP_C11, reg_val[0], 1093 GAMUT_REMAP_C12, reg_val[1]); 1094 REG_SET_2(GAMUT_REMAP_C13_C14, 0, 1095 GAMUT_REMAP_C13, reg_val[2], 1096 GAMUT_REMAP_C14, reg_val[3]); 1097 REG_SET_2(GAMUT_REMAP_C21_C22, 0, 1098 GAMUT_REMAP_C21, reg_val[4], 1099 GAMUT_REMAP_C22, reg_val[5]); 1100 REG_SET_2(GAMUT_REMAP_C23_C24, 0, 1101 GAMUT_REMAP_C23, reg_val[6], 1102 GAMUT_REMAP_C24, reg_val[7]); 1103 REG_SET_2(GAMUT_REMAP_C31_C32, 0, 1104 GAMUT_REMAP_C31, reg_val[8], 1105 GAMUT_REMAP_C32, reg_val[9]); 1106 REG_SET_2(GAMUT_REMAP_C33_C34, 0, 1107 GAMUT_REMAP_C33, reg_val[10], 1108 GAMUT_REMAP_C34, reg_val[11]); 1109 1110 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1); 1111 } else 1112 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0); 1113 1114 } 1115 1116 /* 1117 ***************************************************************************** 1118 * Function: dal_transform_wide_gamut_set_gamut_remap 1119 * 1120 * @param [in] const struct xfm_grph_csc_adjustment *adjust 1121 * 1122 * @return 1123 * void 1124 * 1125 * @note calculate and apply color temperature adjustment to in Rgb color space 1126 * 1127 * @see 1128 * 1129 ***************************************************************************** 1130 */ 1131 static void dce_transform_set_gamut_remap( 1132 struct transform *xfm, 1133 const struct xfm_grph_csc_adjustment *adjust) 1134 { 1135 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1136 int i = 0; 1137 1138 if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) 1139 /* Bypass if type is bypass or hw */ 1140 program_gamut_remap(xfm_dce, NULL); 1141 else { 1142 struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE]; 1143 uint16_t arr_reg_val[GAMUT_MATRIX_SIZE]; 1144 1145 for (i = 0; i < GAMUT_MATRIX_SIZE; i++) 1146 arr_matrix[i] = adjust->temperature_matrix[i]; 1147 1148 convert_float_matrix( 1149 arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE); 1150 1151 program_gamut_remap(xfm_dce, arr_reg_val); 1152 } 1153 } 1154 1155 static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chroma) 1156 { 1157 uint32_t taps; 1158 1159 if (IDENTITY_RATIO(ratio)) { 1160 return 1; 1161 } else if (in_taps != 0) { 1162 taps = in_taps; 1163 } else { 1164 taps = 4; 1165 } 1166 1167 if (chroma) { 1168 taps /= 2; 1169 if (taps < 2) 1170 taps = 2; 1171 } 1172 1173 return taps; 1174 } 1175 1176 1177 bool dce_transform_get_optimal_number_of_taps( 1178 struct transform *xfm, 1179 struct scaler_data *scl_data, 1180 const struct scaling_taps *in_taps) 1181 { 1182 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1183 int pixel_width = scl_data->viewport.width; 1184 uint32_t max_num_of_lines; 1185 1186 if (xfm_dce->prescaler_on && 1187 (scl_data->viewport.width > scl_data->recout.width)) 1188 pixel_width = scl_data->recout.width; 1189 1190 max_num_of_lines = (uint32_t)dce_transform_get_max_num_of_supported_lines( 1191 xfm_dce, 1192 scl_data->lb_params.depth, 1193 pixel_width); 1194 1195 /* Fail if in_taps are impossible */ 1196 if (in_taps->v_taps >= max_num_of_lines) 1197 return false; 1198 1199 /* 1200 * Set taps according to this policy (in this order) 1201 * - Use 1 for no scaling 1202 * - Use input taps 1203 * - Use 4 and reduce as required by line buffer size 1204 * - Decide chroma taps if chroma is scaled 1205 * 1206 * Ignore input chroma taps. Decide based on non-chroma 1207 */ 1208 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); 1209 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); 1210 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); 1211 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); 1212 1213 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { 1214 /* reduce v_taps if needed but ensure we have at least two */ 1215 if (in_taps->v_taps == 0 1216 && max_num_of_lines <= scl_data->taps.v_taps 1217 && scl_data->taps.v_taps > 1) { 1218 scl_data->taps.v_taps = max_num_of_lines - 1; 1219 } 1220 1221 if (scl_data->taps.v_taps <= 1) 1222 return false; 1223 } 1224 1225 if (!IDENTITY_RATIO(scl_data->ratios.vert_c)) { 1226 /* reduce chroma v_taps if needed but ensure we have at least two */ 1227 if (max_num_of_lines <= scl_data->taps.v_taps_c && scl_data->taps.v_taps_c > 1) { 1228 scl_data->taps.v_taps_c = max_num_of_lines - 1; 1229 } 1230 1231 if (scl_data->taps.v_taps_c <= 1) 1232 return false; 1233 } 1234 1235 /* we've got valid taps */ 1236 return true; 1237 } 1238 1239 static void dce_transform_reset(struct transform *xfm) 1240 { 1241 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1242 1243 xfm_dce->filter_h = NULL; 1244 xfm_dce->filter_v = NULL; 1245 } 1246 1247 static void program_color_matrix( 1248 struct dce_transform *xfm_dce, 1249 const struct out_csc_color_matrix *tbl_entry, 1250 enum grph_color_adjust_option options) 1251 { 1252 (void)options; 1253 { 1254 REG_SET_2(OUTPUT_CSC_C11_C12, 0, 1255 OUTPUT_CSC_C11, tbl_entry->regval[0], 1256 OUTPUT_CSC_C12, tbl_entry->regval[1]); 1257 } 1258 { 1259 REG_SET_2(OUTPUT_CSC_C13_C14, 0, 1260 OUTPUT_CSC_C11, tbl_entry->regval[2], 1261 OUTPUT_CSC_C12, tbl_entry->regval[3]); 1262 } 1263 { 1264 REG_SET_2(OUTPUT_CSC_C21_C22, 0, 1265 OUTPUT_CSC_C11, tbl_entry->regval[4], 1266 OUTPUT_CSC_C12, tbl_entry->regval[5]); 1267 } 1268 { 1269 REG_SET_2(OUTPUT_CSC_C23_C24, 0, 1270 OUTPUT_CSC_C11, tbl_entry->regval[6], 1271 OUTPUT_CSC_C12, tbl_entry->regval[7]); 1272 } 1273 { 1274 REG_SET_2(OUTPUT_CSC_C31_C32, 0, 1275 OUTPUT_CSC_C11, tbl_entry->regval[8], 1276 OUTPUT_CSC_C12, tbl_entry->regval[9]); 1277 } 1278 { 1279 REG_SET_2(OUTPUT_CSC_C33_C34, 0, 1280 OUTPUT_CSC_C11, tbl_entry->regval[10], 1281 OUTPUT_CSC_C12, tbl_entry->regval[11]); 1282 } 1283 } 1284 1285 static bool configure_graphics_mode( 1286 struct dce_transform *xfm_dce, 1287 enum csc_color_mode config, 1288 enum graphics_csc_adjust_type csc_adjust_type, 1289 enum dc_color_space color_space) 1290 { 1291 REG_SET(OUTPUT_CSC_CONTROL, 0, 1292 OUTPUT_CSC_GRPH_MODE, 0); 1293 1294 if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) { 1295 if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) { 1296 REG_SET(OUTPUT_CSC_CONTROL, 0, 1297 OUTPUT_CSC_GRPH_MODE, 4); 1298 } else { 1299 1300 switch (color_space) { 1301 case COLOR_SPACE_SRGB: 1302 /* by pass */ 1303 REG_SET(OUTPUT_CSC_CONTROL, 0, 1304 OUTPUT_CSC_GRPH_MODE, 0); 1305 break; 1306 case COLOR_SPACE_SRGB_LIMITED: 1307 /* TV RGB */ 1308 REG_SET(OUTPUT_CSC_CONTROL, 0, 1309 OUTPUT_CSC_GRPH_MODE, 1); 1310 break; 1311 case COLOR_SPACE_YCBCR601: 1312 case COLOR_SPACE_YCBCR601_LIMITED: 1313 /* YCbCr601 */ 1314 REG_SET(OUTPUT_CSC_CONTROL, 0, 1315 OUTPUT_CSC_GRPH_MODE, 2); 1316 break; 1317 case COLOR_SPACE_YCBCR709: 1318 case COLOR_SPACE_YCBCR709_LIMITED: 1319 /* YCbCr709 */ 1320 REG_SET(OUTPUT_CSC_CONTROL, 0, 1321 OUTPUT_CSC_GRPH_MODE, 3); 1322 break; 1323 default: 1324 return false; 1325 } 1326 } 1327 } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) { 1328 switch (color_space) { 1329 case COLOR_SPACE_SRGB: 1330 /* by pass */ 1331 REG_SET(OUTPUT_CSC_CONTROL, 0, 1332 OUTPUT_CSC_GRPH_MODE, 0); 1333 break; 1334 case COLOR_SPACE_SRGB_LIMITED: 1335 /* TV RGB */ 1336 REG_SET(OUTPUT_CSC_CONTROL, 0, 1337 OUTPUT_CSC_GRPH_MODE, 1); 1338 break; 1339 case COLOR_SPACE_YCBCR601: 1340 case COLOR_SPACE_YCBCR601_LIMITED: 1341 /* YCbCr601 */ 1342 REG_SET(OUTPUT_CSC_CONTROL, 0, 1343 OUTPUT_CSC_GRPH_MODE, 2); 1344 break; 1345 case COLOR_SPACE_YCBCR709: 1346 case COLOR_SPACE_YCBCR709_LIMITED: 1347 /* YCbCr709 */ 1348 REG_SET(OUTPUT_CSC_CONTROL, 0, 1349 OUTPUT_CSC_GRPH_MODE, 3); 1350 break; 1351 default: 1352 return false; 1353 } 1354 1355 } else 1356 /* by pass */ 1357 REG_SET(OUTPUT_CSC_CONTROL, 0, 1358 OUTPUT_CSC_GRPH_MODE, 0); 1359 1360 return true; 1361 } 1362 1363 void dce110_opp_set_csc_adjustment( 1364 struct transform *xfm, 1365 const struct out_csc_color_matrix *tbl_entry) 1366 { 1367 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1368 enum csc_color_mode config = 1369 CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; 1370 1371 program_color_matrix( 1372 xfm_dce, tbl_entry, GRPH_COLOR_MATRIX_SW); 1373 1374 /* We did everything ,now program DxOUTPUT_CSC_CONTROL */ 1375 configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW, 1376 tbl_entry->color_space); 1377 } 1378 1379 void dce110_opp_set_csc_default( 1380 struct transform *xfm, 1381 const struct default_adjustment *default_adjust) 1382 { 1383 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1384 enum csc_color_mode config = 1385 CSC_COLOR_MODE_GRAPHICS_PREDEFINED; 1386 1387 if (default_adjust->force_hw_default == false) { 1388 const struct out_csc_color_matrix *elm; 1389 /* currently parameter not in use */ 1390 enum grph_color_adjust_option option = 1391 GRPH_COLOR_MATRIX_HW_DEFAULT; 1392 uint32_t i; 1393 /* 1394 * HW default false we program locally defined matrix 1395 * HW default true we use predefined hw matrix and we 1396 * do not need to program matrix 1397 * OEM wants the HW default via runtime parameter. 1398 */ 1399 option = GRPH_COLOR_MATRIX_SW; 1400 1401 for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) { 1402 elm = &global_color_matrix[i]; 1403 if (elm->color_space != default_adjust->out_color_space) 1404 continue; 1405 /* program the matrix with default values from this 1406 * file */ 1407 program_color_matrix(xfm_dce, elm, option); 1408 config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC; 1409 break; 1410 } 1411 } 1412 1413 /* configure the what we programmed : 1414 * 1. Default values from this file 1415 * 2. Use hardware default from ROM_A and we do not need to program 1416 * matrix */ 1417 1418 configure_graphics_mode(xfm_dce, config, 1419 default_adjust->csc_adjust_type, 1420 default_adjust->out_color_space); 1421 } 1422 1423 static void program_pwl(struct dce_transform *xfm_dce, 1424 const struct pwl_params *params) 1425 { 1426 uint32_t retval; 1427 uint8_t max_tries = 10; 1428 uint8_t counter = 0; 1429 uint32_t i = 0; 1430 const struct pwl_result_data *rgb = params->rgb_resulted; 1431 1432 /* Power on LUT memory */ 1433 if (REG(DCFE_MEM_PWR_CTRL)) 1434 REG_UPDATE(DCFE_MEM_PWR_CTRL, 1435 DCP_REGAMMA_MEM_PWR_DIS, 1); 1436 else 1437 REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, 1438 REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); 1439 1440 while (counter < max_tries) { 1441 if (REG(DCFE_MEM_PWR_STATUS)) { 1442 REG_GET(DCFE_MEM_PWR_STATUS, 1443 DCP_REGAMMA_MEM_PWR_STATE, 1444 &retval); 1445 1446 if (retval == 0) 1447 break; 1448 ++counter; 1449 } else { 1450 REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, 1451 REGAMMA_LUT_MEM_PWR_STATE, 1452 &retval); 1453 1454 if (retval == 0) 1455 break; 1456 ++counter; 1457 } 1458 } 1459 1460 if (counter == max_tries) { 1461 DC_LOG_WARNING("%s: regamma lut was not powered on " 1462 "in a timely manner," 1463 " programming still proceeds\n", 1464 __func__); 1465 } 1466 1467 REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, 1468 REGAMMA_LUT_WRITE_EN_MASK, 7); 1469 1470 REG_WRITE(REGAMMA_LUT_INDEX, 0); 1471 1472 /* Program REGAMMA_LUT_DATA */ 1473 while (i != params->hw_points_num) { 1474 1475 REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); 1476 REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); 1477 REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); 1478 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); 1479 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); 1480 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); 1481 1482 ++rgb; 1483 ++i; 1484 } 1485 1486 /* we are done with DCP LUT memory; re-enable low power mode */ 1487 if (REG(DCFE_MEM_PWR_CTRL)) 1488 REG_UPDATE(DCFE_MEM_PWR_CTRL, 1489 DCP_REGAMMA_MEM_PWR_DIS, 0); 1490 else 1491 REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, 1492 REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); 1493 } 1494 1495 static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, 1496 const struct pwl_params *params) 1497 { 1498 const struct gamma_curve *curve; 1499 1500 REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, 1501 REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, 1502 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); 1503 1504 REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, 1505 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); 1506 1507 REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, 1508 REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); 1509 1510 REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, 1511 REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, 1512 REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope); 1513 1514 curve = params->arr_curve_points; 1515 1516 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, 1517 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1518 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1519 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1520 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1521 curve += 2; 1522 1523 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, 1524 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1525 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1526 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1527 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1528 curve += 2; 1529 1530 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, 1531 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1532 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1533 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1534 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1535 curve += 2; 1536 1537 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, 1538 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1539 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1540 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1541 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1542 curve += 2; 1543 1544 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, 1545 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1546 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1547 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1548 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1549 curve += 2; 1550 1551 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, 1552 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1553 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1554 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1555 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1556 curve += 2; 1557 1558 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, 1559 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1560 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1561 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1562 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1563 curve += 2; 1564 1565 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, 1566 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1567 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1568 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1569 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1570 } 1571 1572 1573 1574 void dce110_opp_program_regamma_pwl(struct transform *xfm, 1575 const struct pwl_params *params) 1576 { 1577 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1578 1579 /* Setup regions */ 1580 regamma_config_regions_and_segments(xfm_dce, params); 1581 1582 /* Program PWL */ 1583 program_pwl(xfm_dce, params); 1584 } 1585 1586 void dce110_opp_power_on_regamma_lut(struct transform *xfm, 1587 bool power_on) 1588 { 1589 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1590 1591 if (REG(DCFE_MEM_PWR_CTRL)) 1592 REG_UPDATE_2(DCFE_MEM_PWR_CTRL, 1593 DCP_REGAMMA_MEM_PWR_DIS, power_on, 1594 DCP_LUT_MEM_PWR_DIS, power_on); 1595 else 1596 REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, 1597 REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, 1598 DCP_LUT_LIGHT_SLEEP_DIS, power_on); 1599 1600 } 1601 1602 void dce110_opp_set_regamma_mode(struct transform *xfm, 1603 enum opp_regamma mode) 1604 { 1605 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); 1606 1607 REG_SET(REGAMMA_CONTROL, 0, 1608 GRPH_REGAMMA_MODE, mode); 1609 } 1610 1611 static const struct transform_funcs dce_transform_funcs = { 1612 .transform_reset = dce_transform_reset, 1613 .transform_set_scaler = dce_transform_set_scaler, 1614 .transform_set_gamut_remap = dce_transform_set_gamut_remap, 1615 .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, 1616 .opp_set_csc_default = dce110_opp_set_csc_default, 1617 .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, 1618 .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, 1619 .opp_set_regamma_mode = dce110_opp_set_regamma_mode, 1620 .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth, 1621 .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps 1622 }; 1623 1624 #if defined(CONFIG_DRM_AMD_DC_SI) 1625 static const struct transform_funcs dce60_transform_funcs = { 1626 .transform_reset = dce_transform_reset, 1627 .transform_set_scaler = dce60_transform_set_scaler, 1628 .transform_set_gamut_remap = dce_transform_set_gamut_remap, 1629 .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, 1630 .opp_set_csc_default = dce110_opp_set_csc_default, 1631 .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, 1632 .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, 1633 .opp_set_regamma_mode = dce110_opp_set_regamma_mode, 1634 .transform_set_pixel_storage_depth = dce60_transform_set_pixel_storage_depth, 1635 .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps 1636 }; 1637 #endif 1638 1639 /*****************************************/ 1640 /* Constructor, Destructor */ 1641 /*****************************************/ 1642 1643 void dce_transform_construct( 1644 struct dce_transform *xfm_dce, 1645 struct dc_context *ctx, 1646 uint32_t inst, 1647 const struct dce_transform_registers *regs, 1648 const struct dce_transform_shift *xfm_shift, 1649 const struct dce_transform_mask *xfm_mask) 1650 { 1651 xfm_dce->base.ctx = ctx; 1652 1653 xfm_dce->base.inst = inst; 1654 xfm_dce->base.funcs = &dce_transform_funcs; 1655 1656 xfm_dce->regs = regs; 1657 xfm_dce->xfm_shift = xfm_shift; 1658 xfm_dce->xfm_mask = xfm_mask; 1659 1660 xfm_dce->prescaler_on = true; 1661 xfm_dce->lb_pixel_depth_supported = 1662 LB_PIXEL_DEPTH_18BPP | 1663 LB_PIXEL_DEPTH_24BPP | 1664 LB_PIXEL_DEPTH_30BPP | 1665 LB_PIXEL_DEPTH_36BPP; 1666 1667 xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; 1668 xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/ 1669 } 1670 1671 #if defined(CONFIG_DRM_AMD_DC_SI) 1672 void dce60_transform_construct( 1673 struct dce_transform *xfm_dce, 1674 struct dc_context *ctx, 1675 uint32_t inst, 1676 const struct dce_transform_registers *regs, 1677 const struct dce_transform_shift *xfm_shift, 1678 const struct dce_transform_mask *xfm_mask) 1679 { 1680 xfm_dce->base.ctx = ctx; 1681 1682 xfm_dce->base.inst = inst; 1683 xfm_dce->base.funcs = &dce60_transform_funcs; 1684 1685 xfm_dce->regs = regs; 1686 xfm_dce->xfm_shift = xfm_shift; 1687 xfm_dce->xfm_mask = xfm_mask; 1688 1689 xfm_dce->prescaler_on = true; 1690 xfm_dce->lb_pixel_depth_supported = 1691 LB_PIXEL_DEPTH_18BPP | 1692 LB_PIXEL_DEPTH_24BPP | 1693 LB_PIXEL_DEPTH_30BPP | 1694 LB_PIXEL_DEPTH_36BPP; 1695 1696 xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY; 1697 xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/ 1698 } 1699 #endif 1700