1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::prelude::*; 4 5 use crate::{ 6 driver::Bar0, 7 fb::hal::FbHal, 8 regs, // 9 }; 10 11 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; 12 13 struct Ga100; 14 15 pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { 16 u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT 17 | u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40()) 18 << FLUSH_SYSMEM_ADDR_SHIFT_HI 19 } 20 21 pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { 22 regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::default() 23 // CAST: `as u32` is used on purpose since the remaining bits are guaranteed to fit within 24 // a `u32`. 25 .set_adr_63_40((addr >> FLUSH_SYSMEM_ADDR_SHIFT_HI) as u32) 26 .write(bar); 27 regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default() 28 // CAST: `as u32` is used on purpose since we want to strip the upper bits that have been 29 // written to `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`. 30 .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32) 31 .write(bar); 32 } 33 34 pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { 35 !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled() 36 } 37 38 /// Shift applied to the sysmem address before it is written into 39 /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`, 40 const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 = 40; 41 42 impl FbHal for Ga100 { 43 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { 44 read_sysmem_flush_page_ga100(bar) 45 } 46 47 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { 48 write_sysmem_flush_page_ga100(bar, addr); 49 50 Ok(()) 51 } 52 53 fn supports_display(&self, bar: &Bar0) -> bool { 54 display_enabled_ga100(bar) 55 } 56 57 fn vidmem_size(&self, bar: &Bar0) -> u64 { 58 super::tu102::vidmem_size_gp102(bar) 59 } 60 } 61 62 const GA100: Ga100 = Ga100; 63 pub(super) const GA100_HAL: &dyn FbHal = &GA100; 64