1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2016 IBM Corp.
4 */
5 #include <linux/bitops.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/pinctrl/pinconf.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/types.h>
17
18 #include "../core.h"
19 #include "../pinctrl-utils.h"
20 #include "pinctrl-aspeed.h"
21
22 /* Wrap some of the common macros for clarity */
23 #define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
24 SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
25
26 #define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
27 #define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
28
29 /*
30 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
31 * references registers by the device/offset mnemonic. The register macros
32 * below are named the same way to ease transcription and verification (as
33 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
34 * reference registers beyond those dedicated to pinmux, such as the system
35 * reset control and MAC clock configuration registers. The AST2500 goes a step
36 * further and references registers in the graphics IP block.
37 */
38 #define SCU2C 0x2C /* Misc. Control Register */
39 #define SCU3C 0x3C /* System Reset Control/Status Register */
40 #define SCU48 0x48 /* MAC Interface Clock Delay Setting */
41 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
42 #define HW_REVISION_ID 0x7C /* Silicon revision ID register */
43 #define SCU80 0x80 /* Multi-function Pin Control #1 */
44 #define SCU84 0x84 /* Multi-function Pin Control #2 */
45 #define SCU88 0x88 /* Multi-function Pin Control #3 */
46 #define SCU8C 0x8C /* Multi-function Pin Control #4 */
47 #define SCU90 0x90 /* Multi-function Pin Control #5 */
48 #define SCU94 0x94 /* Multi-function Pin Control #6 */
49 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
50 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
51 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
52 #define SCUAC 0xAC /* Multi-function Pin Control #10 */
53 #define HW_STRAP2 0xD0 /* Strapping */
54
55 #define ASPEED_G5_NR_PINS 236
56
57 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
58 #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
59
60 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
61 #define LHCR0 0xa0
62 #define GFX064 0x64
63
64 #define B14 0
65 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
66
67 #define D14 1
68 SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
69
70 #define D13 2
71 SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
72 SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
73 PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3);
74 FUNC_GROUP_DECL(SPI1CS1, D13);
75 FUNC_GROUP_DECL(TIMER3, D13);
76
77 #define E13 3
78 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
79
80 #define I2C9_DESC SIG_DESC_SET(SCU90, 22)
81
82 #define C14 4
83 SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1);
84 SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
85 PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5);
86
87 FUNC_GROUP_DECL(TIMER5, C14);
88
89 #define A13 5
90 SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1);
91 SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
92 PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6);
93
94 FUNC_GROUP_DECL(TIMER6, A13);
95
96 FUNC_GROUP_DECL(I2C9, C14, A13);
97
98 #define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
99
100 #define C13 6
101 SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1);
102 SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
103 PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7);
104
105 FUNC_GROUP_DECL(TIMER7, C13);
106
107 #define B13 7
108 SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1);
109 SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
110 PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8);
111
112 FUNC_GROUP_DECL(TIMER8, B13);
113
114 FUNC_GROUP_DECL(MDIO2, C13, B13);
115
116 #define K19 8
117 GPIO_PIN_DECL(K19, GPIOB0);
118
119 #define L19 9
120 GPIO_PIN_DECL(L19, GPIOB1);
121
122 #define L18 10
123 GPIO_PIN_DECL(L18, GPIOB2);
124
125 #define K18 11
126 GPIO_PIN_DECL(K18, GPIOB3);
127
128 #define J20 12
129 SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
130
131 #define H21 13
132 #define H21_DESC SIG_DESC_SET(SCU80, 13)
133 SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC);
134 SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC);
135 PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI);
136 FUNC_GROUP_DECL(LPCPD, H21);
137 FUNC_GROUP_DECL(LPCSMI, H21);
138
139 #define H22 14
140 SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
141
142 #define H20 15
143 GPIO_PIN_DECL(H20, GPIOB7);
144
145 #define SD1_DESC SIG_DESC_SET(SCU90, 0)
146
147 #define C12 16
148 #define I2C10_DESC SIG_DESC_SET(SCU90, 23)
149 SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
150 SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
151 PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
152
153 #define A12 17
154 SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC);
155 SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC);
156 PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10);
157
158 FUNC_GROUP_DECL(I2C10, C12, A12);
159
160 #define B12 18
161 #define I2C11_DESC SIG_DESC_SET(SCU90, 24)
162 SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC);
163 SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC);
164 PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11);
165
166 #define D9 19
167 SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC);
168 SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC);
169 PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11);
170
171 FUNC_GROUP_DECL(I2C11, B12, D9);
172
173 #define D10 20
174 #define I2C12_DESC SIG_DESC_SET(SCU90, 25)
175 SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC);
176 SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC);
177 PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12);
178
179 #define E12 21
180 SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC);
181 SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC);
182 PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12);
183
184 FUNC_GROUP_DECL(I2C12, D10, E12);
185
186 #define C11 22
187 #define I2C13_DESC SIG_DESC_SET(SCU90, 26)
188 SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC);
189 SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC);
190 PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13);
191
192 #define B11 23
193 SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC);
194 SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC);
195 PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13);
196
197 FUNC_GROUP_DECL(I2C13, C11, B11);
198 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
199
200 #define SD2_DESC SIG_DESC_SET(SCU90, 1)
201 #define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
202 #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
203
204 #define F19 24
205 SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC);
206 SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
207 SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
208 SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID);
209 PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN);
210
211 #define E21 25
212 SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC);
213 SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
214 SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
215 SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID);
216 PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT);
217
218 FUNC_GROUP_DECL(GPID0, F19, E21);
219
220 #define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
221
222 #define F20 26
223 SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC);
224 SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
225 SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
226 SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID);
227 PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN);
228
229 #define D20 27
230 SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC);
231 SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
232 SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
233 SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID);
234 PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT);
235
236 FUNC_GROUP_DECL(GPID2, F20, D20);
237
238 #define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
239
240 #define D21 28
241 SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC);
242 SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
243 SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
244 SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID);
245 PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN);
246
247 #define E20 29
248 SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC);
249 SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
250 SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
251 SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID);
252 PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT);
253
254 FUNC_GROUP_DECL(GPID4, D21, E20);
255
256 #define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
257
258 #define G18 30
259 SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC);
260 SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
261 SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
262 SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID);
263 PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN);
264
265 #define C21 31
266 SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC);
267 SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
268 SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
269 SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID);
270 PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT);
271
272 FUNC_GROUP_DECL(GPID6, G18, C21);
273 FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
274
275 #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
276 #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
277
278 #define B20 32
279 SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
280 SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
281 SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
282 SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE);
283 PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN);
284 FUNC_GROUP_DECL(NCTS3, B20);
285
286 #define C20 33
287 SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
288 SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
289 SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
290 SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE);
291 PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT);
292 FUNC_GROUP_DECL(NDCD3, C20);
293
294 FUNC_GROUP_DECL(GPIE0, B20, C20);
295
296 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
297
298 #define F18 34
299 SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
300 SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
301 SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
302 SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE);
303 PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN);
304 FUNC_GROUP_DECL(NDSR3, F18);
305
306
307 #define F17 35
308 SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
309 SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
310 SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
311 SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE);
312 PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT);
313 FUNC_GROUP_DECL(NRI3, F17);
314
315 FUNC_GROUP_DECL(GPIE2, F18, F17);
316
317 #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
318
319 #define E18 36
320 SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
321 SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
322 SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
323 SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE);
324 PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN);
325 FUNC_GROUP_DECL(NDTR3, E18);
326
327 #define D19 37
328 SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
329 SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
330 SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
331 SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE);
332 PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT);
333 FUNC_GROUP_DECL(NRTS3, D19);
334
335 FUNC_GROUP_DECL(GPIE4, E18, D19);
336
337 #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
338
339 #define A20 38
340 SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
341 SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
342 SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
343 SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE);
344 PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN);
345 FUNC_GROUP_DECL(TXD3, A20);
346
347 #define B19 39
348 SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
349 SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
350 SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
351 SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE);
352 PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT);
353 FUNC_GROUP_DECL(RXD3, B19);
354
355 FUNC_GROUP_DECL(GPIE6, A20, B19);
356
357 #define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0)
358 #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
359
360 #define J19 40
361 SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC);
362 SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC);
363 SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS);
364 SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
365 PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4);
366 FUNC_GROUP_DECL(NCTS4, J19);
367
368 #define J18 41
369 SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC);
370 SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC);
371 SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS);
372 SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
373 PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4);
374 FUNC_GROUP_DECL(NDCD4, J18);
375
376 #define B22 42
377 SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC);
378 SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC);
379 SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS);
380 SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
381 PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4);
382 FUNC_GROUP_DECL(NDSR4, B22);
383
384 #define B21 43
385 SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC);
386 SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC);
387 SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS);
388 SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
389 PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4);
390 FUNC_GROUP_DECL(NRI4, B21);
391
392 #define A21 44
393 SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC);
394 SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC);
395 SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS);
396 SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
397 PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4);
398 FUNC_GROUP_DECL(NDTR4, A21);
399
400 #define H19 45
401 SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC);
402 SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC);
403 SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS);
404 SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
405 PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4);
406 FUNC_GROUP_DECL(NRTS4, H19);
407
408 #define G17 46
409 SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC);
410 SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
411 PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4);
412 FUNC_GROUP_DECL(TXD4, G17);
413
414 #define H18 47
415 SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC);
416 SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC);
417 SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS);
418 SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
419 PIN_DECL_2(H18, GPIOF7, LHRST, RXD4);
420 FUNC_GROUP_DECL(RXD4, H18);
421
422 FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
423 FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
424
425 #define A19 48
426 SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
427 PIN_DECL_1(A19, GPIOG0, SGPS1CK);
428
429 #define E19 49
430 SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
431 PIN_DECL_1(E19, GPIOG1, SGPS1LD);
432
433 #define C19 50
434 SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
435 PIN_DECL_1(C19, GPIOG2, SGPS1I0);
436
437 #define E16 51
438 SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
439 PIN_DECL_1(E16, GPIOG3, SGPS1I1);
440
441 FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
442
443 #define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
444
445 #define E17 52
446 SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC);
447 SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
448 PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1);
449 FUNC_GROUP_DECL(SALT1, E17);
450
451 #define D16 53
452 SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC);
453 SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
454 PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2);
455 FUNC_GROUP_DECL(SALT2, D16);
456
457 #define D15 54
458 SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC);
459 SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
460 PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3);
461 FUNC_GROUP_DECL(SALT3, D15);
462
463 #define E14 55
464 SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC);
465 SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
466 PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4);
467 FUNC_GROUP_DECL(SALT4, E14);
468
469 FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
470
471 #define UART6_DESC SIG_DESC_SET(SCU90, 7)
472
473 #define A18 56
474 SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
475 SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC);
476 PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6);
477
478 #define B18 57
479 SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
480 SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC);
481 PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6);
482
483 #define D17 58
484 SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
485 SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC);
486 PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6);
487
488 #define C17 59
489 SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
490 SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC);
491 PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6);
492
493 #define A17 60
494 SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
495 SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC);
496 PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6);
497
498 #define B17 61
499 SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
500 SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC);
501 PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6);
502
503 #define A16 62
504 SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC);
505 PIN_DECL_1(A16, GPIOH6, TXD6);
506
507 #define D18 63
508 SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC);
509 PIN_DECL_1(D18, GPIOH7, RXD6);
510
511 FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
512
513 #define SPI1_DESC \
514 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
515 #define SPI1DEBUG_DESC \
516 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
517 #define SPI1PASSTHRU_DESC \
518 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
519
520 #define C18 64
521 SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
522 SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
523 SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
524 PIN_DECL_1(C18, GPIOI0, SYSCS);
525
526 #define E15 65
527 SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
528 SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
529 SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
530 PIN_DECL_1(E15, GPIOI1, SYSCK);
531
532 #define B16 66
533 SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
534 SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
535 SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
536 PIN_DECL_1(B16, GPIOI2, SYSMOSI);
537
538 #define C16 67
539 SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
540 SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
541 SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
542 PIN_DECL_1(C16, GPIOI3, SYSMISO);
543
544 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
545
546 #define B15 68
547 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC);
548 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
549 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
550 SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
551 SIG_EXPR_PTR(SPI1CS0, SPI1),
552 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
553 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
554 SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1);
555 SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC);
556 PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS);
557
558 #define C15 69
559 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC);
560 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
561 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
562 SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
563 SIG_EXPR_PTR(SPI1CK, SPI1),
564 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
565 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
566 SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1);
567 SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC);
568 PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK);
569
570 #define A14 70
571 SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC);
572 SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
573 SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
574 SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1,
575 SIG_EXPR_PTR(SPI1MOSI, SPI1),
576 SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
577 SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
578 SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1);
579 SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC);
580 PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI);
581
582 #define A15 71
583 SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC);
584 SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
585 SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
586 SIG_EXPR_LIST_DECL(SPI1MISO, SPI1,
587 SIG_EXPR_PTR(SPI1MISO, SPI1),
588 SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
589 SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
590 SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
591 SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
592 PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
593
594 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
595 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
596 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
597 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
598
599 #define R2 72
600 SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
601 PIN_DECL_1(R2, GPIOJ0, SGPMCK);
602
603 #define L2 73
604 SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
605 PIN_DECL_1(L2, GPIOJ1, SGPMLD);
606
607 #define N3 74
608 SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
609 PIN_DECL_1(N3, GPIOJ2, SGPMO);
610
611 #define N4 75
612 SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
613 PIN_DECL_1(N4, GPIOJ3, SGPMI);
614
615 FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
616
617 #define N5 76
618 SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
619 SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
620 PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5);
621 FUNC_GROUP_DECL(VGAHS, N5);
622
623 #define R4 77
624 SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
625 SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
626 PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4);
627 FUNC_GROUP_DECL(VGAVS, R4);
628
629 #define R3 78
630 SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
631 SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
632 PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3);
633 FUNC_GROUP_DECL(DDCCLK, R3);
634
635 #define T3 79
636 SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
637 SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
638 PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3);
639 FUNC_GROUP_DECL(DDCDAT, T3);
640
641 #define I2C5_DESC SIG_DESC_SET(SCU90, 18)
642
643 #define L3 80
644 SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC);
645 PIN_DECL_1(L3, GPIOK0, SCL5);
646
647 #define L4 81
648 SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC);
649 PIN_DECL_1(L4, GPIOK1, SDA5);
650
651 FUNC_GROUP_DECL(I2C5, L3, L4);
652
653 #define I2C6_DESC SIG_DESC_SET(SCU90, 19)
654
655 #define L1 82
656 SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
657 PIN_DECL_1(L1, GPIOK2, SCL6);
658
659 #define N2 83
660 SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
661 PIN_DECL_1(N2, GPIOK3, SDA6);
662
663 FUNC_GROUP_DECL(I2C6, L1, N2);
664
665 #define I2C7_DESC SIG_DESC_SET(SCU90, 20)
666
667 #define N1 84
668 SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
669 PIN_DECL_1(N1, GPIOK4, SCL7);
670
671 #define P1 85
672 SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC);
673 PIN_DECL_1(P1, GPIOK5, SDA7);
674
675 FUNC_GROUP_DECL(I2C7, N1, P1);
676
677 #define I2C8_DESC SIG_DESC_SET(SCU90, 21)
678
679 #define P2 86
680 SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC);
681 PIN_DECL_1(P2, GPIOK6, SCL8);
682
683 #define R1 87
684 SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC);
685 PIN_DECL_1(R1, GPIOK7, SDA8);
686
687 FUNC_GROUP_DECL(I2C8, P2, R1);
688
689 #define T2 88
690 SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
691
692 #define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
693 #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
694 #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
695 #define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
696 #define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
697
698 #define T1 89
699 #define T1_DESC SIG_DESC_SET(SCU84, 17)
700 SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
701 SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2);
702 PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1);
703 FUNC_GROUP_DECL(NDCD1, T1);
704
705 #define U1 90
706 #define U1_DESC SIG_DESC_SET(SCU84, 18)
707 SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
708 SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC);
709 PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1);
710 FUNC_GROUP_DECL(NDSR1, U1);
711
712 #define U2 91
713 #define U2_DESC SIG_DESC_SET(SCU84, 19)
714 SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
715 SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2);
716 PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1);
717 FUNC_GROUP_DECL(NRI1, U2);
718
719 #define P4 92
720 #define P4_DESC SIG_DESC_SET(SCU84, 20)
721 SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
722 SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
723 PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
724 FUNC_GROUP_DECL(NDTR1, P4);
725
726 #define P3 93
727 #define P3_DESC SIG_DESC_SET(SCU84, 21)
728 SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
729 SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2);
730 PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1);
731 FUNC_GROUP_DECL(NRTS1, P3);
732
733 #define V1 94
734 #define V1_DESC SIG_DESC_SET(SCU84, 22)
735 SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
736 SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2);
737 PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1);
738 FUNC_GROUP_DECL(TXD1, V1);
739
740 #define W1 95
741 #define W1_DESC SIG_DESC_SET(SCU84, 23)
742 SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
743 SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2);
744 PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1);
745 FUNC_GROUP_DECL(RXD1, W1);
746
747 #define Y1 96
748 #define Y1_DESC SIG_DESC_SET(SCU84, 24)
749 SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
750 SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2);
751 PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2);
752 FUNC_GROUP_DECL(NCTS2, Y1);
753
754 #define AB2 97
755 #define AB2_DESC SIG_DESC_SET(SCU84, 25)
756 SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
757 SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2);
758 PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2);
759 FUNC_GROUP_DECL(NDCD2, AB2);
760
761 #define AA1 98
762 #define AA1_DESC SIG_DESC_SET(SCU84, 26)
763 SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
764 SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2);
765 PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2);
766 FUNC_GROUP_DECL(NDSR2, AA1);
767
768 #define Y2 99
769 #define Y2_DESC SIG_DESC_SET(SCU84, 27)
770 SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
771 SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2);
772 PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2);
773 FUNC_GROUP_DECL(NRI2, Y2);
774
775 #define AA2 100
776 #define AA2_DESC SIG_DESC_SET(SCU84, 28)
777 SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
778 SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2);
779 PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2);
780 FUNC_GROUP_DECL(NDTR2, AA2);
781
782 #define P5 101
783 #define P5_DESC SIG_DESC_SET(SCU84, 29)
784 SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
785 SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2);
786 PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2);
787 FUNC_GROUP_DECL(NRTS2, P5);
788
789 #define R5 102
790 #define R5_DESC SIG_DESC_SET(SCU84, 30)
791 SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
792 SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2);
793 PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2);
794 FUNC_GROUP_DECL(TXD2, R5);
795
796 #define T5 103
797 #define T5_DESC SIG_DESC_SET(SCU84, 31)
798 SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
799 SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2);
800 PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2);
801 FUNC_GROUP_DECL(RXD2, T5);
802
803 #define V2 104
804 #define V2_DESC SIG_DESC_SET(SCU88, 0)
805 SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
806 SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2);
807 PIN_DECL_2(V2, GPION0, DASHN0, PWM0);
808 FUNC_GROUP_DECL(PWM0, V2);
809
810 #define W2 105
811 #define W2_DESC SIG_DESC_SET(SCU88, 1)
812 SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
813 SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2);
814 PIN_DECL_2(W2, GPION1, DASHN1, PWM1);
815 FUNC_GROUP_DECL(PWM1, W2);
816
817 #define V3 106
818 #define V3_DESC SIG_DESC_SET(SCU88, 2)
819 SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
820 SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
821 SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD);
822 SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2);
823 PIN_DECL_2(V3, GPION2, VPIG2, PWM2);
824 FUNC_GROUP_DECL(PWM2, V3);
825
826 #define U3 107
827 #define U3_DESC SIG_DESC_SET(SCU88, 3)
828 SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
829 SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
830 SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD);
831 SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2);
832 PIN_DECL_2(U3, GPION3, VPIG3, PWM3);
833 FUNC_GROUP_DECL(PWM3, U3);
834
835 #define W3 108
836 #define W3_DESC SIG_DESC_SET(SCU88, 4)
837 SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
838 SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
839 SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD);
840 SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2);
841 PIN_DECL_2(W3, GPION4, VPIG4, PWM4);
842 FUNC_GROUP_DECL(PWM4, W3);
843
844 #define AA3 109
845 #define AA3_DESC SIG_DESC_SET(SCU88, 5)
846 SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
847 SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
848 SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD);
849 SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2);
850 PIN_DECL_2(AA3, GPION5, VPIG5, PWM5);
851 FUNC_GROUP_DECL(PWM5, AA3);
852
853 #define Y3 110
854 #define Y3_DESC SIG_DESC_SET(SCU88, 6)
855 SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC);
856 SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2);
857 PIN_DECL_2(Y3, GPION6, VPIG6, PWM6);
858 FUNC_GROUP_DECL(PWM6, Y3);
859
860 #define T4 111
861 #define T4_DESC SIG_DESC_SET(SCU88, 7)
862 SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC);
863 SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2);
864 PIN_DECL_2(T4, GPION7, VPIG7, PWM7);
865 FUNC_GROUP_DECL(PWM7, T4);
866
867 #define U5 112
868 SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
869 COND2);
870 PIN_DECL_1(U5, GPIOO0, VPIG8);
871
872 #define U4 113
873 SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
874 COND2);
875 PIN_DECL_1(U4, GPIOO1, VPIG9);
876
877 #define V5 114
878 SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC,
879 SIG_DESC_SET(SCU88, 10));
880 PIN_DECL_1(V5, GPIOO2, DASHV5);
881
882 #define AB4 115
883 SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
884 SIG_DESC_SET(SCU88, 11));
885 PIN_DECL_1(AB4, GPIOO3, DASHAB4);
886
887 #define AB3 116
888 SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC,
889 SIG_DESC_SET(SCU88, 12), COND2);
890 PIN_DECL_1(AB3, GPIOO4, VPIR2);
891
892 #define Y4 117
893 SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC,
894 SIG_DESC_SET(SCU88, 13), COND2);
895 PIN_DECL_1(Y4, GPIOO5, VPIR3);
896
897 #define AA4 118
898 SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC,
899 SIG_DESC_SET(SCU88, 14), COND2);
900 PIN_DECL_1(AA4, GPIOO6, VPIR4);
901
902 #define W4 119
903 SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC,
904 SIG_DESC_SET(SCU88, 15), COND2);
905 PIN_DECL_1(W4, GPIOO7, VPIR5);
906
907 #define V4 120
908 SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC,
909 SIG_DESC_SET(SCU88, 16), COND2);
910 PIN_DECL_1(V4, GPIOP0, VPIR6);
911
912 #define W5 121
913 SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC,
914 SIG_DESC_SET(SCU88, 17), COND2);
915 PIN_DECL_1(W5, GPIOP1, VPIR7);
916
917 #define AA5 122
918 SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC,
919 SIG_DESC_SET(SCU88, 18), COND2);
920 PIN_DECL_1(AA5, GPIOP2, VPIR8);
921
922 #define AB5 123
923 SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC,
924 SIG_DESC_SET(SCU88, 19), COND2);
925 PIN_DECL_1(AB5, GPIOP3, VPIR9);
926
927 FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
928 U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
929 AB5);
930
931 #define Y6 124
932 SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
933 SIG_DESC_SET(SCU88, 20));
934 PIN_DECL_1(Y6, GPIOP4, DASHY6);
935
936 #define Y5 125
937 SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
938 SIG_DESC_SET(SCU88, 21));
939 PIN_DECL_1(Y5, GPIOP5, DASHY5);
940
941 #define W6 126
942 SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
943 SIG_DESC_SET(SCU88, 22));
944 PIN_DECL_1(W6, GPIOP6, DASHW6);
945
946 #define V6 127
947 SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
948 SIG_DESC_SET(SCU88, 23));
949 PIN_DECL_1(V6, GPIOP7, DASHV6);
950
951 #define I2C3_DESC SIG_DESC_SET(SCU90, 16)
952
953 #define A11 128
954 SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC);
955 PIN_DECL_1(A11, GPIOQ0, SCL3);
956
957 #define A10 129
958 SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC);
959 PIN_DECL_1(A10, GPIOQ1, SDA3);
960
961 FUNC_GROUP_DECL(I2C3, A11, A10);
962
963 #define I2C4_DESC SIG_DESC_SET(SCU90, 17)
964
965 #define A9 130
966 SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC);
967 PIN_DECL_1(A9, GPIOQ2, SCL4);
968
969 #define B9 131
970 SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC);
971 PIN_DECL_1(B9, GPIOQ3, SDA4);
972
973 FUNC_GROUP_DECL(I2C4, A9, B9);
974
975 #define I2C14_DESC SIG_DESC_SET(SCU90, 27)
976
977 #define N21 132
978 SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC);
979 PIN_DECL_1(N21, GPIOQ4, SCL14);
980
981 #define N22 133
982 SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC);
983 PIN_DECL_1(N22, GPIOQ5, SDA14);
984
985 FUNC_GROUP_DECL(I2C14, N21, N22);
986
987 #define B10 134
988 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
989
990 #define N20 135
991 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
992
993 #define AA19 136
994 SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
995
996 #define T19 137
997 SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
998
999 #define T17 138
1000 SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
1001
1002 #define Y19 139
1003 SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
1004
1005 #define W19 140
1006 SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
1007
1008 #define V19 141
1009 SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
1010
1011 #define D8 142
1012 SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
1013 PIN_DECL_1(D8, GPIOR6, MDC1);
1014
1015 #define E10 143
1016 SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
1017 PIN_DECL_1(E10, GPIOR7, MDIO1);
1018
1019 FUNC_GROUP_DECL(MDIO1, D8, E10);
1020
1021 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
1022 #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
1023 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
1024 #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
1025
1026 #define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
1027
1028 #define V20 144
1029 #define V20_DESC SIG_DESC_SET(SCU8C, 0)
1030 SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1031 SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1032 SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1033 SIG_EXPR_LIST_DECL(VPOB2, VPO,
1034 SIG_EXPR_PTR(VPOB2, VPO),
1035 SIG_EXPR_PTR(VPOB2, VPOOFF1),
1036 SIG_EXPR_PTR(VPOB2, VPOOFF2));
1037 SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO);
1038 SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC);
1039 PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1);
1040 FUNC_GROUP_DECL(SPI2CS1, V20);
1041
1042 #define U19 145
1043 #define U19_DESC SIG_DESC_SET(SCU8C, 1)
1044 SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1045 SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1046 SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1047 SIG_EXPR_LIST_DECL(VPOB3, VPO,
1048 SIG_EXPR_PTR(VPOB3, VPO),
1049 SIG_EXPR_PTR(VPOB3, VPOOFF1),
1050 SIG_EXPR_PTR(VPOB3, VPOOFF2));
1051 SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO);
1052 SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC);
1053 PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT);
1054 FUNC_GROUP_DECL(BMCINT, U19);
1055
1056 #define R18 146
1057 #define R18_DESC SIG_DESC_SET(SCU8C, 2)
1058 SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1059 SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1060 SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1061 SIG_EXPR_LIST_DECL(VPOB4, VPO,
1062 SIG_EXPR_PTR(VPOB4, VPO),
1063 SIG_EXPR_PTR(VPOB4, VPOOFF1),
1064 SIG_EXPR_PTR(VPOB4, VPOOFF2));
1065 SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO);
1066 SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC);
1067 PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5);
1068 FUNC_GROUP_DECL(SALT5, R18);
1069
1070 #define P18 147
1071 #define P18_DESC SIG_DESC_SET(SCU8C, 3)
1072 SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1073 SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1074 SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1075 SIG_EXPR_LIST_DECL(VPOB5, VPO,
1076 SIG_EXPR_PTR(VPOB5, VPO),
1077 SIG_EXPR_PTR(VPOB5, VPOOFF1),
1078 SIG_EXPR_PTR(VPOB5, VPOOFF2));
1079 SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO);
1080 SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC);
1081 PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6);
1082 FUNC_GROUP_DECL(SALT6, P18);
1083
1084 #define R19 148
1085 #define R19_DESC SIG_DESC_SET(SCU8C, 4)
1086 SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1087 SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1088 SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1089 SIG_EXPR_LIST_DECL(VPOB6, VPO,
1090 SIG_EXPR_PTR(VPOB6, VPO),
1091 SIG_EXPR_PTR(VPOB6, VPOOFF1),
1092 SIG_EXPR_PTR(VPOB6, VPOOFF2));
1093 SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO);
1094 PIN_DECL_1(R19, GPIOS4, VPOB6);
1095
1096 #define W20 149
1097 #define W20_DESC SIG_DESC_SET(SCU8C, 5)
1098 SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1099 SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1100 SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1101 SIG_EXPR_LIST_DECL(VPOB7, VPO,
1102 SIG_EXPR_PTR(VPOB7, VPO),
1103 SIG_EXPR_PTR(VPOB7, VPOOFF1),
1104 SIG_EXPR_PTR(VPOB7, VPOOFF2));
1105 SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO);
1106 PIN_DECL_1(W20, GPIOS5, VPOB7);
1107
1108 #define U20 150
1109 #define U20_DESC SIG_DESC_SET(SCU8C, 6)
1110 SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1111 SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1112 SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1113 SIG_EXPR_LIST_DECL(VPOB8, VPO,
1114 SIG_EXPR_PTR(VPOB8, VPO),
1115 SIG_EXPR_PTR(VPOB8, VPOOFF1),
1116 SIG_EXPR_PTR(VPOB8, VPOOFF2));
1117 SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO);
1118 PIN_DECL_1(U20, GPIOS6, VPOB8);
1119
1120 #define AA20 151
1121 #define AA20_DESC SIG_DESC_SET(SCU8C, 7)
1122 SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1123 SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1124 SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1125 SIG_EXPR_LIST_DECL(VPOB9, VPO,
1126 SIG_EXPR_PTR(VPOB9, VPO),
1127 SIG_EXPR_PTR(VPOB9, VPOOFF1),
1128 SIG_EXPR_PTR(VPOB9, VPOOFF2));
1129 SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO);
1130 PIN_DECL_1(AA20, GPIOS7, VPOB9);
1131
1132 /* RGMII1/RMII1 */
1133
1134 #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
1135 #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
1136
1137 #define B5 152
1138 SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
1139 SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC,
1140 SIG_DESC_SET(SCU48, 29));
1141 SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1);
1142 PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO),
1143 SIG_EXPR_LIST_PTR(B5, RGMII1TXCK));
1144
1145 #define E9 153
1146 SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
1147 SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC);
1148 SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1);
1149 PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN),
1150 SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL));
1151
1152 #define F9 154
1153 SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
1154 SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC);
1155 SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1);
1156 PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0),
1157 SIG_EXPR_LIST_PTR(F9, RGMII1TXD0));
1158
1159 #define A5 155
1160 SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
1161 SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC);
1162 SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1);
1163 PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1),
1164 SIG_EXPR_LIST_PTR(A5, RGMII1TXD1));
1165
1166 #define E7 156
1167 SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
1168 SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC);
1169 SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1);
1170 PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0),
1171 SIG_EXPR_LIST_PTR(E7, RGMII1TXD2));
1172
1173 #define D7 157
1174 SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
1175 SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC);
1176 SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1);
1177 PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1),
1178 SIG_EXPR_LIST_PTR(D7, RGMII1TXD3));
1179
1180 #define B2 158
1181 SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
1182 SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC,
1183 SIG_DESC_SET(SCU48, 30));
1184 SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2);
1185 PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO),
1186 SIG_EXPR_LIST_PTR(B2, RGMII2TXCK));
1187
1188 #define B1 159
1189 SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
1190 SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC);
1191 SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2);
1192 PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN),
1193 SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL));
1194
1195 #define A2 160
1196 SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
1197 SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC);
1198 SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2);
1199 PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0),
1200 SIG_EXPR_LIST_PTR(A2, RGMII2TXD0));
1201
1202 #define B3 161
1203 SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
1204 SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC);
1205 SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2);
1206 PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1),
1207 SIG_EXPR_LIST_PTR(B3, RGMII2TXD1));
1208
1209 #define D5 162
1210 SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
1211 SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC);
1212 SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2);
1213 PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0),
1214 SIG_EXPR_LIST_PTR(D5, RGMII2TXD2));
1215
1216 #define D4 163
1217 SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
1218 SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC);
1219 SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2);
1220 PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1),
1221 SIG_EXPR_LIST_PTR(D4, RGMII2TXD3));
1222
1223 #define B4 164
1224 SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
1225 SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC);
1226 SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1);
1227 PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI),
1228 SIG_EXPR_LIST_PTR(B4, RGMII1RXCK));
1229
1230 #define A4 165
1231 SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
1232 SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC);
1233 SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1);
1234 PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2),
1235 SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL));
1236
1237 #define A3 166
1238 SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
1239 SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC);
1240 SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1);
1241 PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0),
1242 SIG_EXPR_LIST_PTR(A3, RGMII1RXD0));
1243
1244 #define D6 167
1245 SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
1246 SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC);
1247 SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1);
1248 PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1),
1249 SIG_EXPR_LIST_PTR(D6, RGMII1RXD1));
1250
1251 #define C5 168
1252 SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
1253 SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
1254 SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
1255 PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
1256 SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
1257
1258 #define C4 169
1259 SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
1260 SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC);
1261 SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1);
1262 PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER),
1263 SIG_EXPR_LIST_PTR(C4, RGMII1RXD3));
1264
1265 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
1266 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
1267
1268 #define C2 170
1269 SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
1270 SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC);
1271 SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2);
1272 PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI),
1273 SIG_EXPR_LIST_PTR(C2, RGMII2RXCK));
1274
1275 #define C1 171
1276 SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
1277 SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC);
1278 SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2);
1279 PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2),
1280 SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL));
1281
1282 #define C3 172
1283 SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
1284 SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC);
1285 SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2);
1286 PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0),
1287 SIG_EXPR_LIST_PTR(C3, RGMII2RXD0));
1288
1289 #define D1 173
1290 SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
1291 SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC);
1292 SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2);
1293 PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1),
1294 SIG_EXPR_LIST_PTR(D1, RGMII2RXD1));
1295
1296 #define D2 174
1297 SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
1298 SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC);
1299 SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2);
1300 PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV),
1301 SIG_EXPR_LIST_PTR(D2, RGMII2RXD2));
1302
1303 #define E6 175
1304 SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
1305 SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC);
1306 SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2);
1307 PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER),
1308 SIG_EXPR_LIST_PTR(E6, RGMII2RXD3));
1309
1310 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
1311 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
1312
1313 #define F4 176
1314 SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
1315 SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0);
1316 PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0));
1317 FUNC_GROUP_DECL(ADC0, F4);
1318
1319 #define F5 177
1320 SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
1321 SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1);
1322 PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1));
1323 FUNC_GROUP_DECL(ADC1, F5);
1324
1325 #define E2 178
1326 SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
1327 SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2);
1328 PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2));
1329 FUNC_GROUP_DECL(ADC2, E2);
1330
1331 #define E1 179
1332 SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
1333 SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3);
1334 PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3));
1335 FUNC_GROUP_DECL(ADC3, E1);
1336
1337 #define F3 180
1338 SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
1339 SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4);
1340 PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4));
1341 FUNC_GROUP_DECL(ADC4, F3);
1342
1343 #define E3 181
1344 SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
1345 SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5);
1346 PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5));
1347 FUNC_GROUP_DECL(ADC5, E3);
1348
1349 #define G5 182
1350 SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
1351 SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6);
1352 PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6));
1353 FUNC_GROUP_DECL(ADC6, G5);
1354
1355 #define G4 183
1356 SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
1357 SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7);
1358 PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7));
1359 FUNC_GROUP_DECL(ADC7, G4);
1360
1361 #define F2 184
1362 SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
1363 SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8);
1364 PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8));
1365 FUNC_GROUP_DECL(ADC8, F2);
1366
1367 #define G3 185
1368 SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
1369 SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9);
1370 PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9));
1371 FUNC_GROUP_DECL(ADC9, G3);
1372
1373 #define G2 186
1374 SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
1375 SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10);
1376 PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10));
1377 FUNC_GROUP_DECL(ADC10, G2);
1378
1379 #define F1 187
1380 SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
1381 SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11);
1382 PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11));
1383 FUNC_GROUP_DECL(ADC11, F1);
1384
1385 #define H5 188
1386 SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
1387 SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12);
1388 PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12));
1389 FUNC_GROUP_DECL(ADC12, H5);
1390
1391 #define G1 189
1392 SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
1393 SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13);
1394 PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13));
1395 FUNC_GROUP_DECL(ADC13, G1);
1396
1397 #define H3 190
1398 SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
1399 SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14);
1400 PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14));
1401 FUNC_GROUP_DECL(ADC14, H3);
1402
1403 #define H4 191
1404 SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
1405 SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15);
1406 PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15));
1407 FUNC_GROUP_DECL(ADC15, H4);
1408
1409 #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
1410
1411 #define R22 192
1412 SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
1413 SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
1414 SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI);
1415 SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
1416 PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22);
1417 FUNC_GROUP_DECL(SIOS3, R22);
1418
1419 #define R21 193
1420 SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
1421 SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
1422 SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI);
1423 SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
1424 PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21);
1425 FUNC_GROUP_DECL(SIOS5, R21);
1426
1427 #define P22 194
1428 SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
1429 SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
1430 SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI);
1431 SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
1432 PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22);
1433 FUNC_GROUP_DECL(SIOPWREQ, P22);
1434
1435 #define P21 195
1436 SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
1437 SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
1438 SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI);
1439 SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
1440 PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21);
1441 FUNC_GROUP_DECL(SIOONCTRL, P21);
1442
1443 #define M18 196
1444 SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
1445
1446 #define M19 197
1447 SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
1448
1449 #define M20 198
1450 SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
1451
1452 #define P20 199
1453 SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
1454
1455 #define PNOR_DESC SIG_DESC_SET(SCU90, 31)
1456
1457 #define Y20 200
1458 #define Y20_DESC SIG_DESC_SET(SCUA4, 16)
1459 SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1460 SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1461 SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1462 SIG_EXPR_LIST_DECL(VPOG2, VPO,
1463 SIG_EXPR_PTR(VPOG2, VPO),
1464 SIG_EXPR_PTR(VPOG2, VPOOFF1),
1465 SIG_EXPR_PTR(VPOG2, VPOOFF2));
1466 SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO);
1467 SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC);
1468 SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC);
1469 SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI);
1470 SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC);
1471 SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0);
1472 PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI),
1473 SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0));
1474 FUNC_GROUP_DECL(SIOPBI, Y20);
1475
1476 #define AB20 201
1477 #define AB20_DESC SIG_DESC_SET(SCUA4, 17)
1478 SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1479 SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1480 SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1481 SIG_EXPR_LIST_DECL(VPOG3, VPO,
1482 SIG_EXPR_PTR(VPOG3, VPO),
1483 SIG_EXPR_PTR(VPOG3, VPOOFF1),
1484 SIG_EXPR_PTR(VPOG3, VPOOFF2));
1485 SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO);
1486 SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC);
1487 SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC);
1488 SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI);
1489 SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC);
1490 SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1);
1491 PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3),
1492 SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1),
1493 SIG_EXPR_LIST_PTR(AB20, GPIOZ1));
1494 FUNC_GROUP_DECL(SIOPWRGD, AB20);
1495
1496 #define AB21 202
1497 #define AB21_DESC SIG_DESC_SET(SCUA4, 18)
1498 SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1499 SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1500 SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1501 SIG_EXPR_LIST_DECL(VPOG4, VPO,
1502 SIG_EXPR_PTR(VPOG4, VPO),
1503 SIG_EXPR_PTR(VPOG4, VPOOFF1),
1504 SIG_EXPR_PTR(VPOG4, VPOOFF2));
1505 SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO);
1506 SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC);
1507 SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC);
1508 SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI);
1509 SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC);
1510 SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2);
1511 PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4),
1512 SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2),
1513 SIG_EXPR_LIST_PTR(AB21, GPIOZ2));
1514 FUNC_GROUP_DECL(SIOPBO, AB21);
1515
1516 #define AA21 203
1517 #define AA21_DESC SIG_DESC_SET(SCUA4, 19)
1518 SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1519 SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1520 SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1521 SIG_EXPR_LIST_DECL(VPOG5, VPO,
1522 SIG_EXPR_PTR(VPOG5, VPO),
1523 SIG_EXPR_PTR(VPOG5, VPOOFF1),
1524 SIG_EXPR_PTR(VPOG5, VPOOFF2));
1525 SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO);
1526 SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC);
1527 SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC);
1528 SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI);
1529 SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC);
1530 SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3);
1531 PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5),
1532 SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3),
1533 SIG_EXPR_LIST_PTR(AA21, GPIOZ3));
1534 FUNC_GROUP_DECL(SIOSCI, AA21);
1535
1536 FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
1537
1538 /* CRT DVO disabled, configured for single-edge mode */
1539 #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
1540
1541 /* CRT DVO disabled, configured for dual-edge mode */
1542 #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
1543
1544 /* CRT DVO enabled, configured for single-edge mode */
1545 #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
1546
1547 /* CRT DVO enabled, configured for dual-edge mode */
1548 #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
1549
1550 #define U21 204
1551 #define U21_DESC SIG_DESC_SET(SCUA4, 20)
1552 SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1553 SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1554 SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1555 SIG_EXPR_LIST_DECL(VPOG6, VPO,
1556 SIG_EXPR_PTR(VPOG6, VPO),
1557 SIG_EXPR_PTR(VPOG6, VPOOFF1),
1558 SIG_EXPR_PTR(VPOG6, VPOOFF2));
1559 SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO);
1560 SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC);
1561 PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4);
1562
1563 #define W22 205
1564 #define W22_DESC SIG_DESC_SET(SCUA4, 21)
1565 SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1566 SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1567 SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1568 SIG_EXPR_LIST_DECL(VPOG7, VPO,
1569 SIG_EXPR_PTR(VPOG7, VPO),
1570 SIG_EXPR_PTR(VPOG7, VPOOFF1),
1571 SIG_EXPR_PTR(VPOG7, VPOOFF2));
1572 SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO);
1573 SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC);
1574 PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5);
1575
1576 #define V22 206
1577 #define V22_DESC SIG_DESC_SET(SCUA4, 22)
1578 SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1579 SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1580 SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1581 SIG_EXPR_LIST_DECL(VPOG8, VPO,
1582 SIG_EXPR_PTR(VPOG8, VPO),
1583 SIG_EXPR_PTR(VPOG8, VPOOFF1),
1584 SIG_EXPR_PTR(VPOG8, VPOOFF2));
1585 SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO);
1586 SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC);
1587 PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6);
1588
1589 #define W21 207
1590 #define W21_DESC SIG_DESC_SET(SCUA4, 23)
1591 SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1592 SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1593 SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1594 SIG_EXPR_LIST_DECL(VPOG9, VPO,
1595 SIG_EXPR_PTR(VPOG9, VPO),
1596 SIG_EXPR_PTR(VPOG9, VPOOFF1),
1597 SIG_EXPR_PTR(VPOG9, VPOOFF2));
1598 SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO);
1599 SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC);
1600 PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7);
1601
1602 #define Y21 208
1603 #define Y21_DESC SIG_DESC_SET(SCUA4, 24)
1604 SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1605 SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1606 SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1607 SIG_EXPR_LIST_DECL(VPOR2, VPO,
1608 SIG_EXPR_PTR(VPOR2, VPO),
1609 SIG_EXPR_PTR(VPOR2, VPOOFF1),
1610 SIG_EXPR_PTR(VPOR2, VPOOFF2));
1611 SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO);
1612 SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC);
1613 SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC);
1614 SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0);
1615 PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7),
1616 SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0));
1617 FUNC_GROUP_DECL(SALT7, Y21);
1618
1619 #define V21 209
1620 #define V21_DESC SIG_DESC_SET(SCUA4, 25)
1621 SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1622 SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1623 SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1624 SIG_EXPR_LIST_DECL(VPOR3, VPO,
1625 SIG_EXPR_PTR(VPOR3, VPO),
1626 SIG_EXPR_PTR(VPOR3, VPOOFF1),
1627 SIG_EXPR_PTR(VPOR3, VPOOFF2));
1628 SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO);
1629 SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC);
1630 SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC);
1631 SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1);
1632 PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8),
1633 SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1));
1634 FUNC_GROUP_DECL(SALT8, V21);
1635
1636 #define Y22 210
1637 #define Y22_DESC SIG_DESC_SET(SCUA4, 26)
1638 SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1639 SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1640 SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1641 SIG_EXPR_LIST_DECL(VPOR4, VPO,
1642 SIG_EXPR_PTR(VPOR4, VPO),
1643 SIG_EXPR_PTR(VPOR4, VPOOFF1),
1644 SIG_EXPR_PTR(VPOR4, VPOOFF2));
1645 SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO);
1646 SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC);
1647 SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC);
1648 SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2);
1649 PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9),
1650 SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2));
1651 FUNC_GROUP_DECL(SALT9, Y22);
1652
1653 #define AA22 211
1654 #define AA22_DESC SIG_DESC_SET(SCUA4, 27)
1655 SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1656 SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1657 SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1658 SIG_EXPR_LIST_DECL(VPOR5, VPO,
1659 SIG_EXPR_PTR(VPOR5, VPO),
1660 SIG_EXPR_PTR(VPOR5, VPOOFF1),
1661 SIG_EXPR_PTR(VPOR5, VPOOFF2));
1662 SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO);
1663 SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC);
1664 SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC);
1665 SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3);
1666 PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5),
1667 SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3),
1668 SIG_EXPR_LIST_PTR(AA22, GPIOAA3));
1669 FUNC_GROUP_DECL(SALT10, AA22);
1670
1671 #define U22 212
1672 #define U22_DESC SIG_DESC_SET(SCUA4, 28)
1673 SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1674 SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1675 SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1676 SIG_EXPR_LIST_DECL(VPOR6, VPO,
1677 SIG_EXPR_PTR(VPOR6, VPO),
1678 SIG_EXPR_PTR(VPOR6, VPOOFF1),
1679 SIG_EXPR_PTR(VPOR6, VPOOFF2));
1680 SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO);
1681 SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC);
1682 SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC);
1683 SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4);
1684 PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11),
1685 SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4));
1686 FUNC_GROUP_DECL(SALT11, U22);
1687
1688 #define T20 213
1689 #define T20_DESC SIG_DESC_SET(SCUA4, 29)
1690 SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1691 SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1692 SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1693 SIG_EXPR_LIST_DECL(VPOR7, VPO,
1694 SIG_EXPR_PTR(VPOR7, VPO),
1695 SIG_EXPR_PTR(VPOR7, VPOOFF1),
1696 SIG_EXPR_PTR(VPOR7, VPOOFF2));
1697 SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO);
1698 SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC);
1699 SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC);
1700 SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5);
1701 PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12),
1702 SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5));
1703 FUNC_GROUP_DECL(SALT12, T20);
1704
1705 #define N18 214
1706 #define N18_DESC SIG_DESC_SET(SCUA4, 30)
1707 SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1708 SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1709 SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1710 SIG_EXPR_LIST_DECL(VPOR8, VPO,
1711 SIG_EXPR_PTR(VPOR8, VPO),
1712 SIG_EXPR_PTR(VPOR8, VPOOFF1),
1713 SIG_EXPR_PTR(VPOR8, VPOOFF2));
1714 SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO);
1715 SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC);
1716 SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC);
1717 SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6);
1718 PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13),
1719 SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6));
1720 FUNC_GROUP_DECL(SALT13, N18);
1721
1722 #define P19 215
1723 #define P19_DESC SIG_DESC_SET(SCUA4, 31)
1724 SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1725 SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1726 SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1727 SIG_EXPR_LIST_DECL(VPOR9, VPO,
1728 SIG_EXPR_PTR(VPOR9, VPO),
1729 SIG_EXPR_PTR(VPOR9, VPOOFF1),
1730 SIG_EXPR_PTR(VPOR9, VPOOFF2));
1731 SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO);
1732 SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC);
1733 SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC);
1734 SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7);
1735 PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14),
1736 SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7));
1737 FUNC_GROUP_DECL(SALT14, P19);
1738
1739 #define N19 216
1740 #define N19_DESC SIG_DESC_SET(SCUA8, 0)
1741 SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1742 SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1743 SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1744 SIG_EXPR_LIST_DECL(VPODE, VPO,
1745 SIG_EXPR_PTR(VPODE, VPO),
1746 SIG_EXPR_PTR(VPODE, VPOOFF1),
1747 SIG_EXPR_PTR(VPODE, VPOOFF2));
1748 SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO);
1749 SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC);
1750 PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE);
1751
1752 #define T21 217
1753 #define T21_DESC SIG_DESC_SET(SCUA8, 1)
1754 SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1755 SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1756 SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1757 SIG_EXPR_LIST_DECL(VPOHS, VPO,
1758 SIG_EXPR_PTR(VPOHS, VPO),
1759 SIG_EXPR_PTR(VPOHS, VPOOFF1),
1760 SIG_EXPR_PTR(VPOHS, VPOOFF2));
1761 SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO);
1762 SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC);
1763 PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE);
1764
1765 FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
1766 AA22, U22, T20, N18, P19, N19, T21);
1767
1768 #define T22 218
1769 #define T22_DESC SIG_DESC_SET(SCUA8, 2)
1770 SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1771 SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1772 SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1773 SIG_EXPR_LIST_DECL(VPOVS, VPO,
1774 SIG_EXPR_PTR(VPOVS, VPO),
1775 SIG_EXPR_PTR(VPOVS, VPOOFF1),
1776 SIG_EXPR_PTR(VPOVS, VPOOFF2));
1777 SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO);
1778 SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC);
1779 PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1);
1780 FUNC_GROUP_DECL(WDTRST1, T22);
1781
1782 #define R20 219
1783 #define R20_DESC SIG_DESC_SET(SCUA8, 3)
1784 SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1785 SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1786 SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1787 SIG_EXPR_LIST_DECL(VPOCLK, VPO,
1788 SIG_EXPR_PTR(VPOCLK, VPO),
1789 SIG_EXPR_PTR(VPOCLK, VPOOFF1),
1790 SIG_EXPR_PTR(VPOCLK, VPOOFF2));
1791 SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO);
1792 SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC);
1793 PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2);
1794 FUNC_GROUP_DECL(WDTRST2, R20);
1795
1796 FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
1797 AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
1798 N18, P19, N19, T21, T22, R20);
1799
1800 #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
1801
1802 #define G21 224
1803 SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC);
1804 SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
1805 PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0);
1806 FUNC_GROUP_DECL(LAD0, G21);
1807
1808 #define G20 225
1809 SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC);
1810 SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
1811 PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1);
1812 FUNC_GROUP_DECL(LAD1, G20);
1813
1814 #define D22 226
1815 SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC);
1816 SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
1817 PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2);
1818 FUNC_GROUP_DECL(LAD2, D22);
1819
1820 #define E22 227
1821 SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC);
1822 SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
1823 PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3);
1824 FUNC_GROUP_DECL(LAD3, E22);
1825
1826 #define C22 228
1827 SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC);
1828 SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
1829 PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK);
1830 FUNC_GROUP_DECL(LCLK, C22);
1831
1832 #define F21 229
1833 SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC);
1834 SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
1835 PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME);
1836 FUNC_GROUP_DECL(LFRAME, F21);
1837
1838 #define F22 230
1839 SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC);
1840 SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
1841 PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ);
1842 FUNC_GROUP_DECL(LSIRQ, F22);
1843
1844 #define G22 231
1845 SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC);
1846 SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
1847 PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST);
1848 FUNC_GROUP_DECL(LPCRST, G22);
1849
1850 FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
1851
1852 #define A7 232
1853 SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
1854 SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1855 PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP));
1856
1857 #define A8 233
1858 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
1859 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1860 PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
1861
1862 FUNC_GROUP_DECL(USB2AH, A7, A8);
1863 FUNC_GROUP_DECL(USB2AD, A7, A8);
1864
1865 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
1866 #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
1867 #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
1868 #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
1869
1870 #define B6 234
1871 SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC);
1872 SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC);
1873 SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC);
1874 SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC);
1875 SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH,
1876 SIG_EXPR_PTR(USB2BHDP1, USB2BH),
1877 SIG_EXPR_PTR(USB2BHDP2, USB2BH));
1878 SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH);
1879 PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP),
1880 SIG_EXPR_LIST_PTR(B6, USB2BHDP));
1881
1882 #define A6 235
1883 SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC);
1884 SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC);
1885 SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC);
1886 SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC);
1887 SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH,
1888 SIG_EXPR_PTR(USB2BHDN1, USB2BH),
1889 SIG_EXPR_PTR(USB2BHDN2, USB2BH));
1890 SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH);
1891 PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN),
1892 SIG_EXPR_LIST_PTR(A6, USB2BHDN));
1893
1894 FUNC_GROUP_DECL(USB11BHID, B6, A6);
1895 FUNC_GROUP_DECL(USB2BD, B6, A6);
1896 FUNC_GROUP_DECL(USB2BH, B6, A6);
1897
1898 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1899
1900 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
1901 ASPEED_PINCTRL_PIN(A10),
1902 ASPEED_PINCTRL_PIN(A11),
1903 ASPEED_PINCTRL_PIN(A12),
1904 ASPEED_PINCTRL_PIN(A13),
1905 ASPEED_PINCTRL_PIN(A14),
1906 ASPEED_PINCTRL_PIN(A15),
1907 ASPEED_PINCTRL_PIN(A16),
1908 ASPEED_PINCTRL_PIN(A17),
1909 ASPEED_PINCTRL_PIN(A18),
1910 ASPEED_PINCTRL_PIN(A19),
1911 ASPEED_PINCTRL_PIN(A2),
1912 ASPEED_PINCTRL_PIN(A20),
1913 ASPEED_PINCTRL_PIN(A21),
1914 ASPEED_PINCTRL_PIN(A3),
1915 ASPEED_PINCTRL_PIN(A4),
1916 ASPEED_PINCTRL_PIN(A5),
1917 ASPEED_PINCTRL_PIN(A6),
1918 ASPEED_PINCTRL_PIN(A7),
1919 ASPEED_PINCTRL_PIN(A8),
1920 ASPEED_PINCTRL_PIN(A9),
1921 ASPEED_PINCTRL_PIN(AA1),
1922 ASPEED_PINCTRL_PIN(AA19),
1923 ASPEED_PINCTRL_PIN(AA2),
1924 ASPEED_PINCTRL_PIN(AA20),
1925 ASPEED_PINCTRL_PIN(AA21),
1926 ASPEED_PINCTRL_PIN(AA22),
1927 ASPEED_PINCTRL_PIN(AA3),
1928 ASPEED_PINCTRL_PIN(AA4),
1929 ASPEED_PINCTRL_PIN(AA5),
1930 ASPEED_PINCTRL_PIN(AB2),
1931 ASPEED_PINCTRL_PIN(AB20),
1932 ASPEED_PINCTRL_PIN(AB21),
1933 ASPEED_PINCTRL_PIN(AB3),
1934 ASPEED_PINCTRL_PIN(AB4),
1935 ASPEED_PINCTRL_PIN(AB5),
1936 ASPEED_PINCTRL_PIN(B1),
1937 ASPEED_PINCTRL_PIN(B10),
1938 ASPEED_PINCTRL_PIN(B11),
1939 ASPEED_PINCTRL_PIN(B12),
1940 ASPEED_PINCTRL_PIN(B13),
1941 ASPEED_PINCTRL_PIN(B14),
1942 ASPEED_PINCTRL_PIN(B15),
1943 ASPEED_PINCTRL_PIN(B16),
1944 ASPEED_PINCTRL_PIN(B17),
1945 ASPEED_PINCTRL_PIN(B18),
1946 ASPEED_PINCTRL_PIN(B19),
1947 ASPEED_PINCTRL_PIN(B2),
1948 ASPEED_PINCTRL_PIN(B20),
1949 ASPEED_PINCTRL_PIN(B21),
1950 ASPEED_PINCTRL_PIN(B22),
1951 ASPEED_PINCTRL_PIN(B3),
1952 ASPEED_PINCTRL_PIN(B4),
1953 ASPEED_PINCTRL_PIN(B5),
1954 ASPEED_PINCTRL_PIN(B6),
1955 ASPEED_PINCTRL_PIN(B9),
1956 ASPEED_PINCTRL_PIN(C1),
1957 ASPEED_PINCTRL_PIN(C11),
1958 ASPEED_PINCTRL_PIN(C12),
1959 ASPEED_PINCTRL_PIN(C13),
1960 ASPEED_PINCTRL_PIN(C14),
1961 ASPEED_PINCTRL_PIN(C15),
1962 ASPEED_PINCTRL_PIN(C16),
1963 ASPEED_PINCTRL_PIN(C17),
1964 ASPEED_PINCTRL_PIN(C18),
1965 ASPEED_PINCTRL_PIN(C19),
1966 ASPEED_PINCTRL_PIN(C2),
1967 ASPEED_PINCTRL_PIN(C20),
1968 ASPEED_PINCTRL_PIN(C21),
1969 ASPEED_PINCTRL_PIN(C22),
1970 ASPEED_PINCTRL_PIN(C3),
1971 ASPEED_PINCTRL_PIN(C4),
1972 ASPEED_PINCTRL_PIN(C5),
1973 ASPEED_PINCTRL_PIN(D1),
1974 ASPEED_PINCTRL_PIN(D10),
1975 ASPEED_PINCTRL_PIN(D13),
1976 ASPEED_PINCTRL_PIN(D14),
1977 ASPEED_PINCTRL_PIN(D15),
1978 ASPEED_PINCTRL_PIN(D16),
1979 ASPEED_PINCTRL_PIN(D17),
1980 ASPEED_PINCTRL_PIN(D18),
1981 ASPEED_PINCTRL_PIN(D19),
1982 ASPEED_PINCTRL_PIN(D2),
1983 ASPEED_PINCTRL_PIN(D20),
1984 ASPEED_PINCTRL_PIN(D21),
1985 ASPEED_PINCTRL_PIN(D22),
1986 ASPEED_PINCTRL_PIN(D4),
1987 ASPEED_PINCTRL_PIN(D5),
1988 ASPEED_PINCTRL_PIN(D6),
1989 ASPEED_PINCTRL_PIN(D7),
1990 ASPEED_PINCTRL_PIN(D8),
1991 ASPEED_PINCTRL_PIN(D9),
1992 ASPEED_PINCTRL_PIN(E1),
1993 ASPEED_PINCTRL_PIN(E10),
1994 ASPEED_PINCTRL_PIN(E12),
1995 ASPEED_PINCTRL_PIN(E13),
1996 ASPEED_PINCTRL_PIN(E14),
1997 ASPEED_PINCTRL_PIN(E15),
1998 ASPEED_PINCTRL_PIN(E16),
1999 ASPEED_PINCTRL_PIN(E17),
2000 ASPEED_PINCTRL_PIN(E18),
2001 ASPEED_PINCTRL_PIN(E19),
2002 ASPEED_PINCTRL_PIN(E2),
2003 ASPEED_PINCTRL_PIN(E20),
2004 ASPEED_PINCTRL_PIN(E21),
2005 ASPEED_PINCTRL_PIN(E22),
2006 ASPEED_PINCTRL_PIN(E3),
2007 ASPEED_PINCTRL_PIN(E6),
2008 ASPEED_PINCTRL_PIN(E7),
2009 ASPEED_PINCTRL_PIN(E9),
2010 ASPEED_PINCTRL_PIN(F1),
2011 ASPEED_PINCTRL_PIN(F17),
2012 ASPEED_PINCTRL_PIN(F18),
2013 ASPEED_PINCTRL_PIN(F19),
2014 ASPEED_PINCTRL_PIN(F2),
2015 ASPEED_PINCTRL_PIN(F20),
2016 ASPEED_PINCTRL_PIN(F21),
2017 ASPEED_PINCTRL_PIN(F22),
2018 ASPEED_PINCTRL_PIN(F3),
2019 ASPEED_PINCTRL_PIN(F4),
2020 ASPEED_PINCTRL_PIN(F5),
2021 ASPEED_PINCTRL_PIN(F9),
2022 ASPEED_PINCTRL_PIN(G1),
2023 ASPEED_PINCTRL_PIN(G17),
2024 ASPEED_PINCTRL_PIN(G18),
2025 ASPEED_PINCTRL_PIN(G2),
2026 ASPEED_PINCTRL_PIN(G20),
2027 ASPEED_PINCTRL_PIN(G21),
2028 ASPEED_PINCTRL_PIN(G22),
2029 ASPEED_PINCTRL_PIN(G3),
2030 ASPEED_PINCTRL_PIN(G4),
2031 ASPEED_PINCTRL_PIN(G5),
2032 ASPEED_PINCTRL_PIN(H18),
2033 ASPEED_PINCTRL_PIN(H19),
2034 ASPEED_PINCTRL_PIN(H20),
2035 ASPEED_PINCTRL_PIN(H21),
2036 ASPEED_PINCTRL_PIN(H22),
2037 ASPEED_PINCTRL_PIN(H3),
2038 ASPEED_PINCTRL_PIN(H4),
2039 ASPEED_PINCTRL_PIN(H5),
2040 ASPEED_PINCTRL_PIN(J18),
2041 ASPEED_PINCTRL_PIN(J19),
2042 ASPEED_PINCTRL_PIN(J20),
2043 ASPEED_PINCTRL_PIN(K18),
2044 ASPEED_PINCTRL_PIN(K19),
2045 ASPEED_PINCTRL_PIN(L1),
2046 ASPEED_PINCTRL_PIN(L18),
2047 ASPEED_PINCTRL_PIN(L19),
2048 ASPEED_PINCTRL_PIN(L2),
2049 ASPEED_PINCTRL_PIN(L3),
2050 ASPEED_PINCTRL_PIN(L4),
2051 ASPEED_PINCTRL_PIN(M18),
2052 ASPEED_PINCTRL_PIN(M19),
2053 ASPEED_PINCTRL_PIN(M20),
2054 ASPEED_PINCTRL_PIN(N1),
2055 ASPEED_PINCTRL_PIN(N18),
2056 ASPEED_PINCTRL_PIN(N19),
2057 ASPEED_PINCTRL_PIN(N2),
2058 ASPEED_PINCTRL_PIN(N20),
2059 ASPEED_PINCTRL_PIN(N21),
2060 ASPEED_PINCTRL_PIN(N22),
2061 ASPEED_PINCTRL_PIN(N3),
2062 ASPEED_PINCTRL_PIN(N4),
2063 ASPEED_PINCTRL_PIN(N5),
2064 ASPEED_PINCTRL_PIN(P1),
2065 ASPEED_PINCTRL_PIN(P18),
2066 ASPEED_PINCTRL_PIN(P19),
2067 ASPEED_PINCTRL_PIN(P2),
2068 ASPEED_PINCTRL_PIN(P20),
2069 ASPEED_PINCTRL_PIN(P21),
2070 ASPEED_PINCTRL_PIN(P22),
2071 ASPEED_PINCTRL_PIN(P3),
2072 ASPEED_PINCTRL_PIN(P4),
2073 ASPEED_PINCTRL_PIN(P5),
2074 ASPEED_PINCTRL_PIN(R1),
2075 ASPEED_PINCTRL_PIN(R18),
2076 ASPEED_PINCTRL_PIN(R19),
2077 ASPEED_PINCTRL_PIN(R2),
2078 ASPEED_PINCTRL_PIN(R20),
2079 ASPEED_PINCTRL_PIN(R21),
2080 ASPEED_PINCTRL_PIN(R22),
2081 ASPEED_PINCTRL_PIN(R3),
2082 ASPEED_PINCTRL_PIN(R4),
2083 ASPEED_PINCTRL_PIN(R5),
2084 ASPEED_PINCTRL_PIN(T1),
2085 ASPEED_PINCTRL_PIN(T17),
2086 ASPEED_PINCTRL_PIN(T19),
2087 ASPEED_PINCTRL_PIN(T2),
2088 ASPEED_PINCTRL_PIN(T20),
2089 ASPEED_PINCTRL_PIN(T21),
2090 ASPEED_PINCTRL_PIN(T22),
2091 ASPEED_PINCTRL_PIN(T3),
2092 ASPEED_PINCTRL_PIN(T4),
2093 ASPEED_PINCTRL_PIN(T5),
2094 ASPEED_PINCTRL_PIN(U1),
2095 ASPEED_PINCTRL_PIN(U19),
2096 ASPEED_PINCTRL_PIN(U2),
2097 ASPEED_PINCTRL_PIN(U20),
2098 ASPEED_PINCTRL_PIN(U21),
2099 ASPEED_PINCTRL_PIN(U22),
2100 ASPEED_PINCTRL_PIN(U3),
2101 ASPEED_PINCTRL_PIN(U4),
2102 ASPEED_PINCTRL_PIN(U5),
2103 ASPEED_PINCTRL_PIN(V1),
2104 ASPEED_PINCTRL_PIN(V19),
2105 ASPEED_PINCTRL_PIN(V2),
2106 ASPEED_PINCTRL_PIN(V20),
2107 ASPEED_PINCTRL_PIN(V21),
2108 ASPEED_PINCTRL_PIN(V22),
2109 ASPEED_PINCTRL_PIN(V3),
2110 ASPEED_PINCTRL_PIN(V4),
2111 ASPEED_PINCTRL_PIN(V5),
2112 ASPEED_PINCTRL_PIN(V6),
2113 ASPEED_PINCTRL_PIN(W1),
2114 ASPEED_PINCTRL_PIN(W19),
2115 ASPEED_PINCTRL_PIN(W2),
2116 ASPEED_PINCTRL_PIN(W20),
2117 ASPEED_PINCTRL_PIN(W21),
2118 ASPEED_PINCTRL_PIN(W22),
2119 ASPEED_PINCTRL_PIN(W3),
2120 ASPEED_PINCTRL_PIN(W4),
2121 ASPEED_PINCTRL_PIN(W5),
2122 ASPEED_PINCTRL_PIN(W6),
2123 ASPEED_PINCTRL_PIN(Y1),
2124 ASPEED_PINCTRL_PIN(Y19),
2125 ASPEED_PINCTRL_PIN(Y2),
2126 ASPEED_PINCTRL_PIN(Y20),
2127 ASPEED_PINCTRL_PIN(Y21),
2128 ASPEED_PINCTRL_PIN(Y22),
2129 ASPEED_PINCTRL_PIN(Y3),
2130 ASPEED_PINCTRL_PIN(Y4),
2131 ASPEED_PINCTRL_PIN(Y5),
2132 ASPEED_PINCTRL_PIN(Y6),
2133 };
2134
2135 static const struct aspeed_pin_group aspeed_g5_groups[] = {
2136 ASPEED_PINCTRL_GROUP(ACPI),
2137 ASPEED_PINCTRL_GROUP(ADC0),
2138 ASPEED_PINCTRL_GROUP(ADC1),
2139 ASPEED_PINCTRL_GROUP(ADC10),
2140 ASPEED_PINCTRL_GROUP(ADC11),
2141 ASPEED_PINCTRL_GROUP(ADC12),
2142 ASPEED_PINCTRL_GROUP(ADC13),
2143 ASPEED_PINCTRL_GROUP(ADC14),
2144 ASPEED_PINCTRL_GROUP(ADC15),
2145 ASPEED_PINCTRL_GROUP(ADC2),
2146 ASPEED_PINCTRL_GROUP(ADC3),
2147 ASPEED_PINCTRL_GROUP(ADC4),
2148 ASPEED_PINCTRL_GROUP(ADC5),
2149 ASPEED_PINCTRL_GROUP(ADC6),
2150 ASPEED_PINCTRL_GROUP(ADC7),
2151 ASPEED_PINCTRL_GROUP(ADC8),
2152 ASPEED_PINCTRL_GROUP(ADC9),
2153 ASPEED_PINCTRL_GROUP(BMCINT),
2154 ASPEED_PINCTRL_GROUP(DDCCLK),
2155 ASPEED_PINCTRL_GROUP(DDCDAT),
2156 ASPEED_PINCTRL_GROUP(ESPI),
2157 ASPEED_PINCTRL_GROUP(FWSPICS1),
2158 ASPEED_PINCTRL_GROUP(FWSPICS2),
2159 ASPEED_PINCTRL_GROUP(GPID0),
2160 ASPEED_PINCTRL_GROUP(GPID2),
2161 ASPEED_PINCTRL_GROUP(GPID4),
2162 ASPEED_PINCTRL_GROUP(GPID6),
2163 ASPEED_PINCTRL_GROUP(GPIE0),
2164 ASPEED_PINCTRL_GROUP(GPIE2),
2165 ASPEED_PINCTRL_GROUP(GPIE4),
2166 ASPEED_PINCTRL_GROUP(GPIE6),
2167 ASPEED_PINCTRL_GROUP(I2C10),
2168 ASPEED_PINCTRL_GROUP(I2C11),
2169 ASPEED_PINCTRL_GROUP(I2C12),
2170 ASPEED_PINCTRL_GROUP(I2C13),
2171 ASPEED_PINCTRL_GROUP(I2C14),
2172 ASPEED_PINCTRL_GROUP(I2C3),
2173 ASPEED_PINCTRL_GROUP(I2C4),
2174 ASPEED_PINCTRL_GROUP(I2C5),
2175 ASPEED_PINCTRL_GROUP(I2C6),
2176 ASPEED_PINCTRL_GROUP(I2C7),
2177 ASPEED_PINCTRL_GROUP(I2C8),
2178 ASPEED_PINCTRL_GROUP(I2C9),
2179 ASPEED_PINCTRL_GROUP(LAD0),
2180 ASPEED_PINCTRL_GROUP(LAD1),
2181 ASPEED_PINCTRL_GROUP(LAD2),
2182 ASPEED_PINCTRL_GROUP(LAD3),
2183 ASPEED_PINCTRL_GROUP(LCLK),
2184 ASPEED_PINCTRL_GROUP(LFRAME),
2185 ASPEED_PINCTRL_GROUP(LPCHC),
2186 ASPEED_PINCTRL_GROUP(LPCPD),
2187 ASPEED_PINCTRL_GROUP(LPCPLUS),
2188 ASPEED_PINCTRL_GROUP(LPCPME),
2189 ASPEED_PINCTRL_GROUP(LPCRST),
2190 ASPEED_PINCTRL_GROUP(LPCSMI),
2191 ASPEED_PINCTRL_GROUP(LSIRQ),
2192 ASPEED_PINCTRL_GROUP(MAC1LINK),
2193 ASPEED_PINCTRL_GROUP(MAC2LINK),
2194 ASPEED_PINCTRL_GROUP(MDIO1),
2195 ASPEED_PINCTRL_GROUP(MDIO2),
2196 ASPEED_PINCTRL_GROUP(NCTS1),
2197 ASPEED_PINCTRL_GROUP(NCTS2),
2198 ASPEED_PINCTRL_GROUP(NCTS3),
2199 ASPEED_PINCTRL_GROUP(NCTS4),
2200 ASPEED_PINCTRL_GROUP(NDCD1),
2201 ASPEED_PINCTRL_GROUP(NDCD2),
2202 ASPEED_PINCTRL_GROUP(NDCD3),
2203 ASPEED_PINCTRL_GROUP(NDCD4),
2204 ASPEED_PINCTRL_GROUP(NDSR1),
2205 ASPEED_PINCTRL_GROUP(NDSR2),
2206 ASPEED_PINCTRL_GROUP(NDSR3),
2207 ASPEED_PINCTRL_GROUP(NDSR4),
2208 ASPEED_PINCTRL_GROUP(NDTR1),
2209 ASPEED_PINCTRL_GROUP(NDTR2),
2210 ASPEED_PINCTRL_GROUP(NDTR3),
2211 ASPEED_PINCTRL_GROUP(NDTR4),
2212 ASPEED_PINCTRL_GROUP(NRI1),
2213 ASPEED_PINCTRL_GROUP(NRI2),
2214 ASPEED_PINCTRL_GROUP(NRI3),
2215 ASPEED_PINCTRL_GROUP(NRI4),
2216 ASPEED_PINCTRL_GROUP(NRTS1),
2217 ASPEED_PINCTRL_GROUP(NRTS2),
2218 ASPEED_PINCTRL_GROUP(NRTS3),
2219 ASPEED_PINCTRL_GROUP(NRTS4),
2220 ASPEED_PINCTRL_GROUP(OSCCLK),
2221 ASPEED_PINCTRL_GROUP(PEWAKE),
2222 ASPEED_PINCTRL_GROUP(PNOR),
2223 ASPEED_PINCTRL_GROUP(PWM0),
2224 ASPEED_PINCTRL_GROUP(PWM1),
2225 ASPEED_PINCTRL_GROUP(PWM2),
2226 ASPEED_PINCTRL_GROUP(PWM3),
2227 ASPEED_PINCTRL_GROUP(PWM4),
2228 ASPEED_PINCTRL_GROUP(PWM5),
2229 ASPEED_PINCTRL_GROUP(PWM6),
2230 ASPEED_PINCTRL_GROUP(PWM7),
2231 ASPEED_PINCTRL_GROUP(RGMII1),
2232 ASPEED_PINCTRL_GROUP(RGMII2),
2233 ASPEED_PINCTRL_GROUP(RMII1),
2234 ASPEED_PINCTRL_GROUP(RMII2),
2235 ASPEED_PINCTRL_GROUP(RXD1),
2236 ASPEED_PINCTRL_GROUP(RXD2),
2237 ASPEED_PINCTRL_GROUP(RXD3),
2238 ASPEED_PINCTRL_GROUP(RXD4),
2239 ASPEED_PINCTRL_GROUP(SALT1),
2240 ASPEED_PINCTRL_GROUP(SALT10),
2241 ASPEED_PINCTRL_GROUP(SALT11),
2242 ASPEED_PINCTRL_GROUP(SALT12),
2243 ASPEED_PINCTRL_GROUP(SALT13),
2244 ASPEED_PINCTRL_GROUP(SALT14),
2245 ASPEED_PINCTRL_GROUP(SALT2),
2246 ASPEED_PINCTRL_GROUP(SALT3),
2247 ASPEED_PINCTRL_GROUP(SALT4),
2248 ASPEED_PINCTRL_GROUP(SALT5),
2249 ASPEED_PINCTRL_GROUP(SALT6),
2250 ASPEED_PINCTRL_GROUP(SALT7),
2251 ASPEED_PINCTRL_GROUP(SALT8),
2252 ASPEED_PINCTRL_GROUP(SALT9),
2253 ASPEED_PINCTRL_GROUP(SCL1),
2254 ASPEED_PINCTRL_GROUP(SCL2),
2255 ASPEED_PINCTRL_GROUP(SD1),
2256 ASPEED_PINCTRL_GROUP(SD2),
2257 ASPEED_PINCTRL_GROUP(SDA1),
2258 ASPEED_PINCTRL_GROUP(SDA2),
2259 ASPEED_PINCTRL_GROUP(SGPM),
2260 ASPEED_PINCTRL_GROUP(SGPS1),
2261 ASPEED_PINCTRL_GROUP(SGPS2),
2262 ASPEED_PINCTRL_GROUP(SIOONCTRL),
2263 ASPEED_PINCTRL_GROUP(SIOPBI),
2264 ASPEED_PINCTRL_GROUP(SIOPBO),
2265 ASPEED_PINCTRL_GROUP(SIOPWREQ),
2266 ASPEED_PINCTRL_GROUP(SIOPWRGD),
2267 ASPEED_PINCTRL_GROUP(SIOS3),
2268 ASPEED_PINCTRL_GROUP(SIOS5),
2269 ASPEED_PINCTRL_GROUP(SIOSCI),
2270 ASPEED_PINCTRL_GROUP(SPI1),
2271 ASPEED_PINCTRL_GROUP(SPI1CS1),
2272 ASPEED_PINCTRL_GROUP(SPI1DEBUG),
2273 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
2274 ASPEED_PINCTRL_GROUP(SPI2CK),
2275 ASPEED_PINCTRL_GROUP(SPI2CS0),
2276 ASPEED_PINCTRL_GROUP(SPI2CS1),
2277 ASPEED_PINCTRL_GROUP(SPI2MISO),
2278 ASPEED_PINCTRL_GROUP(SPI2MOSI),
2279 ASPEED_PINCTRL_GROUP(TIMER3),
2280 ASPEED_PINCTRL_GROUP(TIMER4),
2281 ASPEED_PINCTRL_GROUP(TIMER5),
2282 ASPEED_PINCTRL_GROUP(TIMER6),
2283 ASPEED_PINCTRL_GROUP(TIMER7),
2284 ASPEED_PINCTRL_GROUP(TIMER8),
2285 ASPEED_PINCTRL_GROUP(TXD1),
2286 ASPEED_PINCTRL_GROUP(TXD2),
2287 ASPEED_PINCTRL_GROUP(TXD3),
2288 ASPEED_PINCTRL_GROUP(TXD4),
2289 ASPEED_PINCTRL_GROUP(UART6),
2290 ASPEED_PINCTRL_GROUP(USB11BHID),
2291 ASPEED_PINCTRL_GROUP(USB2AD),
2292 ASPEED_PINCTRL_GROUP(USB2AH),
2293 ASPEED_PINCTRL_GROUP(USB2BD),
2294 ASPEED_PINCTRL_GROUP(USB2BH),
2295 ASPEED_PINCTRL_GROUP(USBCKI),
2296 ASPEED_PINCTRL_GROUP(VGABIOSROM),
2297 ASPEED_PINCTRL_GROUP(VGAHS),
2298 ASPEED_PINCTRL_GROUP(VGAVS),
2299 ASPEED_PINCTRL_GROUP(VPI24),
2300 ASPEED_PINCTRL_GROUP(VPO),
2301 ASPEED_PINCTRL_GROUP(WDTRST1),
2302 ASPEED_PINCTRL_GROUP(WDTRST2),
2303 };
2304
2305 static const struct aspeed_pin_function aspeed_g5_functions[] = {
2306 ASPEED_PINCTRL_FUNC(ACPI),
2307 ASPEED_PINCTRL_FUNC(ADC0),
2308 ASPEED_PINCTRL_FUNC(ADC1),
2309 ASPEED_PINCTRL_FUNC(ADC10),
2310 ASPEED_PINCTRL_FUNC(ADC11),
2311 ASPEED_PINCTRL_FUNC(ADC12),
2312 ASPEED_PINCTRL_FUNC(ADC13),
2313 ASPEED_PINCTRL_FUNC(ADC14),
2314 ASPEED_PINCTRL_FUNC(ADC15),
2315 ASPEED_PINCTRL_FUNC(ADC2),
2316 ASPEED_PINCTRL_FUNC(ADC3),
2317 ASPEED_PINCTRL_FUNC(ADC4),
2318 ASPEED_PINCTRL_FUNC(ADC5),
2319 ASPEED_PINCTRL_FUNC(ADC6),
2320 ASPEED_PINCTRL_FUNC(ADC7),
2321 ASPEED_PINCTRL_FUNC(ADC8),
2322 ASPEED_PINCTRL_FUNC(ADC9),
2323 ASPEED_PINCTRL_FUNC(BMCINT),
2324 ASPEED_PINCTRL_FUNC(DDCCLK),
2325 ASPEED_PINCTRL_FUNC(DDCDAT),
2326 ASPEED_PINCTRL_FUNC(ESPI),
2327 ASPEED_PINCTRL_FUNC(FWSPICS1),
2328 ASPEED_PINCTRL_FUNC(FWSPICS2),
2329 ASPEED_PINCTRL_FUNC(GPID0),
2330 ASPEED_PINCTRL_FUNC(GPID2),
2331 ASPEED_PINCTRL_FUNC(GPID4),
2332 ASPEED_PINCTRL_FUNC(GPID6),
2333 ASPEED_PINCTRL_FUNC(GPIE0),
2334 ASPEED_PINCTRL_FUNC(GPIE2),
2335 ASPEED_PINCTRL_FUNC(GPIE4),
2336 ASPEED_PINCTRL_FUNC(GPIE6),
2337 ASPEED_PINCTRL_FUNC(I2C10),
2338 ASPEED_PINCTRL_FUNC(I2C11),
2339 ASPEED_PINCTRL_FUNC(I2C12),
2340 ASPEED_PINCTRL_FUNC(I2C13),
2341 ASPEED_PINCTRL_FUNC(I2C14),
2342 ASPEED_PINCTRL_FUNC(I2C3),
2343 ASPEED_PINCTRL_FUNC(I2C4),
2344 ASPEED_PINCTRL_FUNC(I2C5),
2345 ASPEED_PINCTRL_FUNC(I2C6),
2346 ASPEED_PINCTRL_FUNC(I2C7),
2347 ASPEED_PINCTRL_FUNC(I2C8),
2348 ASPEED_PINCTRL_FUNC(I2C9),
2349 ASPEED_PINCTRL_FUNC(LAD0),
2350 ASPEED_PINCTRL_FUNC(LAD1),
2351 ASPEED_PINCTRL_FUNC(LAD2),
2352 ASPEED_PINCTRL_FUNC(LAD3),
2353 ASPEED_PINCTRL_FUNC(LCLK),
2354 ASPEED_PINCTRL_FUNC(LFRAME),
2355 ASPEED_PINCTRL_FUNC(LPCHC),
2356 ASPEED_PINCTRL_FUNC(LPCPD),
2357 ASPEED_PINCTRL_FUNC(LPCPLUS),
2358 ASPEED_PINCTRL_FUNC(LPCPME),
2359 ASPEED_PINCTRL_FUNC(LPCRST),
2360 ASPEED_PINCTRL_FUNC(LPCSMI),
2361 ASPEED_PINCTRL_FUNC(LSIRQ),
2362 ASPEED_PINCTRL_FUNC(MAC1LINK),
2363 ASPEED_PINCTRL_FUNC(MAC2LINK),
2364 ASPEED_PINCTRL_FUNC(MDIO1),
2365 ASPEED_PINCTRL_FUNC(MDIO2),
2366 ASPEED_PINCTRL_FUNC(NCTS1),
2367 ASPEED_PINCTRL_FUNC(NCTS2),
2368 ASPEED_PINCTRL_FUNC(NCTS3),
2369 ASPEED_PINCTRL_FUNC(NCTS4),
2370 ASPEED_PINCTRL_FUNC(NDCD1),
2371 ASPEED_PINCTRL_FUNC(NDCD2),
2372 ASPEED_PINCTRL_FUNC(NDCD3),
2373 ASPEED_PINCTRL_FUNC(NDCD4),
2374 ASPEED_PINCTRL_FUNC(NDSR1),
2375 ASPEED_PINCTRL_FUNC(NDSR2),
2376 ASPEED_PINCTRL_FUNC(NDSR3),
2377 ASPEED_PINCTRL_FUNC(NDSR4),
2378 ASPEED_PINCTRL_FUNC(NDTR1),
2379 ASPEED_PINCTRL_FUNC(NDTR2),
2380 ASPEED_PINCTRL_FUNC(NDTR3),
2381 ASPEED_PINCTRL_FUNC(NDTR4),
2382 ASPEED_PINCTRL_FUNC(NRI1),
2383 ASPEED_PINCTRL_FUNC(NRI2),
2384 ASPEED_PINCTRL_FUNC(NRI3),
2385 ASPEED_PINCTRL_FUNC(NRI4),
2386 ASPEED_PINCTRL_FUNC(NRTS1),
2387 ASPEED_PINCTRL_FUNC(NRTS2),
2388 ASPEED_PINCTRL_FUNC(NRTS3),
2389 ASPEED_PINCTRL_FUNC(NRTS4),
2390 ASPEED_PINCTRL_FUNC(OSCCLK),
2391 ASPEED_PINCTRL_FUNC(PEWAKE),
2392 ASPEED_PINCTRL_FUNC(PNOR),
2393 ASPEED_PINCTRL_FUNC(PWM0),
2394 ASPEED_PINCTRL_FUNC(PWM1),
2395 ASPEED_PINCTRL_FUNC(PWM2),
2396 ASPEED_PINCTRL_FUNC(PWM3),
2397 ASPEED_PINCTRL_FUNC(PWM4),
2398 ASPEED_PINCTRL_FUNC(PWM5),
2399 ASPEED_PINCTRL_FUNC(PWM6),
2400 ASPEED_PINCTRL_FUNC(PWM7),
2401 ASPEED_PINCTRL_FUNC(RGMII1),
2402 ASPEED_PINCTRL_FUNC(RGMII2),
2403 ASPEED_PINCTRL_FUNC(RMII1),
2404 ASPEED_PINCTRL_FUNC(RMII2),
2405 ASPEED_PINCTRL_FUNC(RXD1),
2406 ASPEED_PINCTRL_FUNC(RXD2),
2407 ASPEED_PINCTRL_FUNC(RXD3),
2408 ASPEED_PINCTRL_FUNC(RXD4),
2409 ASPEED_PINCTRL_FUNC(SALT1),
2410 ASPEED_PINCTRL_FUNC(SALT10),
2411 ASPEED_PINCTRL_FUNC(SALT11),
2412 ASPEED_PINCTRL_FUNC(SALT12),
2413 ASPEED_PINCTRL_FUNC(SALT13),
2414 ASPEED_PINCTRL_FUNC(SALT14),
2415 ASPEED_PINCTRL_FUNC(SALT2),
2416 ASPEED_PINCTRL_FUNC(SALT3),
2417 ASPEED_PINCTRL_FUNC(SALT4),
2418 ASPEED_PINCTRL_FUNC(SALT5),
2419 ASPEED_PINCTRL_FUNC(SALT6),
2420 ASPEED_PINCTRL_FUNC(SALT7),
2421 ASPEED_PINCTRL_FUNC(SALT8),
2422 ASPEED_PINCTRL_FUNC(SALT9),
2423 ASPEED_PINCTRL_FUNC(SCL1),
2424 ASPEED_PINCTRL_FUNC(SCL2),
2425 ASPEED_PINCTRL_FUNC(SD1),
2426 ASPEED_PINCTRL_FUNC(SD2),
2427 ASPEED_PINCTRL_FUNC(SDA1),
2428 ASPEED_PINCTRL_FUNC(SDA2),
2429 ASPEED_PINCTRL_FUNC(SGPM),
2430 ASPEED_PINCTRL_FUNC(SGPS1),
2431 ASPEED_PINCTRL_FUNC(SGPS2),
2432 ASPEED_PINCTRL_FUNC(SIOONCTRL),
2433 ASPEED_PINCTRL_FUNC(SIOPBI),
2434 ASPEED_PINCTRL_FUNC(SIOPBO),
2435 ASPEED_PINCTRL_FUNC(SIOPWREQ),
2436 ASPEED_PINCTRL_FUNC(SIOPWRGD),
2437 ASPEED_PINCTRL_FUNC(SIOS3),
2438 ASPEED_PINCTRL_FUNC(SIOS5),
2439 ASPEED_PINCTRL_FUNC(SIOSCI),
2440 ASPEED_PINCTRL_FUNC(SPI1),
2441 ASPEED_PINCTRL_FUNC(SPI1CS1),
2442 ASPEED_PINCTRL_FUNC(SPI1DEBUG),
2443 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
2444 ASPEED_PINCTRL_FUNC(SPI2CK),
2445 ASPEED_PINCTRL_FUNC(SPI2CS0),
2446 ASPEED_PINCTRL_FUNC(SPI2CS1),
2447 ASPEED_PINCTRL_FUNC(SPI2MISO),
2448 ASPEED_PINCTRL_FUNC(SPI2MOSI),
2449 ASPEED_PINCTRL_FUNC(TIMER3),
2450 ASPEED_PINCTRL_FUNC(TIMER4),
2451 ASPEED_PINCTRL_FUNC(TIMER5),
2452 ASPEED_PINCTRL_FUNC(TIMER6),
2453 ASPEED_PINCTRL_FUNC(TIMER7),
2454 ASPEED_PINCTRL_FUNC(TIMER8),
2455 ASPEED_PINCTRL_FUNC(TXD1),
2456 ASPEED_PINCTRL_FUNC(TXD2),
2457 ASPEED_PINCTRL_FUNC(TXD3),
2458 ASPEED_PINCTRL_FUNC(TXD4),
2459 ASPEED_PINCTRL_FUNC(UART6),
2460 ASPEED_PINCTRL_FUNC(USB11BHID),
2461 ASPEED_PINCTRL_FUNC(USB2AD),
2462 ASPEED_PINCTRL_FUNC(USB2AH),
2463 ASPEED_PINCTRL_FUNC(USB2BD),
2464 ASPEED_PINCTRL_FUNC(USB2BH),
2465 ASPEED_PINCTRL_FUNC(USBCKI),
2466 ASPEED_PINCTRL_FUNC(VGABIOSROM),
2467 ASPEED_PINCTRL_FUNC(VGAHS),
2468 ASPEED_PINCTRL_FUNC(VGAVS),
2469 ASPEED_PINCTRL_FUNC(VPI24),
2470 ASPEED_PINCTRL_FUNC(VPO),
2471 ASPEED_PINCTRL_FUNC(WDTRST1),
2472 ASPEED_PINCTRL_FUNC(WDTRST2),
2473 };
2474
2475 static struct aspeed_pin_config aspeed_g5_configs[] = {
2476 /* GPIOA, GPIOQ */
2477 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16),
2478 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16),
2479 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16),
2480 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16),
2481
2482 /* GPIOB, GPIOR */
2483 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17),
2484 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17),
2485 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
2486 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
2487
2488 /* GPIOC, GPIOS*/
2489 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
2490 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
2491 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18),
2492 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18),
2493
2494 /* GPIOD, GPIOY */
2495 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19),
2496 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19),
2497 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19),
2498 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19),
2499
2500 /* GPIOE, GPIOZ */
2501 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20),
2502 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20),
2503 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20),
2504 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20),
2505
2506 /* GPIOF, GPIOAA */
2507 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21),
2508 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21),
2509 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21),
2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21),
2511
2512 /* GPIOG, GPIOAB */
2513 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22),
2514 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22),
2515 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22),
2516 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22),
2517
2518 /* GPIOH, GPIOAC */
2519 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23),
2520 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23),
2521 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23),
2522 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23),
2523
2524 /* GPIOs [I, P] */
2525 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
2526 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24),
2527 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25),
2528 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25),
2529 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26),
2530 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26),
2531 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27),
2532 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27),
2533 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
2534 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
2535 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
2536 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
2537 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30),
2538 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30),
2539 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31),
2540 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31),
2541
2542 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2543 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8),
2544 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9),
2545 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12),
2546 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12),
2547
2548 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2549 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
2550 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11),
2551 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
2552 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
2553
2554 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2555 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
2556 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
2557
2558 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2559 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
2560 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
2561
2562 /* ADC pull-downs (SCUA8[19:4]) */
2563 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),
2564 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),
2565 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5),
2566 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5),
2567 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6),
2568 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6),
2569 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7),
2570 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7),
2571 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),
2572 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),
2573 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9),
2574 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9),
2575 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10),
2576 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10),
2577 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11),
2578 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11),
2579 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12),
2580 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12),
2581 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
2582 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
2583 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14),
2584 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14),
2585 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15),
2586 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15),
2587 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16),
2588 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16),
2589 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17),
2590 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17),
2591 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18),
2592 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18),
2593 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19),
2594 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19),
2595
2596 /*
2597 * Debounce settings for GPIOs D and E passthrough mode are in
2598 * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
2599 * banks D and E is handled by the GPIO driver - GPIO passthrough is
2600 * treated like any other non-GPIO mux function. There is a catch
2601 * however, in that the debounce period is configured in the GPIO
2602 * controller. Due to this tangle between GPIO and pinctrl we don't yet
2603 * fully support pass-through debounce.
2604 */
2605 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20),
2606 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21),
2607 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22),
2608 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23),
2609 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24),
2610 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25),
2611 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26),
2612 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27),
2613 };
2614
aspeed_g5_acquire_regmap(struct aspeed_pinmux_data * ctx,int ip)2615 static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
2616 int ip)
2617 {
2618 if (ip == ASPEED_IP_SCU) {
2619 WARN(!ctx->maps[ip], "Missing SCU syscon!");
2620 return ctx->maps[ip];
2621 }
2622
2623 if (ip >= ASPEED_NR_PINMUX_IPS)
2624 return ERR_PTR(-EINVAL);
2625
2626 if (likely(ctx->maps[ip]))
2627 return ctx->maps[ip];
2628
2629 if (ip == ASPEED_IP_GFX) {
2630 struct device_node *node;
2631 struct regmap *map;
2632
2633 node = of_parse_phandle(ctx->dev->of_node,
2634 "aspeed,external-nodes", 0);
2635 if (node) {
2636 map = syscon_node_to_regmap(node);
2637 of_node_put(node);
2638 if (IS_ERR(map))
2639 return map;
2640 } else
2641 return ERR_PTR(-ENODEV);
2642
2643 ctx->maps[ASPEED_IP_GFX] = map;
2644 dev_dbg(ctx->dev, "Acquired GFX regmap");
2645 return map;
2646 }
2647
2648 if (ip == ASPEED_IP_LPC) {
2649 struct device_node *np;
2650 struct regmap *map;
2651
2652 np = of_parse_phandle(ctx->dev->of_node,
2653 "aspeed,external-nodes", 1);
2654 if (np) {
2655 if (!of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2"))
2656 return ERR_PTR(-ENODEV);
2657
2658 map = syscon_node_to_regmap(np->parent);
2659 of_node_put(np);
2660 if (IS_ERR(map))
2661 return map;
2662 } else
2663 return ERR_PTR(-ENODEV);
2664
2665 ctx->maps[ASPEED_IP_LPC] = map;
2666 dev_dbg(ctx->dev, "Acquired LPC regmap");
2667 return map;
2668 }
2669
2670 return ERR_PTR(-EINVAL);
2671 }
2672
aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data * ctx,const struct aspeed_sig_expr * expr,bool enabled)2673 static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx,
2674 const struct aspeed_sig_expr *expr,
2675 bool enabled)
2676 {
2677 int ret;
2678 int i;
2679
2680 for (i = 0; i < expr->ndescs; i++) {
2681 const struct aspeed_sig_desc *desc = &expr->descs[i];
2682 struct regmap *map;
2683
2684 map = aspeed_g5_acquire_regmap(ctx, desc->ip);
2685 if (IS_ERR(map)) {
2686 dev_err(ctx->dev,
2687 "Failed to acquire regmap for IP block %d\n",
2688 desc->ip);
2689 return PTR_ERR(map);
2690 }
2691
2692 ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
2693 if (ret <= 0)
2694 return ret;
2695 }
2696
2697 return 1;
2698 }
2699
2700 /**
2701 * aspeed_g5_sig_expr_set() - Configure a pin's signal by applying an
2702 * expression's descriptor state for all descriptors in the expression.
2703 *
2704 * @ctx: The pinmux context
2705 * @expr: The expression associated with the function whose signal is to be
2706 * configured
2707 * @enable: true to enable an function's signal through a pin's signal
2708 * expression, false to disable the function's signal
2709 *
2710 * Return: 0 if the expression is configured as requested and a negative error
2711 * code otherwise
2712 */
aspeed_g5_sig_expr_set(struct aspeed_pinmux_data * ctx,const struct aspeed_sig_expr * expr,bool enable)2713 static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
2714 const struct aspeed_sig_expr *expr,
2715 bool enable)
2716 {
2717 int ret;
2718 int i;
2719
2720 for (i = 0; i < expr->ndescs; i++) {
2721 const struct aspeed_sig_desc *desc = &expr->descs[i];
2722 u32 pattern = enable ? desc->enable : desc->disable;
2723 u32 val = (pattern << __ffs(desc->mask));
2724 struct regmap *map;
2725
2726 map = aspeed_g5_acquire_regmap(ctx, desc->ip);
2727 if (IS_ERR(map)) {
2728 dev_err(ctx->dev,
2729 "Failed to acquire regmap for IP block %d\n",
2730 desc->ip);
2731 return PTR_ERR(map);
2732 }
2733
2734 /*
2735 * Strap registers are configured in hardware or by early-boot
2736 * firmware. Treat them as read-only despite that we can write
2737 * them. This may mean that certain functions cannot be
2738 * deconfigured and is the reason we re-evaluate after writing
2739 * all descriptor bits.
2740 *
2741 * We make two exceptions to the read-only rule:
2742 *
2743 * - The passthrough mode of GPIO ports D and E are commonly
2744 * used with front-panel buttons to allow normal operation
2745 * of the host if the BMC is powered off or fails to boot.
2746 * Once the BMC has booted, the loopback mode must be
2747 * disabled for the BMC to control host power-on and reset.
2748 *
2749 * - The operating mode of the SPI1 interface is simply
2750 * strapped incorrectly on some systems and requires a
2751 * software fixup, which we allow to be done via pinctrl.
2752 */
2753 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
2754 !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12))))
2755 continue;
2756
2757 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
2758 continue;
2759
2760 /* On AST2500, Set bits in SCU70 are cleared from SCU7C */
2761 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
2762 u32 value = ~val & desc->mask;
2763
2764 if (value) {
2765 ret = regmap_write(ctx->maps[desc->ip],
2766 HW_REVISION_ID, value);
2767 if (ret < 0)
2768 return ret;
2769 }
2770 }
2771
2772 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
2773 desc->mask, val);
2774
2775 if (ret)
2776 return ret;
2777 }
2778
2779 ret = aspeed_sig_expr_eval(ctx, expr, enable);
2780 if (ret < 0)
2781 return ret;
2782
2783 if (!ret)
2784 return -EPERM;
2785
2786 return 0;
2787 }
2788
2789 static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = {
2790 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2791 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2792 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2793 { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
2794 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
2795 };
2796
2797 static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2798 .eval = aspeed_g5_sig_expr_eval,
2799 .set = aspeed_g5_sig_expr_set,
2800 };
2801
2802 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
2803 .pins = aspeed_g5_pins,
2804 .npins = ARRAY_SIZE(aspeed_g5_pins),
2805 .pinmux = {
2806 .ops = &aspeed_g5_ops,
2807 .groups = aspeed_g5_groups,
2808 .ngroups = ARRAY_SIZE(aspeed_g5_groups),
2809 .functions = aspeed_g5_functions,
2810 .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
2811 },
2812 .configs = aspeed_g5_configs,
2813 .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
2814 .confmaps = aspeed_g5_pin_config_map,
2815 .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map),
2816 };
2817
2818 static const struct pinmux_ops aspeed_g5_pinmux_ops = {
2819 .get_functions_count = aspeed_pinmux_get_fn_count,
2820 .get_function_name = aspeed_pinmux_get_fn_name,
2821 .get_function_groups = aspeed_pinmux_get_fn_groups,
2822 .set_mux = aspeed_pinmux_set_mux,
2823 .gpio_request_enable = aspeed_gpio_request_enable,
2824 .strict = true,
2825 };
2826
2827 static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
2828 .get_groups_count = aspeed_pinctrl_get_groups_count,
2829 .get_group_name = aspeed_pinctrl_get_group_name,
2830 .get_group_pins = aspeed_pinctrl_get_group_pins,
2831 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
2832 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2833 .dt_free_map = pinctrl_utils_free_map,
2834 };
2835
2836 static const struct pinconf_ops aspeed_g5_conf_ops = {
2837 .is_generic = true,
2838 .pin_config_get = aspeed_pin_config_get,
2839 .pin_config_set = aspeed_pin_config_set,
2840 .pin_config_group_get = aspeed_pin_config_group_get,
2841 .pin_config_group_set = aspeed_pin_config_group_set,
2842 };
2843
2844 static const struct pinctrl_desc aspeed_g5_pinctrl_desc = {
2845 .name = "aspeed-g5-pinctrl",
2846 .pins = aspeed_g5_pins,
2847 .npins = ARRAY_SIZE(aspeed_g5_pins),
2848 .pctlops = &aspeed_g5_pinctrl_ops,
2849 .pmxops = &aspeed_g5_pinmux_ops,
2850 .confops = &aspeed_g5_conf_ops,
2851 };
2852
aspeed_g5_pinctrl_probe(struct platform_device * pdev)2853 static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
2854 {
2855 int i;
2856
2857 for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
2858 aspeed_g5_pins[i].number = i;
2859
2860 aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
2861
2862 return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
2863 &aspeed_g5_pinctrl_data);
2864 }
2865
2866 static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
2867 { .compatible = "aspeed,ast2500-pinctrl", },
2868 /*
2869 * The aspeed,g5-pinctrl compatible has been removed the from the
2870 * bindings, but keep the match in case of old devicetrees.
2871 */
2872 { .compatible = "aspeed,g5-pinctrl", },
2873 { },
2874 };
2875
2876 static struct platform_driver aspeed_g5_pinctrl_driver = {
2877 .probe = aspeed_g5_pinctrl_probe,
2878 .driver = {
2879 .name = "aspeed-g5-pinctrl",
2880 .of_match_table = aspeed_g5_pinctrl_of_match,
2881 },
2882 };
2883
aspeed_g5_pinctrl_init(void)2884 static int aspeed_g5_pinctrl_init(void)
2885 {
2886 return platform_driver_register(&aspeed_g5_pinctrl_driver);
2887 }
2888
2889 arch_initcall(aspeed_g5_pinctrl_init);
2890