1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for MTK architected m4u v1 implementations
4 *
5 * Copyright (c) 2015-2016 MediaTek Inc.
6 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
7 *
8 * Based on driver/iommu/mtk_iommu.c
9 */
10 #include <linux/bug.h>
11 #include <linux/clk.h>
12 #include <linux/component.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iommu.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/string_choices.h>
29 #include <asm/barrier.h>
30 #include <dt-bindings/memory/mtk-memory-port.h>
31 #include <dt-bindings/memory/mt2701-larb-port.h>
32 #include <soc/mediatek/smi.h>
33
34 #if defined(CONFIG_ARM)
35 #include <asm/dma-iommu.h>
36 #else
37 #define arm_iommu_create_mapping(...) NULL
38 #define arm_iommu_attach_device(...) -ENODEV
39 struct dma_iommu_mapping {
40 struct iommu_domain *domain;
41 };
42 #endif
43
44 #define REG_MMU_PT_BASE_ADDR 0x000
45
46 #define F_ALL_INVLD 0x2
47 #define F_MMU_INV_RANGE 0x1
48 #define F_INVLD_EN0 BIT(0)
49 #define F_INVLD_EN1 BIT(1)
50
51 #define F_MMU_FAULT_VA_MSK 0xfffff000
52 #define MTK_PROTECT_PA_ALIGN 128
53
54 #define REG_MMU_CTRL_REG 0x210
55 #define F_MMU_CTRL_COHERENT_EN BIT(8)
56 #define REG_MMU_IVRP_PADDR 0x214
57 #define REG_MMU_INT_CONTROL 0x220
58 #define F_INT_TRANSLATION_FAULT BIT(0)
59 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
60 #define F_INT_INVALID_PA_FAULT BIT(2)
61 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
62 #define F_INT_TABLE_WALK_FAULT BIT(4)
63 #define F_INT_TLB_MISS_FAULT BIT(5)
64 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
65 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
66
67 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
68 #define F_INT_CLR_BIT BIT(12)
69
70 #define REG_MMU_FAULT_ST 0x224
71 #define REG_MMU_FAULT_VA 0x228
72 #define REG_MMU_INVLD_PA 0x22C
73 #define REG_MMU_INT_ID 0x388
74 #define REG_MMU_INVALIDATE 0x5c0
75 #define REG_MMU_INVLD_START_A 0x5c4
76 #define REG_MMU_INVLD_END_A 0x5c8
77
78 #define REG_MMU_INV_SEL 0x5d8
79 #define REG_MMU_STANDARD_AXI_MODE 0x5e8
80
81 #define REG_MMU_DCM 0x5f0
82 #define F_MMU_DCM_ON BIT(1)
83 #define REG_MMU_CPE_DONE 0x60c
84 #define F_DESC_VALID 0x2
85 #define F_DESC_NONSEC BIT(3)
86 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
87 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
88 /* MTK generation one iommu HW only support 4K size mapping */
89 #define MT2701_IOMMU_PAGE_SHIFT 12
90 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
91 #define MT2701_LARB_NR_MAX 3
92
93 /*
94 * MTK m4u support 4GB iova address space, and only support 4K page
95 * mapping. So the pagetable size should be exactly as 4M.
96 */
97 #define M2701_IOMMU_PGT_SIZE SZ_4M
98
99 struct mtk_iommu_v1_suspend_reg {
100 u32 standard_axi_mode;
101 u32 dcm_dis;
102 u32 ctrl_reg;
103 u32 int_control0;
104 };
105
106 struct mtk_iommu_v1_data {
107 void __iomem *base;
108 int irq;
109 struct device *dev;
110 struct clk *bclk;
111 phys_addr_t protect_base; /* protect memory base */
112 struct mtk_iommu_v1_domain *m4u_dom;
113
114 struct iommu_device iommu;
115 struct dma_iommu_mapping *mapping;
116 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
117
118 struct mtk_iommu_v1_suspend_reg reg;
119 };
120
121 struct mtk_iommu_v1_domain {
122 spinlock_t pgtlock; /* lock for page table */
123 struct iommu_domain domain;
124 u32 *pgt_va;
125 dma_addr_t pgt_pa;
126 struct mtk_iommu_v1_data *data;
127 };
128
mtk_iommu_v1_bind(struct device * dev)129 static int mtk_iommu_v1_bind(struct device *dev)
130 {
131 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
132
133 return component_bind_all(dev, &data->larb_imu);
134 }
135
mtk_iommu_v1_unbind(struct device * dev)136 static void mtk_iommu_v1_unbind(struct device *dev)
137 {
138 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
139
140 component_unbind_all(dev, &data->larb_imu);
141 }
142
to_mtk_domain(struct iommu_domain * dom)143 static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom)
144 {
145 return container_of(dom, struct mtk_iommu_v1_domain, domain);
146 }
147
148 static const int mt2701_m4u_in_larb[] = {
149 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
150 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
151 };
152
mt2701_m4u_to_larb(int id)153 static inline int mt2701_m4u_to_larb(int id)
154 {
155 int i;
156
157 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
158 if ((id) >= mt2701_m4u_in_larb[i])
159 return i;
160
161 return 0;
162 }
163
mt2701_m4u_to_port(int id)164 static inline int mt2701_m4u_to_port(int id)
165 {
166 int larb = mt2701_m4u_to_larb(id);
167
168 return id - mt2701_m4u_in_larb[larb];
169 }
170
mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data * data)171 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data)
172 {
173 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
174 data->base + REG_MMU_INV_SEL);
175 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
176 wmb(); /* Make sure the tlb flush all done */
177 }
178
mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data * data,unsigned long iova,size_t size)179 static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data,
180 unsigned long iova, size_t size)
181 {
182 int ret;
183 u32 tmp;
184
185 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
186 data->base + REG_MMU_INV_SEL);
187 writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
188 data->base + REG_MMU_INVLD_START_A);
189 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
190 data->base + REG_MMU_INVLD_END_A);
191 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
192
193 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
194 tmp, tmp != 0, 10, 100000);
195 if (ret) {
196 dev_warn(data->dev,
197 "Partial TLB flush timed out, falling back to full flush\n");
198 mtk_iommu_v1_tlb_flush_all(data);
199 }
200 /* Clear the CPE status */
201 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
202 }
203
mtk_iommu_v1_isr(int irq,void * dev_id)204 static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id)
205 {
206 struct mtk_iommu_v1_data *data = dev_id;
207 struct mtk_iommu_v1_domain *dom = data->m4u_dom;
208 u32 int_state, regval, fault_iova, fault_pa;
209 unsigned int fault_larb, fault_port;
210
211 /* Read error information from registers */
212 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
213 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
214
215 fault_iova &= F_MMU_FAULT_VA_MSK;
216 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
217 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
218 fault_larb = MT2701_M4U_TF_LARB(regval);
219 fault_port = MT2701_M4U_TF_PORT(regval);
220
221 /*
222 * MTK v1 iommu HW could not determine whether the fault is read or
223 * write fault, report as read fault.
224 */
225 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
226 IOMMU_FAULT_READ))
227 dev_err_ratelimited(data->dev,
228 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
229 int_state, fault_iova, fault_pa,
230 fault_larb, fault_port);
231
232 /* Interrupt clear */
233 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
234 regval |= F_INT_CLR_BIT;
235 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
236
237 mtk_iommu_v1_tlb_flush_all(data);
238
239 return IRQ_HANDLED;
240 }
241
mtk_iommu_v1_config(struct mtk_iommu_v1_data * data,struct device * dev,bool enable)242 static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data,
243 struct device *dev, bool enable)
244 {
245 struct mtk_smi_larb_iommu *larb_mmu;
246 unsigned int larbid, portid;
247 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
248 int i;
249
250 for (i = 0; i < fwspec->num_ids; ++i) {
251 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
252 portid = mt2701_m4u_to_port(fwspec->ids[i]);
253 larb_mmu = &data->larb_imu[larbid];
254
255 dev_dbg(dev, "%s iommu port: %d\n",
256 str_enable_disable(enable), portid);
257
258 if (enable)
259 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
260 else
261 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
262 }
263 }
264
mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data * data)265 static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data)
266 {
267 struct mtk_iommu_v1_domain *dom = data->m4u_dom;
268
269 spin_lock_init(&dom->pgtlock);
270
271 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
272 &dom->pgt_pa, GFP_KERNEL);
273 if (!dom->pgt_va)
274 return -ENOMEM;
275
276 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
277
278 dom->data = data;
279
280 return 0;
281 }
282
mtk_iommu_v1_domain_alloc_paging(struct device * dev)283 static struct iommu_domain *mtk_iommu_v1_domain_alloc_paging(struct device *dev)
284 {
285 struct mtk_iommu_v1_domain *dom;
286
287 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
288 if (!dom)
289 return NULL;
290
291 dom->domain.pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE;
292
293 return &dom->domain;
294 }
295
mtk_iommu_v1_domain_free(struct iommu_domain * domain)296 static void mtk_iommu_v1_domain_free(struct iommu_domain *domain)
297 {
298 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
299 struct mtk_iommu_v1_data *data = dom->data;
300
301 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
302 dom->pgt_va, dom->pgt_pa);
303 kfree(to_mtk_domain(domain));
304 }
305
mtk_iommu_v1_attach_device(struct iommu_domain * domain,struct device * dev,struct iommu_domain * old)306 static int mtk_iommu_v1_attach_device(struct iommu_domain *domain,
307 struct device *dev,
308 struct iommu_domain *old)
309 {
310 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
311 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
312 struct dma_iommu_mapping *mtk_mapping;
313 int ret;
314
315 /* Only allow the domain created internally. */
316 mtk_mapping = data->mapping;
317 if (mtk_mapping->domain != domain)
318 return 0;
319
320 if (!data->m4u_dom) {
321 data->m4u_dom = dom;
322 ret = mtk_iommu_v1_domain_finalise(data);
323 if (ret) {
324 data->m4u_dom = NULL;
325 return ret;
326 }
327 }
328
329 mtk_iommu_v1_config(data, dev, true);
330 return 0;
331 }
332
mtk_iommu_v1_identity_attach(struct iommu_domain * identity_domain,struct device * dev,struct iommu_domain * old)333 static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain,
334 struct device *dev,
335 struct iommu_domain *old)
336 {
337 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
338
339 mtk_iommu_v1_config(data, dev, false);
340 return 0;
341 }
342
343 static struct iommu_domain_ops mtk_iommu_v1_identity_ops = {
344 .attach_dev = mtk_iommu_v1_identity_attach,
345 };
346
347 static struct iommu_domain mtk_iommu_v1_identity_domain = {
348 .type = IOMMU_DOMAIN_IDENTITY,
349 .ops = &mtk_iommu_v1_identity_ops,
350 };
351
mtk_iommu_v1_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)352 static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova,
353 phys_addr_t paddr, size_t pgsize, size_t pgcount,
354 int prot, gfp_t gfp, size_t *mapped)
355 {
356 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
357 unsigned long flags;
358 unsigned int i;
359 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
360 u32 pabase = (u32)paddr;
361
362 spin_lock_irqsave(&dom->pgtlock, flags);
363 for (i = 0; i < pgcount; i++) {
364 if (pgt_base_iova[i])
365 break;
366 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
367 pabase += MT2701_IOMMU_PAGE_SIZE;
368 }
369
370 spin_unlock_irqrestore(&dom->pgtlock, flags);
371
372 *mapped = i * MT2701_IOMMU_PAGE_SIZE;
373 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped);
374
375 return i == pgcount ? 0 : -EEXIST;
376 }
377
mtk_iommu_v1_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)378 static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova,
379 size_t pgsize, size_t pgcount,
380 struct iommu_iotlb_gather *gather)
381 {
382 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
383 unsigned long flags;
384 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
385 size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE;
386
387 spin_lock_irqsave(&dom->pgtlock, flags);
388 memset(pgt_base_iova, 0, pgcount * sizeof(u32));
389 spin_unlock_irqrestore(&dom->pgtlock, flags);
390
391 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
392
393 return size;
394 }
395
mtk_iommu_v1_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)396 static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
397 {
398 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
399 unsigned long flags;
400 phys_addr_t pa;
401
402 spin_lock_irqsave(&dom->pgtlock, flags);
403 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
404 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
405 spin_unlock_irqrestore(&dom->pgtlock, flags);
406
407 return pa;
408 }
409
410 static const struct iommu_ops mtk_iommu_v1_ops;
411
412 /*
413 * MTK generation one iommu HW only support one iommu domain, and all the client
414 * sharing the same iova address space.
415 */
mtk_iommu_v1_create_mapping(struct device * dev,const struct of_phandle_args * args)416 static int mtk_iommu_v1_create_mapping(struct device *dev,
417 const struct of_phandle_args *args)
418 {
419 struct mtk_iommu_v1_data *data;
420 struct platform_device *m4updev;
421 struct dma_iommu_mapping *mtk_mapping;
422 int ret;
423
424 if (args->args_count != 1) {
425 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
426 args->args_count);
427 return -EINVAL;
428 }
429
430 ret = iommu_fwspec_init(dev, of_fwnode_handle(args->np));
431 if (ret)
432 return ret;
433
434 if (!dev_iommu_priv_get(dev)) {
435 /* Get the m4u device */
436 m4updev = of_find_device_by_node(args->np);
437 if (WARN_ON(!m4updev))
438 return -EINVAL;
439
440 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
441
442 put_device(&m4updev->dev);
443 }
444
445 ret = iommu_fwspec_add_ids(dev, args->args, 1);
446 if (ret)
447 return ret;
448
449 data = dev_iommu_priv_get(dev);
450 mtk_mapping = data->mapping;
451 if (!mtk_mapping) {
452 /* MTK iommu support 4GB iova address space. */
453 mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32);
454 if (IS_ERR(mtk_mapping))
455 return PTR_ERR(mtk_mapping);
456
457 data->mapping = mtk_mapping;
458 }
459
460 return 0;
461 }
462
mtk_iommu_v1_probe_device(struct device * dev)463 static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)
464 {
465 struct iommu_fwspec *fwspec = NULL;
466 struct of_phandle_args iommu_spec;
467 struct mtk_iommu_v1_data *data;
468 int err, idx = 0, larbid, larbidx;
469 struct device_link *link;
470 struct device *larbdev;
471
472 while (!of_parse_phandle_with_args(dev->of_node, "iommus",
473 "#iommu-cells",
474 idx, &iommu_spec)) {
475
476 err = mtk_iommu_v1_create_mapping(dev, &iommu_spec);
477 of_node_put(iommu_spec.np);
478 if (err)
479 return ERR_PTR(err);
480
481 /* dev->iommu_fwspec might have changed */
482 fwspec = dev_iommu_fwspec_get(dev);
483 idx++;
484 }
485
486 if (!fwspec)
487 return ERR_PTR(-ENODEV);
488
489 data = dev_iommu_priv_get(dev);
490
491 /* Link the consumer device with the smi-larb device(supplier) */
492 larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
493 if (larbid >= MT2701_LARB_NR_MAX)
494 return ERR_PTR(-EINVAL);
495
496 for (idx = 1; idx < fwspec->num_ids; idx++) {
497 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]);
498 if (larbid != larbidx) {
499 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
500 larbid, larbidx);
501 return ERR_PTR(-EINVAL);
502 }
503 }
504
505 larbdev = data->larb_imu[larbid].dev;
506 if (!larbdev)
507 return ERR_PTR(-EINVAL);
508
509 link = device_link_add(dev, larbdev,
510 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
511 if (!link)
512 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
513
514 return &data->iommu;
515 }
516
mtk_iommu_v1_probe_finalize(struct device * dev)517 static void mtk_iommu_v1_probe_finalize(struct device *dev)
518 {
519 __maybe_unused struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
520 int err;
521
522 err = arm_iommu_attach_device(dev, data->mapping);
523 if (err)
524 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
525 }
526
mtk_iommu_v1_release_device(struct device * dev)527 static void mtk_iommu_v1_release_device(struct device *dev)
528 {
529 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
530 struct mtk_iommu_v1_data *data;
531 struct device *larbdev;
532 unsigned int larbid;
533
534 data = dev_iommu_priv_get(dev);
535 larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
536 larbdev = data->larb_imu[larbid].dev;
537 device_link_remove(dev, larbdev);
538 }
539
mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data * data)540 static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data)
541 {
542 u32 regval;
543 int ret;
544
545 ret = clk_prepare_enable(data->bclk);
546 if (ret) {
547 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
548 return ret;
549 }
550
551 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
552 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
553
554 regval = F_INT_TRANSLATION_FAULT |
555 F_INT_MAIN_MULTI_HIT_FAULT |
556 F_INT_INVALID_PA_FAULT |
557 F_INT_ENTRY_REPLACEMENT_FAULT |
558 F_INT_TABLE_WALK_FAULT |
559 F_INT_TLB_MISS_FAULT |
560 F_INT_PFH_DMA_FIFO_OVERFLOW |
561 F_INT_MISS_DMA_FIFO_OVERFLOW;
562 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
563
564 /* protect memory,hw will write here while translation fault */
565 writel_relaxed(data->protect_base,
566 data->base + REG_MMU_IVRP_PADDR);
567
568 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
569
570 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0,
571 dev_name(data->dev), (void *)data)) {
572 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
573 clk_disable_unprepare(data->bclk);
574 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
575 return -ENODEV;
576 }
577
578 return 0;
579 }
580
581 static const struct iommu_ops mtk_iommu_v1_ops = {
582 .identity_domain = &mtk_iommu_v1_identity_domain,
583 .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging,
584 .probe_device = mtk_iommu_v1_probe_device,
585 .probe_finalize = mtk_iommu_v1_probe_finalize,
586 .release_device = mtk_iommu_v1_release_device,
587 .device_group = generic_device_group,
588 .owner = THIS_MODULE,
589 .default_domain_ops = &(const struct iommu_domain_ops) {
590 .attach_dev = mtk_iommu_v1_attach_device,
591 .map_pages = mtk_iommu_v1_map,
592 .unmap_pages = mtk_iommu_v1_unmap,
593 .iova_to_phys = mtk_iommu_v1_iova_to_phys,
594 .free = mtk_iommu_v1_domain_free,
595 }
596 };
597
598 static const struct of_device_id mtk_iommu_v1_of_ids[] = {
599 { .compatible = "mediatek,mt2701-m4u", },
600 {}
601 };
602 MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids);
603
604 static const struct component_master_ops mtk_iommu_v1_com_ops = {
605 .bind = mtk_iommu_v1_bind,
606 .unbind = mtk_iommu_v1_unbind,
607 };
608
mtk_iommu_v1_probe(struct platform_device * pdev)609 static int mtk_iommu_v1_probe(struct platform_device *pdev)
610 {
611 struct device *dev = &pdev->dev;
612 struct mtk_iommu_v1_data *data;
613 struct resource *res;
614 struct component_match *match = NULL;
615 void *protect;
616 int larb_nr, ret, i;
617
618 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
619 if (!data)
620 return -ENOMEM;
621
622 data->dev = dev;
623
624 /* Protect memory. HW will access here while translation fault.*/
625 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN,
626 GFP_KERNEL | GFP_DMA);
627 if (!protect)
628 return -ENOMEM;
629 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
630
631 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 data->base = devm_ioremap_resource(dev, res);
633 if (IS_ERR(data->base))
634 return PTR_ERR(data->base);
635
636 data->irq = platform_get_irq(pdev, 0);
637 if (data->irq < 0)
638 return data->irq;
639
640 data->bclk = devm_clk_get(dev, "bclk");
641 if (IS_ERR(data->bclk))
642 return PTR_ERR(data->bclk);
643
644 larb_nr = of_count_phandle_with_args(dev->of_node,
645 "mediatek,larbs", NULL);
646 if (larb_nr < 0)
647 return larb_nr;
648
649 if (larb_nr > MTK_LARB_NR_MAX)
650 return -EINVAL;
651
652 for (i = 0; i < larb_nr; i++) {
653 struct device_node *larbnode;
654 struct platform_device *plarbdev;
655
656 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
657 if (!larbnode) {
658 ret = -EINVAL;
659 goto out_put_larbs;
660 }
661
662 if (!of_device_is_available(larbnode)) {
663 of_node_put(larbnode);
664 continue;
665 }
666
667 plarbdev = of_find_device_by_node(larbnode);
668 if (!plarbdev) {
669 of_node_put(larbnode);
670 ret = -ENODEV;
671 goto out_put_larbs;
672 }
673 if (!plarbdev->dev.driver) {
674 of_node_put(larbnode);
675 put_device(&plarbdev->dev);
676 ret = -EPROBE_DEFER;
677 goto out_put_larbs;
678 }
679 data->larb_imu[i].dev = &plarbdev->dev;
680
681 component_match_add_release(dev, &match, component_release_of,
682 component_compare_of, larbnode);
683 }
684
685 platform_set_drvdata(pdev, data);
686
687 ret = mtk_iommu_v1_hw_init(data);
688 if (ret)
689 goto out_put_larbs;
690
691 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
692 dev_name(&pdev->dev));
693 if (ret)
694 goto out_clk_unprepare;
695
696 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev);
697 if (ret)
698 goto out_sysfs_remove;
699
700 ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match);
701 if (ret)
702 goto out_dev_unreg;
703 return ret;
704
705 out_dev_unreg:
706 iommu_device_unregister(&data->iommu);
707 out_sysfs_remove:
708 iommu_device_sysfs_remove(&data->iommu);
709 out_clk_unprepare:
710 clk_disable_unprepare(data->bclk);
711 out_put_larbs:
712 for (i = 0; i < MTK_LARB_NR_MAX; i++)
713 put_device(data->larb_imu[i].dev);
714
715 return ret;
716 }
717
mtk_iommu_v1_remove(struct platform_device * pdev)718 static void mtk_iommu_v1_remove(struct platform_device *pdev)
719 {
720 struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev);
721 int i;
722
723 iommu_device_sysfs_remove(&data->iommu);
724 iommu_device_unregister(&data->iommu);
725
726 clk_disable_unprepare(data->bclk);
727 devm_free_irq(&pdev->dev, data->irq, data);
728 component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops);
729
730 for (i = 0; i < MTK_LARB_NR_MAX; i++)
731 put_device(data->larb_imu[i].dev);
732 }
733
mtk_iommu_v1_suspend(struct device * dev)734 static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev)
735 {
736 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
737 struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
738 void __iomem *base = data->base;
739
740 reg->standard_axi_mode = readl_relaxed(base +
741 REG_MMU_STANDARD_AXI_MODE);
742 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
743 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
744 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
745 return 0;
746 }
747
mtk_iommu_v1_resume(struct device * dev)748 static int __maybe_unused mtk_iommu_v1_resume(struct device *dev)
749 {
750 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
751 struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
752 void __iomem *base = data->base;
753
754 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
755 writel_relaxed(reg->standard_axi_mode,
756 base + REG_MMU_STANDARD_AXI_MODE);
757 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
758 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
759 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
760 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
761 return 0;
762 }
763
764 static const struct dev_pm_ops mtk_iommu_v1_pm_ops = {
765 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume)
766 };
767
768 static struct platform_driver mtk_iommu_v1_driver = {
769 .probe = mtk_iommu_v1_probe,
770 .remove = mtk_iommu_v1_remove,
771 .driver = {
772 .name = "mtk-iommu-v1",
773 .of_match_table = mtk_iommu_v1_of_ids,
774 .pm = &mtk_iommu_v1_pm_ops,
775 }
776 };
777 module_platform_driver(mtk_iommu_v1_driver);
778
779 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
780 MODULE_LICENSE("GPL v2");
781