1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * set_id_regs - Test for setting ID register from usersapce. 4 * 5 * Copyright (c) 2023 Google LLC. 6 * 7 * 8 * Test that KVM supports setting ID registers from userspace and handles the 9 * feature set correctly. 10 */ 11 12 #include <stdint.h> 13 #include "kvm_util.h" 14 #include "processor.h" 15 #include "test_util.h" 16 #include <linux/bitfield.h> 17 18 enum ftr_type { 19 FTR_EXACT, /* Use a predefined safe value */ 20 FTR_LOWER_SAFE, /* Smaller value is safe */ 21 FTR_HIGHER_SAFE, /* Bigger value is safe */ 22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 23 FTR_END, /* Mark the last ftr bits */ 24 }; 25 26 #define FTR_SIGNED true /* Value should be treated as signed */ 27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 28 29 struct reg_ftr_bits { 30 char *name; 31 bool sign; 32 enum ftr_type type; 33 uint8_t shift; 34 uint64_t mask; 35 /* 36 * For FTR_EXACT, safe_val is used as the exact safe value. 37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. 38 */ 39 int64_t safe_val; 40 }; 41 42 struct test_feature_reg { 43 uint32_t reg; 44 const struct reg_ftr_bits *ftr_bits; 45 }; 46 47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \ 48 { \ 49 .name = #NAME, \ 50 .sign = SIGNED, \ 51 .type = TYPE, \ 52 .shift = SHIFT, \ 53 .mask = MASK, \ 54 .safe_val = SAFE_VAL, \ 55 } 56 57 #define REG_FTR_BITS(type, reg, field, safe_val) \ 58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 59 reg##_##field##_MASK, safe_val) 60 61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \ 62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \ 63 reg##_##field##_MASK, safe_val) 64 65 #define REG_FTR_END \ 66 { \ 67 .type = FTR_END, \ 68 } 69 70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = { 71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0), 72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0), 73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0), 74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP), 75 REG_FTR_END, 76 }; 77 78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = { 79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3), 80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8), 81 REG_FTR_END, 82 }; 83 84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = { 85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0), 86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0), 87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0), 88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0), 89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0), 90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0), 91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0), 92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0), 93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0), 94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0), 95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0), 96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0), 97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0), 98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0), 99 REG_FTR_END, 100 }; 101 102 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = { 103 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0), 104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0), 105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0), 106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0), 107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0), 108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0), 109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0), 110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0), 111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0), 112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0), 113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0), 114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0), 115 REG_FTR_END, 116 }; 117 118 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = { 119 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0), 120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0), 121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0), 122 REG_FTR_END, 123 }; 124 125 static const struct reg_ftr_bits ftr_id_aa64isar3_el1[] = { 126 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FPRCVT, 0), 127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, LSFE, 0), 128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FAMINMAX, 0), 129 REG_FTR_END, 130 }; 131 132 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { 133 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0), 134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), 135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0), 136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0), 137 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0), 138 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1), 139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1), 140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1), 141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1), 142 REG_FTR_END, 143 }; 144 145 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = { 146 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0), 147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0), 148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI), 149 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), 150 REG_FTR_END, 151 }; 152 153 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = { 154 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0), 155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0), 156 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1), 157 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1), 158 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1), 159 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0), 160 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0), 161 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0), 162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0), 163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0), 164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0), 165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0), 166 REG_FTR_END, 167 }; 168 169 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = { 170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0), 171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0), 172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HCX, 0), 173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0), 174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TWED, 0), 175 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0), 176 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0), 177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0), 178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0), 179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0), 180 REG_FTR_END, 181 }; 182 183 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = { 184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0), 185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0), 186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0), 187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0), 188 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0), 189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0), 190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0), 191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0), 192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0), 193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0), 194 REG_FTR_END, 195 }; 196 197 static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = { 198 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1POE, 0), 199 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1PIE, 0), 200 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, SCTLRX, 0), 201 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, TCRX, 0), 202 REG_FTR_END, 203 }; 204 205 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = { 206 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0), 207 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0), 208 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0), 209 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0), 210 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0), 211 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0), 212 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0), 213 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0), 214 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0), 215 REG_FTR_END, 216 }; 217 218 #define TEST_REG(id, table) \ 219 { \ 220 .reg = id, \ 221 .ftr_bits = &((table)[0]), \ 222 } 223 224 static struct test_feature_reg test_regs[] = { 225 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), 226 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1), 227 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), 228 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), 229 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), 230 TEST_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1), 231 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), 232 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), 233 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), 234 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), 235 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), 236 TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1), 237 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), 238 }; 239 240 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0); 241 242 static void guest_code(void) 243 { 244 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1); 245 GUEST_REG_SYNC(SYS_ID_DFR0_EL1); 246 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1); 247 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1); 248 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1); 249 GUEST_REG_SYNC(SYS_ID_AA64ISAR3_EL1); 250 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1); 251 GUEST_REG_SYNC(SYS_ID_AA64PFR1_EL1); 252 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); 253 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); 254 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); 255 GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1); 256 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); 257 GUEST_REG_SYNC(SYS_MPIDR_EL1); 258 GUEST_REG_SYNC(SYS_CLIDR_EL1); 259 GUEST_REG_SYNC(SYS_CTR_EL0); 260 GUEST_REG_SYNC(SYS_MIDR_EL1); 261 GUEST_REG_SYNC(SYS_REVIDR_EL1); 262 GUEST_REG_SYNC(SYS_AIDR_EL1); 263 264 GUEST_DONE(); 265 } 266 267 /* Return a safe value to a given ftr_bits an ftr value */ 268 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 269 { 270 uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift; 271 272 TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features"); 273 274 if (ftr_bits->sign == FTR_UNSIGNED) { 275 switch (ftr_bits->type) { 276 case FTR_EXACT: 277 ftr = ftr_bits->safe_val; 278 break; 279 case FTR_LOWER_SAFE: 280 if (ftr > ftr_bits->safe_val) 281 ftr--; 282 break; 283 case FTR_HIGHER_SAFE: 284 if (ftr < ftr_max) 285 ftr++; 286 break; 287 case FTR_HIGHER_OR_ZERO_SAFE: 288 if (ftr == ftr_max) 289 ftr = 0; 290 else if (ftr != 0) 291 ftr++; 292 break; 293 default: 294 break; 295 } 296 } else if (ftr != ftr_max) { 297 switch (ftr_bits->type) { 298 case FTR_EXACT: 299 ftr = ftr_bits->safe_val; 300 break; 301 case FTR_LOWER_SAFE: 302 if (ftr > ftr_bits->safe_val) 303 ftr--; 304 break; 305 case FTR_HIGHER_SAFE: 306 if (ftr < ftr_max - 1) 307 ftr++; 308 break; 309 case FTR_HIGHER_OR_ZERO_SAFE: 310 if (ftr != 0 && ftr != ftr_max - 1) 311 ftr++; 312 break; 313 default: 314 break; 315 } 316 } 317 318 return ftr; 319 } 320 321 /* Return an invalid value to a given ftr_bits an ftr value */ 322 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 323 { 324 uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift; 325 326 TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features"); 327 328 if (ftr_bits->sign == FTR_UNSIGNED) { 329 switch (ftr_bits->type) { 330 case FTR_EXACT: 331 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 332 break; 333 case FTR_LOWER_SAFE: 334 ftr++; 335 break; 336 case FTR_HIGHER_SAFE: 337 ftr--; 338 break; 339 case FTR_HIGHER_OR_ZERO_SAFE: 340 if (ftr == 0) 341 ftr = ftr_max; 342 else 343 ftr--; 344 break; 345 default: 346 break; 347 } 348 } else if (ftr != ftr_max) { 349 switch (ftr_bits->type) { 350 case FTR_EXACT: 351 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 352 break; 353 case FTR_LOWER_SAFE: 354 ftr++; 355 break; 356 case FTR_HIGHER_SAFE: 357 ftr--; 358 break; 359 case FTR_HIGHER_OR_ZERO_SAFE: 360 if (ftr == 0) 361 ftr = ftr_max - 1; 362 else 363 ftr--; 364 break; 365 default: 366 break; 367 } 368 } else { 369 ftr = 0; 370 } 371 372 return ftr; 373 } 374 375 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, 376 const struct reg_ftr_bits *ftr_bits) 377 { 378 uint8_t shift = ftr_bits->shift; 379 uint64_t mask = ftr_bits->mask; 380 uint64_t val, new_val, ftr; 381 382 val = vcpu_get_reg(vcpu, reg); 383 ftr = (val & mask) >> shift; 384 385 ftr = get_safe_value(ftr_bits, ftr); 386 387 ftr <<= shift; 388 val &= ~mask; 389 val |= ftr; 390 391 vcpu_set_reg(vcpu, reg, val); 392 new_val = vcpu_get_reg(vcpu, reg); 393 TEST_ASSERT_EQ(new_val, val); 394 395 return new_val; 396 } 397 398 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, 399 const struct reg_ftr_bits *ftr_bits) 400 { 401 uint8_t shift = ftr_bits->shift; 402 uint64_t mask = ftr_bits->mask; 403 uint64_t val, old_val, ftr; 404 int r; 405 406 val = vcpu_get_reg(vcpu, reg); 407 ftr = (val & mask) >> shift; 408 409 ftr = get_invalid_value(ftr_bits, ftr); 410 411 old_val = val; 412 ftr <<= shift; 413 val &= ~mask; 414 val |= ftr; 415 416 r = __vcpu_set_reg(vcpu, reg, val); 417 TEST_ASSERT(r < 0 && errno == EINVAL, 418 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); 419 420 val = vcpu_get_reg(vcpu, reg); 421 TEST_ASSERT_EQ(val, old_val); 422 } 423 424 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 425 426 #define encoding_to_range_idx(encoding) \ 427 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \ 428 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \ 429 sys_reg_Op2(encoding)) 430 431 432 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) 433 { 434 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 435 struct reg_mask_range range = { 436 .addr = (__u64)masks, 437 }; 438 int ret; 439 440 /* KVM should return error when reserved field is not zero */ 441 range.reserved[0] = 1; 442 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 443 TEST_ASSERT(ret, "KVM doesn't check invalid parameters."); 444 445 /* Get writable masks for feature ID registers */ 446 memset(range.reserved, 0, sizeof(range.reserved)); 447 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 448 449 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { 450 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits; 451 uint32_t reg_id = test_regs[i].reg; 452 uint64_t reg = KVM_ARM64_SYS_REG(reg_id); 453 int idx; 454 455 /* Get the index to masks array for the idreg */ 456 idx = encoding_to_range_idx(reg_id); 457 458 for (int j = 0; ftr_bits[j].type != FTR_END; j++) { 459 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ 460 if (aarch64_only && sys_reg_CRm(reg_id) < 4) { 461 ksft_test_result_skip("%s on AARCH64 only system\n", 462 ftr_bits[j].name); 463 continue; 464 } 465 466 /* Make sure the feature field is writable */ 467 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask); 468 469 test_reg_set_fail(vcpu, reg, &ftr_bits[j]); 470 471 test_reg_vals[idx] = test_reg_set_success(vcpu, reg, 472 &ftr_bits[j]); 473 474 ksft_test_result_pass("%s\n", ftr_bits[j].name); 475 } 476 } 477 } 478 479 #define MPAM_IDREG_TEST 6 480 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu) 481 { 482 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 483 struct reg_mask_range range = { 484 .addr = (__u64)masks, 485 }; 486 uint64_t val; 487 int idx, err; 488 489 /* 490 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero, 491 * check that if it can be set to 1, (i.e. it is supported by the 492 * hardware), that it can't be set to other values. 493 */ 494 495 /* Get writable masks for feature ID registers */ 496 memset(range.reserved, 0, sizeof(range.reserved)); 497 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 498 499 /* Writeable? Nothing to test! */ 500 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1); 501 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) { 502 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n"); 503 return; 504 } 505 506 /* Get the id register value */ 507 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 508 509 /* Try to set MPAM=0. This should always be possible. */ 510 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 511 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0); 512 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 513 if (err) 514 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n"); 515 else 516 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n"); 517 518 /* Try to set MPAM=1 */ 519 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 520 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1); 521 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 522 if (err) 523 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n"); 524 else 525 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n"); 526 527 /* Try to set MPAM=2 */ 528 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 529 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2); 530 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 531 if (err) 532 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n"); 533 else 534 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n"); 535 536 /* And again for ID_AA64PFR1_EL1.MPAM_frac */ 537 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1); 538 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) { 539 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n"); 540 return; 541 } 542 543 /* Get the id register value */ 544 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 545 546 /* Try to set MPAM_frac=0. This should always be possible. */ 547 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 548 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0); 549 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 550 if (err) 551 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n"); 552 else 553 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n"); 554 555 /* Try to set MPAM_frac=1 */ 556 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 557 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1); 558 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 559 if (err) 560 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n"); 561 else 562 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n"); 563 564 /* Try to set MPAM_frac=2 */ 565 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 566 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2); 567 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 568 if (err) 569 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n"); 570 else 571 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n"); 572 } 573 574 #define MTE_IDREG_TEST 1 575 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu) 576 { 577 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 578 struct reg_mask_range range = { 579 .addr = (__u64)masks, 580 }; 581 uint64_t val; 582 uint64_t mte; 583 uint64_t mte_frac; 584 int idx, err; 585 586 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 587 mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val); 588 if (!mte) { 589 ksft_test_result_skip("MTE capability not supported, nothing to test\n"); 590 return; 591 } 592 593 /* Get writable masks for feature ID registers */ 594 memset(range.reserved, 0, sizeof(range.reserved)); 595 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 596 597 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1); 598 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) { 599 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n"); 600 return; 601 } 602 603 /* 604 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2) 605 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported 606 * and MTE_frac == 0 indicates it is supported. 607 * 608 * As MTE_frac was previously unconditionally read as 0, check 609 * that the set to 0 succeeds but does not change MTE_frac 610 * from unsupported (0xF) to supported (0). 611 * 612 */ 613 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 614 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 || 615 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) { 616 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n"); 617 return; 618 } 619 620 /* Try to set MTE_frac=0. */ 621 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 622 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0); 623 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 624 if (err) { 625 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n"); 626 return; 627 } 628 629 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 630 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 631 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI) 632 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n"); 633 else 634 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n"); 635 } 636 637 static void test_guest_reg_read(struct kvm_vcpu *vcpu) 638 { 639 bool done = false; 640 struct ucall uc; 641 642 while (!done) { 643 vcpu_run(vcpu); 644 645 switch (get_ucall(vcpu, &uc)) { 646 case UCALL_ABORT: 647 REPORT_GUEST_ASSERT(uc); 648 break; 649 case UCALL_SYNC: 650 /* Make sure the written values are seen by guest */ 651 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])], 652 uc.args[3]); 653 break; 654 case UCALL_DONE: 655 done = true; 656 break; 657 default: 658 TEST_FAIL("Unexpected ucall: %lu", uc.cmd); 659 } 660 } 661 } 662 663 /* Politely lifted from arch/arm64/include/asm/cache.h */ 664 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 665 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 666 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) 667 #define CLIDR_CTYPE(clidr, level) \ 668 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) 669 670 static void test_clidr(struct kvm_vcpu *vcpu) 671 { 672 uint64_t clidr; 673 int level; 674 675 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1)); 676 677 /* find the first empty level in the cache hierarchy */ 678 for (level = 1; level <= 7; level++) { 679 if (!CLIDR_CTYPE(clidr, level)) 680 break; 681 } 682 683 /* 684 * If you have a mind-boggling 7 levels of cache, congratulations, you 685 * get to fix this. 686 */ 687 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy"); 688 689 /* stick in a unified cache level */ 690 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level); 691 692 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr); 693 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr; 694 } 695 696 static void test_ctr(struct kvm_vcpu *vcpu) 697 { 698 u64 ctr; 699 700 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0)); 701 ctr &= ~CTR_EL0_DIC_MASK; 702 if (ctr & CTR_EL0_IminLine_MASK) 703 ctr--; 704 705 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr); 706 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr; 707 } 708 709 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id) 710 { 711 u64 val; 712 713 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id)); 714 val++; 715 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val); 716 test_reg_vals[encoding_to_range_idx(id)] = val; 717 } 718 719 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu) 720 { 721 test_clidr(vcpu); 722 test_ctr(vcpu); 723 724 test_id_reg(vcpu, SYS_MPIDR_EL1); 725 ksft_test_result_pass("%s\n", __func__); 726 } 727 728 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu) 729 { 730 test_id_reg(vcpu, SYS_MIDR_EL1); 731 test_id_reg(vcpu, SYS_REVIDR_EL1); 732 test_id_reg(vcpu, SYS_AIDR_EL1); 733 734 ksft_test_result_pass("%s\n", __func__); 735 } 736 737 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding) 738 { 739 size_t idx = encoding_to_range_idx(encoding); 740 uint64_t observed; 741 742 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); 743 TEST_ASSERT_EQ(test_reg_vals[idx], observed); 744 } 745 746 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu) 747 { 748 /* 749 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an 750 * architectural reset of the vCPU. 751 */ 752 aarch64_vcpu_setup(vcpu, NULL); 753 754 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) 755 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg); 756 757 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1); 758 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1); 759 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0); 760 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1); 761 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1); 762 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1); 763 764 ksft_test_result_pass("%s\n", __func__); 765 } 766 767 int main(void) 768 { 769 struct kvm_vcpu *vcpu; 770 struct kvm_vm *vm; 771 bool aarch64_only; 772 uint64_t val, el0; 773 int test_cnt, i, j; 774 775 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES)); 776 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS)); 777 778 test_wants_mte(); 779 780 vm = vm_create(1); 781 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0); 782 vcpu = vm_vcpu_add(vm, 0, guest_code); 783 kvm_arch_vm_finalize_vcpus(vm); 784 785 /* Check for AARCH64 only system */ 786 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 787 el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val); 788 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP); 789 790 ksft_print_header(); 791 792 test_cnt = 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST; 793 for (i = 0; i < ARRAY_SIZE(test_regs); i++) 794 for (j = 0; test_regs[i].ftr_bits[j].type != FTR_END; j++) 795 test_cnt++; 796 797 ksft_set_plan(test_cnt); 798 799 test_vm_ftr_id_regs(vcpu, aarch64_only); 800 test_vcpu_ftr_id_regs(vcpu); 801 test_vcpu_non_ftr_id_regs(vcpu); 802 test_user_set_mpam_reg(vcpu); 803 test_user_set_mte_reg(vcpu); 804 805 test_guest_reg_read(vcpu); 806 807 test_reset_preserves_id_regs(vcpu); 808 809 kvm_vm_free(vm); 810 811 ksft_finished(); 812 } 813