1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for PCI support. 4 */ 5 #define FL_BASE_MASK 0x0007 6 #define FL_BASE0 0x0000 7 #define FL_BASE1 0x0001 8 #define FL_BASE2 0x0002 9 #define FL_BASE3 0x0003 10 #define FL_BASE4 0x0004 11 #define FL_GET_BASE(x) (x & FL_BASE_MASK) 12 13 /* Use successive BARs (PCI base address registers), 14 else use offset into some specified BAR */ 15 #define FL_BASE_BARS 0x0008 16 17 /* do not assign an irq */ 18 #define FL_NOIRQ 0x0080 19 20 /* Use the Base address register size to cap number of ports */ 21 #define FL_REGION_SZ_CAP 0x0100 22 23 struct pciserial_board { 24 unsigned int flags; 25 unsigned int num_ports; 26 unsigned int base_baud; 27 unsigned int uart_offset; 28 unsigned int reg_shift; 29 unsigned int first_offset; 30 }; 31 32 struct serial_private; 33 34 struct serial_private * 35 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board); 36 void pciserial_remove_ports(struct serial_private *priv); 37 void pciserial_suspend_ports(struct serial_private *priv); 38 void pciserial_resume_ports(struct serial_private *priv); 39