1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Broadcom Corporation 4 * Copyright 2013 Linaro Limited 5 */ 6 7 #ifndef _CLK_KONA_H 8 #define _CLK_KONA_H 9 10 #include <linux/kernel.h> 11 #include <linux/list.h> 12 #include <linux/spinlock.h> 13 #include <linux/slab.h> 14 #include <linux/device.h> 15 #include <linux/of.h> 16 #include <linux/clk-provider.h> 17 18 #define BILLION 1000000000 19 20 /* The common clock framework uses u8 to represent a parent index */ 21 #define PARENT_COUNT_MAX ((u32)U8_MAX) 22 23 #define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ 24 #define BAD_CLK_NAME ((const char *)-1) 25 26 #define BAD_SCALED_DIV_VALUE U64_MAX 27 28 /* 29 * Utility macros for object flag management. If possible, flags 30 * should be defined such that 0 is the desired default value. 31 */ 32 #define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag 33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) 34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) 35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 37 38 /* CCU field state tests */ 39 40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0) 41 42 /* Clock field state tests */ 43 44 #define policy_exists(policy) ((policy)->offset != 0) 45 46 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 47 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 48 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 49 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) 50 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) 51 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) 52 53 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) 54 55 #define hyst_exists(hyst) ((hyst)->offset != 0) 56 57 #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) 58 #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) 59 #define divider_has_fraction(div) (!divider_is_fixed(div) && \ 60 (div)->u.s.frac_width > 0) 61 62 #define selector_exists(sel) ((sel)->width != 0) 63 #define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) 64 65 #define policy_lvm_en_exists(enable) ((enable)->offset != 0) 66 #define policy_ctl_exists(control) ((control)->offset != 0) 67 68 /* Clock type, used to tell common block what it's part of */ 69 enum bcm_clk_type { 70 bcm_clk_none, /* undefined clock type */ 71 bcm_clk_bus, 72 bcm_clk_core, 73 bcm_clk_peri 74 }; 75 76 /* 77 * CCU policy control for clocks. Clocks can be enabled or disabled 78 * based on the CCU policy in effect. One bit in each policy mask 79 * register (one per CCU policy) represents whether the clock is 80 * enabled when that policy is effect or not. The CCU policy engine 81 * must be stopped to update these bits, and must be restarted again 82 * afterward. 83 */ 84 struct bcm_clk_policy { 85 u32 offset; /* first policy mask register offset */ 86 u32 bit; /* bit used in all mask registers */ 87 }; 88 89 /* Policy initialization macro */ 90 91 #define POLICY(_offset, _bit) \ 92 { \ 93 .offset = (_offset), \ 94 .bit = (_bit), \ 95 } 96 97 /* 98 * Gating control and status is managed by a 32-bit gate register. 99 * 100 * There are several types of gating available: 101 * - (no gate) 102 * A clock with no gate is assumed to be always enabled. 103 * - hardware-only gating (auto-gating) 104 * Enabling or disabling clocks with this type of gate is 105 * managed automatically by the hardware. Such clocks can be 106 * considered by the software to be enabled. The current status 107 * of auto-gated clocks can be read from the gate status bit. 108 * - software-only gating 109 * Auto-gating is not available for this type of clock. 110 * Instead, software manages whether it's enabled by setting or 111 * clearing the enable bit. The current gate status of a gate 112 * under software control can be read from the gate status bit. 113 * To ensure a change to the gating status is complete, the 114 * status bit can be polled to verify that the gate has entered 115 * the desired state. 116 * - selectable hardware or software gating 117 * Gating for this type of clock can be configured to be either 118 * under software or hardware control. Which type is in use is 119 * determined by the hw_sw_sel bit of the gate register. 120 */ 121 struct bcm_clk_gate { 122 u32 offset; /* gate register offset */ 123 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ 124 u32 en_bit; /* 0: disable; 1: enable */ 125 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ 126 u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ 127 }; 128 129 /* 130 * Gate flags: 131 * HW means this gate can be auto-gated 132 * SW means the state of this gate can be software controlled 133 * NO_DISABLE means this gate is (only) enabled if under software control 134 * SW_MANAGED means the status of this gate is under software control 135 * ENABLED means this software-managed gate is *supposed* to be enabled 136 */ 137 #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ 138 #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ 139 #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ 140 #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ 141 #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ 142 #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ 143 144 /* 145 * Gate initialization macros. 146 * 147 * Any gate initially under software control will be enabled. 148 */ 149 150 /* A hardware/software gate initially under software control */ 151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 152 { \ 153 .offset = (_offset), \ 154 .status_bit = (_status_bit), \ 155 .en_bit = (_en_bit), \ 156 .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 157 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 158 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ 159 FLAG(GATE, EXISTS), \ 160 } 161 162 /* A hardware/software gate initially under hardware control */ 163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 164 { \ 165 .offset = (_offset), \ 166 .status_bit = (_status_bit), \ 167 .en_bit = (_en_bit), \ 168 .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 169 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 170 FLAG(GATE, EXISTS), \ 171 } 172 173 /* A hardware-or-enabled gate (enabled if not under hardware control) */ 174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 175 { \ 176 .offset = (_offset), \ 177 .status_bit = (_status_bit), \ 178 .en_bit = (_en_bit), \ 179 .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 181 FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ 182 } 183 184 /* A software-only gate */ 185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ 186 { \ 187 .offset = (_offset), \ 188 .status_bit = (_status_bit), \ 189 .en_bit = (_en_bit), \ 190 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ 191 FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ 192 } 193 194 /* A hardware-only gate */ 195 #define HW_ONLY_GATE(_offset, _status_bit) \ 196 { \ 197 .offset = (_offset), \ 198 .status_bit = (_status_bit), \ 199 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ 200 } 201 202 /* Gate hysteresis for clocks */ 203 struct bcm_clk_hyst { 204 u32 offset; /* hyst register offset (normally CLKGATE) */ 205 u32 en_bit; /* bit used to enable hysteresis */ 206 u32 val_bit; /* if enabled: 0 = low delay; 1 = high delay */ 207 }; 208 209 /* Hysteresis initialization macro */ 210 211 #define HYST(_offset, _en_bit, _val_bit) \ 212 { \ 213 .offset = (_offset), \ 214 .en_bit = (_en_bit), \ 215 .val_bit = (_val_bit), \ 216 } 217 218 /* 219 * Each clock can have zero, one, or two dividers which change the 220 * output rate of the clock. Each divider can be either fixed or 221 * variable. If there are two dividers, they are the "pre-divider" 222 * and the "regular" or "downstream" divider. If there is only one, 223 * there is no pre-divider. 224 * 225 * A fixed divider is any non-zero (positive) value, and it 226 * indicates how the input rate is affected by the divider. 227 * 228 * The value of a variable divider is maintained in a sub-field of a 229 * 32-bit divider register. The position of the field in the 230 * register is defined by its offset and width. The value recorded 231 * in this field is always 1 less than the value it represents. 232 * 233 * In addition, a variable divider can indicate that some subset 234 * of its bits represent a "fractional" part of the divider. Such 235 * bits comprise the low-order portion of the divider field, and can 236 * be viewed as representing the portion of the divider that lies to 237 * the right of the decimal point. Most variable dividers have zero 238 * fractional bits. Variable dividers with non-zero fraction width 239 * still record a value 1 less than the value they represent; the 240 * added 1 does *not* affect the low-order bit in this case, it 241 * affects the bits above the fractional part only. (Often in this 242 * code a divider field value is distinguished from the value it 243 * represents by referring to the latter as a "divisor".) 244 * 245 * In order to avoid dealing with fractions, divider arithmetic is 246 * performed using "scaled" values. A scaled value is one that's 247 * been left-shifted by the fractional width of a divider. Dividing 248 * a scaled value by a scaled divisor produces the desired quotient 249 * without loss of precision and without any other special handling 250 * for fractions. 251 * 252 * The recorded value of a variable divider can be modified. To 253 * modify either divider (or both), a clock must be enabled (i.e., 254 * using its gate). In addition, a trigger register (described 255 * below) must be used to commit the change, and polled to verify 256 * the change is complete. 257 */ 258 struct bcm_clk_div { 259 union { 260 struct { /* variable divider */ 261 u32 offset; /* divider register offset */ 262 u32 shift; /* field shift */ 263 u32 width; /* field width */ 264 u32 frac_width; /* field fraction width */ 265 266 u64 scaled_div; /* scaled divider value */ 267 } s; 268 u32 fixed; /* non-zero fixed divider value */ 269 } u; 270 u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ 271 }; 272 273 /* 274 * Divider flags: 275 * EXISTS means this divider exists 276 * FIXED means it is a fixed-rate divider 277 */ 278 #define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ 279 #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ 280 281 /* Divider initialization macros */ 282 283 /* A fixed (non-zero) divider */ 284 #define FIXED_DIVIDER(_value) \ 285 { \ 286 .u.fixed = (_value), \ 287 .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ 288 } 289 290 /* A divider with an integral divisor */ 291 #define DIVIDER(_offset, _shift, _width) \ 292 { \ 293 .u.s.offset = (_offset), \ 294 .u.s.shift = (_shift), \ 295 .u.s.width = (_width), \ 296 .u.s.scaled_div = BAD_SCALED_DIV_VALUE, \ 297 .flags = FLAG(DIV, EXISTS), \ 298 } 299 300 /* A divider whose divisor has an integer and fractional part */ 301 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ 302 { \ 303 .u.s.offset = (_offset), \ 304 .u.s.shift = (_shift), \ 305 .u.s.width = (_width), \ 306 .u.s.frac_width = (_frac_width), \ 307 .u.s.scaled_div = BAD_SCALED_DIV_VALUE, \ 308 .flags = FLAG(DIV, EXISTS), \ 309 } 310 311 /* 312 * Clocks may have multiple "parent" clocks. If there is more than 313 * one, a selector must be specified to define which of the parent 314 * clocks is currently in use. The selected clock is indicated in a 315 * sub-field of a 32-bit selector register. The range of 316 * representable selector values typically exceeds the number of 317 * available parent clocks. Occasionally the reset value of a 318 * selector field is explicitly set to a (specific) value that does 319 * not correspond to a defined input clock. 320 * 321 * We register all known parent clocks with the common clock code 322 * using a packed array (i.e., no empty slots) of (parent) clock 323 * names, and refer to them later using indexes into that array. 324 * We maintain an array of selector values indexed by common clock 325 * index values in order to map between these common clock indexes 326 * and the selector values used by the hardware. 327 * 328 * Like dividers, a selector can be modified, but to do so a clock 329 * must be enabled, and a trigger must be used to commit the change. 330 */ 331 struct bcm_clk_sel { 332 u32 offset; /* selector register offset */ 333 u32 shift; /* field shift */ 334 u32 width; /* field width */ 335 336 u32 parent_count; /* number of entries in parent_sel[] */ 337 u32 *parent_sel; /* array of parent selector values */ 338 u8 clk_index; /* current selected index in parent_sel[] */ 339 }; 340 341 /* Selector initialization macro */ 342 #define SELECTOR(_offset, _shift, _width) \ 343 { \ 344 .offset = (_offset), \ 345 .shift = (_shift), \ 346 .width = (_width), \ 347 .clk_index = BAD_CLK_INDEX, \ 348 } 349 350 /* 351 * Making changes to a variable divider or a selector for a clock 352 * requires the use of a trigger. A trigger is defined by a single 353 * bit within a register. To signal a change, a 1 is written into 354 * that bit. To determine when the change has been completed, that 355 * trigger bit is polled; the read value will be 1 while the change 356 * is in progress, and 0 when it is complete. 357 * 358 * Occasionally a clock will have more than one trigger. In this 359 * case, the "pre-trigger" will be used when changing a clock's 360 * selector and/or its pre-divider. 361 */ 362 struct bcm_clk_trig { 363 u32 offset; /* trigger register offset */ 364 u32 bit; /* trigger bit */ 365 u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ 366 }; 367 368 /* 369 * Trigger flags: 370 * EXISTS means this trigger exists 371 */ 372 #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ 373 374 /* Trigger initialization macro */ 375 #define TRIGGER(_offset, _bit) \ 376 { \ 377 .offset = (_offset), \ 378 .bit = (_bit), \ 379 .flags = FLAG(TRIG, EXISTS), \ 380 } 381 382 struct peri_clk_data { 383 struct bcm_clk_policy policy; 384 struct bcm_clk_gate gate; 385 struct bcm_clk_hyst hyst; 386 struct bcm_clk_trig pre_trig; 387 struct bcm_clk_div pre_div; 388 struct bcm_clk_trig trig; 389 struct bcm_clk_div div; 390 struct bcm_clk_sel sel; 391 const char *clocks[]; /* must be last; use CLOCKS() to declare */ 392 }; 393 #define CLOCKS(...) { __VA_ARGS__, NULL, } 394 #define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ 395 396 struct kona_clk { 397 struct clk_hw hw; 398 struct clk_init_data init_data; /* includes name of this clock */ 399 struct ccu_data *ccu; /* ccu this clock is associated with */ 400 enum bcm_clk_type type; 401 union { 402 void *data; 403 struct peri_clk_data *peri; 404 } u; 405 }; 406 #define to_kona_clk(_hw) \ 407 container_of(_hw, struct kona_clk, hw) 408 409 /* Initialization macro for an entry in a CCU's kona_clks[] array. */ 410 #define KONA_CLK(_ccu_name, _clk_name, _type) \ 411 { \ 412 .init_data = { \ 413 .name = #_clk_name, \ 414 .ops = &kona_ ## _type ## _clk_ops, \ 415 }, \ 416 .ccu = &_ccu_name ## _ccu_data, \ 417 .type = bcm_clk_ ## _type, \ 418 .u.data = &_clk_name ## _data, \ 419 } 420 #define LAST_KONA_CLK { .type = bcm_clk_none } 421 422 /* 423 * CCU policy control. To enable software update of the policy 424 * tables the CCU policy engine must be stopped by setting the 425 * software update enable bit (LVM_EN). After an update the engine 426 * is restarted using the GO bit and either the GO_ATL or GO_AC bit. 427 */ 428 struct bcm_lvm_en { 429 u32 offset; /* LVM_EN register offset */ 430 u32 bit; /* POLICY_CONFIG_EN bit in register */ 431 }; 432 433 /* Policy enable initialization macro */ 434 #define CCU_LVM_EN(_offset, _bit) \ 435 { \ 436 .offset = (_offset), \ 437 .bit = (_bit), \ 438 } 439 440 struct bcm_policy_ctl { 441 u32 offset; /* POLICY_CTL register offset */ 442 u32 go_bit; 443 u32 atl_bit; /* GO, GO_ATL, and GO_AC bits */ 444 u32 ac_bit; 445 }; 446 447 /* Policy control initialization macro */ 448 #define CCU_POLICY_CTL(_offset, _go_bit, _ac_bit, _atl_bit) \ 449 { \ 450 .offset = (_offset), \ 451 .go_bit = (_go_bit), \ 452 .ac_bit = (_ac_bit), \ 453 .atl_bit = (_atl_bit), \ 454 } 455 456 struct ccu_policy { 457 struct bcm_lvm_en enable; 458 struct bcm_policy_ctl control; 459 }; 460 461 /* 462 * Each CCU defines a mapped area of memory containing registers 463 * used to manage clocks implemented by the CCU. Access to memory 464 * within the CCU's space is serialized by a spinlock. Before any 465 * (other) address can be written, a special access "password" value 466 * must be written to its WR_ACCESS register (located at the base 467 * address of the range). We keep track of the name of each CCU as 468 * it is set up, and maintain them in a list. 469 */ 470 struct ccu_data { 471 void __iomem *base; /* base of mapped address space */ 472 spinlock_t lock; /* serialization lock */ 473 bool write_enabled; /* write access is currently enabled */ 474 struct ccu_policy policy; 475 struct device_node *node; 476 size_t clk_num; 477 const char *name; 478 u32 range; /* byte range of address space */ 479 struct kona_clk kona_clks[]; /* must be last */ 480 }; 481 482 /* Initialization for common fields in a Kona ccu_data structure */ 483 #define KONA_CCU_COMMON(_prefix, _name, _ccuname) \ 484 .name = #_name "_ccu", \ 485 .lock = __SPIN_LOCK_UNLOCKED(_name ## _ccu_data.lock), \ 486 .clk_num = _prefix ## _ ## _ccuname ## _CCU_CLOCK_COUNT 487 488 /* Exported globals */ 489 490 extern struct clk_ops kona_peri_clk_ops; 491 492 /* Externally visible functions */ 493 494 extern u64 scaled_div_max(struct bcm_clk_div *div); 495 extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, 496 u32 billionths); 497 498 extern void __init kona_dt_ccu_setup(struct ccu_data *ccu, 499 struct device_node *node); 500 extern bool __init kona_ccu_init(struct ccu_data *ccu); 501 502 #endif /* _CLK_KONA_H */ 503