1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
70
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
75
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
78
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
97
98 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003
99 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024
100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025
101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026
102
103 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
104 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
106
107 /*
108 * init function returns:
109 * > 0 - number of ports
110 * = 0 - use board->num_ports
111 * < 0 - error
112 */
113 struct pci_serial_quirk {
114 u32 vendor;
115 u32 device;
116 u32 subvendor;
117 u32 subdevice;
118 int (*probe)(struct pci_dev *dev);
119 int (*init)(struct pci_dev *dev);
120 int (*setup)(struct serial_private *,
121 const struct pciserial_board *,
122 struct uart_8250_port *, int);
123 void (*exit)(struct pci_dev *dev);
124 };
125
126 struct f815xxa_data {
127 spinlock_t lock;
128 int idx;
129 };
130
131 struct serial_private {
132 struct pci_dev *dev;
133 unsigned int nr;
134 struct pci_serial_quirk *quirk;
135 const struct pciserial_board *board;
136 int line[];
137 };
138
139 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
140
141 static const struct pci_device_id pci_use_msi[] = {
142 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
143 0xA000, 0x1000) },
144 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
145 0xA000, 0x1000) },
146 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
147 0xA000, 0x1000) },
148 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
149 0xA000, 0x1000) },
150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
151 PCI_ANY_ID, PCI_ANY_ID) },
152 { }
153 };
154
155 static int pci_default_setup(struct serial_private*,
156 const struct pciserial_board*, struct uart_8250_port *, int);
157
moan_device(const char * str,struct pci_dev * dev)158 static void moan_device(const char *str, struct pci_dev *dev)
159 {
160 pci_err(dev, "%s\n"
161 "Please send the output of lspci -vv, this\n"
162 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
163 "manufacturer and name of serial board or\n"
164 "modem board to <linux-serial@vger.kernel.org>.\n",
165 str, dev->vendor, dev->device,
166 dev->subsystem_vendor, dev->subsystem_device);
167 }
168
169 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)170 setup_port(struct serial_private *priv, struct uart_8250_port *port,
171 u8 bar, unsigned int offset, int regshift)
172 {
173 void __iomem *iomem = NULL;
174
175 if (pci_resource_flags(priv->dev, bar) & IORESOURCE_MEM) {
176 iomem = pcim_iomap(priv->dev, bar, 0);
177 if (!iomem)
178 return -ENOMEM;
179 }
180
181 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift, iomem);
182 }
183
184 /*
185 * ADDI-DATA GmbH communication cards <info@addi-data.com>
186 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)187 static int addidata_apci7800_setup(struct serial_private *priv,
188 const struct pciserial_board *board,
189 struct uart_8250_port *port, int idx)
190 {
191 unsigned int bar = 0, offset = board->first_offset;
192 bar = FL_GET_BASE(board->flags);
193
194 if (idx < 2) {
195 offset += idx * board->uart_offset;
196 } else if ((idx >= 2) && (idx < 4)) {
197 bar += 1;
198 offset += ((idx - 2) * board->uart_offset);
199 } else if ((idx >= 4) && (idx < 6)) {
200 bar += 2;
201 offset += ((idx - 4) * board->uart_offset);
202 } else if (idx >= 6) {
203 bar += 3;
204 offset += ((idx - 6) * board->uart_offset);
205 }
206
207 return setup_port(priv, port, bar, offset, board->reg_shift);
208 }
209
210 /*
211 * AFAVLAB uses a different mixture of BARs and offsets
212 * Not that ugly ;) -- HW
213 */
214 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)215 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
216 struct uart_8250_port *port, int idx)
217 {
218 unsigned int bar, offset = board->first_offset;
219
220 bar = FL_GET_BASE(board->flags);
221 if (idx < 4)
222 bar += idx;
223 else {
224 bar = 4;
225 offset += (idx - 4) * board->uart_offset;
226 }
227
228 return setup_port(priv, port, bar, offset, board->reg_shift);
229 }
230
231 /*
232 * HP's Remote Management Console. The Diva chip came in several
233 * different versions. N-class, L2000 and A500 have two Diva chips, each
234 * with 3 UARTs (the third UART on the second chip is unused). Superdome
235 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
236 * one Diva chip, but it has been expanded to 5 UARTs.
237 */
pci_hp_diva_init(struct pci_dev * dev)238 static int pci_hp_diva_init(struct pci_dev *dev)
239 {
240 int rc = 0;
241
242 switch (dev->subsystem_device) {
243 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
244 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
245 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
246 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
247 rc = 3;
248 break;
249 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
250 rc = 2;
251 break;
252 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
253 rc = 4;
254 break;
255 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
256 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
257 rc = 1;
258 break;
259 }
260
261 return rc;
262 }
263
264 /*
265 * HP's Diva chip puts the 4th/5th serial port further out, and
266 * some serial ports are supposed to be hidden on certain models.
267 */
268 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)269 pci_hp_diva_setup(struct serial_private *priv,
270 const struct pciserial_board *board,
271 struct uart_8250_port *port, int idx)
272 {
273 unsigned int offset = board->first_offset;
274 unsigned int bar = FL_GET_BASE(board->flags);
275
276 switch (priv->dev->subsystem_device) {
277 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
278 if (idx == 3)
279 idx++;
280 break;
281 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
282 if (idx > 0)
283 idx++;
284 if (idx > 2)
285 idx++;
286 break;
287 }
288 if (idx > 2)
289 offset = 0x18;
290
291 offset += idx * board->uart_offset;
292
293 return setup_port(priv, port, bar, offset, board->reg_shift);
294 }
295
296 /*
297 * Added for EKF Intel i960 serial boards
298 */
pci_inteli960ni_init(struct pci_dev * dev)299 static int pci_inteli960ni_init(struct pci_dev *dev)
300 {
301 u32 oldval;
302
303 if (!(dev->subsystem_device & 0x1000))
304 return -ENODEV;
305
306 /* is firmware started? */
307 pci_read_config_dword(dev, 0x44, &oldval);
308 if (oldval == 0x00001000L) { /* RESET value */
309 pci_dbg(dev, "Local i960 firmware missing\n");
310 return -ENODEV;
311 }
312 return 0;
313 }
314
315 /*
316 * Some PCI serial cards using the PLX 9050 PCI interface chip require
317 * that the card interrupt be explicitly enabled or disabled. This
318 * seems to be mainly needed on card using the PLX which also use I/O
319 * mapped memory.
320 */
pci_plx9050_init(struct pci_dev * dev)321 static int pci_plx9050_init(struct pci_dev *dev)
322 {
323 u8 irq_config;
324 void __iomem *p;
325
326 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
327 moan_device("no memory in bar 0", dev);
328 return 0;
329 }
330
331 irq_config = 0x41;
332 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
333 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
334 irq_config = 0x43;
335
336 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
337 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
338 /*
339 * As the megawolf cards have the int pins active
340 * high, and have 2 UART chips, both ints must be
341 * enabled on the 9050. Also, the UARTS are set in
342 * 16450 mode by default, so we have to enable the
343 * 16C950 'enhanced' mode so that we can use the
344 * deep FIFOs
345 */
346 irq_config = 0x5b;
347 /*
348 * enable/disable interrupts
349 */
350 p = ioremap(pci_resource_start(dev, 0), 0x80);
351 if (p == NULL)
352 return -ENOMEM;
353 writel(irq_config, p + 0x4c);
354
355 /*
356 * Read the register back to ensure that it took effect.
357 */
358 readl(p + 0x4c);
359 iounmap(p);
360
361 return 0;
362 }
363
pci_plx9050_exit(struct pci_dev * dev)364 static void pci_plx9050_exit(struct pci_dev *dev)
365 {
366 u8 __iomem *p;
367
368 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
369 return;
370
371 /*
372 * disable interrupts
373 */
374 p = ioremap(pci_resource_start(dev, 0), 0x80);
375 if (p != NULL) {
376 writel(0, p + 0x4c);
377
378 /*
379 * Read the register back to ensure that it took effect.
380 */
381 readl(p + 0x4c);
382 iounmap(p);
383 }
384 }
385
386 #define NI8420_INT_ENABLE_REG 0x38
387 #define NI8420_INT_ENABLE_BIT 0x2000
388
pci_ni8420_exit(struct pci_dev * dev)389 static void pci_ni8420_exit(struct pci_dev *dev)
390 {
391 void __iomem *p;
392 unsigned int bar = 0;
393
394 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
395 moan_device("no memory in bar", dev);
396 return;
397 }
398
399 p = pci_ioremap_bar(dev, bar);
400 if (p == NULL)
401 return;
402
403 /* Disable the CPU Interrupt */
404 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
405 p + NI8420_INT_ENABLE_REG);
406 iounmap(p);
407 }
408
409
410 /* MITE registers */
411 #define MITE_IOWBSR1 0xc4
412 #define MITE_IOWCR1 0xf4
413 #define MITE_LCIMR1 0x08
414 #define MITE_LCIMR2 0x10
415
416 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
417
pci_ni8430_exit(struct pci_dev * dev)418 static void pci_ni8430_exit(struct pci_dev *dev)
419 {
420 void __iomem *p;
421 unsigned int bar = 0;
422
423 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
424 moan_device("no memory in bar", dev);
425 return;
426 }
427
428 p = pci_ioremap_bar(dev, bar);
429 if (p == NULL)
430 return;
431
432 /* Disable the CPU Interrupt */
433 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
434 iounmap(p);
435 }
436
437 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
438 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)439 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
440 struct uart_8250_port *port, int idx)
441 {
442 unsigned int bar, offset = board->first_offset;
443
444 bar = 0;
445
446 if (idx < 4) {
447 /* first four channels map to 0, 0x100, 0x200, 0x300 */
448 offset += idx * board->uart_offset;
449 } else if (idx < 8) {
450 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
451 offset += idx * board->uart_offset + 0xC00;
452 } else /* we have only 8 ports on PMC-OCTALPRO */
453 return 1;
454
455 return setup_port(priv, port, bar, offset, board->reg_shift);
456 }
457
458 /*
459 * This does initialization for PMC OCTALPRO cards:
460 * maps the device memory, resets the UARTs (needed, bc
461 * if the module is removed and inserted again, the card
462 * is in the sleep mode) and enables global interrupt.
463 */
464
465 /* global control register offset for SBS PMC-OctalPro */
466 #define OCT_REG_CR_OFF 0x500
467
sbs_init(struct pci_dev * dev)468 static int sbs_init(struct pci_dev *dev)
469 {
470 u8 __iomem *p;
471
472 p = pci_ioremap_bar(dev, 0);
473
474 if (p == NULL)
475 return -ENOMEM;
476 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
477 writeb(0x10, p + OCT_REG_CR_OFF);
478 udelay(50);
479 writeb(0x0, p + OCT_REG_CR_OFF);
480
481 /* Set bit-2 (INTENABLE) of Control Register */
482 writeb(0x4, p + OCT_REG_CR_OFF);
483 iounmap(p);
484
485 return 0;
486 }
487
488 /*
489 * Disables the global interrupt of PMC-OctalPro
490 */
491
sbs_exit(struct pci_dev * dev)492 static void sbs_exit(struct pci_dev *dev)
493 {
494 u8 __iomem *p;
495
496 p = pci_ioremap_bar(dev, 0);
497 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
498 if (p != NULL)
499 writeb(0, p + OCT_REG_CR_OFF);
500 iounmap(p);
501 }
502
503 /*
504 * SIIG serial cards have an PCI interface chip which also controls
505 * the UART clocking frequency. Each UART can be clocked independently
506 * (except cards equipped with 4 UARTs) and initial clocking settings
507 * are stored in the EEPROM chip. It can cause problems because this
508 * version of serial driver doesn't support differently clocked UART's
509 * on single PCI card. To prevent this, initialization functions set
510 * high frequency clocking for all UART's on given card. It is safe (I
511 * hope) because it doesn't touch EEPROM settings to prevent conflicts
512 * with other OSes (like M$ DOS).
513 *
514 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
515 *
516 * There is two family of SIIG serial cards with different PCI
517 * interface chip and different configuration methods:
518 * - 10x cards have control registers in IO and/or memory space;
519 * - 20x cards have control registers in standard PCI configuration space.
520 *
521 * Note: all 10x cards have PCI device ids 0x10..
522 * all 20x cards have PCI device ids 0x20..
523 *
524 * There are also Quartet Serial cards which use Oxford Semiconductor
525 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
526 *
527 * Note: some SIIG cards are probed by the parport_serial object.
528 */
529
530 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
531 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
532
pci_siig10x_init(struct pci_dev * dev)533 static int pci_siig10x_init(struct pci_dev *dev)
534 {
535 u16 data;
536 void __iomem *p;
537
538 switch (dev->device & 0xfff8) {
539 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
540 data = 0xffdf;
541 break;
542 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
543 data = 0xf7ff;
544 break;
545 default: /* 1S1P, 4S */
546 data = 0xfffb;
547 break;
548 }
549
550 p = ioremap(pci_resource_start(dev, 0), 0x80);
551 if (p == NULL)
552 return -ENOMEM;
553
554 writew(readw(p + 0x28) & data, p + 0x28);
555 readw(p + 0x28);
556 iounmap(p);
557 return 0;
558 }
559
560 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
561 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
562
pci_siig20x_init(struct pci_dev * dev)563 static int pci_siig20x_init(struct pci_dev *dev)
564 {
565 u8 data;
566
567 /* Change clock frequency for the first UART. */
568 pci_read_config_byte(dev, 0x6f, &data);
569 pci_write_config_byte(dev, 0x6f, data & 0xef);
570
571 /* If this card has 2 UART, we have to do the same with second UART. */
572 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
573 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
574 pci_read_config_byte(dev, 0x73, &data);
575 pci_write_config_byte(dev, 0x73, data & 0xef);
576 }
577 return 0;
578 }
579
pci_siig_init(struct pci_dev * dev)580 static int pci_siig_init(struct pci_dev *dev)
581 {
582 unsigned int type = dev->device & 0xff00;
583
584 if (type == 0x1000)
585 return pci_siig10x_init(dev);
586 if (type == 0x2000)
587 return pci_siig20x_init(dev);
588
589 moan_device("Unknown SIIG card", dev);
590 return -ENODEV;
591 }
592
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)593 static int pci_siig_setup(struct serial_private *priv,
594 const struct pciserial_board *board,
595 struct uart_8250_port *port, int idx)
596 {
597 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
598
599 if (idx > 3) {
600 bar = 4;
601 offset = (idx - 4) * 8;
602 }
603
604 return setup_port(priv, port, bar, offset, 0);
605 }
606
607 /*
608 * Timedia has an explosion of boards, and to avoid the PCI table from
609 * growing *huge*, we use this function to collapse some 70 entries
610 * in the PCI table into one, for sanity's and compactness's sake.
611 */
612 static const unsigned short timedia_single_port[] = {
613 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
614 };
615
616 static const unsigned short timedia_dual_port[] = {
617 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
618 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
619 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
620 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
621 0xD079, 0
622 };
623
624 static const unsigned short timedia_quad_port[] = {
625 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
626 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
627 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
628 0xB157, 0
629 };
630
631 static const unsigned short timedia_eight_port[] = {
632 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
633 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
634 };
635
636 static const struct timedia_struct {
637 int num;
638 const unsigned short *ids;
639 } timedia_data[] = {
640 { 1, timedia_single_port },
641 { 2, timedia_dual_port },
642 { 4, timedia_quad_port },
643 { 8, timedia_eight_port }
644 };
645
646 /*
647 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
648 * listing them individually, this driver merely grabs them all with
649 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
650 * and should be left free to be claimed by parport_serial instead.
651 */
pci_timedia_probe(struct pci_dev * dev)652 static int pci_timedia_probe(struct pci_dev *dev)
653 {
654 /*
655 * Check the third digit of the subdevice ID
656 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
657 */
658 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
659 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
660 dev->subsystem_device);
661 return -ENODEV;
662 }
663
664 return 0;
665 }
666
pci_timedia_init(struct pci_dev * dev)667 static int pci_timedia_init(struct pci_dev *dev)
668 {
669 const unsigned short *ids;
670 int i, j;
671
672 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
673 ids = timedia_data[i].ids;
674 for (j = 0; ids[j]; j++)
675 if (dev->subsystem_device == ids[j])
676 return timedia_data[i].num;
677 }
678 return 0;
679 }
680
681 /*
682 * Timedia/SUNIX uses a mixture of BARs and offsets
683 * Ugh, this is ugly as all hell --- TYT
684 */
685 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)686 pci_timedia_setup(struct serial_private *priv,
687 const struct pciserial_board *board,
688 struct uart_8250_port *port, int idx)
689 {
690 unsigned int bar = 0, offset = board->first_offset;
691
692 switch (idx) {
693 case 0:
694 bar = 0;
695 break;
696 case 1:
697 offset = board->uart_offset;
698 bar = 0;
699 break;
700 case 2:
701 bar = 1;
702 break;
703 case 3:
704 offset = board->uart_offset;
705 fallthrough;
706 case 4: /* BAR 2 */
707 case 5: /* BAR 3 */
708 case 6: /* BAR 4 */
709 case 7: /* BAR 5 */
710 bar = idx - 2;
711 }
712
713 return setup_port(priv, port, bar, offset, board->reg_shift);
714 }
715
716 /*
717 * Some Titan cards are also a little weird
718 */
719 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)720 titan_400l_800l_setup(struct serial_private *priv,
721 const struct pciserial_board *board,
722 struct uart_8250_port *port, int idx)
723 {
724 unsigned int bar, offset = board->first_offset;
725
726 switch (idx) {
727 case 0:
728 bar = 1;
729 break;
730 case 1:
731 bar = 2;
732 break;
733 default:
734 bar = 4;
735 offset = (idx - 2) * board->uart_offset;
736 }
737
738 return setup_port(priv, port, bar, offset, board->reg_shift);
739 }
740
pci_xircom_init(struct pci_dev * dev)741 static int pci_xircom_init(struct pci_dev *dev)
742 {
743 msleep(100);
744 return 0;
745 }
746
pci_ni8420_init(struct pci_dev * dev)747 static int pci_ni8420_init(struct pci_dev *dev)
748 {
749 void __iomem *p;
750 unsigned int bar = 0;
751
752 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
753 moan_device("no memory in bar", dev);
754 return 0;
755 }
756
757 p = pci_ioremap_bar(dev, bar);
758 if (p == NULL)
759 return -ENOMEM;
760
761 /* Enable CPU Interrupt */
762 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
763 p + NI8420_INT_ENABLE_REG);
764
765 iounmap(p);
766 return 0;
767 }
768
769 #define MITE_IOWBSR1_WSIZE 0xa
770 #define MITE_IOWBSR1_WIN_OFFSET 0x800
771 #define MITE_IOWBSR1_WENAB (1 << 7)
772 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
773 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
774 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
775
pci_ni8430_init(struct pci_dev * dev)776 static int pci_ni8430_init(struct pci_dev *dev)
777 {
778 void __iomem *p;
779 struct pci_bus_region region;
780 u32 device_window;
781 unsigned int bar = 0;
782
783 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
784 moan_device("no memory in bar", dev);
785 return 0;
786 }
787
788 p = pci_ioremap_bar(dev, bar);
789 if (p == NULL)
790 return -ENOMEM;
791
792 /*
793 * Set device window address and size in BAR0, while acknowledging that
794 * the resource structure may contain a translated address that differs
795 * from the address the device responds to.
796 */
797 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
798 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
799 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
800 writel(device_window, p + MITE_IOWBSR1);
801
802 /* Set window access to go to RAMSEL IO address space */
803 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
804 p + MITE_IOWCR1);
805
806 /* Enable IO Bus Interrupt 0 */
807 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
808
809 /* Enable CPU Interrupt */
810 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
811
812 iounmap(p);
813 return 0;
814 }
815
816 /* UART Port Control Register */
817 #define NI8430_PORTCON 0x0f
818 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
819
820 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)821 pci_ni8430_setup(struct serial_private *priv,
822 const struct pciserial_board *board,
823 struct uart_8250_port *port, int idx)
824 {
825 struct pci_dev *dev = priv->dev;
826 void __iomem *p;
827 unsigned int bar, offset = board->first_offset;
828
829 if (idx >= board->num_ports)
830 return 1;
831
832 bar = FL_GET_BASE(board->flags);
833 offset += idx * board->uart_offset;
834
835 p = pci_ioremap_bar(dev, bar);
836 if (!p)
837 return -ENOMEM;
838
839 /* enable the transceiver */
840 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
841 p + offset + NI8430_PORTCON);
842
843 iounmap(p);
844
845 return setup_port(priv, port, bar, offset, board->reg_shift);
846 }
847
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)848 static int pci_netmos_9900_setup(struct serial_private *priv,
849 const struct pciserial_board *board,
850 struct uart_8250_port *port, int idx)
851 {
852 unsigned int bar;
853
854 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
855 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
856 /* netmos apparently orders BARs by datasheet layout, so serial
857 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
858 */
859 bar = 3 * idx;
860
861 return setup_port(priv, port, bar, 0, board->reg_shift);
862 }
863
864 return pci_default_setup(priv, board, port, idx);
865 }
866
867 /* the 99xx series comes with a range of device IDs and a variety
868 * of capabilities:
869 *
870 * 9900 has varying capabilities and can cascade to sub-controllers
871 * (cascading should be purely internal)
872 * 9904 is hardwired with 4 serial ports
873 * 9912 and 9922 are hardwired with 2 serial ports
874 */
pci_netmos_9900_numports(struct pci_dev * dev)875 static int pci_netmos_9900_numports(struct pci_dev *dev)
876 {
877 unsigned int c = dev->class;
878 unsigned int pi;
879 unsigned short sub_serports;
880
881 pi = c & 0xff;
882
883 if (pi == 2)
884 return 1;
885
886 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
887 /* two possibilities: 0x30ps encodes number of parallel and
888 * serial ports, or 0x1000 indicates *something*. This is not
889 * immediately obvious, since the 2s1p+4s configuration seems
890 * to offer all functionality on functions 0..2, while still
891 * advertising the same function 3 as the 4s+2s1p config.
892 */
893 sub_serports = dev->subsystem_device & 0xf;
894 if (sub_serports > 0)
895 return sub_serports;
896
897 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
898 return 0;
899 }
900
901 moan_device("unknown NetMos/Mostech program interface", dev);
902 return 0;
903 }
904
pci_netmos_init(struct pci_dev * dev)905 static int pci_netmos_init(struct pci_dev *dev)
906 {
907 /* subdevice 0x00PS means <P> parallel, <S> serial */
908 unsigned int num_serial = dev->subsystem_device & 0xf;
909
910 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
911 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
912 return 0;
913
914 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
915 dev->subsystem_device == 0x0299)
916 return 0;
917
918 switch (dev->device) { /* FALLTHROUGH on all */
919 case PCI_DEVICE_ID_NETMOS_9904:
920 case PCI_DEVICE_ID_NETMOS_9912:
921 case PCI_DEVICE_ID_NETMOS_9922:
922 case PCI_DEVICE_ID_NETMOS_9900:
923 num_serial = pci_netmos_9900_numports(dev);
924 break;
925
926 default:
927 break;
928 }
929
930 if (num_serial == 0) {
931 moan_device("unknown NetMos/Mostech device", dev);
932 return -ENODEV;
933 }
934
935 return num_serial;
936 }
937
938 /*
939 * These chips are available with optionally one parallel port and up to
940 * two serial ports. Unfortunately they all have the same product id.
941 *
942 * Basic configuration is done over a region of 32 I/O ports. The base
943 * ioport is called INTA or INTC, depending on docs/other drivers.
944 *
945 * The region of the 32 I/O ports is configured in POSIO0R...
946 */
947
948 /* registers */
949 #define ITE_887x_MISCR 0x9c
950 #define ITE_887x_INTCBAR 0x78
951 #define ITE_887x_UARTBAR 0x7c
952 #define ITE_887x_PS0BAR 0x10
953 #define ITE_887x_POSIO0 0x60
954
955 /* I/O space size */
956 #define ITE_887x_IOSIZE 32
957 /* I/O space size (bits 26-24; 8 bytes = 011b) */
958 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
959 /* I/O space size (bits 26-24; 32 bytes = 101b) */
960 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
961 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
962 #define ITE_887x_POSIO_SPEED (3 << 29)
963 /* enable IO_Space bit */
964 #define ITE_887x_POSIO_ENABLE (1 << 31)
965
966 /* inta_addr are the configuration addresses of the ITE */
967 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)968 static int pci_ite887x_init(struct pci_dev *dev)
969 {
970 int ret, i, type;
971 struct resource *iobase = NULL;
972 u32 miscr, uartbar, ioport;
973
974 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
975 return serial_8250_warn_need_ioport(dev);
976
977 /* search for the base-ioport */
978 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
979 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
980 "ite887x");
981 if (iobase != NULL) {
982 /* write POSIO0R - speed | size | ioport */
983 pci_write_config_dword(dev, ITE_887x_POSIO0,
984 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
985 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
986 /* write INTCBAR - ioport */
987 pci_write_config_dword(dev, ITE_887x_INTCBAR,
988 inta_addr[i]);
989 ret = inb(inta_addr[i]);
990 if (ret != 0xff) {
991 /* ioport connected */
992 break;
993 }
994 release_region(iobase->start, ITE_887x_IOSIZE);
995 }
996 }
997
998 if (i == ARRAY_SIZE(inta_addr)) {
999 pci_err(dev, "could not find iobase\n");
1000 return -ENODEV;
1001 }
1002
1003 /* start of undocumented type checking (see parport_pc.c) */
1004 type = inb(iobase->start + 0x18) & 0x0f;
1005
1006 switch (type) {
1007 case 0x2: /* ITE8871 (1P) */
1008 case 0xa: /* ITE8875 (1P) */
1009 ret = 0;
1010 break;
1011 case 0xe: /* ITE8872 (2S1P) */
1012 ret = 2;
1013 break;
1014 case 0x6: /* ITE8873 (1S) */
1015 ret = 1;
1016 break;
1017 case 0x8: /* ITE8874 (2S) */
1018 ret = 2;
1019 break;
1020 default:
1021 moan_device("Unknown ITE887x", dev);
1022 ret = -ENODEV;
1023 }
1024
1025 /* configure all serial ports */
1026 for (i = 0; i < ret; i++) {
1027 /* read the I/O port from the device */
1028 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1029 &ioport);
1030 ioport &= 0x0000FF00; /* the actual base address */
1031 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1032 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1033 ITE_887x_POSIO_IOSIZE_8 | ioport);
1034
1035 /* write the ioport to the UARTBAR */
1036 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1037 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1038 uartbar |= (ioport << (16 * i)); /* set the ioport */
1039 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1040
1041 /* get current config */
1042 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1043 /* disable interrupts (UARTx_Routing[3:0]) */
1044 miscr &= ~(0xf << (12 - 4 * i));
1045 /* activate the UART (UARTx_En) */
1046 miscr |= 1 << (23 - i);
1047 /* write new config with activated UART */
1048 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1049 }
1050
1051 if (ret <= 0) {
1052 /* the device has no UARTs if we get here */
1053 release_region(iobase->start, ITE_887x_IOSIZE);
1054 }
1055
1056 return ret;
1057 }
1058
pci_ite887x_exit(struct pci_dev * dev)1059 static void pci_ite887x_exit(struct pci_dev *dev)
1060 {
1061 u32 ioport;
1062 /* the ioport is bit 0-15 in POSIO0R */
1063 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1064 ioport &= 0xffff;
1065 release_region(ioport, ITE_887x_IOSIZE);
1066 }
1067
1068 /*
1069 * Oxford Semiconductor Inc.
1070 * Check if an OxSemi device is part of the Tornado range of devices.
1071 */
1072 #define PCI_VENDOR_ID_ENDRUN 0x7401
1073 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1074
pci_oxsemi_tornado_p(struct pci_dev * dev)1075 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1076 {
1077 /* OxSemi Tornado devices are all 0xCxxx */
1078 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1079 (dev->device & 0xf000) != 0xc000)
1080 return false;
1081
1082 /* EndRun devices are all 0xExxx */
1083 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1084 (dev->device & 0xf000) != 0xe000)
1085 return false;
1086
1087 return true;
1088 }
1089
1090 /*
1091 * Determine the number of ports available on a Tornado device.
1092 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1093 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1094 {
1095 u8 __iomem *p;
1096 unsigned long deviceID;
1097 unsigned int number_uarts = 0;
1098
1099 if (!pci_oxsemi_tornado_p(dev))
1100 return 0;
1101
1102 p = pci_iomap(dev, 0, 5);
1103 if (p == NULL)
1104 return -ENOMEM;
1105
1106 deviceID = ioread32(p);
1107 /* Tornado device */
1108 if (deviceID == 0x07000200) {
1109 number_uarts = ioread8(p + 4);
1110 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1111 number_uarts,
1112 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1113 "EndRun" : "Oxford");
1114 }
1115 pci_iounmap(dev, p);
1116 return number_uarts;
1117 }
1118
1119 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1120 #define OXSEMI_TORNADO_TCR_MASK 0xf
1121 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1122 #define OXSEMI_TORNADO_CPR_MIN 0x008
1123 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1124
1125 /*
1126 * Determine the oversampling rate, the clock prescaler, and the clock
1127 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1128 * which is four times the baud base, and the prescaler increments in
1129 * steps of 1/8. Therefore to make calculations on integers we need
1130 * to use a scaled clock rate, which is the baud base multiplied by 32
1131 * (or our assumed UART clock rate multiplied by 2).
1132 *
1133 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1134 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1135 * values between 1.000 and 63.875 inclusive (operation for values from
1136 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1137 * unsigned 16-bit integer.
1138 *
1139 * For the most accurate baud rate we use a table of predetermined
1140 * oversampling rates and clock prescalers that records all possible
1141 * products of the two parameters in the range from 4 up to 255 inclusive,
1142 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1143 * by 8. The table is sorted by the decreasing value of the oversampling
1144 * rate and ties are resolved by sorting by the decreasing value of the
1145 * product. This way preference is given to higher oversampling rates.
1146 *
1147 * We iterate over the table and choose the product of an oversampling
1148 * rate and a clock prescaler that gives the lowest integer division
1149 * result deviation, or if an exact integer divider is found we stop
1150 * looking for it right away. We do some fixup if the resulting clock
1151 * divisor required would be out of its unsigned 16-bit integer range.
1152 *
1153 * Finally we abuse the supposed fractional part returned to encode the
1154 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1155 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1156 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1157 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1158 unsigned int baud,
1159 unsigned int *frac)
1160 {
1161 static u8 p[][2] = {
1162 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1163 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1164 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1165 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1166 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1167 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1168 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1169 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1170 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1171 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1172 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1173 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1174 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1175 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1176 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1177 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1178 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1179 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1180 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1181 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1182 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1183 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1184 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1185 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1186 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1187 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1188 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1189 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1190 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1191 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1192 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1193 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1194 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1195 { 4, 9, }, { 4, 8, },
1196 };
1197 /* Scale the quotient for comparison to get the fractional part. */
1198 const unsigned int quot_scale = 65536;
1199 unsigned int sclk = port->uartclk * 2;
1200 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1201 unsigned int best_squot;
1202 unsigned int squot;
1203 unsigned int quot;
1204 u16 cpr;
1205 u8 tcr;
1206 int i;
1207
1208 /* Old custom speed handling. */
1209 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1210 unsigned int cust_div = port->custom_divisor;
1211
1212 quot = cust_div & UART_DIV_MAX;
1213 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1214 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1215 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1216 cpr = OXSEMI_TORNADO_CPR_DEF;
1217 } else {
1218 best_squot = quot_scale;
1219 for (i = 0; i < ARRAY_SIZE(p); i++) {
1220 unsigned int spre;
1221 unsigned int srem;
1222 u8 cp;
1223 u8 tc;
1224
1225 tc = p[i][0];
1226 cp = p[i][1];
1227 spre = tc * cp;
1228
1229 srem = sdiv % spre;
1230 if (srem > spre / 2)
1231 srem = spre - srem;
1232 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1233
1234 if (srem == 0) {
1235 tcr = tc;
1236 cpr = cp;
1237 quot = sdiv / spre;
1238 break;
1239 } else if (squot < best_squot) {
1240 best_squot = squot;
1241 tcr = tc;
1242 cpr = cp;
1243 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1244 }
1245 }
1246 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1247 quot % 2 == 0) {
1248 quot >>= 1;
1249 tcr <<= 1;
1250 }
1251 while (quot > UART_DIV_MAX) {
1252 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1253 quot >>= 1;
1254 tcr <<= 1;
1255 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1256 quot >>= 1;
1257 cpr <<= 1;
1258 } else {
1259 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1260 cpr = OXSEMI_TORNADO_CPR_MASK;
1261 }
1262 }
1263 }
1264
1265 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1266 return quot;
1267 }
1268
1269 /*
1270 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1271 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1272 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1273 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1274 * has to be written first, followed by CPR2, which occupies the location
1275 * of CKS used with earlier UART designs.
1276 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1277 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1278 unsigned int baud,
1279 unsigned int quot,
1280 unsigned int quot_frac)
1281 {
1282 struct uart_8250_port *up = up_to_u8250p(port);
1283 u8 cpr2 = quot_frac >> 16;
1284 u8 cpr = quot_frac >> 8;
1285 u8 tcr = quot_frac;
1286
1287 serial_icr_write(up, UART_TCR, tcr);
1288 serial_icr_write(up, UART_CPR, cpr);
1289 serial_icr_write(up, UART_CKS, cpr2);
1290 serial8250_do_set_divisor(port, baud, quot);
1291 }
1292
1293 /*
1294 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1295 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1296 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1297 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1298 unsigned int mctrl)
1299 {
1300 struct uart_8250_port *up = up_to_u8250p(port);
1301
1302 up->mcr |= UART_MCR_CLKSEL;
1303 serial8250_do_set_mctrl(port, mctrl);
1304 }
1305
1306 /*
1307 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1308 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1309 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1310 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1311 const struct pciserial_board *board,
1312 struct uart_8250_port *up, int idx)
1313 {
1314 struct pci_dev *dev = priv->dev;
1315
1316 if (pci_oxsemi_tornado_p(dev)) {
1317 up->port.flags |= UPF_FULL_PROBE;
1318 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1319 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1320 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1321 }
1322
1323 return pci_default_setup(priv, board, up, idx);
1324 }
1325
1326 #define QPCR_TEST_FOR1 0x3F
1327 #define QPCR_TEST_GET1 0x00
1328 #define QPCR_TEST_FOR2 0x40
1329 #define QPCR_TEST_GET2 0x40
1330 #define QPCR_TEST_FOR3 0x80
1331 #define QPCR_TEST_GET3 0x40
1332 #define QPCR_TEST_FOR4 0xC0
1333 #define QPCR_TEST_GET4 0x80
1334
1335 #define QOPR_CLOCK_X1 0x0000
1336 #define QOPR_CLOCK_X2 0x0001
1337 #define QOPR_CLOCK_X4 0x0002
1338 #define QOPR_CLOCK_X8 0x0003
1339 #define QOPR_CLOCK_RATE_MASK 0x0003
1340
1341 /* Quatech devices have their own extra interface features */
1342 static struct pci_device_id quatech_cards[] = {
1343 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1344 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1345 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1346 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1347 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1349 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1350 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1351 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1352 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1353 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1354 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1355 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1356 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1357 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1358 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1359 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1360 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1361 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1362 { 0, }
1363 };
1364
pci_quatech_rqopr(struct uart_8250_port * port)1365 static int pci_quatech_rqopr(struct uart_8250_port *port)
1366 {
1367 unsigned long base = port->port.iobase;
1368 u8 LCR, val;
1369
1370 LCR = inb(base + UART_LCR);
1371 outb(0xBF, base + UART_LCR);
1372 val = inb(base + UART_SCR);
1373 outb(LCR, base + UART_LCR);
1374 return val;
1375 }
1376
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1377 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1378 {
1379 unsigned long base = port->port.iobase;
1380 u8 LCR;
1381
1382 LCR = inb(base + UART_LCR);
1383 outb(0xBF, base + UART_LCR);
1384 inb(base + UART_SCR);
1385 outb(qopr, base + UART_SCR);
1386 outb(LCR, base + UART_LCR);
1387 }
1388
pci_quatech_rqmcr(struct uart_8250_port * port)1389 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1390 {
1391 unsigned long base = port->port.iobase;
1392 u8 LCR, val, qmcr;
1393
1394 LCR = inb(base + UART_LCR);
1395 outb(0xBF, base + UART_LCR);
1396 val = inb(base + UART_SCR);
1397 outb(val | 0x10, base + UART_SCR);
1398 qmcr = inb(base + UART_MCR);
1399 outb(val, base + UART_SCR);
1400 outb(LCR, base + UART_LCR);
1401
1402 return qmcr;
1403 }
1404
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1405 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1406 {
1407 unsigned long base = port->port.iobase;
1408 u8 LCR, val;
1409
1410 LCR = inb(base + UART_LCR);
1411 outb(0xBF, base + UART_LCR);
1412 val = inb(base + UART_SCR);
1413 outb(val | 0x10, base + UART_SCR);
1414 outb(qmcr, base + UART_MCR);
1415 outb(val, base + UART_SCR);
1416 outb(LCR, base + UART_LCR);
1417 }
1418
pci_quatech_has_qmcr(struct uart_8250_port * port)1419 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1420 {
1421 unsigned long base = port->port.iobase;
1422 u8 LCR, val;
1423
1424 LCR = inb(base + UART_LCR);
1425 outb(0xBF, base + UART_LCR);
1426 val = inb(base + UART_SCR);
1427 if (val & 0x20) {
1428 outb(0x80, UART_LCR);
1429 if (!(inb(UART_SCR) & 0x20)) {
1430 outb(LCR, base + UART_LCR);
1431 return 1;
1432 }
1433 }
1434 return 0;
1435 }
1436
pci_quatech_test(struct uart_8250_port * port)1437 static int pci_quatech_test(struct uart_8250_port *port)
1438 {
1439 u8 reg, qopr;
1440
1441 qopr = pci_quatech_rqopr(port);
1442 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1443 reg = pci_quatech_rqopr(port) & 0xC0;
1444 if (reg != QPCR_TEST_GET1)
1445 return -EINVAL;
1446 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1447 reg = pci_quatech_rqopr(port) & 0xC0;
1448 if (reg != QPCR_TEST_GET2)
1449 return -EINVAL;
1450 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1451 reg = pci_quatech_rqopr(port) & 0xC0;
1452 if (reg != QPCR_TEST_GET3)
1453 return -EINVAL;
1454 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1455 reg = pci_quatech_rqopr(port) & 0xC0;
1456 if (reg != QPCR_TEST_GET4)
1457 return -EINVAL;
1458
1459 pci_quatech_wqopr(port, qopr);
1460 return 0;
1461 }
1462
pci_quatech_clock(struct uart_8250_port * port)1463 static int pci_quatech_clock(struct uart_8250_port *port)
1464 {
1465 u8 qopr, reg, set;
1466 unsigned long clock;
1467
1468 if (pci_quatech_test(port) < 0)
1469 return 1843200;
1470
1471 qopr = pci_quatech_rqopr(port);
1472
1473 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1474 reg = pci_quatech_rqopr(port);
1475 if (reg & QOPR_CLOCK_X8) {
1476 clock = 1843200;
1477 goto out;
1478 }
1479 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1480 reg = pci_quatech_rqopr(port);
1481 if (!(reg & QOPR_CLOCK_X8)) {
1482 clock = 1843200;
1483 goto out;
1484 }
1485 reg &= QOPR_CLOCK_X8;
1486 if (reg == QOPR_CLOCK_X2) {
1487 clock = 3685400;
1488 set = QOPR_CLOCK_X2;
1489 } else if (reg == QOPR_CLOCK_X4) {
1490 clock = 7372800;
1491 set = QOPR_CLOCK_X4;
1492 } else if (reg == QOPR_CLOCK_X8) {
1493 clock = 14745600;
1494 set = QOPR_CLOCK_X8;
1495 } else {
1496 clock = 1843200;
1497 set = QOPR_CLOCK_X1;
1498 }
1499 qopr &= ~QOPR_CLOCK_RATE_MASK;
1500 qopr |= set;
1501
1502 out:
1503 pci_quatech_wqopr(port, qopr);
1504 return clock;
1505 }
1506
pci_quatech_rs422(struct uart_8250_port * port)1507 static int pci_quatech_rs422(struct uart_8250_port *port)
1508 {
1509 u8 qmcr;
1510 int rs422 = 0;
1511
1512 if (!pci_quatech_has_qmcr(port))
1513 return 0;
1514 qmcr = pci_quatech_rqmcr(port);
1515 pci_quatech_wqmcr(port, 0xFF);
1516 if (pci_quatech_rqmcr(port))
1517 rs422 = 1;
1518 pci_quatech_wqmcr(port, qmcr);
1519 return rs422;
1520 }
1521
pci_quatech_init(struct pci_dev * dev)1522 static int pci_quatech_init(struct pci_dev *dev)
1523 {
1524 const struct pci_device_id *match;
1525 bool amcc = false;
1526
1527 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1528 return serial_8250_warn_need_ioport(dev);
1529
1530 match = pci_match_id(quatech_cards, dev);
1531 if (match)
1532 amcc = match->driver_data;
1533 else
1534 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1535
1536 if (amcc) {
1537 unsigned long base = pci_resource_start(dev, 0);
1538 if (base) {
1539 u32 tmp;
1540
1541 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1542 tmp = inl(base + 0x3c);
1543 outl(tmp | 0x01000000, base + 0x3c);
1544 outl(tmp & ~0x01000000, base + 0x3c);
1545 }
1546 }
1547 return 0;
1548 }
1549
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1550 static int pci_quatech_setup(struct serial_private *priv,
1551 const struct pciserial_board *board,
1552 struct uart_8250_port *port, int idx)
1553 {
1554 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1555 return serial_8250_warn_need_ioport(priv->dev);
1556
1557 /* Needed by pci_quatech calls below */
1558 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1559 /* Set up the clocking */
1560 port->port.uartclk = pci_quatech_clock(port);
1561 /* For now just warn about RS422 */
1562 if (pci_quatech_rs422(port))
1563 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1564 return pci_default_setup(priv, board, port, idx);
1565 }
1566
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1567 static int pci_default_setup(struct serial_private *priv,
1568 const struct pciserial_board *board,
1569 struct uart_8250_port *port, int idx)
1570 {
1571 unsigned int bar, offset = board->first_offset, maxnr;
1572
1573 bar = FL_GET_BASE(board->flags);
1574 if (board->flags & FL_BASE_BARS)
1575 bar += idx;
1576 else
1577 offset += idx * board->uart_offset;
1578
1579 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1580 (board->reg_shift + 3);
1581
1582 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1583 return 1;
1584
1585 return setup_port(priv, port, bar, offset, board->reg_shift);
1586 }
1587
1588 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1589 ce4100_serial_setup(struct serial_private *priv,
1590 const struct pciserial_board *board,
1591 struct uart_8250_port *port, int idx)
1592 {
1593 int ret;
1594
1595 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1596 port->port.iotype = UPIO_MEM32;
1597 port->port.type = PORT_XSCALE;
1598 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1599 port->port.regshift = 2;
1600
1601 return ret;
1602 }
1603
1604 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1605 pci_omegapci_setup(struct serial_private *priv,
1606 const struct pciserial_board *board,
1607 struct uart_8250_port *port, int idx)
1608 {
1609 return setup_port(priv, port, 2, idx * 8, 0);
1610 }
1611
1612 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1613 pci_brcm_trumanage_setup(struct serial_private *priv,
1614 const struct pciserial_board *board,
1615 struct uart_8250_port *port, int idx)
1616 {
1617 int ret = pci_default_setup(priv, board, port, idx);
1618
1619 port->port.type = PORT_BRCM_TRUMANAGE;
1620 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1621 return ret;
1622 }
1623
1624 /* RTS will control by MCR if this bit is 0 */
1625 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1626 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1627 #define FINTEK_RTS_INVERT BIT(5)
1628
1629 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1630 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1631 struct serial_rs485 *rs485)
1632 {
1633 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1634 u8 setting;
1635 u8 *index = (u8 *) port->private_data;
1636
1637 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1638
1639 if (rs485->flags & SER_RS485_ENABLED) {
1640 /* Enable RTS H/W control mode */
1641 setting |= FINTEK_RTS_CONTROL_BY_HW;
1642
1643 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1644 /* RTS driving high on TX */
1645 setting &= ~FINTEK_RTS_INVERT;
1646 } else {
1647 /* RTS driving low on TX */
1648 setting |= FINTEK_RTS_INVERT;
1649 }
1650 } else {
1651 /* Disable RTS H/W control mode */
1652 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1653 }
1654
1655 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1656
1657 return 0;
1658 }
1659
1660 static const struct serial_rs485 pci_fintek_rs485_supported = {
1661 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1662 /* F81504/508/512 does not support RTS delay before or after send */
1663 };
1664
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1665 static int pci_fintek_setup(struct serial_private *priv,
1666 const struct pciserial_board *board,
1667 struct uart_8250_port *port, int idx)
1668 {
1669 struct pci_dev *pdev = priv->dev;
1670 u8 *data;
1671 u8 config_base;
1672 u16 iobase;
1673
1674 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1675 return serial_8250_warn_need_ioport(pdev);
1676
1677 config_base = 0x40 + 0x08 * idx;
1678
1679 /* Get the io address from configuration space */
1680 pci_read_config_word(pdev, config_base + 4, &iobase);
1681
1682 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1683
1684 port->port.iotype = UPIO_PORT;
1685 port->port.iobase = iobase;
1686 port->port.rs485_config = pci_fintek_rs485_config;
1687 port->port.rs485_supported = pci_fintek_rs485_supported;
1688
1689 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1690 if (!data)
1691 return -ENOMEM;
1692
1693 /* preserve index in PCI configuration space */
1694 *data = idx;
1695 port->port.private_data = data;
1696
1697 return 0;
1698 }
1699
pci_fintek_init(struct pci_dev * dev)1700 static int pci_fintek_init(struct pci_dev *dev)
1701 {
1702 unsigned long iobase;
1703 u32 max_port, i;
1704 resource_size_t bar_data[3];
1705 u8 config_base;
1706 struct serial_private *priv = pci_get_drvdata(dev);
1707
1708 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1709 return serial_8250_warn_need_ioport(dev);
1710
1711 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1712 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1713 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1714 return -ENODEV;
1715
1716 switch (dev->device) {
1717 case 0x1104: /* 4 ports */
1718 case 0x1108: /* 8 ports */
1719 max_port = dev->device & 0xff;
1720 break;
1721 case 0x1112: /* 12 ports */
1722 max_port = 12;
1723 break;
1724 default:
1725 return -EINVAL;
1726 }
1727
1728 /* Get the io address dispatch from the BIOS */
1729 bar_data[0] = pci_resource_start(dev, 5);
1730 bar_data[1] = pci_resource_start(dev, 4);
1731 bar_data[2] = pci_resource_start(dev, 3);
1732
1733 for (i = 0; i < max_port; ++i) {
1734 /* UART0 configuration offset start from 0x40 */
1735 config_base = 0x40 + 0x08 * i;
1736
1737 /* Calculate Real IO Port */
1738 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1739
1740 /* Enable UART I/O port */
1741 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1742
1743 /* Select 128-byte FIFO and 8x FIFO threshold */
1744 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1745
1746 /* LSB UART */
1747 pci_write_config_byte(dev, config_base + 0x04,
1748 (u8)(iobase & 0xff));
1749
1750 /* MSB UART */
1751 pci_write_config_byte(dev, config_base + 0x05,
1752 (u8)((iobase & 0xff00) >> 8));
1753
1754 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1755
1756 if (!priv) {
1757 /* First init without port data
1758 * force init to RS232 Mode
1759 */
1760 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1761 }
1762 }
1763
1764 return max_port;
1765 }
1766
f815xxa_mem_serial_out(struct uart_port * p,unsigned int offset,u32 value)1767 static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
1768 {
1769 struct f815xxa_data *data = p->private_data;
1770 unsigned long flags;
1771
1772 spin_lock_irqsave(&data->lock, flags);
1773 writeb(value, p->membase + offset);
1774 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1775 spin_unlock_irqrestore(&data->lock, flags);
1776 }
1777
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1778 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1779 const struct pciserial_board *board,
1780 struct uart_8250_port *port, int idx)
1781 {
1782 struct pci_dev *pdev = priv->dev;
1783 struct f815xxa_data *data;
1784
1785 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1786 if (!data)
1787 return -ENOMEM;
1788
1789 data->idx = idx;
1790 spin_lock_init(&data->lock);
1791
1792 port->port.private_data = data;
1793 port->port.iotype = UPIO_MEM;
1794 port->port.flags |= UPF_IOREMAP;
1795 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1796 port->port.serial_out = f815xxa_mem_serial_out;
1797
1798 return 0;
1799 }
1800
pci_fintek_f815xxa_init(struct pci_dev * dev)1801 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1802 {
1803 u32 max_port, i;
1804 int config_base;
1805
1806 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1807 return -ENODEV;
1808
1809 switch (dev->device) {
1810 case 0x1204: /* 4 ports */
1811 case 0x1208: /* 8 ports */
1812 max_port = dev->device & 0xff;
1813 break;
1814 case 0x1212: /* 12 ports */
1815 max_port = 12;
1816 break;
1817 default:
1818 return -EINVAL;
1819 }
1820
1821 /* Set to mmio decode */
1822 pci_write_config_byte(dev, 0x209, 0x40);
1823
1824 for (i = 0; i < max_port; ++i) {
1825 /* UART0 configuration offset start from 0x2A0 */
1826 config_base = 0x2A0 + 0x08 * i;
1827
1828 /* Select 128-byte FIFO and 8x FIFO threshold */
1829 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1830
1831 /* Enable UART I/O port */
1832 pci_write_config_byte(dev, config_base + 0, 0x01);
1833 }
1834
1835 return max_port;
1836 }
1837
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1838 static int skip_tx_en_setup(struct serial_private *priv,
1839 const struct pciserial_board *board,
1840 struct uart_8250_port *port, int idx)
1841 {
1842 port->port.quirks |= UPQ_NO_TXEN_TEST;
1843 pci_dbg(priv->dev,
1844 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1845 priv->dev->vendor, priv->dev->device,
1846 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1847
1848 return pci_default_setup(priv, board, port, idx);
1849 }
1850
kt_handle_break(struct uart_port * p)1851 static void kt_handle_break(struct uart_port *p)
1852 {
1853 struct uart_8250_port *up = up_to_u8250p(p);
1854 /*
1855 * On receipt of a BI, serial device in Intel ME (Intel
1856 * management engine) needs to have its fifos cleared for sane
1857 * SOL (Serial Over Lan) output.
1858 */
1859 serial8250_clear_and_reinit_fifos(up);
1860 }
1861
kt_serial_in(struct uart_port * p,unsigned int offset)1862 static u32 kt_serial_in(struct uart_port *p, unsigned int offset)
1863 {
1864 struct uart_8250_port *up = up_to_u8250p(p);
1865 u32 val;
1866
1867 /*
1868 * When the Intel ME (management engine) gets reset its serial
1869 * port registers could return 0 momentarily. Functions like
1870 * serial8250_console_write, read and save the IER, perform
1871 * some operation and then restore it. In order to avoid
1872 * setting IER register inadvertently to 0, if the value read
1873 * is 0, double check with ier value in uart_8250_port and use
1874 * that instead. up->ier should be the same value as what is
1875 * currently configured.
1876 */
1877 val = inb(p->iobase + offset);
1878 if (offset == UART_IER) {
1879 if (val == 0)
1880 val = up->ier;
1881 }
1882 return val;
1883 }
1884
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1885 static int kt_serial_setup(struct serial_private *priv,
1886 const struct pciserial_board *board,
1887 struct uart_8250_port *port, int idx)
1888 {
1889 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1890 return serial_8250_warn_need_ioport(priv->dev);
1891
1892 port->port.flags |= UPF_BUG_THRE;
1893 port->port.serial_in = kt_serial_in;
1894 port->port.handle_break = kt_handle_break;
1895 return skip_tx_en_setup(priv, board, port, idx);
1896 }
1897
pci_eg20t_init(struct pci_dev * dev)1898 static int pci_eg20t_init(struct pci_dev *dev)
1899 {
1900 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1901 return -ENODEV;
1902 #else
1903 return 0;
1904 #endif
1905 }
1906
1907 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1908 pci_wch_ch353_setup(struct serial_private *priv,
1909 const struct pciserial_board *board,
1910 struct uart_8250_port *port, int idx)
1911 {
1912 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1913 return serial_8250_warn_need_ioport(priv->dev);
1914
1915 port->port.flags |= UPF_FIXED_TYPE;
1916 port->port.type = PORT_16550A;
1917 return pci_default_setup(priv, board, port, idx);
1918 }
1919
1920 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1921 pci_wch_ch355_setup(struct serial_private *priv,
1922 const struct pciserial_board *board,
1923 struct uart_8250_port *port, int idx)
1924 {
1925 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1926 return serial_8250_warn_need_ioport(priv->dev);
1927
1928 port->port.flags |= UPF_FIXED_TYPE;
1929 port->port.type = PORT_16550A;
1930 return pci_default_setup(priv, board, port, idx);
1931 }
1932
1933 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1934 pci_wch_ch38x_setup(struct serial_private *priv,
1935 const struct pciserial_board *board,
1936 struct uart_8250_port *port, int idx)
1937 {
1938 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1939 return serial_8250_warn_need_ioport(priv->dev);
1940
1941 port->port.flags |= UPF_FIXED_TYPE;
1942 port->port.type = PORT_16850;
1943 return pci_default_setup(priv, board, port, idx);
1944 }
1945
1946
1947 #define CH384_XINT_ENABLE_REG 0xEB
1948 #define CH384_XINT_ENABLE_BIT 0x02
1949
pci_wch_ch38x_init(struct pci_dev * dev)1950 static int pci_wch_ch38x_init(struct pci_dev *dev)
1951 {
1952 int max_port;
1953 unsigned long iobase;
1954
1955 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1956 return serial_8250_warn_need_ioport(dev);
1957
1958 switch (dev->device) {
1959 case 0x3853: /* 8 ports */
1960 max_port = 8;
1961 break;
1962 default:
1963 return -EINVAL;
1964 }
1965
1966 iobase = pci_resource_start(dev, 0);
1967 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1968
1969 return max_port;
1970 }
1971
pci_wch_ch38x_exit(struct pci_dev * dev)1972 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1973 {
1974 unsigned long iobase;
1975
1976 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
1977 serial_8250_warn_need_ioport(dev);
1978 return;
1979 }
1980
1981 iobase = pci_resource_start(dev, 0);
1982 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1983 }
1984
1985
1986 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1987 pci_sunix_setup(struct serial_private *priv,
1988 const struct pciserial_board *board,
1989 struct uart_8250_port *port, int idx)
1990 {
1991 int bar;
1992 int offset;
1993
1994 port->port.flags |= UPF_FIXED_TYPE;
1995 port->port.type = PORT_SUNIX;
1996
1997 if (idx < 4) {
1998 bar = 0;
1999 offset = idx * board->uart_offset;
2000 } else {
2001 bar = 1;
2002 idx -= 4;
2003 idx = div_s64_rem(idx, 4, &offset);
2004 offset = idx * 64 + offset * board->uart_offset;
2005 }
2006
2007 return setup_port(priv, port, bar, offset, 0);
2008 }
2009
2010 #define MOXA_PUART_GPIO_EN 0x09
2011 #define MOXA_PUART_GPIO_OUT 0x0A
2012
2013 #define MOXA_GPIO_PIN2 BIT(2)
2014
2015 #define MOXA_RS232 0x00
2016 #define MOXA_RS422 0x01
2017 #define MOXA_RS485_4W 0x0B
2018 #define MOXA_RS485_2W 0x0F
2019 #define MOXA_UIR_OFFSET 0x04
2020 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2021 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
2022
2023 enum {
2024 MOXA_SUPP_RS232 = BIT(0),
2025 MOXA_SUPP_RS422 = BIT(1),
2026 MOXA_SUPP_RS485 = BIT(2),
2027 };
2028
moxa_get_nports(unsigned short device)2029 static unsigned short moxa_get_nports(unsigned short device)
2030 {
2031 switch (device) {
2032 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
2033 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
2034 return 8;
2035 }
2036
2037 return FIELD_GET(0x00F0, device);
2038 }
2039
pci_moxa_is_mini_pcie(unsigned short device)2040 static bool pci_moxa_is_mini_pcie(unsigned short device)
2041 {
2042 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2043 device == PCI_DEVICE_ID_MOXA_CP104N ||
2044 device == PCI_DEVICE_ID_MOXA_CP112N ||
2045 device == PCI_DEVICE_ID_MOXA_CP114N ||
2046 device == PCI_DEVICE_ID_MOXA_CP132N ||
2047 device == PCI_DEVICE_ID_MOXA_CP134N)
2048 return true;
2049
2050 return false;
2051 }
2052
pci_moxa_supported_rs(struct pci_dev * dev)2053 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2054 {
2055 switch (dev->device & 0x0F00) {
2056 case 0x0000:
2057 case 0x0600:
2058 return MOXA_SUPP_RS232;
2059 case 0x0100:
2060 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2061 case 0x0300:
2062 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2063 }
2064 return 0;
2065 }
2066
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2067 static int pci_moxa_set_interface(const struct pci_dev *dev,
2068 unsigned int port_idx,
2069 u8 mode)
2070 {
2071 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2072 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2073 u8 val;
2074
2075 val = inb(UIR_addr);
2076
2077 if (port_idx % 2) {
2078 val &= ~MOXA_ODD_RS_MASK;
2079 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2080 } else {
2081 val &= ~MOXA_EVEN_RS_MASK;
2082 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2083 }
2084 outb(val, UIR_addr);
2085
2086 return 0;
2087 }
2088
pci_moxa_init(struct pci_dev * dev)2089 static int pci_moxa_init(struct pci_dev *dev)
2090 {
2091 unsigned short device = dev->device;
2092 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2093 unsigned int i, num_ports = moxa_get_nports(device);
2094 u8 val, init_mode = MOXA_RS232;
2095
2096 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2097 return serial_8250_warn_need_ioport(dev);
2098
2099 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2100 init_mode = MOXA_RS422;
2101 }
2102 for (i = 0; i < num_ports; ++i)
2103 pci_moxa_set_interface(dev, i, init_mode);
2104
2105 /*
2106 * Enable hardware buffer to prevent break signal output when system boots up.
2107 * This hardware buffer is only supported on Mini PCIe series.
2108 */
2109 if (pci_moxa_is_mini_pcie(device)) {
2110 /* Set GPIO direction */
2111 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2112 val |= MOXA_GPIO_PIN2;
2113 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2114 /* Enable low GPIO */
2115 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2116 val &= ~MOXA_GPIO_PIN2;
2117 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2118 }
2119
2120 return num_ports;
2121 }
2122
2123 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2124 pci_moxa_setup(struct serial_private *priv,
2125 const struct pciserial_board *board,
2126 struct uart_8250_port *port, int idx)
2127 {
2128 unsigned int bar = FL_GET_BASE(board->flags);
2129 int offset;
2130
2131 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2132 return serial_8250_warn_need_ioport(priv->dev);
2133
2134 if (board->num_ports == 4 && idx == 3)
2135 offset = 7 * board->uart_offset;
2136 else
2137 offset = idx * board->uart_offset;
2138
2139 return setup_port(priv, port, bar, offset, 0);
2140 }
2141
2142 /*
2143 * Master list of serial port init/setup/exit quirks.
2144 * This does not describe the general nature of the port.
2145 * (ie, baud base, number and location of ports, etc)
2146 *
2147 * This list is ordered alphabetically by vendor then device.
2148 * Specific entries must come before more generic entries.
2149 */
2150 static struct pci_serial_quirk pci_serial_quirks[] = {
2151 /*
2152 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2153 */
2154 {
2155 .vendor = PCI_VENDOR_ID_AMCC,
2156 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
2159 .setup = addidata_apci7800_setup,
2160 },
2161 /*
2162 * AFAVLAB cards - these may be called via parport_serial
2163 * It is not clear whether this applies to all products.
2164 */
2165 {
2166 .vendor = PCI_VENDOR_ID_AFAVLAB,
2167 .device = PCI_ANY_ID,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .setup = afavlab_setup,
2171 },
2172 /*
2173 * HP Diva
2174 */
2175 {
2176 .vendor = PCI_VENDOR_ID_HP,
2177 .device = PCI_DEVICE_ID_HP_DIVA,
2178 .subvendor = PCI_ANY_ID,
2179 .subdevice = PCI_ANY_ID,
2180 .init = pci_hp_diva_init,
2181 .setup = pci_hp_diva_setup,
2182 },
2183 /*
2184 * HPE PCI serial device
2185 */
2186 {
2187 .vendor = PCI_VENDOR_ID_HP_3PAR,
2188 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .setup = pci_hp_diva_setup,
2192 },
2193 /*
2194 * Intel
2195 */
2196 {
2197 .vendor = PCI_VENDOR_ID_INTEL,
2198 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2199 .subvendor = 0xe4bf,
2200 .subdevice = PCI_ANY_ID,
2201 .init = pci_inteli960ni_init,
2202 .setup = pci_default_setup,
2203 },
2204 {
2205 .vendor = PCI_VENDOR_ID_INTEL,
2206 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2207 .subvendor = PCI_ANY_ID,
2208 .subdevice = PCI_ANY_ID,
2209 .setup = skip_tx_en_setup,
2210 },
2211 {
2212 .vendor = PCI_VENDOR_ID_INTEL,
2213 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2214 .subvendor = PCI_ANY_ID,
2215 .subdevice = PCI_ANY_ID,
2216 .setup = skip_tx_en_setup,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_INTEL,
2220 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .setup = skip_tx_en_setup,
2224 },
2225 {
2226 .vendor = PCI_VENDOR_ID_INTEL,
2227 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .setup = ce4100_serial_setup,
2231 },
2232 {
2233 .vendor = PCI_VENDOR_ID_INTEL,
2234 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2235 .subvendor = PCI_ANY_ID,
2236 .subdevice = PCI_ANY_ID,
2237 .setup = kt_serial_setup,
2238 },
2239 /*
2240 * ITE
2241 */
2242 {
2243 .vendor = PCI_VENDOR_ID_ITE,
2244 .device = PCI_DEVICE_ID_ITE_8872,
2245 .subvendor = PCI_ANY_ID,
2246 .subdevice = PCI_ANY_ID,
2247 .init = pci_ite887x_init,
2248 .setup = pci_default_setup,
2249 .exit = pci_ite887x_exit,
2250 },
2251 /*
2252 * National Instruments
2253 */
2254 {
2255 .vendor = PCI_VENDOR_ID_NI,
2256 .device = PCI_DEVICE_ID_NI_PCI23216,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .init = pci_ni8420_init,
2260 .setup = pci_default_setup,
2261 .exit = pci_ni8420_exit,
2262 },
2263 {
2264 .vendor = PCI_VENDOR_ID_NI,
2265 .device = PCI_DEVICE_ID_NI_PCI2328,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .init = pci_ni8420_init,
2269 .setup = pci_default_setup,
2270 .exit = pci_ni8420_exit,
2271 },
2272 {
2273 .vendor = PCI_VENDOR_ID_NI,
2274 .device = PCI_DEVICE_ID_NI_PCI2324,
2275 .subvendor = PCI_ANY_ID,
2276 .subdevice = PCI_ANY_ID,
2277 .init = pci_ni8420_init,
2278 .setup = pci_default_setup,
2279 .exit = pci_ni8420_exit,
2280 },
2281 {
2282 .vendor = PCI_VENDOR_ID_NI,
2283 .device = PCI_DEVICE_ID_NI_PCI2322,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .init = pci_ni8420_init,
2287 .setup = pci_default_setup,
2288 .exit = pci_ni8420_exit,
2289 },
2290 {
2291 .vendor = PCI_VENDOR_ID_NI,
2292 .device = PCI_DEVICE_ID_NI_PCI2324I,
2293 .subvendor = PCI_ANY_ID,
2294 .subdevice = PCI_ANY_ID,
2295 .init = pci_ni8420_init,
2296 .setup = pci_default_setup,
2297 .exit = pci_ni8420_exit,
2298 },
2299 {
2300 .vendor = PCI_VENDOR_ID_NI,
2301 .device = PCI_DEVICE_ID_NI_PCI2322I,
2302 .subvendor = PCI_ANY_ID,
2303 .subdevice = PCI_ANY_ID,
2304 .init = pci_ni8420_init,
2305 .setup = pci_default_setup,
2306 .exit = pci_ni8420_exit,
2307 },
2308 {
2309 .vendor = PCI_VENDOR_ID_NI,
2310 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2311 .subvendor = PCI_ANY_ID,
2312 .subdevice = PCI_ANY_ID,
2313 .init = pci_ni8420_init,
2314 .setup = pci_default_setup,
2315 .exit = pci_ni8420_exit,
2316 },
2317 {
2318 .vendor = PCI_VENDOR_ID_NI,
2319 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .init = pci_ni8420_init,
2323 .setup = pci_default_setup,
2324 .exit = pci_ni8420_exit,
2325 },
2326 {
2327 .vendor = PCI_VENDOR_ID_NI,
2328 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2329 .subvendor = PCI_ANY_ID,
2330 .subdevice = PCI_ANY_ID,
2331 .init = pci_ni8420_init,
2332 .setup = pci_default_setup,
2333 .exit = pci_ni8420_exit,
2334 },
2335 {
2336 .vendor = PCI_VENDOR_ID_NI,
2337 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .init = pci_ni8420_init,
2341 .setup = pci_default_setup,
2342 .exit = pci_ni8420_exit,
2343 },
2344 {
2345 .vendor = PCI_VENDOR_ID_NI,
2346 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2347 .subvendor = PCI_ANY_ID,
2348 .subdevice = PCI_ANY_ID,
2349 .init = pci_ni8420_init,
2350 .setup = pci_default_setup,
2351 .exit = pci_ni8420_exit,
2352 },
2353 {
2354 .vendor = PCI_VENDOR_ID_NI,
2355 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2356 .subvendor = PCI_ANY_ID,
2357 .subdevice = PCI_ANY_ID,
2358 .init = pci_ni8420_init,
2359 .setup = pci_default_setup,
2360 .exit = pci_ni8420_exit,
2361 },
2362 {
2363 .vendor = PCI_VENDOR_ID_NI,
2364 .device = PCI_ANY_ID,
2365 .subvendor = PCI_ANY_ID,
2366 .subdevice = PCI_ANY_ID,
2367 .init = pci_ni8430_init,
2368 .setup = pci_ni8430_setup,
2369 .exit = pci_ni8430_exit,
2370 },
2371 /* Quatech */
2372 {
2373 .vendor = PCI_VENDOR_ID_QUATECH,
2374 .device = PCI_ANY_ID,
2375 .subvendor = PCI_ANY_ID,
2376 .subdevice = PCI_ANY_ID,
2377 .init = pci_quatech_init,
2378 .setup = pci_quatech_setup,
2379 },
2380 /*
2381 * Panacom
2382 */
2383 {
2384 .vendor = PCI_VENDOR_ID_PANACOM,
2385 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .init = pci_plx9050_init,
2389 .setup = pci_default_setup,
2390 .exit = pci_plx9050_exit,
2391 },
2392 {
2393 .vendor = PCI_VENDOR_ID_PANACOM,
2394 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .init = pci_plx9050_init,
2398 .setup = pci_default_setup,
2399 .exit = pci_plx9050_exit,
2400 },
2401 /*
2402 * PLX
2403 */
2404 {
2405 .vendor = PCI_VENDOR_ID_PLX,
2406 .device = PCI_DEVICE_ID_PLX_9050,
2407 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2408 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2409 .init = pci_plx9050_init,
2410 .setup = pci_default_setup,
2411 .exit = pci_plx9050_exit,
2412 },
2413 {
2414 .vendor = PCI_VENDOR_ID_PLX,
2415 .device = PCI_DEVICE_ID_PLX_9050,
2416 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2417 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2418 .init = pci_plx9050_init,
2419 .setup = pci_default_setup,
2420 .exit = pci_plx9050_exit,
2421 },
2422 {
2423 .vendor = PCI_VENDOR_ID_PLX,
2424 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2425 .subvendor = PCI_VENDOR_ID_PLX,
2426 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2427 .init = pci_plx9050_init,
2428 .setup = pci_default_setup,
2429 .exit = pci_plx9050_exit,
2430 },
2431 /*
2432 * SBS Technologies, Inc., PMC-OCTALPRO 232
2433 */
2434 {
2435 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2436 .device = PCI_DEVICE_ID_OCTPRO,
2437 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2438 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2439 .init = sbs_init,
2440 .setup = sbs_setup,
2441 .exit = sbs_exit,
2442 },
2443 /*
2444 * SBS Technologies, Inc., PMC-OCTALPRO 422
2445 */
2446 {
2447 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2448 .device = PCI_DEVICE_ID_OCTPRO,
2449 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2450 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2451 .init = sbs_init,
2452 .setup = sbs_setup,
2453 .exit = sbs_exit,
2454 },
2455 /*
2456 * SBS Technologies, Inc., P-Octal 232
2457 */
2458 {
2459 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2460 .device = PCI_DEVICE_ID_OCTPRO,
2461 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2462 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2463 .init = sbs_init,
2464 .setup = sbs_setup,
2465 .exit = sbs_exit,
2466 },
2467 /*
2468 * SBS Technologies, Inc., P-Octal 422
2469 */
2470 {
2471 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2472 .device = PCI_DEVICE_ID_OCTPRO,
2473 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2474 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2475 .init = sbs_init,
2476 .setup = sbs_setup,
2477 .exit = sbs_exit,
2478 },
2479 /*
2480 * SIIG cards - these may be called via parport_serial
2481 */
2482 {
2483 .vendor = PCI_VENDOR_ID_SIIG,
2484 .device = PCI_ANY_ID,
2485 .subvendor = PCI_ANY_ID,
2486 .subdevice = PCI_ANY_ID,
2487 .init = pci_siig_init,
2488 .setup = pci_siig_setup,
2489 },
2490 /*
2491 * Titan cards
2492 */
2493 {
2494 .vendor = PCI_VENDOR_ID_TITAN,
2495 .device = PCI_DEVICE_ID_TITAN_400L,
2496 .subvendor = PCI_ANY_ID,
2497 .subdevice = PCI_ANY_ID,
2498 .setup = titan_400l_800l_setup,
2499 },
2500 {
2501 .vendor = PCI_VENDOR_ID_TITAN,
2502 .device = PCI_DEVICE_ID_TITAN_800L,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .setup = titan_400l_800l_setup,
2506 },
2507 /*
2508 * Timedia cards
2509 */
2510 {
2511 .vendor = PCI_VENDOR_ID_TIMEDIA,
2512 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2513 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2514 .subdevice = PCI_ANY_ID,
2515 .probe = pci_timedia_probe,
2516 .init = pci_timedia_init,
2517 .setup = pci_timedia_setup,
2518 },
2519 {
2520 .vendor = PCI_VENDOR_ID_TIMEDIA,
2521 .device = PCI_ANY_ID,
2522 .subvendor = PCI_ANY_ID,
2523 .subdevice = PCI_ANY_ID,
2524 .setup = pci_timedia_setup,
2525 },
2526 /*
2527 * Sunix PCI serial boards
2528 */
2529 {
2530 .vendor = PCI_VENDOR_ID_SUNIX,
2531 .device = PCI_DEVICE_ID_SUNIX_1999,
2532 .subvendor = PCI_VENDOR_ID_SUNIX,
2533 .subdevice = PCI_ANY_ID,
2534 .setup = pci_sunix_setup,
2535 },
2536 /*
2537 * Xircom cards
2538 */
2539 {
2540 .vendor = PCI_VENDOR_ID_XIRCOM,
2541 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .init = pci_xircom_init,
2545 .setup = pci_default_setup,
2546 },
2547 /*
2548 * Netmos cards - these may be called via parport_serial
2549 */
2550 {
2551 .vendor = PCI_VENDOR_ID_NETMOS,
2552 .device = PCI_ANY_ID,
2553 .subvendor = PCI_ANY_ID,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_netmos_init,
2556 .setup = pci_netmos_9900_setup,
2557 },
2558 /*
2559 * EndRun Technologies
2560 */
2561 {
2562 .vendor = PCI_VENDOR_ID_ENDRUN,
2563 .device = PCI_ANY_ID,
2564 .subvendor = PCI_ANY_ID,
2565 .subdevice = PCI_ANY_ID,
2566 .init = pci_oxsemi_tornado_init,
2567 .setup = pci_default_setup,
2568 },
2569 /*
2570 * For Oxford Semiconductor Tornado based devices
2571 */
2572 {
2573 .vendor = PCI_VENDOR_ID_OXSEMI,
2574 .device = PCI_ANY_ID,
2575 .subvendor = PCI_ANY_ID,
2576 .subdevice = PCI_ANY_ID,
2577 .init = pci_oxsemi_tornado_init,
2578 .setup = pci_oxsemi_tornado_setup,
2579 },
2580 {
2581 .vendor = PCI_VENDOR_ID_MAINPINE,
2582 .device = PCI_ANY_ID,
2583 .subvendor = PCI_ANY_ID,
2584 .subdevice = PCI_ANY_ID,
2585 .init = pci_oxsemi_tornado_init,
2586 .setup = pci_oxsemi_tornado_setup,
2587 },
2588 {
2589 .vendor = PCI_VENDOR_ID_DIGI,
2590 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2591 .subvendor = PCI_SUBVENDOR_ID_IBM,
2592 .subdevice = PCI_ANY_ID,
2593 .init = pci_oxsemi_tornado_init,
2594 .setup = pci_oxsemi_tornado_setup,
2595 },
2596 /*
2597 * Brainboxes devices - all Oxsemi based
2598 */
2599 {
2600 .vendor = PCI_VENDOR_ID_INTASHIELD,
2601 .device = 0x4027,
2602 .subvendor = PCI_ANY_ID,
2603 .subdevice = PCI_ANY_ID,
2604 .init = pci_oxsemi_tornado_init,
2605 .setup = pci_oxsemi_tornado_setup,
2606 },
2607 {
2608 .vendor = PCI_VENDOR_ID_INTASHIELD,
2609 .device = 0x4028,
2610 .subvendor = PCI_ANY_ID,
2611 .subdevice = PCI_ANY_ID,
2612 .init = pci_oxsemi_tornado_init,
2613 .setup = pci_oxsemi_tornado_setup,
2614 },
2615 {
2616 .vendor = PCI_VENDOR_ID_INTASHIELD,
2617 .device = 0x4029,
2618 .subvendor = PCI_ANY_ID,
2619 .subdevice = PCI_ANY_ID,
2620 .init = pci_oxsemi_tornado_init,
2621 .setup = pci_oxsemi_tornado_setup,
2622 },
2623 {
2624 .vendor = PCI_VENDOR_ID_INTASHIELD,
2625 .device = 0x4019,
2626 .subvendor = PCI_ANY_ID,
2627 .subdevice = PCI_ANY_ID,
2628 .init = pci_oxsemi_tornado_init,
2629 .setup = pci_oxsemi_tornado_setup,
2630 },
2631 {
2632 .vendor = PCI_VENDOR_ID_INTASHIELD,
2633 .device = 0x4016,
2634 .subvendor = PCI_ANY_ID,
2635 .subdevice = PCI_ANY_ID,
2636 .init = pci_oxsemi_tornado_init,
2637 .setup = pci_oxsemi_tornado_setup,
2638 },
2639 {
2640 .vendor = PCI_VENDOR_ID_INTASHIELD,
2641 .device = 0x4015,
2642 .subvendor = PCI_ANY_ID,
2643 .subdevice = PCI_ANY_ID,
2644 .init = pci_oxsemi_tornado_init,
2645 .setup = pci_oxsemi_tornado_setup,
2646 },
2647 {
2648 .vendor = PCI_VENDOR_ID_INTASHIELD,
2649 .device = 0x400A,
2650 .subvendor = PCI_ANY_ID,
2651 .subdevice = PCI_ANY_ID,
2652 .init = pci_oxsemi_tornado_init,
2653 .setup = pci_oxsemi_tornado_setup,
2654 },
2655 {
2656 .vendor = PCI_VENDOR_ID_INTASHIELD,
2657 .device = 0x400E,
2658 .subvendor = PCI_ANY_ID,
2659 .subdevice = PCI_ANY_ID,
2660 .init = pci_oxsemi_tornado_init,
2661 .setup = pci_oxsemi_tornado_setup,
2662 },
2663 {
2664 .vendor = PCI_VENDOR_ID_INTASHIELD,
2665 .device = 0x400C,
2666 .subvendor = PCI_ANY_ID,
2667 .subdevice = PCI_ANY_ID,
2668 .init = pci_oxsemi_tornado_init,
2669 .setup = pci_oxsemi_tornado_setup,
2670 },
2671 {
2672 .vendor = PCI_VENDOR_ID_INTASHIELD,
2673 .device = 0x400B,
2674 .subvendor = PCI_ANY_ID,
2675 .subdevice = PCI_ANY_ID,
2676 .init = pci_oxsemi_tornado_init,
2677 .setup = pci_oxsemi_tornado_setup,
2678 },
2679 {
2680 .vendor = PCI_VENDOR_ID_INTASHIELD,
2681 .device = 0x400F,
2682 .subvendor = PCI_ANY_ID,
2683 .subdevice = PCI_ANY_ID,
2684 .init = pci_oxsemi_tornado_init,
2685 .setup = pci_oxsemi_tornado_setup,
2686 },
2687 {
2688 .vendor = PCI_VENDOR_ID_INTASHIELD,
2689 .device = 0x4010,
2690 .subvendor = PCI_ANY_ID,
2691 .subdevice = PCI_ANY_ID,
2692 .init = pci_oxsemi_tornado_init,
2693 .setup = pci_oxsemi_tornado_setup,
2694 },
2695 {
2696 .vendor = PCI_VENDOR_ID_INTASHIELD,
2697 .device = 0x4011,
2698 .subvendor = PCI_ANY_ID,
2699 .subdevice = PCI_ANY_ID,
2700 .init = pci_oxsemi_tornado_init,
2701 .setup = pci_oxsemi_tornado_setup,
2702 },
2703 {
2704 .vendor = PCI_VENDOR_ID_INTASHIELD,
2705 .device = 0x401D,
2706 .subvendor = PCI_ANY_ID,
2707 .subdevice = PCI_ANY_ID,
2708 .init = pci_oxsemi_tornado_init,
2709 .setup = pci_oxsemi_tornado_setup,
2710 },
2711 {
2712 .vendor = PCI_VENDOR_ID_INTASHIELD,
2713 .device = 0x401E,
2714 .subvendor = PCI_ANY_ID,
2715 .subdevice = PCI_ANY_ID,
2716 .init = pci_oxsemi_tornado_init,
2717 .setup = pci_oxsemi_tornado_setup,
2718 },
2719 {
2720 .vendor = PCI_VENDOR_ID_INTASHIELD,
2721 .device = 0x4013,
2722 .subvendor = PCI_ANY_ID,
2723 .subdevice = PCI_ANY_ID,
2724 .init = pci_oxsemi_tornado_init,
2725 .setup = pci_oxsemi_tornado_setup,
2726 },
2727 {
2728 .vendor = PCI_VENDOR_ID_INTASHIELD,
2729 .device = 0x4017,
2730 .subvendor = PCI_ANY_ID,
2731 .subdevice = PCI_ANY_ID,
2732 .init = pci_oxsemi_tornado_init,
2733 .setup = pci_oxsemi_tornado_setup,
2734 },
2735 {
2736 .vendor = PCI_VENDOR_ID_INTASHIELD,
2737 .device = 0x4018,
2738 .subvendor = PCI_ANY_ID,
2739 .subdevice = PCI_ANY_ID,
2740 .init = pci_oxsemi_tornado_init,
2741 .setup = pci_oxsemi_tornado_setup,
2742 },
2743 {
2744 .vendor = PCI_VENDOR_ID_INTASHIELD,
2745 .device = 0x4026,
2746 .subvendor = PCI_ANY_ID,
2747 .subdevice = PCI_ANY_ID,
2748 .init = pci_oxsemi_tornado_init,
2749 .setup = pci_oxsemi_tornado_setup,
2750 },
2751 {
2752 .vendor = PCI_VENDOR_ID_INTASHIELD,
2753 .device = 0x4021,
2754 .subvendor = PCI_ANY_ID,
2755 .subdevice = PCI_ANY_ID,
2756 .init = pci_oxsemi_tornado_init,
2757 .setup = pci_oxsemi_tornado_setup,
2758 },
2759 {
2760 .vendor = PCI_VENDOR_ID_INTEL,
2761 .device = 0x8811,
2762 .subvendor = PCI_ANY_ID,
2763 .subdevice = PCI_ANY_ID,
2764 .init = pci_eg20t_init,
2765 .setup = pci_default_setup,
2766 },
2767 {
2768 .vendor = PCI_VENDOR_ID_INTEL,
2769 .device = 0x8812,
2770 .subvendor = PCI_ANY_ID,
2771 .subdevice = PCI_ANY_ID,
2772 .init = pci_eg20t_init,
2773 .setup = pci_default_setup,
2774 },
2775 {
2776 .vendor = PCI_VENDOR_ID_INTEL,
2777 .device = 0x8813,
2778 .subvendor = PCI_ANY_ID,
2779 .subdevice = PCI_ANY_ID,
2780 .init = pci_eg20t_init,
2781 .setup = pci_default_setup,
2782 },
2783 {
2784 .vendor = PCI_VENDOR_ID_INTEL,
2785 .device = 0x8814,
2786 .subvendor = PCI_ANY_ID,
2787 .subdevice = PCI_ANY_ID,
2788 .init = pci_eg20t_init,
2789 .setup = pci_default_setup,
2790 },
2791 {
2792 .vendor = 0x10DB,
2793 .device = 0x8027,
2794 .subvendor = PCI_ANY_ID,
2795 .subdevice = PCI_ANY_ID,
2796 .init = pci_eg20t_init,
2797 .setup = pci_default_setup,
2798 },
2799 {
2800 .vendor = 0x10DB,
2801 .device = 0x8028,
2802 .subvendor = PCI_ANY_ID,
2803 .subdevice = PCI_ANY_ID,
2804 .init = pci_eg20t_init,
2805 .setup = pci_default_setup,
2806 },
2807 {
2808 .vendor = 0x10DB,
2809 .device = 0x8029,
2810 .subvendor = PCI_ANY_ID,
2811 .subdevice = PCI_ANY_ID,
2812 .init = pci_eg20t_init,
2813 .setup = pci_default_setup,
2814 },
2815 {
2816 .vendor = 0x10DB,
2817 .device = 0x800C,
2818 .subvendor = PCI_ANY_ID,
2819 .subdevice = PCI_ANY_ID,
2820 .init = pci_eg20t_init,
2821 .setup = pci_default_setup,
2822 },
2823 {
2824 .vendor = 0x10DB,
2825 .device = 0x800D,
2826 .subvendor = PCI_ANY_ID,
2827 .subdevice = PCI_ANY_ID,
2828 .init = pci_eg20t_init,
2829 .setup = pci_default_setup,
2830 },
2831 /*
2832 * Cronyx Omega PCI (PLX-chip based)
2833 */
2834 {
2835 .vendor = PCI_VENDOR_ID_PLX,
2836 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2837 .subvendor = PCI_ANY_ID,
2838 .subdevice = PCI_ANY_ID,
2839 .setup = pci_omegapci_setup,
2840 },
2841 /* WCH CH353 1S1P card (16550 clone) */
2842 {
2843 .vendor = PCI_VENDOR_ID_WCHCN,
2844 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P,
2845 .subvendor = PCI_ANY_ID,
2846 .subdevice = PCI_ANY_ID,
2847 .setup = pci_wch_ch353_setup,
2848 },
2849 /* WCH CH353 2S1P card (16550 clone) */
2850 {
2851 .vendor = PCI_VENDOR_ID_WCHCN,
2852 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P,
2853 .subvendor = PCI_ANY_ID,
2854 .subdevice = PCI_ANY_ID,
2855 .setup = pci_wch_ch353_setup,
2856 },
2857 /* WCH CH353 4S card (16550 clone) */
2858 {
2859 .vendor = PCI_VENDOR_ID_WCHCN,
2860 .device = PCI_DEVICE_ID_WCHCN_CH353_4S,
2861 .subvendor = PCI_ANY_ID,
2862 .subdevice = PCI_ANY_ID,
2863 .setup = pci_wch_ch353_setup,
2864 },
2865 /* WCH CH353 2S1PF card (16550 clone) */
2866 {
2867 .vendor = PCI_VENDOR_ID_WCHCN,
2868 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
2869 .subvendor = PCI_ANY_ID,
2870 .subdevice = PCI_ANY_ID,
2871 .setup = pci_wch_ch353_setup,
2872 },
2873 /* WCH CH352 2S card (16550 clone) */
2874 {
2875 .vendor = PCI_VENDOR_ID_WCHCN,
2876 .device = PCI_DEVICE_ID_WCHCN_CH352_2S,
2877 .subvendor = PCI_ANY_ID,
2878 .subdevice = PCI_ANY_ID,
2879 .setup = pci_wch_ch353_setup,
2880 },
2881 /* WCH CH355 4S card (16550 clone) */
2882 {
2883 .vendor = PCI_VENDOR_ID_WCHCN,
2884 .device = PCI_DEVICE_ID_WCHCN_CH355_4S,
2885 .subvendor = PCI_ANY_ID,
2886 .subdevice = PCI_ANY_ID,
2887 .setup = pci_wch_ch355_setup,
2888 },
2889 /* WCH CH382 2S card (16850 clone) */
2890 {
2891 .vendor = PCI_VENDOR_ID_WCHIC,
2892 .device = PCI_DEVICE_ID_WCHIC_CH382_2S,
2893 .subvendor = PCI_ANY_ID,
2894 .subdevice = PCI_ANY_ID,
2895 .setup = pci_wch_ch38x_setup,
2896 },
2897 /* WCH CH382 2S1P card (16850 clone) */
2898 {
2899 .vendor = PCI_VENDOR_ID_WCHIC,
2900 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P,
2901 .subvendor = PCI_ANY_ID,
2902 .subdevice = PCI_ANY_ID,
2903 .setup = pci_wch_ch38x_setup,
2904 },
2905 /* WCH CH384 4S card (16850 clone) */
2906 {
2907 .vendor = PCI_VENDOR_ID_WCHIC,
2908 .device = PCI_DEVICE_ID_WCHIC_CH384_4S,
2909 .subvendor = PCI_ANY_ID,
2910 .subdevice = PCI_ANY_ID,
2911 .setup = pci_wch_ch38x_setup,
2912 },
2913 /* WCH CH384 8S card (16850 clone) */
2914 {
2915 .vendor = PCI_VENDOR_ID_WCHIC,
2916 .device = PCI_DEVICE_ID_WCHIC_CH384_8S,
2917 .subvendor = PCI_ANY_ID,
2918 .subdevice = PCI_ANY_ID,
2919 .init = pci_wch_ch38x_init,
2920 .exit = pci_wch_ch38x_exit,
2921 .setup = pci_wch_ch38x_setup,
2922 },
2923 /*
2924 * Broadcom TruManage (NetXtreme)
2925 */
2926 {
2927 .vendor = PCI_VENDOR_ID_BROADCOM,
2928 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2929 .subvendor = PCI_ANY_ID,
2930 .subdevice = PCI_ANY_ID,
2931 .setup = pci_brcm_trumanage_setup,
2932 },
2933 {
2934 .vendor = 0x1c29,
2935 .device = 0x1104,
2936 .subvendor = PCI_ANY_ID,
2937 .subdevice = PCI_ANY_ID,
2938 .setup = pci_fintek_setup,
2939 .init = pci_fintek_init,
2940 },
2941 {
2942 .vendor = 0x1c29,
2943 .device = 0x1108,
2944 .subvendor = PCI_ANY_ID,
2945 .subdevice = PCI_ANY_ID,
2946 .setup = pci_fintek_setup,
2947 .init = pci_fintek_init,
2948 },
2949 {
2950 .vendor = 0x1c29,
2951 .device = 0x1112,
2952 .subvendor = PCI_ANY_ID,
2953 .subdevice = PCI_ANY_ID,
2954 .setup = pci_fintek_setup,
2955 .init = pci_fintek_init,
2956 },
2957 /*
2958 * MOXA
2959 */
2960 {
2961 .vendor = PCI_VENDOR_ID_MOXA,
2962 .device = PCI_ANY_ID,
2963 .subvendor = PCI_ANY_ID,
2964 .subdevice = PCI_ANY_ID,
2965 .init = pci_moxa_init,
2966 .setup = pci_moxa_setup,
2967 },
2968 {
2969 .vendor = 0x1c29,
2970 .device = 0x1204,
2971 .subvendor = PCI_ANY_ID,
2972 .subdevice = PCI_ANY_ID,
2973 .setup = pci_fintek_f815xxa_setup,
2974 .init = pci_fintek_f815xxa_init,
2975 },
2976 {
2977 .vendor = 0x1c29,
2978 .device = 0x1208,
2979 .subvendor = PCI_ANY_ID,
2980 .subdevice = PCI_ANY_ID,
2981 .setup = pci_fintek_f815xxa_setup,
2982 .init = pci_fintek_f815xxa_init,
2983 },
2984 {
2985 .vendor = 0x1c29,
2986 .device = 0x1212,
2987 .subvendor = PCI_ANY_ID,
2988 .subdevice = PCI_ANY_ID,
2989 .setup = pci_fintek_f815xxa_setup,
2990 .init = pci_fintek_f815xxa_init,
2991 },
2992
2993 /*
2994 * Default "match everything" terminator entry
2995 */
2996 {
2997 .vendor = PCI_ANY_ID,
2998 .device = PCI_ANY_ID,
2999 .subvendor = PCI_ANY_ID,
3000 .subdevice = PCI_ANY_ID,
3001 .setup = pci_default_setup,
3002 }
3003 };
3004
quirk_id_matches(u32 quirk_id,u32 dev_id)3005 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
3006 {
3007 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
3008 }
3009
find_quirk(struct pci_dev * dev)3010 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
3011 {
3012 struct pci_serial_quirk *quirk;
3013
3014 for (quirk = pci_serial_quirks; ; quirk++)
3015 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
3016 quirk_id_matches(quirk->device, dev->device) &&
3017 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
3018 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
3019 break;
3020 return quirk;
3021 }
3022
3023 /*
3024 * This is the configuration table for all of the PCI serial boards
3025 * which we support. It is directly indexed by the pci_board_num_t enum
3026 * value, which is encoded in the pci_device_id PCI probe table's
3027 * driver_data member.
3028 *
3029 * The makeup of these names are:
3030 * pbn_bn{_bt}_n_baud{_offsetinhex}
3031 *
3032 * bn = PCI BAR number
3033 * bt = Index using PCI BARs
3034 * n = number of serial ports
3035 * baud = baud rate
3036 * offsetinhex = offset for each sequential port (in hex)
3037 *
3038 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
3039 *
3040 * Please note: in theory if n = 1, _bt infix should make no difference.
3041 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
3042 */
3043 enum pci_board_num_t {
3044 pbn_default = 0,
3045
3046 pbn_b0_1_115200,
3047 pbn_b0_2_115200,
3048 pbn_b0_4_115200,
3049 pbn_b0_5_115200,
3050 pbn_b0_8_115200,
3051
3052 pbn_b0_1_921600,
3053 pbn_b0_2_921600,
3054 pbn_b0_4_921600,
3055
3056 pbn_b0_2_1130000,
3057
3058 pbn_b0_4_1152000,
3059
3060 pbn_b0_4_1250000,
3061
3062 pbn_b0_2_1843200,
3063 pbn_b0_4_1843200,
3064
3065 pbn_b0_1_15625000,
3066
3067 pbn_b0_bt_1_115200,
3068 pbn_b0_bt_2_115200,
3069 pbn_b0_bt_4_115200,
3070 pbn_b0_bt_8_115200,
3071
3072 pbn_b0_bt_1_460800,
3073 pbn_b0_bt_2_460800,
3074 pbn_b0_bt_4_460800,
3075
3076 pbn_b0_bt_1_921600,
3077 pbn_b0_bt_2_921600,
3078 pbn_b0_bt_4_921600,
3079 pbn_b0_bt_8_921600,
3080
3081 pbn_b1_1_115200,
3082 pbn_b1_2_115200,
3083 pbn_b1_4_115200,
3084 pbn_b1_8_115200,
3085 pbn_b1_16_115200,
3086
3087 pbn_b1_1_921600,
3088 pbn_b1_2_921600,
3089 pbn_b1_4_921600,
3090 pbn_b1_8_921600,
3091
3092 pbn_b1_2_1250000,
3093
3094 pbn_b1_bt_1_115200,
3095 pbn_b1_bt_2_115200,
3096 pbn_b1_bt_4_115200,
3097
3098 pbn_b1_bt_2_921600,
3099
3100 pbn_b1_1_1382400,
3101 pbn_b1_2_1382400,
3102 pbn_b1_4_1382400,
3103 pbn_b1_8_1382400,
3104
3105 pbn_b2_1_115200,
3106 pbn_b2_2_115200,
3107 pbn_b2_4_115200,
3108 pbn_b2_8_115200,
3109
3110 pbn_b2_1_460800,
3111 pbn_b2_4_460800,
3112 pbn_b2_8_460800,
3113 pbn_b2_16_460800,
3114
3115 pbn_b2_1_921600,
3116 pbn_b2_4_921600,
3117 pbn_b2_8_921600,
3118
3119 pbn_b2_8_1152000,
3120
3121 pbn_b2_bt_1_115200,
3122 pbn_b2_bt_2_115200,
3123 pbn_b2_bt_4_115200,
3124
3125 pbn_b2_bt_2_921600,
3126 pbn_b2_bt_4_921600,
3127
3128 pbn_b3_2_115200,
3129 pbn_b3_4_115200,
3130 pbn_b3_8_115200,
3131
3132 pbn_b4_bt_2_921600,
3133 pbn_b4_bt_4_921600,
3134 pbn_b4_bt_8_921600,
3135
3136 /*
3137 * Board-specific versions.
3138 */
3139 pbn_panacom,
3140 pbn_panacom2,
3141 pbn_panacom4,
3142 pbn_plx_romulus,
3143 pbn_oxsemi,
3144 pbn_oxsemi_1_15625000,
3145 pbn_oxsemi_2_15625000,
3146 pbn_oxsemi_4_15625000,
3147 pbn_oxsemi_8_15625000,
3148 pbn_intel_i960,
3149 pbn_sgi_ioc3,
3150 pbn_computone_4,
3151 pbn_computone_6,
3152 pbn_computone_8,
3153 pbn_sbsxrsio,
3154 pbn_pasemi_1682M,
3155 pbn_ni8430_2,
3156 pbn_ni8430_4,
3157 pbn_ni8430_8,
3158 pbn_ni8430_16,
3159 pbn_ADDIDATA_PCIe_1_3906250,
3160 pbn_ADDIDATA_PCIe_2_3906250,
3161 pbn_ADDIDATA_PCIe_4_3906250,
3162 pbn_ADDIDATA_PCIe_8_3906250,
3163 pbn_ce4100_1_115200,
3164 pbn_omegapci,
3165 pbn_NETMOS9900_2s_115200,
3166 pbn_brcm_trumanage,
3167 pbn_fintek_4,
3168 pbn_fintek_8,
3169 pbn_fintek_12,
3170 pbn_fintek_F81504A,
3171 pbn_fintek_F81508A,
3172 pbn_fintek_F81512A,
3173 pbn_wch382_2,
3174 pbn_wch384_4,
3175 pbn_wch384_8,
3176 pbn_sunix_pci_1s,
3177 pbn_sunix_pci_2s,
3178 pbn_sunix_pci_4s,
3179 pbn_sunix_pci_8s,
3180 pbn_sunix_pci_16s,
3181 pbn_titan_1_4000000,
3182 pbn_titan_2_4000000,
3183 pbn_titan_4_4000000,
3184 pbn_titan_8_4000000,
3185 pbn_moxa_2,
3186 pbn_moxa_4,
3187 pbn_moxa_8,
3188 };
3189
3190 /*
3191 * uart_offset - the space between channels
3192 * reg_shift - describes how the UART registers are mapped
3193 * to PCI memory by the card.
3194 * For example IER register on SBS, Inc. PMC-OctPro is located at
3195 * offset 0x10 from the UART base, while UART_IER is defined as 1
3196 * in include/linux/serial_reg.h,
3197 * see first lines of serial_in() and serial_out() in 8250.c
3198 */
3199
3200 static struct pciserial_board pci_boards[] = {
3201 [pbn_default] = {
3202 .flags = FL_BASE0,
3203 .num_ports = 1,
3204 .base_baud = 115200,
3205 .uart_offset = 8,
3206 },
3207 [pbn_b0_1_115200] = {
3208 .flags = FL_BASE0,
3209 .num_ports = 1,
3210 .base_baud = 115200,
3211 .uart_offset = 8,
3212 },
3213 [pbn_b0_2_115200] = {
3214 .flags = FL_BASE0,
3215 .num_ports = 2,
3216 .base_baud = 115200,
3217 .uart_offset = 8,
3218 },
3219 [pbn_b0_4_115200] = {
3220 .flags = FL_BASE0,
3221 .num_ports = 4,
3222 .base_baud = 115200,
3223 .uart_offset = 8,
3224 },
3225 [pbn_b0_5_115200] = {
3226 .flags = FL_BASE0,
3227 .num_ports = 5,
3228 .base_baud = 115200,
3229 .uart_offset = 8,
3230 },
3231 [pbn_b0_8_115200] = {
3232 .flags = FL_BASE0,
3233 .num_ports = 8,
3234 .base_baud = 115200,
3235 .uart_offset = 8,
3236 },
3237 [pbn_b0_1_921600] = {
3238 .flags = FL_BASE0,
3239 .num_ports = 1,
3240 .base_baud = 921600,
3241 .uart_offset = 8,
3242 },
3243 [pbn_b0_2_921600] = {
3244 .flags = FL_BASE0,
3245 .num_ports = 2,
3246 .base_baud = 921600,
3247 .uart_offset = 8,
3248 },
3249 [pbn_b0_4_921600] = {
3250 .flags = FL_BASE0,
3251 .num_ports = 4,
3252 .base_baud = 921600,
3253 .uart_offset = 8,
3254 },
3255
3256 [pbn_b0_2_1130000] = {
3257 .flags = FL_BASE0,
3258 .num_ports = 2,
3259 .base_baud = 1130000,
3260 .uart_offset = 8,
3261 },
3262
3263 [pbn_b0_4_1152000] = {
3264 .flags = FL_BASE0,
3265 .num_ports = 4,
3266 .base_baud = 1152000,
3267 .uart_offset = 8,
3268 },
3269
3270 [pbn_b0_4_1250000] = {
3271 .flags = FL_BASE0,
3272 .num_ports = 4,
3273 .base_baud = 1250000,
3274 .uart_offset = 8,
3275 },
3276
3277 [pbn_b0_2_1843200] = {
3278 .flags = FL_BASE0,
3279 .num_ports = 2,
3280 .base_baud = 1843200,
3281 .uart_offset = 8,
3282 },
3283 [pbn_b0_4_1843200] = {
3284 .flags = FL_BASE0,
3285 .num_ports = 4,
3286 .base_baud = 1843200,
3287 .uart_offset = 8,
3288 },
3289
3290 [pbn_b0_1_15625000] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 1,
3293 .base_baud = 15625000,
3294 .uart_offset = 8,
3295 },
3296
3297 [pbn_b0_bt_1_115200] = {
3298 .flags = FL_BASE0|FL_BASE_BARS,
3299 .num_ports = 1,
3300 .base_baud = 115200,
3301 .uart_offset = 8,
3302 },
3303 [pbn_b0_bt_2_115200] = {
3304 .flags = FL_BASE0|FL_BASE_BARS,
3305 .num_ports = 2,
3306 .base_baud = 115200,
3307 .uart_offset = 8,
3308 },
3309 [pbn_b0_bt_4_115200] = {
3310 .flags = FL_BASE0|FL_BASE_BARS,
3311 .num_ports = 4,
3312 .base_baud = 115200,
3313 .uart_offset = 8,
3314 },
3315 [pbn_b0_bt_8_115200] = {
3316 .flags = FL_BASE0|FL_BASE_BARS,
3317 .num_ports = 8,
3318 .base_baud = 115200,
3319 .uart_offset = 8,
3320 },
3321
3322 [pbn_b0_bt_1_460800] = {
3323 .flags = FL_BASE0|FL_BASE_BARS,
3324 .num_ports = 1,
3325 .base_baud = 460800,
3326 .uart_offset = 8,
3327 },
3328 [pbn_b0_bt_2_460800] = {
3329 .flags = FL_BASE0|FL_BASE_BARS,
3330 .num_ports = 2,
3331 .base_baud = 460800,
3332 .uart_offset = 8,
3333 },
3334 [pbn_b0_bt_4_460800] = {
3335 .flags = FL_BASE0|FL_BASE_BARS,
3336 .num_ports = 4,
3337 .base_baud = 460800,
3338 .uart_offset = 8,
3339 },
3340
3341 [pbn_b0_bt_1_921600] = {
3342 .flags = FL_BASE0|FL_BASE_BARS,
3343 .num_ports = 1,
3344 .base_baud = 921600,
3345 .uart_offset = 8,
3346 },
3347 [pbn_b0_bt_2_921600] = {
3348 .flags = FL_BASE0|FL_BASE_BARS,
3349 .num_ports = 2,
3350 .base_baud = 921600,
3351 .uart_offset = 8,
3352 },
3353 [pbn_b0_bt_4_921600] = {
3354 .flags = FL_BASE0|FL_BASE_BARS,
3355 .num_ports = 4,
3356 .base_baud = 921600,
3357 .uart_offset = 8,
3358 },
3359 [pbn_b0_bt_8_921600] = {
3360 .flags = FL_BASE0|FL_BASE_BARS,
3361 .num_ports = 8,
3362 .base_baud = 921600,
3363 .uart_offset = 8,
3364 },
3365
3366 [pbn_b1_1_115200] = {
3367 .flags = FL_BASE1,
3368 .num_ports = 1,
3369 .base_baud = 115200,
3370 .uart_offset = 8,
3371 },
3372 [pbn_b1_2_115200] = {
3373 .flags = FL_BASE1,
3374 .num_ports = 2,
3375 .base_baud = 115200,
3376 .uart_offset = 8,
3377 },
3378 [pbn_b1_4_115200] = {
3379 .flags = FL_BASE1,
3380 .num_ports = 4,
3381 .base_baud = 115200,
3382 .uart_offset = 8,
3383 },
3384 [pbn_b1_8_115200] = {
3385 .flags = FL_BASE1,
3386 .num_ports = 8,
3387 .base_baud = 115200,
3388 .uart_offset = 8,
3389 },
3390 [pbn_b1_16_115200] = {
3391 .flags = FL_BASE1,
3392 .num_ports = 16,
3393 .base_baud = 115200,
3394 .uart_offset = 8,
3395 },
3396
3397 [pbn_b1_1_921600] = {
3398 .flags = FL_BASE1,
3399 .num_ports = 1,
3400 .base_baud = 921600,
3401 .uart_offset = 8,
3402 },
3403 [pbn_b1_2_921600] = {
3404 .flags = FL_BASE1,
3405 .num_ports = 2,
3406 .base_baud = 921600,
3407 .uart_offset = 8,
3408 },
3409 [pbn_b1_4_921600] = {
3410 .flags = FL_BASE1,
3411 .num_ports = 4,
3412 .base_baud = 921600,
3413 .uart_offset = 8,
3414 },
3415 [pbn_b1_8_921600] = {
3416 .flags = FL_BASE1,
3417 .num_ports = 8,
3418 .base_baud = 921600,
3419 .uart_offset = 8,
3420 },
3421 [pbn_b1_2_1250000] = {
3422 .flags = FL_BASE1,
3423 .num_ports = 2,
3424 .base_baud = 1250000,
3425 .uart_offset = 8,
3426 },
3427
3428 [pbn_b1_bt_1_115200] = {
3429 .flags = FL_BASE1|FL_BASE_BARS,
3430 .num_ports = 1,
3431 .base_baud = 115200,
3432 .uart_offset = 8,
3433 },
3434 [pbn_b1_bt_2_115200] = {
3435 .flags = FL_BASE1|FL_BASE_BARS,
3436 .num_ports = 2,
3437 .base_baud = 115200,
3438 .uart_offset = 8,
3439 },
3440 [pbn_b1_bt_4_115200] = {
3441 .flags = FL_BASE1|FL_BASE_BARS,
3442 .num_ports = 4,
3443 .base_baud = 115200,
3444 .uart_offset = 8,
3445 },
3446
3447 [pbn_b1_bt_2_921600] = {
3448 .flags = FL_BASE1|FL_BASE_BARS,
3449 .num_ports = 2,
3450 .base_baud = 921600,
3451 .uart_offset = 8,
3452 },
3453
3454 [pbn_b1_1_1382400] = {
3455 .flags = FL_BASE1,
3456 .num_ports = 1,
3457 .base_baud = 1382400,
3458 .uart_offset = 8,
3459 },
3460 [pbn_b1_2_1382400] = {
3461 .flags = FL_BASE1,
3462 .num_ports = 2,
3463 .base_baud = 1382400,
3464 .uart_offset = 8,
3465 },
3466 [pbn_b1_4_1382400] = {
3467 .flags = FL_BASE1,
3468 .num_ports = 4,
3469 .base_baud = 1382400,
3470 .uart_offset = 8,
3471 },
3472 [pbn_b1_8_1382400] = {
3473 .flags = FL_BASE1,
3474 .num_ports = 8,
3475 .base_baud = 1382400,
3476 .uart_offset = 8,
3477 },
3478
3479 [pbn_b2_1_115200] = {
3480 .flags = FL_BASE2,
3481 .num_ports = 1,
3482 .base_baud = 115200,
3483 .uart_offset = 8,
3484 },
3485 [pbn_b2_2_115200] = {
3486 .flags = FL_BASE2,
3487 .num_ports = 2,
3488 .base_baud = 115200,
3489 .uart_offset = 8,
3490 },
3491 [pbn_b2_4_115200] = {
3492 .flags = FL_BASE2,
3493 .num_ports = 4,
3494 .base_baud = 115200,
3495 .uart_offset = 8,
3496 },
3497 [pbn_b2_8_115200] = {
3498 .flags = FL_BASE2,
3499 .num_ports = 8,
3500 .base_baud = 115200,
3501 .uart_offset = 8,
3502 },
3503
3504 [pbn_b2_1_460800] = {
3505 .flags = FL_BASE2,
3506 .num_ports = 1,
3507 .base_baud = 460800,
3508 .uart_offset = 8,
3509 },
3510 [pbn_b2_4_460800] = {
3511 .flags = FL_BASE2,
3512 .num_ports = 4,
3513 .base_baud = 460800,
3514 .uart_offset = 8,
3515 },
3516 [pbn_b2_8_460800] = {
3517 .flags = FL_BASE2,
3518 .num_ports = 8,
3519 .base_baud = 460800,
3520 .uart_offset = 8,
3521 },
3522 [pbn_b2_16_460800] = {
3523 .flags = FL_BASE2,
3524 .num_ports = 16,
3525 .base_baud = 460800,
3526 .uart_offset = 8,
3527 },
3528
3529 [pbn_b2_1_921600] = {
3530 .flags = FL_BASE2,
3531 .num_ports = 1,
3532 .base_baud = 921600,
3533 .uart_offset = 8,
3534 },
3535 [pbn_b2_4_921600] = {
3536 .flags = FL_BASE2,
3537 .num_ports = 4,
3538 .base_baud = 921600,
3539 .uart_offset = 8,
3540 },
3541 [pbn_b2_8_921600] = {
3542 .flags = FL_BASE2,
3543 .num_ports = 8,
3544 .base_baud = 921600,
3545 .uart_offset = 8,
3546 },
3547
3548 [pbn_b2_8_1152000] = {
3549 .flags = FL_BASE2,
3550 .num_ports = 8,
3551 .base_baud = 1152000,
3552 .uart_offset = 8,
3553 },
3554
3555 [pbn_b2_bt_1_115200] = {
3556 .flags = FL_BASE2|FL_BASE_BARS,
3557 .num_ports = 1,
3558 .base_baud = 115200,
3559 .uart_offset = 8,
3560 },
3561 [pbn_b2_bt_2_115200] = {
3562 .flags = FL_BASE2|FL_BASE_BARS,
3563 .num_ports = 2,
3564 .base_baud = 115200,
3565 .uart_offset = 8,
3566 },
3567 [pbn_b2_bt_4_115200] = {
3568 .flags = FL_BASE2|FL_BASE_BARS,
3569 .num_ports = 4,
3570 .base_baud = 115200,
3571 .uart_offset = 8,
3572 },
3573
3574 [pbn_b2_bt_2_921600] = {
3575 .flags = FL_BASE2|FL_BASE_BARS,
3576 .num_ports = 2,
3577 .base_baud = 921600,
3578 .uart_offset = 8,
3579 },
3580 [pbn_b2_bt_4_921600] = {
3581 .flags = FL_BASE2|FL_BASE_BARS,
3582 .num_ports = 4,
3583 .base_baud = 921600,
3584 .uart_offset = 8,
3585 },
3586
3587 [pbn_b3_2_115200] = {
3588 .flags = FL_BASE3,
3589 .num_ports = 2,
3590 .base_baud = 115200,
3591 .uart_offset = 8,
3592 },
3593 [pbn_b3_4_115200] = {
3594 .flags = FL_BASE3,
3595 .num_ports = 4,
3596 .base_baud = 115200,
3597 .uart_offset = 8,
3598 },
3599 [pbn_b3_8_115200] = {
3600 .flags = FL_BASE3,
3601 .num_ports = 8,
3602 .base_baud = 115200,
3603 .uart_offset = 8,
3604 },
3605
3606 [pbn_b4_bt_2_921600] = {
3607 .flags = FL_BASE4,
3608 .num_ports = 2,
3609 .base_baud = 921600,
3610 .uart_offset = 8,
3611 },
3612 [pbn_b4_bt_4_921600] = {
3613 .flags = FL_BASE4,
3614 .num_ports = 4,
3615 .base_baud = 921600,
3616 .uart_offset = 8,
3617 },
3618 [pbn_b4_bt_8_921600] = {
3619 .flags = FL_BASE4,
3620 .num_ports = 8,
3621 .base_baud = 921600,
3622 .uart_offset = 8,
3623 },
3624
3625 /*
3626 * Entries following this are board-specific.
3627 */
3628
3629 /*
3630 * Panacom - IOMEM
3631 */
3632 [pbn_panacom] = {
3633 .flags = FL_BASE2,
3634 .num_ports = 2,
3635 .base_baud = 921600,
3636 .uart_offset = 0x400,
3637 .reg_shift = 7,
3638 },
3639 [pbn_panacom2] = {
3640 .flags = FL_BASE2|FL_BASE_BARS,
3641 .num_ports = 2,
3642 .base_baud = 921600,
3643 .uart_offset = 0x400,
3644 .reg_shift = 7,
3645 },
3646 [pbn_panacom4] = {
3647 .flags = FL_BASE2|FL_BASE_BARS,
3648 .num_ports = 4,
3649 .base_baud = 921600,
3650 .uart_offset = 0x400,
3651 .reg_shift = 7,
3652 },
3653
3654 /* I think this entry is broken - the first_offset looks wrong --rmk */
3655 [pbn_plx_romulus] = {
3656 .flags = FL_BASE2,
3657 .num_ports = 4,
3658 .base_baud = 921600,
3659 .uart_offset = 8 << 2,
3660 .reg_shift = 2,
3661 .first_offset = 0x03,
3662 },
3663
3664 /*
3665 * This board uses the size of PCI Base region 0 to
3666 * signal now many ports are available
3667 */
3668 [pbn_oxsemi] = {
3669 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3670 .num_ports = 32,
3671 .base_baud = 115200,
3672 .uart_offset = 8,
3673 },
3674 [pbn_oxsemi_1_15625000] = {
3675 .flags = FL_BASE0,
3676 .num_ports = 1,
3677 .base_baud = 15625000,
3678 .uart_offset = 0x200,
3679 .first_offset = 0x1000,
3680 },
3681 [pbn_oxsemi_2_15625000] = {
3682 .flags = FL_BASE0,
3683 .num_ports = 2,
3684 .base_baud = 15625000,
3685 .uart_offset = 0x200,
3686 .first_offset = 0x1000,
3687 },
3688 [pbn_oxsemi_4_15625000] = {
3689 .flags = FL_BASE0,
3690 .num_ports = 4,
3691 .base_baud = 15625000,
3692 .uart_offset = 0x200,
3693 .first_offset = 0x1000,
3694 },
3695 [pbn_oxsemi_8_15625000] = {
3696 .flags = FL_BASE0,
3697 .num_ports = 8,
3698 .base_baud = 15625000,
3699 .uart_offset = 0x200,
3700 .first_offset = 0x1000,
3701 },
3702
3703
3704 /*
3705 * EKF addition for i960 Boards form EKF with serial port.
3706 * Max 256 ports.
3707 */
3708 [pbn_intel_i960] = {
3709 .flags = FL_BASE0,
3710 .num_ports = 32,
3711 .base_baud = 921600,
3712 .uart_offset = 8 << 2,
3713 .reg_shift = 2,
3714 .first_offset = 0x10000,
3715 },
3716 [pbn_sgi_ioc3] = {
3717 .flags = FL_BASE0|FL_NOIRQ,
3718 .num_ports = 1,
3719 .base_baud = 458333,
3720 .uart_offset = 8,
3721 .reg_shift = 0,
3722 .first_offset = 0x20178,
3723 },
3724
3725 /*
3726 * Computone - uses IOMEM.
3727 */
3728 [pbn_computone_4] = {
3729 .flags = FL_BASE0,
3730 .num_ports = 4,
3731 .base_baud = 921600,
3732 .uart_offset = 0x40,
3733 .reg_shift = 2,
3734 .first_offset = 0x200,
3735 },
3736 [pbn_computone_6] = {
3737 .flags = FL_BASE0,
3738 .num_ports = 6,
3739 .base_baud = 921600,
3740 .uart_offset = 0x40,
3741 .reg_shift = 2,
3742 .first_offset = 0x200,
3743 },
3744 [pbn_computone_8] = {
3745 .flags = FL_BASE0,
3746 .num_ports = 8,
3747 .base_baud = 921600,
3748 .uart_offset = 0x40,
3749 .reg_shift = 2,
3750 .first_offset = 0x200,
3751 },
3752 [pbn_sbsxrsio] = {
3753 .flags = FL_BASE0,
3754 .num_ports = 8,
3755 .base_baud = 460800,
3756 .uart_offset = 256,
3757 .reg_shift = 4,
3758 },
3759 /*
3760 * PA Semi PWRficient PA6T-1682M on-chip UART
3761 */
3762 [pbn_pasemi_1682M] = {
3763 .flags = FL_BASE0,
3764 .num_ports = 1,
3765 .base_baud = 8333333,
3766 },
3767 /*
3768 * National Instruments 843x
3769 */
3770 [pbn_ni8430_16] = {
3771 .flags = FL_BASE0,
3772 .num_ports = 16,
3773 .base_baud = 3686400,
3774 .uart_offset = 0x10,
3775 .first_offset = 0x800,
3776 },
3777 [pbn_ni8430_8] = {
3778 .flags = FL_BASE0,
3779 .num_ports = 8,
3780 .base_baud = 3686400,
3781 .uart_offset = 0x10,
3782 .first_offset = 0x800,
3783 },
3784 [pbn_ni8430_4] = {
3785 .flags = FL_BASE0,
3786 .num_ports = 4,
3787 .base_baud = 3686400,
3788 .uart_offset = 0x10,
3789 .first_offset = 0x800,
3790 },
3791 [pbn_ni8430_2] = {
3792 .flags = FL_BASE0,
3793 .num_ports = 2,
3794 .base_baud = 3686400,
3795 .uart_offset = 0x10,
3796 .first_offset = 0x800,
3797 },
3798 /*
3799 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3800 */
3801 [pbn_ADDIDATA_PCIe_1_3906250] = {
3802 .flags = FL_BASE0,
3803 .num_ports = 1,
3804 .base_baud = 3906250,
3805 .uart_offset = 0x200,
3806 .first_offset = 0x1000,
3807 },
3808 [pbn_ADDIDATA_PCIe_2_3906250] = {
3809 .flags = FL_BASE0,
3810 .num_ports = 2,
3811 .base_baud = 3906250,
3812 .uart_offset = 0x200,
3813 .first_offset = 0x1000,
3814 },
3815 [pbn_ADDIDATA_PCIe_4_3906250] = {
3816 .flags = FL_BASE0,
3817 .num_ports = 4,
3818 .base_baud = 3906250,
3819 .uart_offset = 0x200,
3820 .first_offset = 0x1000,
3821 },
3822 [pbn_ADDIDATA_PCIe_8_3906250] = {
3823 .flags = FL_BASE0,
3824 .num_ports = 8,
3825 .base_baud = 3906250,
3826 .uart_offset = 0x200,
3827 .first_offset = 0x1000,
3828 },
3829 [pbn_ce4100_1_115200] = {
3830 .flags = FL_BASE_BARS,
3831 .num_ports = 2,
3832 .base_baud = 921600,
3833 .reg_shift = 2,
3834 },
3835 [pbn_omegapci] = {
3836 .flags = FL_BASE0,
3837 .num_ports = 8,
3838 .base_baud = 115200,
3839 .uart_offset = 0x200,
3840 },
3841 [pbn_NETMOS9900_2s_115200] = {
3842 .flags = FL_BASE0,
3843 .num_ports = 2,
3844 .base_baud = 115200,
3845 },
3846 [pbn_brcm_trumanage] = {
3847 .flags = FL_BASE0,
3848 .num_ports = 1,
3849 .reg_shift = 2,
3850 .base_baud = 115200,
3851 },
3852 [pbn_fintek_4] = {
3853 .num_ports = 4,
3854 .uart_offset = 8,
3855 .base_baud = 115200,
3856 .first_offset = 0x40,
3857 },
3858 [pbn_fintek_8] = {
3859 .num_ports = 8,
3860 .uart_offset = 8,
3861 .base_baud = 115200,
3862 .first_offset = 0x40,
3863 },
3864 [pbn_fintek_12] = {
3865 .num_ports = 12,
3866 .uart_offset = 8,
3867 .base_baud = 115200,
3868 .first_offset = 0x40,
3869 },
3870 [pbn_fintek_F81504A] = {
3871 .num_ports = 4,
3872 .uart_offset = 8,
3873 .base_baud = 115200,
3874 },
3875 [pbn_fintek_F81508A] = {
3876 .num_ports = 8,
3877 .uart_offset = 8,
3878 .base_baud = 115200,
3879 },
3880 [pbn_fintek_F81512A] = {
3881 .num_ports = 12,
3882 .uart_offset = 8,
3883 .base_baud = 115200,
3884 },
3885 [pbn_wch382_2] = {
3886 .flags = FL_BASE0,
3887 .num_ports = 2,
3888 .base_baud = 115200,
3889 .uart_offset = 8,
3890 .first_offset = 0xC0,
3891 },
3892 [pbn_wch384_4] = {
3893 .flags = FL_BASE0,
3894 .num_ports = 4,
3895 .base_baud = 115200,
3896 .uart_offset = 8,
3897 .first_offset = 0xC0,
3898 },
3899 [pbn_wch384_8] = {
3900 .flags = FL_BASE0,
3901 .num_ports = 8,
3902 .base_baud = 115200,
3903 .uart_offset = 8,
3904 .first_offset = 0x00,
3905 },
3906 [pbn_sunix_pci_1s] = {
3907 .num_ports = 1,
3908 .base_baud = 921600,
3909 .uart_offset = 0x8,
3910 },
3911 [pbn_sunix_pci_2s] = {
3912 .num_ports = 2,
3913 .base_baud = 921600,
3914 .uart_offset = 0x8,
3915 },
3916 [pbn_sunix_pci_4s] = {
3917 .num_ports = 4,
3918 .base_baud = 921600,
3919 .uart_offset = 0x8,
3920 },
3921 [pbn_sunix_pci_8s] = {
3922 .num_ports = 8,
3923 .base_baud = 921600,
3924 .uart_offset = 0x8,
3925 },
3926 [pbn_sunix_pci_16s] = {
3927 .num_ports = 16,
3928 .base_baud = 921600,
3929 .uart_offset = 0x8,
3930 },
3931 [pbn_titan_1_4000000] = {
3932 .flags = FL_BASE0,
3933 .num_ports = 1,
3934 .base_baud = 4000000,
3935 .uart_offset = 0x200,
3936 .first_offset = 0x1000,
3937 },
3938 [pbn_titan_2_4000000] = {
3939 .flags = FL_BASE0,
3940 .num_ports = 2,
3941 .base_baud = 4000000,
3942 .uart_offset = 0x200,
3943 .first_offset = 0x1000,
3944 },
3945 [pbn_titan_4_4000000] = {
3946 .flags = FL_BASE0,
3947 .num_ports = 4,
3948 .base_baud = 4000000,
3949 .uart_offset = 0x200,
3950 .first_offset = 0x1000,
3951 },
3952 [pbn_titan_8_4000000] = {
3953 .flags = FL_BASE0,
3954 .num_ports = 8,
3955 .base_baud = 4000000,
3956 .uart_offset = 0x200,
3957 .first_offset = 0x1000,
3958 },
3959 [pbn_moxa_2] = {
3960 .flags = FL_BASE1,
3961 .num_ports = 2,
3962 .base_baud = 921600,
3963 .uart_offset = 0x200,
3964 },
3965 [pbn_moxa_4] = {
3966 .flags = FL_BASE1,
3967 .num_ports = 4,
3968 .base_baud = 921600,
3969 .uart_offset = 0x200,
3970 },
3971 [pbn_moxa_8] = {
3972 .flags = FL_BASE1,
3973 .num_ports = 8,
3974 .base_baud = 921600,
3975 .uart_offset = 0x200,
3976 },
3977 };
3978
3979 #define REPORT_CONFIG(option) \
3980 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3981 #define REPORT_8250_CONFIG(option) \
3982 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3983 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3984
3985 static const struct pci_device_id blacklist[] = {
3986 /* softmodems */
3987 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3988 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3989 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3990
3991 /* multi-io cards handled by parport_serial */
3992 /* WCH CH353 2S1P */
3993 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3994 /* WCH CH353 1S1P */
3995 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3996 /* WCH CH382 2S1P */
3997 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
3998
3999 /* Intel platforms with MID UART */
4000 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
4001 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
4002 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
4003 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
4004 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
4005 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
4006
4007 /* Intel platforms with DesignWare UART */
4008 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
4009 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
4010 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
4011 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
4012 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4013 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4014 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4015 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4016 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4017 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4018 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4019 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4020 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4021
4022 /* Exar devices */
4023 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4024 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4025
4026 /* Pericom devices */
4027 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4028 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4029
4030 /* End of the black list */
4031 { }
4032 };
4033
serial_pci_is_class_communication(struct pci_dev * dev)4034 static int serial_pci_is_class_communication(struct pci_dev *dev)
4035 {
4036 /*
4037 * If it is not a communications device or the programming
4038 * interface is greater than 6, give up.
4039 */
4040 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4041 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4042 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4043 (dev->class & 0xff) > 6)
4044 return -ENODEV;
4045
4046 return 0;
4047 }
4048
4049 /*
4050 * Given a complete unknown PCI device, try to use some heuristics to
4051 * guess what the configuration might be, based on the pitiful PCI
4052 * serial specs. Returns 0 on success, -ENODEV on failure.
4053 */
4054 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4055 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4056 {
4057 int num_iomem, num_port, first_port = -1, i;
4058 int rc;
4059
4060 rc = serial_pci_is_class_communication(dev);
4061 if (rc)
4062 return rc;
4063
4064 /*
4065 * Should we try to make guesses for multiport serial devices later?
4066 */
4067 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4068 return -ENODEV;
4069
4070 num_iomem = num_port = 0;
4071 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4072 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4073 num_port++;
4074 if (first_port == -1)
4075 first_port = i;
4076 }
4077 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4078 num_iomem++;
4079 }
4080
4081 /*
4082 * If there is 1 or 0 iomem regions, and exactly one port,
4083 * use it. We guess the number of ports based on the IO
4084 * region size.
4085 */
4086 if (num_iomem <= 1 && num_port == 1) {
4087 board->flags = first_port;
4088 board->num_ports = pci_resource_len(dev, first_port) / 8;
4089 return 0;
4090 }
4091
4092 /*
4093 * Now guess if we've got a board which indexes by BARs.
4094 * Each IO BAR should be 8 bytes, and they should follow
4095 * consecutively.
4096 */
4097 first_port = -1;
4098 num_port = 0;
4099 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4100 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4101 pci_resource_len(dev, i) == 8 &&
4102 (first_port == -1 || (first_port + num_port) == i)) {
4103 num_port++;
4104 if (first_port == -1)
4105 first_port = i;
4106 }
4107 }
4108
4109 if (num_port > 1) {
4110 board->flags = first_port | FL_BASE_BARS;
4111 board->num_ports = num_port;
4112 return 0;
4113 }
4114
4115 return -ENODEV;
4116 }
4117
4118 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4119 serial_pci_matches(const struct pciserial_board *board,
4120 const struct pciserial_board *guessed)
4121 {
4122 return
4123 board->num_ports == guessed->num_ports &&
4124 board->base_baud == guessed->base_baud &&
4125 board->uart_offset == guessed->uart_offset &&
4126 board->reg_shift == guessed->reg_shift &&
4127 board->first_offset == guessed->first_offset;
4128 }
4129
4130 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4131 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4132 {
4133 struct uart_8250_port uart;
4134 struct serial_private *priv;
4135 struct pci_serial_quirk *quirk;
4136 int rc, nr_ports, i;
4137
4138 nr_ports = board->num_ports;
4139
4140 /*
4141 * Find an init and setup quirks.
4142 */
4143 quirk = find_quirk(dev);
4144
4145 /*
4146 * Run the new-style initialization function.
4147 * The initialization function returns:
4148 * <0 - error
4149 * 0 - use board->num_ports
4150 * >0 - number of ports
4151 */
4152 if (quirk->init) {
4153 rc = quirk->init(dev);
4154 if (rc < 0) {
4155 priv = ERR_PTR(rc);
4156 goto err_out;
4157 }
4158 if (rc)
4159 nr_ports = rc;
4160 }
4161
4162 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
4163 if (!priv) {
4164 priv = ERR_PTR(-ENOMEM);
4165 goto err_deinit;
4166 }
4167
4168 priv->dev = dev;
4169 priv->quirk = quirk;
4170
4171 memset(&uart, 0, sizeof(uart));
4172 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4173 uart.port.uartclk = board->base_baud * 16;
4174
4175 if (board->flags & FL_NOIRQ) {
4176 uart.port.irq = 0;
4177 } else {
4178 if (pci_match_id(pci_use_msi, dev)) {
4179 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4180 pci_set_master(dev);
4181 uart.port.flags &= ~UPF_SHARE_IRQ;
4182 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4183 } else {
4184 pci_dbg(dev, "Using legacy interrupts\n");
4185 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4186 }
4187 if (rc < 0) {
4188 kfree(priv);
4189 priv = ERR_PTR(rc);
4190 goto err_deinit;
4191 }
4192
4193 uart.port.irq = pci_irq_vector(dev, 0);
4194 }
4195
4196 uart.port.dev = &dev->dev;
4197
4198 for (i = 0; i < nr_ports; i++) {
4199 if (quirk->setup(priv, board, &uart, i))
4200 break;
4201
4202 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4203 uart.port.iobase, uart.port.irq, uart.port.iotype);
4204
4205 priv->line[i] = serial8250_register_8250_port(&uart);
4206 if (priv->line[i] < 0) {
4207 pci_err(dev,
4208 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4209 uart.port.iobase, uart.port.irq,
4210 uart.port.iotype, priv->line[i]);
4211 break;
4212 }
4213 }
4214 priv->nr = i;
4215 priv->board = board;
4216 return priv;
4217
4218 err_deinit:
4219 if (quirk->exit)
4220 quirk->exit(dev);
4221 err_out:
4222 return priv;
4223 }
4224 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4225
pciserial_detach_ports(struct serial_private * priv)4226 static void pciserial_detach_ports(struct serial_private *priv)
4227 {
4228 struct pci_serial_quirk *quirk;
4229 int i;
4230
4231 for (i = 0; i < priv->nr; i++)
4232 serial8250_unregister_port(priv->line[i]);
4233
4234 /*
4235 * Find the exit quirks.
4236 */
4237 quirk = find_quirk(priv->dev);
4238 if (quirk->exit)
4239 quirk->exit(priv->dev);
4240 }
4241
pciserial_remove_ports(struct serial_private * priv)4242 void pciserial_remove_ports(struct serial_private *priv)
4243 {
4244 pciserial_detach_ports(priv);
4245 kfree(priv);
4246 }
4247 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4248
pciserial_suspend_ports(struct serial_private * priv)4249 void pciserial_suspend_ports(struct serial_private *priv)
4250 {
4251 int i;
4252
4253 for (i = 0; i < priv->nr; i++)
4254 if (priv->line[i] >= 0)
4255 serial8250_suspend_port(priv->line[i]);
4256
4257 /*
4258 * Ensure that every init quirk is properly torn down
4259 */
4260 if (priv->quirk->exit)
4261 priv->quirk->exit(priv->dev);
4262 }
4263 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4264
pciserial_resume_ports(struct serial_private * priv)4265 void pciserial_resume_ports(struct serial_private *priv)
4266 {
4267 int i;
4268
4269 /*
4270 * Ensure that the board is correctly configured.
4271 */
4272 if (priv->quirk->init)
4273 priv->quirk->init(priv->dev);
4274
4275 for (i = 0; i < priv->nr; i++)
4276 if (priv->line[i] >= 0)
4277 serial8250_resume_port(priv->line[i]);
4278 }
4279 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4280
4281 /*
4282 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4283 * to the arrangement of serial ports on a PCI card.
4284 */
4285 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4286 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4287 {
4288 struct pci_serial_quirk *quirk;
4289 struct serial_private *priv;
4290 const struct pciserial_board *board;
4291 const struct pci_device_id *exclude;
4292 struct pciserial_board tmp;
4293 int rc;
4294
4295 quirk = find_quirk(dev);
4296 if (quirk->probe) {
4297 rc = quirk->probe(dev);
4298 if (rc)
4299 return rc;
4300 }
4301
4302 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4303 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4304 return -EINVAL;
4305 }
4306
4307 board = &pci_boards[ent->driver_data];
4308
4309 exclude = pci_match_id(blacklist, dev);
4310 if (exclude) {
4311 if (exclude->driver_data)
4312 pci_warn(dev, "ignoring port, enable %s to handle\n",
4313 (const char *)exclude->driver_data);
4314 return -ENODEV;
4315 }
4316
4317 rc = pcim_enable_device(dev);
4318 pci_save_state(dev);
4319 if (rc)
4320 return rc;
4321
4322 if (ent->driver_data == pbn_default) {
4323 /*
4324 * Use a copy of the pci_board entry for this;
4325 * avoid changing entries in the table.
4326 */
4327 memcpy(&tmp, board, sizeof(struct pciserial_board));
4328 board = &tmp;
4329
4330 /*
4331 * We matched one of our class entries. Try to
4332 * determine the parameters of this board.
4333 */
4334 rc = serial_pci_guess_board(dev, &tmp);
4335 if (rc)
4336 return rc;
4337 } else {
4338 /*
4339 * We matched an explicit entry. If we are able to
4340 * detect this boards settings with our heuristic,
4341 * then we no longer need this entry.
4342 */
4343 memcpy(&tmp, &pci_boards[pbn_default],
4344 sizeof(struct pciserial_board));
4345 rc = serial_pci_guess_board(dev, &tmp);
4346 if (rc == 0 && serial_pci_matches(board, &tmp))
4347 moan_device("Redundant entry in serial pci_table.",
4348 dev);
4349 }
4350
4351 priv = pciserial_init_ports(dev, board);
4352 if (IS_ERR(priv))
4353 return PTR_ERR(priv);
4354
4355 pci_set_drvdata(dev, priv);
4356 return 0;
4357 }
4358
pciserial_remove_one(struct pci_dev * dev)4359 static void pciserial_remove_one(struct pci_dev *dev)
4360 {
4361 struct serial_private *priv = pci_get_drvdata(dev);
4362
4363 pciserial_remove_ports(priv);
4364 }
4365
4366 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4367 static int pciserial_suspend_one(struct device *dev)
4368 {
4369 struct serial_private *priv = dev_get_drvdata(dev);
4370
4371 if (priv)
4372 pciserial_suspend_ports(priv);
4373
4374 return 0;
4375 }
4376
pciserial_resume_one(struct device * dev)4377 static int pciserial_resume_one(struct device *dev)
4378 {
4379 struct pci_dev *pdev = to_pci_dev(dev);
4380 struct serial_private *priv = pci_get_drvdata(pdev);
4381 int err;
4382
4383 if (priv) {
4384 /*
4385 * The device may have been disabled. Re-enable it.
4386 */
4387 err = pci_enable_device(pdev);
4388 /* FIXME: We cannot simply error out here */
4389 if (err)
4390 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4391 pciserial_resume_ports(priv);
4392 }
4393 return 0;
4394 }
4395 #endif
4396
4397 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4398 pciserial_resume_one);
4399
4400 static const struct pci_device_id serial_pci_tbl[] = {
4401 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4402 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4403 pbn_b0_4_921600 },
4404 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4405 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4406 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4407 pbn_b2_8_921600 },
4408 /* Advantech also use 0x3618 and 0xf618 */
4409 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4410 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4411 pbn_b0_4_921600 },
4412 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4413 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4414 pbn_b0_4_921600 },
4415 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4416 PCI_SUBVENDOR_ID_CONNECT_TECH,
4417 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4418 pbn_b1_8_1382400 },
4419 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4420 PCI_SUBVENDOR_ID_CONNECT_TECH,
4421 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4422 pbn_b1_4_1382400 },
4423 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4424 PCI_SUBVENDOR_ID_CONNECT_TECH,
4425 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4426 pbn_b1_2_1382400 },
4427 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4428 PCI_SUBVENDOR_ID_CONNECT_TECH,
4429 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4430 pbn_b1_8_1382400 },
4431 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4432 PCI_SUBVENDOR_ID_CONNECT_TECH,
4433 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4434 pbn_b1_4_1382400 },
4435 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4436 PCI_SUBVENDOR_ID_CONNECT_TECH,
4437 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4438 pbn_b1_2_1382400 },
4439 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4440 PCI_SUBVENDOR_ID_CONNECT_TECH,
4441 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4442 pbn_b1_8_921600 },
4443 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4444 PCI_SUBVENDOR_ID_CONNECT_TECH,
4445 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4446 pbn_b1_8_921600 },
4447 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4448 PCI_SUBVENDOR_ID_CONNECT_TECH,
4449 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4450 pbn_b1_4_921600 },
4451 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4452 PCI_SUBVENDOR_ID_CONNECT_TECH,
4453 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4454 pbn_b1_4_921600 },
4455 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4456 PCI_SUBVENDOR_ID_CONNECT_TECH,
4457 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4458 pbn_b1_2_921600 },
4459 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4460 PCI_SUBVENDOR_ID_CONNECT_TECH,
4461 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4462 pbn_b1_8_921600 },
4463 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4464 PCI_SUBVENDOR_ID_CONNECT_TECH,
4465 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4466 pbn_b1_8_921600 },
4467 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4468 PCI_SUBVENDOR_ID_CONNECT_TECH,
4469 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4470 pbn_b1_4_921600 },
4471 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4472 PCI_SUBVENDOR_ID_CONNECT_TECH,
4473 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4474 pbn_b1_2_1250000 },
4475 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4476 PCI_SUBVENDOR_ID_CONNECT_TECH,
4477 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4478 pbn_b0_2_1843200 },
4479 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4480 PCI_SUBVENDOR_ID_CONNECT_TECH,
4481 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4482 pbn_b0_4_1843200 },
4483 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4484 PCI_VENDOR_ID_AFAVLAB,
4485 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4486 pbn_b0_4_1152000 },
4487 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b2_bt_1_115200 },
4490 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_b2_bt_2_115200 },
4493 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 pbn_b2_bt_4_115200 },
4496 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 pbn_b2_bt_2_115200 },
4499 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 pbn_b2_bt_4_115200 },
4502 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b2_8_115200 },
4505 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b2_8_460800 },
4508 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b2_8_115200 },
4511
4512 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b2_bt_2_115200 },
4515 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_b2_bt_2_921600 },
4518 /*
4519 * VScom SPCOM800, from sl@s.pl
4520 */
4521 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_b2_8_921600 },
4524 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_b2_4_921600 },
4527 /* Unknown card - subdevice 0x1584 */
4528 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4529 PCI_VENDOR_ID_PLX,
4530 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4531 pbn_b2_4_115200 },
4532 /* Unknown card - subdevice 0x1588 */
4533 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4534 PCI_VENDOR_ID_PLX,
4535 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4536 pbn_b2_8_115200 },
4537 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4538 PCI_SUBVENDOR_ID_KEYSPAN,
4539 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4540 pbn_panacom },
4541 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543 pbn_panacom4 },
4544 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 pbn_panacom2 },
4547 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4548 PCI_VENDOR_ID_ESDGMBH,
4549 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4550 pbn_b2_4_115200 },
4551 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4552 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4553 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4554 pbn_b2_4_460800 },
4555 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4556 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4557 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4558 pbn_b2_8_460800 },
4559 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4560 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4561 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4562 pbn_b2_16_460800 },
4563 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4564 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4565 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4566 pbn_b2_16_460800 },
4567 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4568 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4569 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4570 pbn_b2_4_460800 },
4571 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4572 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4573 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4574 pbn_b2_8_460800 },
4575 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4576 PCI_SUBVENDOR_ID_EXSYS,
4577 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4578 pbn_b2_4_115200 },
4579 /*
4580 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4581 * (Exoray@isys.ca)
4582 */
4583 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4584 0x10b5, 0x106a, 0, 0,
4585 pbn_plx_romulus },
4586 /*
4587 * Quatech cards. These actually have configurable clocks but for
4588 * now we just use the default.
4589 *
4590 * 100 series are RS232, 200 series RS422,
4591 */
4592 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 pbn_b1_4_115200 },
4595 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_b1_2_115200 },
4598 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_b2_2_115200 },
4601 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_b1_2_115200 },
4604 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_b2_2_115200 },
4607 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_b1_4_115200 },
4610 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_b1_8_115200 },
4613 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_b1_8_115200 },
4616 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_b1_4_115200 },
4619 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b1_2_115200 },
4622 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b1_4_115200 },
4625 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b1_2_115200 },
4628 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b2_4_115200 },
4631 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b2_2_115200 },
4634 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b2_1_115200 },
4637 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b2_4_115200 },
4640 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b2_2_115200 },
4643 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b2_1_115200 },
4646 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b0_8_115200 },
4649
4650 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4651 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4652 0, 0,
4653 pbn_b0_4_921600 },
4654 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4655 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4656 0, 0,
4657 pbn_b0_4_1152000 },
4658 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_b0_bt_2_921600 },
4661
4662 /*
4663 * The below card is a little controversial since it is the
4664 * subject of a PCI vendor/device ID clash. (See
4665 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4666 * For now just used the hex ID 0x950a.
4667 */
4668 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4669 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4670 0, 0, pbn_b0_2_115200 },
4671 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4672 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4673 0, 0, pbn_b0_2_115200 },
4674 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_b0_2_1130000 },
4677 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4678 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4679 pbn_b0_1_921600 },
4680 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_b0_4_115200 },
4683 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685 pbn_b0_bt_2_921600 },
4686 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_b2_8_1152000 },
4689
4690 /*
4691 * Oxford Semiconductor Inc. Tornado PCI express device range.
4692 */
4693 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_b0_1_15625000 },
4696 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_b0_1_15625000 },
4699 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_oxsemi_1_15625000 },
4702 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_oxsemi_1_15625000 },
4705 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b0_1_15625000 },
4708 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b0_1_15625000 },
4711 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_oxsemi_1_15625000 },
4714 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_oxsemi_1_15625000 },
4717 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_b0_1_15625000 },
4720 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_b0_1_15625000 },
4723 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_b0_1_15625000 },
4726 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_1_15625000 },
4729 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_oxsemi_2_15625000 },
4732 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_oxsemi_2_15625000 },
4735 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_oxsemi_4_15625000 },
4738 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_oxsemi_4_15625000 },
4741 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_oxsemi_8_15625000 },
4744 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_oxsemi_8_15625000 },
4747 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_oxsemi_1_15625000 },
4750 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_oxsemi_1_15625000 },
4753 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_oxsemi_1_15625000 },
4756 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_oxsemi_1_15625000 },
4759 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_oxsemi_1_15625000 },
4762 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_oxsemi_1_15625000 },
4765 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_oxsemi_1_15625000 },
4768 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_oxsemi_1_15625000 },
4771 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_oxsemi_1_15625000 },
4774 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_oxsemi_1_15625000 },
4777 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_oxsemi_1_15625000 },
4780 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_oxsemi_1_15625000 },
4783 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_oxsemi_1_15625000 },
4786 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_oxsemi_1_15625000 },
4789 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_oxsemi_1_15625000 },
4792 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_oxsemi_1_15625000 },
4795 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 pbn_oxsemi_1_15625000 },
4798 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_oxsemi_1_15625000 },
4801 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 pbn_oxsemi_1_15625000 },
4804 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 pbn_oxsemi_1_15625000 },
4807 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 pbn_oxsemi_1_15625000 },
4810 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 pbn_oxsemi_1_15625000 },
4813 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 pbn_oxsemi_1_15625000 },
4816 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818 pbn_oxsemi_1_15625000 },
4819 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4821 pbn_oxsemi_1_15625000 },
4822 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824 pbn_oxsemi_1_15625000 },
4825 /*
4826 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4827 */
4828 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4829 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4830 pbn_oxsemi_1_15625000 },
4831 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4832 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4833 pbn_oxsemi_2_15625000 },
4834 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4835 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4836 pbn_oxsemi_4_15625000 },
4837 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4838 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4839 pbn_oxsemi_8_15625000 },
4840
4841 /*
4842 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4843 */
4844 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4845 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4846 pbn_oxsemi_2_15625000 },
4847 /*
4848 * EndRun Technologies. PCI express device range.
4849 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4850 */
4851 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_oxsemi_2_15625000 },
4854
4855 /*
4856 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4857 * from skokodyn@yahoo.com
4858 */
4859 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4860 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4861 pbn_sbsxrsio },
4862 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4863 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4864 pbn_sbsxrsio },
4865 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4866 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4867 pbn_sbsxrsio },
4868 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4869 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4870 pbn_sbsxrsio },
4871
4872 /*
4873 * Digitan DS560-558, from jimd@esoft.com
4874 */
4875 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 pbn_b1_1_115200 },
4878
4879 /*
4880 * Titan Electronic cards
4881 * The 400L and 800L have a custom setup quirk.
4882 */
4883 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_1_921600 },
4886 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_2_921600 },
4889 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_4_921600 },
4892 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_4_921600 },
4895 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_b1_1_921600 },
4898 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 pbn_b1_bt_2_921600 },
4901 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_b0_bt_4_921600 },
4904 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 pbn_b0_bt_8_921600 },
4907 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 pbn_b4_bt_2_921600 },
4910 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_b4_bt_4_921600 },
4913 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_b4_bt_8_921600 },
4916 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_b0_4_921600 },
4919 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_b0_4_921600 },
4922 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924 pbn_b0_4_921600 },
4925 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 pbn_titan_1_4000000 },
4928 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 pbn_titan_2_4000000 },
4931 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933 pbn_titan_4_4000000 },
4934 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936 pbn_titan_8_4000000 },
4937 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 pbn_titan_2_4000000 },
4940 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 pbn_titan_2_4000000 },
4943 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945 pbn_b0_bt_2_921600 },
4946 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948 pbn_b0_4_921600 },
4949 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b0_4_921600 },
4952 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954 pbn_b0_4_921600 },
4955 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_b0_4_921600 },
4958
4959 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4961 pbn_b2_1_460800 },
4962 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b2_1_460800 },
4965 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 pbn_b2_1_460800 },
4968 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970 pbn_b2_bt_2_921600 },
4971 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973 pbn_b2_bt_2_921600 },
4974 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976 pbn_b2_bt_2_921600 },
4977 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979 pbn_b2_bt_4_921600 },
4980 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982 pbn_b2_bt_4_921600 },
4983 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_b2_bt_4_921600 },
4986 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988 pbn_b0_1_921600 },
4989 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4991 pbn_b0_1_921600 },
4992 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4994 pbn_b0_1_921600 },
4995 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4997 pbn_b0_bt_2_921600 },
4998 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000 pbn_b0_bt_2_921600 },
5001 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003 pbn_b0_bt_2_921600 },
5004 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006 pbn_b0_bt_4_921600 },
5007 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5009 pbn_b0_bt_4_921600 },
5010 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 pbn_b0_bt_4_921600 },
5013 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015 pbn_b0_bt_8_921600 },
5016 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018 pbn_b0_bt_8_921600 },
5019 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021 pbn_b0_bt_8_921600 },
5022
5023 /*
5024 * Computone devices submitted by Doug McNash dmcnash@computone.com
5025 */
5026 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5027 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5028 0, 0, pbn_computone_4 },
5029 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5030 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5031 0, 0, pbn_computone_8 },
5032 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5033 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5034 0, 0, pbn_computone_6 },
5035
5036 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_oxsemi },
5039 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5040 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5041 pbn_b0_bt_1_921600 },
5042
5043 /*
5044 * Sunix PCI serial boards
5045 */
5046 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5047 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5048 pbn_sunix_pci_1s },
5049 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5050 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5051 pbn_sunix_pci_2s },
5052 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5053 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5054 pbn_sunix_pci_4s },
5055 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5056 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5057 pbn_sunix_pci_4s },
5058 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5059 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5060 pbn_sunix_pci_8s },
5061 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5062 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5063 pbn_sunix_pci_8s },
5064 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5065 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5066 pbn_sunix_pci_16s },
5067
5068 /*
5069 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5070 */
5071 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073 pbn_b0_bt_8_115200 },
5074 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 pbn_b0_bt_8_115200 },
5077
5078 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080 pbn_b0_bt_2_115200 },
5081 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083 pbn_b0_bt_2_115200 },
5084 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5086 pbn_b0_bt_2_115200 },
5087 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 pbn_b0_bt_4_460800 },
5090 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_b0_bt_4_460800 },
5093 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 pbn_b0_bt_2_460800 },
5096 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 pbn_b0_bt_2_460800 },
5099 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101 pbn_b0_bt_2_460800 },
5102 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5104 pbn_b0_bt_1_115200 },
5105 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5107 pbn_b0_bt_1_460800 },
5108
5109 /*
5110 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5111 * Cards are identified by their subsystem vendor IDs, which
5112 * (in hex) match the model number.
5113 *
5114 * Note that JC140x are RS422/485 cards which require ox950
5115 * ACR = 0x10, and as such are not currently fully supported.
5116 */
5117 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5118 0x1204, 0x0004, 0, 0,
5119 pbn_b0_4_921600 },
5120 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5121 0x1208, 0x0004, 0, 0,
5122 pbn_b0_4_921600 },
5123 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5124 0x1402, 0x0002, 0, 0,
5125 pbn_b0_2_921600 }, */
5126 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5127 0x1404, 0x0004, 0, 0,
5128 pbn_b0_4_921600 }, */
5129 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5130 0x1208, 0x0004, 0, 0,
5131 pbn_b0_4_921600 },
5132
5133 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5134 0x1204, 0x0004, 0, 0,
5135 pbn_b0_4_921600 },
5136 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5137 0x1208, 0x0004, 0, 0,
5138 pbn_b0_4_921600 },
5139 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5140 0x1208, 0x0004, 0, 0,
5141 pbn_b0_4_921600 },
5142 /*
5143 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5144 */
5145 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5147 pbn_b1_1_1382400 },
5148
5149 /*
5150 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5151 */
5152 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 pbn_b1_1_1382400 },
5155
5156 /*
5157 * RAStel 2 port modem, gerg@moreton.com.au
5158 */
5159 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5161 pbn_b2_bt_2_115200 },
5162
5163 /*
5164 * EKF addition for i960 Boards form EKF with serial port
5165 */
5166 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5167 0xE4BF, PCI_ANY_ID, 0, 0,
5168 pbn_intel_i960 },
5169
5170 /*
5171 * Xircom Cardbus/Ethernet combos
5172 */
5173 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5175 pbn_b0_1_115200 },
5176 /*
5177 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5178 */
5179 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181 pbn_b0_1_115200 },
5182
5183 /*
5184 * Untested PCI modems, sent in from various folks...
5185 */
5186
5187 /*
5188 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5189 */
5190 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5191 0x1048, 0x1500, 0, 0,
5192 pbn_b1_1_115200 },
5193
5194 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5195 0xFF00, 0, 0, 0,
5196 pbn_sgi_ioc3 },
5197
5198 /*
5199 * HP Diva card
5200 */
5201 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5202 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5203 pbn_b1_1_115200 },
5204 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 pbn_b0_5_115200 },
5207 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209 pbn_b2_1_115200 },
5210 /* HPE PCI serial device */
5211 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5213 pbn_b1_1_115200 },
5214
5215 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5217 pbn_b3_2_115200 },
5218 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5220 pbn_b3_4_115200 },
5221 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5223 pbn_b3_8_115200 },
5224 /*
5225 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5226 */
5227 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5229 pbn_b0_1_115200 },
5230 /*
5231 * ITE
5232 */
5233 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5234 PCI_ANY_ID, PCI_ANY_ID,
5235 0, 0,
5236 pbn_b1_bt_1_115200 },
5237
5238 /*
5239 * IntaShield IS-100
5240 */
5241 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5243 pbn_b2_1_115200 },
5244 /*
5245 * IntaShield IS-200
5246 */
5247 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5249 pbn_b2_2_115200 },
5250 /*
5251 * IntaShield IS-400
5252 */
5253 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5255 pbn_b2_4_115200 },
5256 /*
5257 * IntaShield IX-100
5258 */
5259 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5260 PCI_ANY_ID, PCI_ANY_ID,
5261 0, 0,
5262 pbn_oxsemi_1_15625000 },
5263 /*
5264 * IntaShield IX-200
5265 */
5266 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5267 PCI_ANY_ID, PCI_ANY_ID,
5268 0, 0,
5269 pbn_oxsemi_2_15625000 },
5270 /*
5271 * IntaShield IX-400
5272 */
5273 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5274 PCI_ANY_ID, PCI_ANY_ID,
5275 0, 0,
5276 pbn_oxsemi_4_15625000 },
5277 /* Brainboxes Devices */
5278 /*
5279 * Brainboxes UC-101
5280 */
5281 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5282 PCI_ANY_ID, PCI_ANY_ID,
5283 0, 0,
5284 pbn_b2_2_115200 },
5285 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5286 PCI_ANY_ID, PCI_ANY_ID,
5287 0, 0,
5288 pbn_b2_2_115200 },
5289 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5290 PCI_ANY_ID, PCI_ANY_ID,
5291 0, 0,
5292 pbn_b2_2_115200 },
5293 /*
5294 * Brainboxes UC-235/246
5295 */
5296 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5297 PCI_ANY_ID, PCI_ANY_ID,
5298 0, 0,
5299 pbn_b2_1_115200 },
5300 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5301 PCI_ANY_ID, PCI_ANY_ID,
5302 0, 0,
5303 pbn_b2_1_115200 },
5304 /*
5305 * Brainboxes UC-253/UC-734
5306 */
5307 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5308 PCI_ANY_ID, PCI_ANY_ID,
5309 0, 0,
5310 pbn_b2_2_115200 },
5311 /*
5312 * Brainboxes UC-260/271/701/756
5313 */
5314 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5315 PCI_ANY_ID, PCI_ANY_ID,
5316 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5317 pbn_b2_4_115200 },
5318 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5319 PCI_ANY_ID, PCI_ANY_ID,
5320 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5321 pbn_b2_4_115200 },
5322 /*
5323 * Brainboxes UC-268
5324 */
5325 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5326 PCI_ANY_ID, PCI_ANY_ID,
5327 0, 0,
5328 pbn_b2_4_115200 },
5329 /*
5330 * Brainboxes UC-275/279
5331 */
5332 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5333 PCI_ANY_ID, PCI_ANY_ID,
5334 0, 0,
5335 pbn_b2_8_115200 },
5336 /*
5337 * Brainboxes UC-302
5338 */
5339 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5340 PCI_ANY_ID, PCI_ANY_ID,
5341 0, 0,
5342 pbn_b2_2_115200 },
5343 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5344 PCI_ANY_ID, PCI_ANY_ID,
5345 0, 0,
5346 pbn_b2_2_115200 },
5347 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5348 PCI_ANY_ID, PCI_ANY_ID,
5349 0, 0,
5350 pbn_b2_2_115200 },
5351 /*
5352 * Brainboxes UC-310
5353 */
5354 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5355 PCI_ANY_ID, PCI_ANY_ID,
5356 0, 0,
5357 pbn_b2_2_115200 },
5358 /*
5359 * Brainboxes UC-313
5360 */
5361 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5362 PCI_ANY_ID, PCI_ANY_ID,
5363 0, 0,
5364 pbn_b2_2_115200 },
5365 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5366 PCI_ANY_ID, PCI_ANY_ID,
5367 0, 0,
5368 pbn_b2_2_115200 },
5369 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5370 PCI_ANY_ID, PCI_ANY_ID,
5371 0, 0,
5372 pbn_b2_2_115200 },
5373 /*
5374 * Brainboxes UC-320/324
5375 */
5376 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5377 PCI_ANY_ID, PCI_ANY_ID,
5378 0, 0,
5379 pbn_b2_1_115200 },
5380 /*
5381 * Brainboxes UC-346
5382 */
5383 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5384 PCI_ANY_ID, PCI_ANY_ID,
5385 0, 0,
5386 pbn_b2_4_115200 },
5387 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5388 PCI_ANY_ID, PCI_ANY_ID,
5389 0, 0,
5390 pbn_b2_4_115200 },
5391 /*
5392 * Brainboxes UC-357
5393 */
5394 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5395 PCI_ANY_ID, PCI_ANY_ID,
5396 0, 0,
5397 pbn_b2_2_115200 },
5398 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5399 PCI_ANY_ID, PCI_ANY_ID,
5400 0, 0,
5401 pbn_b2_2_115200 },
5402 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5403 PCI_ANY_ID, PCI_ANY_ID,
5404 0, 0,
5405 pbn_b2_2_115200 },
5406 /*
5407 * Brainboxes UC-368
5408 */
5409 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5410 PCI_ANY_ID, PCI_ANY_ID,
5411 0, 0,
5412 pbn_b2_4_115200 },
5413 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5414 PCI_ANY_ID, PCI_ANY_ID,
5415 0, 0,
5416 pbn_b2_4_115200 },
5417 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5418 PCI_ANY_ID, PCI_ANY_ID,
5419 0, 0,
5420 pbn_b2_4_115200 },
5421 /*
5422 * Brainboxes UC-420
5423 */
5424 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5425 PCI_ANY_ID, PCI_ANY_ID,
5426 0, 0,
5427 pbn_b2_4_115200 },
5428 /*
5429 * Brainboxes UC-607
5430 */
5431 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5432 PCI_ANY_ID, PCI_ANY_ID,
5433 0, 0,
5434 pbn_b2_2_115200 },
5435 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5436 PCI_ANY_ID, PCI_ANY_ID,
5437 0, 0,
5438 pbn_b2_2_115200 },
5439 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5440 PCI_ANY_ID, PCI_ANY_ID,
5441 0, 0,
5442 pbn_b2_2_115200 },
5443 /*
5444 * Brainboxes UC-836
5445 */
5446 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5447 PCI_ANY_ID, PCI_ANY_ID,
5448 0, 0,
5449 pbn_b2_4_115200 },
5450 /*
5451 * Brainboxes UP-189
5452 */
5453 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5454 PCI_ANY_ID, PCI_ANY_ID,
5455 0, 0,
5456 pbn_b2_2_115200 },
5457 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5458 PCI_ANY_ID, PCI_ANY_ID,
5459 0, 0,
5460 pbn_b2_2_115200 },
5461 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5462 PCI_ANY_ID, PCI_ANY_ID,
5463 0, 0,
5464 pbn_b2_2_115200 },
5465 /*
5466 * Brainboxes UP-200
5467 */
5468 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5469 PCI_ANY_ID, PCI_ANY_ID,
5470 0, 0,
5471 pbn_b2_2_115200 },
5472 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5473 PCI_ANY_ID, PCI_ANY_ID,
5474 0, 0,
5475 pbn_b2_2_115200 },
5476 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5477 PCI_ANY_ID, PCI_ANY_ID,
5478 0, 0,
5479 pbn_b2_2_115200 },
5480 /*
5481 * Brainboxes UP-869
5482 */
5483 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5484 PCI_ANY_ID, PCI_ANY_ID,
5485 0, 0,
5486 pbn_b2_2_115200 },
5487 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5488 PCI_ANY_ID, PCI_ANY_ID,
5489 0, 0,
5490 pbn_b2_2_115200 },
5491 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5492 PCI_ANY_ID, PCI_ANY_ID,
5493 0, 0,
5494 pbn_b2_2_115200 },
5495 /*
5496 * Brainboxes UP-880
5497 */
5498 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5499 PCI_ANY_ID, PCI_ANY_ID,
5500 0, 0,
5501 pbn_b2_2_115200 },
5502 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5503 PCI_ANY_ID, PCI_ANY_ID,
5504 0, 0,
5505 pbn_b2_2_115200 },
5506 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5507 PCI_ANY_ID, PCI_ANY_ID,
5508 0, 0,
5509 pbn_b2_2_115200 },
5510 /*
5511 * Brainboxes PX-101
5512 */
5513 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5514 PCI_ANY_ID, PCI_ANY_ID,
5515 0, 0,
5516 pbn_b0_2_115200 },
5517 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5518 PCI_ANY_ID, PCI_ANY_ID,
5519 0, 0,
5520 pbn_oxsemi_2_15625000 },
5521 /*
5522 * Brainboxes PX-235/246
5523 */
5524 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5525 PCI_ANY_ID, PCI_ANY_ID,
5526 0, 0,
5527 pbn_b0_1_115200 },
5528 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5529 PCI_ANY_ID, PCI_ANY_ID,
5530 0, 0,
5531 pbn_oxsemi_1_15625000 },
5532 /*
5533 * Brainboxes PX-203/PX-257
5534 */
5535 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5536 PCI_ANY_ID, PCI_ANY_ID,
5537 0, 0,
5538 pbn_b0_2_115200 },
5539 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5540 PCI_ANY_ID, PCI_ANY_ID,
5541 0, 0,
5542 pbn_oxsemi_2_15625000 },
5543 /*
5544 * Brainboxes PX-260/PX-701
5545 */
5546 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5547 PCI_ANY_ID, PCI_ANY_ID,
5548 0, 0,
5549 pbn_oxsemi_4_15625000 },
5550 /*
5551 * Brainboxes PX-275/279
5552 */
5553 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5554 PCI_ANY_ID, PCI_ANY_ID,
5555 0, 0,
5556 pbn_b2_8_115200 },
5557 /*
5558 * Brainboxes PX-310
5559 */
5560 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5561 PCI_ANY_ID, PCI_ANY_ID,
5562 0, 0,
5563 pbn_oxsemi_2_15625000 },
5564 /*
5565 * Brainboxes PX-313
5566 */
5567 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5568 PCI_ANY_ID, PCI_ANY_ID,
5569 0, 0,
5570 pbn_oxsemi_2_15625000 },
5571 /*
5572 * Brainboxes PX-320/324/PX-376/PX-387
5573 */
5574 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5575 PCI_ANY_ID, PCI_ANY_ID,
5576 0, 0,
5577 pbn_oxsemi_1_15625000 },
5578 /*
5579 * Brainboxes PX-335/346
5580 */
5581 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5582 PCI_ANY_ID, PCI_ANY_ID,
5583 0, 0,
5584 pbn_oxsemi_4_15625000 },
5585 /*
5586 * Brainboxes PX-368
5587 */
5588 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5589 PCI_ANY_ID, PCI_ANY_ID,
5590 0, 0,
5591 pbn_oxsemi_4_15625000 },
5592 /*
5593 * Brainboxes PX-420
5594 */
5595 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5596 PCI_ANY_ID, PCI_ANY_ID,
5597 0, 0,
5598 pbn_b0_4_115200 },
5599 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5600 PCI_ANY_ID, PCI_ANY_ID,
5601 0, 0,
5602 pbn_oxsemi_4_15625000 },
5603 /*
5604 * Brainboxes PX-475
5605 */
5606 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5607 PCI_ANY_ID, PCI_ANY_ID,
5608 0, 0,
5609 pbn_oxsemi_1_15625000 },
5610 /*
5611 * Brainboxes PX-803/PX-857
5612 */
5613 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5614 PCI_ANY_ID, PCI_ANY_ID,
5615 0, 0,
5616 pbn_b0_2_115200 },
5617 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5618 PCI_ANY_ID, PCI_ANY_ID,
5619 0, 0,
5620 pbn_oxsemi_2_15625000 },
5621 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5622 PCI_ANY_ID, PCI_ANY_ID,
5623 0, 0,
5624 pbn_oxsemi_2_15625000 },
5625 /*
5626 * Brainboxes PX-820
5627 */
5628 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5629 PCI_ANY_ID, PCI_ANY_ID,
5630 0, 0,
5631 pbn_b0_4_115200 },
5632 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5633 PCI_ANY_ID, PCI_ANY_ID,
5634 0, 0,
5635 pbn_oxsemi_4_15625000 },
5636 /*
5637 * Brainboxes PX-835/PX-846
5638 */
5639 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5640 PCI_ANY_ID, PCI_ANY_ID,
5641 0, 0,
5642 pbn_b0_1_115200 },
5643 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5644 PCI_ANY_ID, PCI_ANY_ID,
5645 0, 0,
5646 pbn_oxsemi_1_15625000 },
5647 /*
5648 * Brainboxes XC-235
5649 */
5650 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5651 PCI_ANY_ID, PCI_ANY_ID,
5652 0, 0,
5653 pbn_oxsemi_1_15625000 },
5654 /*
5655 * Brainboxes XC-475
5656 */
5657 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5658 PCI_ANY_ID, PCI_ANY_ID,
5659 0, 0,
5660 pbn_oxsemi_1_15625000 },
5661
5662 /*
5663 * Perle PCI-RAS cards
5664 */
5665 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5666 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5667 0, 0, pbn_b2_4_921600 },
5668 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5669 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5670 0, 0, pbn_b2_8_921600 },
5671
5672 /*
5673 * Mainpine series cards: Fairly standard layout but fools
5674 * parts of the autodetect in some cases and uses otherwise
5675 * unmatched communications subclasses in the PCI Express case
5676 */
5677
5678 { /* RockForceDUO */
5679 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5680 PCI_VENDOR_ID_MAINPINE, 0x0200,
5681 0, 0, pbn_b0_2_115200 },
5682 { /* RockForceQUATRO */
5683 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5684 PCI_VENDOR_ID_MAINPINE, 0x0300,
5685 0, 0, pbn_b0_4_115200 },
5686 { /* RockForceDUO+ */
5687 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5688 PCI_VENDOR_ID_MAINPINE, 0x0400,
5689 0, 0, pbn_b0_2_115200 },
5690 { /* RockForceQUATRO+ */
5691 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5692 PCI_VENDOR_ID_MAINPINE, 0x0500,
5693 0, 0, pbn_b0_4_115200 },
5694 { /* RockForce+ */
5695 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5696 PCI_VENDOR_ID_MAINPINE, 0x0600,
5697 0, 0, pbn_b0_2_115200 },
5698 { /* RockForce+ */
5699 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5700 PCI_VENDOR_ID_MAINPINE, 0x0700,
5701 0, 0, pbn_b0_4_115200 },
5702 { /* RockForceOCTO+ */
5703 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5704 PCI_VENDOR_ID_MAINPINE, 0x0800,
5705 0, 0, pbn_b0_8_115200 },
5706 { /* RockForceDUO+ */
5707 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5708 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5709 0, 0, pbn_b0_2_115200 },
5710 { /* RockForceQUARTRO+ */
5711 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5712 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5713 0, 0, pbn_b0_4_115200 },
5714 { /* RockForceOCTO+ */
5715 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5716 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5717 0, 0, pbn_b0_8_115200 },
5718 { /* RockForceD1 */
5719 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5720 PCI_VENDOR_ID_MAINPINE, 0x2000,
5721 0, 0, pbn_b0_1_115200 },
5722 { /* RockForceF1 */
5723 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5724 PCI_VENDOR_ID_MAINPINE, 0x2100,
5725 0, 0, pbn_b0_1_115200 },
5726 { /* RockForceD2 */
5727 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5728 PCI_VENDOR_ID_MAINPINE, 0x2200,
5729 0, 0, pbn_b0_2_115200 },
5730 { /* RockForceF2 */
5731 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5732 PCI_VENDOR_ID_MAINPINE, 0x2300,
5733 0, 0, pbn_b0_2_115200 },
5734 { /* RockForceD4 */
5735 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5736 PCI_VENDOR_ID_MAINPINE, 0x2400,
5737 0, 0, pbn_b0_4_115200 },
5738 { /* RockForceF4 */
5739 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5740 PCI_VENDOR_ID_MAINPINE, 0x2500,
5741 0, 0, pbn_b0_4_115200 },
5742 { /* RockForceD8 */
5743 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5744 PCI_VENDOR_ID_MAINPINE, 0x2600,
5745 0, 0, pbn_b0_8_115200 },
5746 { /* RockForceF8 */
5747 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5748 PCI_VENDOR_ID_MAINPINE, 0x2700,
5749 0, 0, pbn_b0_8_115200 },
5750 { /* IQ Express D1 */
5751 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5752 PCI_VENDOR_ID_MAINPINE, 0x3000,
5753 0, 0, pbn_b0_1_115200 },
5754 { /* IQ Express F1 */
5755 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5756 PCI_VENDOR_ID_MAINPINE, 0x3100,
5757 0, 0, pbn_b0_1_115200 },
5758 { /* IQ Express D2 */
5759 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5760 PCI_VENDOR_ID_MAINPINE, 0x3200,
5761 0, 0, pbn_b0_2_115200 },
5762 { /* IQ Express F2 */
5763 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5764 PCI_VENDOR_ID_MAINPINE, 0x3300,
5765 0, 0, pbn_b0_2_115200 },
5766 { /* IQ Express D4 */
5767 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5768 PCI_VENDOR_ID_MAINPINE, 0x3400,
5769 0, 0, pbn_b0_4_115200 },
5770 { /* IQ Express F4 */
5771 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5772 PCI_VENDOR_ID_MAINPINE, 0x3500,
5773 0, 0, pbn_b0_4_115200 },
5774 { /* IQ Express D8 */
5775 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5776 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5777 0, 0, pbn_b0_8_115200 },
5778 { /* IQ Express F8 */
5779 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5780 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5781 0, 0, pbn_b0_8_115200 },
5782
5783
5784 /*
5785 * PA Semi PA6T-1682M on-chip UART
5786 */
5787 { PCI_VENDOR_ID_PASEMI, 0xa004,
5788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5789 pbn_pasemi_1682M },
5790
5791 /*
5792 * National Instruments
5793 */
5794 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5796 pbn_b1_16_115200 },
5797 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5799 pbn_b1_8_115200 },
5800 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5802 pbn_b1_bt_4_115200 },
5803 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5805 pbn_b1_bt_2_115200 },
5806 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5808 pbn_b1_bt_4_115200 },
5809 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5811 pbn_b1_bt_2_115200 },
5812 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5814 pbn_b1_16_115200 },
5815 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5817 pbn_b1_8_115200 },
5818 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5820 pbn_b1_bt_4_115200 },
5821 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5823 pbn_b1_bt_2_115200 },
5824 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5826 pbn_b1_bt_4_115200 },
5827 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5829 pbn_b1_bt_2_115200 },
5830 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5832 pbn_ni8430_2 },
5833 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5835 pbn_ni8430_2 },
5836 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5838 pbn_ni8430_4 },
5839 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5841 pbn_ni8430_4 },
5842 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5844 pbn_ni8430_8 },
5845 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5847 pbn_ni8430_8 },
5848 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5850 pbn_ni8430_16 },
5851 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5853 pbn_ni8430_16 },
5854 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5856 pbn_ni8430_2 },
5857 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5859 pbn_ni8430_2 },
5860 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5862 pbn_ni8430_4 },
5863 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5865 pbn_ni8430_4 },
5866
5867 /*
5868 * MOXA
5869 */
5870 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5871 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5872 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5873 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5874 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5875 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5876 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5877 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5878 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5879 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5880 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5881 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5882 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5883 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5884 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5885 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5886 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5887 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5888
5889 /*
5890 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5891 */
5892 { PCI_VENDOR_ID_ADDIDATA,
5893 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5894 PCI_ANY_ID,
5895 PCI_ANY_ID,
5896 0,
5897 0,
5898 pbn_b0_4_115200 },
5899
5900 { PCI_VENDOR_ID_ADDIDATA,
5901 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5902 PCI_ANY_ID,
5903 PCI_ANY_ID,
5904 0,
5905 0,
5906 pbn_b0_2_115200 },
5907
5908 { PCI_VENDOR_ID_ADDIDATA,
5909 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5910 PCI_ANY_ID,
5911 PCI_ANY_ID,
5912 0,
5913 0,
5914 pbn_b0_1_115200 },
5915
5916 { PCI_VENDOR_ID_AMCC,
5917 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5918 PCI_ANY_ID,
5919 PCI_ANY_ID,
5920 0,
5921 0,
5922 pbn_b1_8_115200 },
5923
5924 { PCI_VENDOR_ID_ADDIDATA,
5925 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5926 PCI_ANY_ID,
5927 PCI_ANY_ID,
5928 0,
5929 0,
5930 pbn_b0_4_115200 },
5931
5932 { PCI_VENDOR_ID_ADDIDATA,
5933 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5934 PCI_ANY_ID,
5935 PCI_ANY_ID,
5936 0,
5937 0,
5938 pbn_b0_2_115200 },
5939
5940 { PCI_VENDOR_ID_ADDIDATA,
5941 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5942 PCI_ANY_ID,
5943 PCI_ANY_ID,
5944 0,
5945 0,
5946 pbn_b0_1_115200 },
5947
5948 { PCI_VENDOR_ID_ADDIDATA,
5949 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5950 PCI_ANY_ID,
5951 PCI_ANY_ID,
5952 0,
5953 0,
5954 pbn_b0_4_115200 },
5955
5956 { PCI_VENDOR_ID_ADDIDATA,
5957 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5958 PCI_ANY_ID,
5959 PCI_ANY_ID,
5960 0,
5961 0,
5962 pbn_b0_2_115200 },
5963
5964 { PCI_VENDOR_ID_ADDIDATA,
5965 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5966 PCI_ANY_ID,
5967 PCI_ANY_ID,
5968 0,
5969 0,
5970 pbn_b0_1_115200 },
5971
5972 { PCI_VENDOR_ID_ADDIDATA,
5973 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5974 PCI_ANY_ID,
5975 PCI_ANY_ID,
5976 0,
5977 0,
5978 pbn_b0_8_115200 },
5979
5980 { PCI_VENDOR_ID_ADDIDATA,
5981 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5982 PCI_ANY_ID,
5983 PCI_ANY_ID,
5984 0,
5985 0,
5986 pbn_ADDIDATA_PCIe_4_3906250 },
5987
5988 { PCI_VENDOR_ID_ADDIDATA,
5989 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5990 PCI_ANY_ID,
5991 PCI_ANY_ID,
5992 0,
5993 0,
5994 pbn_ADDIDATA_PCIe_2_3906250 },
5995
5996 { PCI_VENDOR_ID_ADDIDATA,
5997 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5998 PCI_ANY_ID,
5999 PCI_ANY_ID,
6000 0,
6001 0,
6002 pbn_ADDIDATA_PCIe_1_3906250 },
6003
6004 { PCI_VENDOR_ID_ADDIDATA,
6005 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
6006 PCI_ANY_ID,
6007 PCI_ANY_ID,
6008 0,
6009 0,
6010 pbn_ADDIDATA_PCIe_8_3906250 },
6011
6012 { PCI_VENDOR_ID_ADDIDATA,
6013 PCI_DEVICE_ID_ADDIDATA_CPCI7500,
6014 PCI_ANY_ID,
6015 PCI_ANY_ID,
6016 0,
6017 0,
6018 pbn_b0_4_115200 },
6019
6020 { PCI_VENDOR_ID_ADDIDATA,
6021 PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG,
6022 PCI_ANY_ID,
6023 PCI_ANY_ID,
6024 0,
6025 0,
6026 pbn_b0_4_115200 },
6027
6028 { PCI_VENDOR_ID_ADDIDATA,
6029 PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG,
6030 PCI_ANY_ID,
6031 PCI_ANY_ID,
6032 0,
6033 0,
6034 pbn_b0_2_115200 },
6035
6036 { PCI_VENDOR_ID_ADDIDATA,
6037 PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG,
6038 PCI_ANY_ID,
6039 PCI_ANY_ID,
6040 0,
6041 0,
6042 pbn_b0_1_115200 },
6043
6044 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
6045 PCI_VENDOR_ID_IBM, 0x0299,
6046 0, 0, pbn_b0_bt_2_115200 },
6047
6048 /*
6049 * other NetMos 9835 devices are most likely handled by the
6050 * parport_serial driver, check drivers/parport/parport_serial.c
6051 * before adding them here.
6052 */
6053
6054 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
6055 0xA000, 0x1000,
6056 0, 0, pbn_b0_1_115200 },
6057
6058 /* the 9901 is a rebranded 9912 */
6059 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
6060 0xA000, 0x1000,
6061 0, 0, pbn_b0_1_115200 },
6062
6063 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
6064 0xA000, 0x1000,
6065 0, 0, pbn_b0_1_115200 },
6066
6067 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
6068 0xA000, 0x1000,
6069 0, 0, pbn_b0_1_115200 },
6070
6071 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6072 0xA000, 0x1000,
6073 0, 0, pbn_b0_1_115200 },
6074
6075 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6076 0xA000, 0x3002,
6077 0, 0, pbn_NETMOS9900_2s_115200 },
6078
6079 /*
6080 * Best Connectivity and Rosewill PCI Multi I/O cards
6081 */
6082
6083 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6084 0xA000, 0x1000,
6085 0, 0, pbn_b0_1_115200 },
6086
6087 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6088 0xA000, 0x3002,
6089 0, 0, pbn_b0_bt_2_115200 },
6090
6091 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6092 0xA000, 0x3004,
6093 0, 0, pbn_b0_bt_4_115200 },
6094
6095 /*
6096 * ASIX AX99100 PCIe to Multi I/O Controller
6097 */
6098 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6099 0xA000, 0x1000,
6100 0, 0, pbn_b0_1_115200 },
6101
6102 /* Intel CE4100 */
6103 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6105 pbn_ce4100_1_115200 },
6106
6107 /*
6108 * Cronyx Omega PCI
6109 */
6110 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6112 pbn_omegapci },
6113
6114 /*
6115 * Broadcom TruManage
6116 */
6117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6119 pbn_brcm_trumanage },
6120
6121 /*
6122 * AgeStar as-prs2-009
6123 */
6124 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6125 PCI_ANY_ID, PCI_ANY_ID,
6126 0, 0, pbn_b0_bt_2_115200 },
6127
6128 /*
6129 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6130 * so not listed here.
6131 */
6132 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
6133 PCI_ANY_ID, PCI_ANY_ID,
6134 0, 0, pbn_b0_bt_4_115200 },
6135
6136 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
6137 PCI_ANY_ID, PCI_ANY_ID,
6138 0, 0, pbn_b0_bt_2_115200 },
6139
6140 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
6141 PCI_ANY_ID, PCI_ANY_ID,
6142 0, 0, pbn_b0_bt_4_115200 },
6143
6144 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
6145 PCI_ANY_ID, PCI_ANY_ID,
6146 0, 0, pbn_wch382_2 },
6147
6148 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
6149 PCI_ANY_ID, PCI_ANY_ID,
6150 0, 0, pbn_wch384_4 },
6151
6152 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
6153 PCI_ANY_ID, PCI_ANY_ID,
6154 0, 0, pbn_wch384_8 },
6155 /*
6156 * Realtek RealManage
6157 */
6158 { PCI_VENDOR_ID_REALTEK, 0x816a,
6159 PCI_ANY_ID, PCI_ANY_ID,
6160 0, 0, pbn_b0_1_115200 },
6161
6162 { PCI_VENDOR_ID_REALTEK, 0x816b,
6163 PCI_ANY_ID, PCI_ANY_ID,
6164 0, 0, pbn_b0_1_115200 },
6165
6166 /* Fintek PCI serial cards */
6167 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6168 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6169 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6170 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6171 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6172 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6173
6174 /* MKS Tenta SCOM-080x serial cards */
6175 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6176 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6177
6178 /* Amazon PCI serial device */
6179 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6180
6181 /*
6182 * These entries match devices with class COMMUNICATION_SERIAL,
6183 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6184 */
6185 { PCI_ANY_ID, PCI_ANY_ID,
6186 PCI_ANY_ID, PCI_ANY_ID,
6187 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6188 0xffff00, pbn_default },
6189 { PCI_ANY_ID, PCI_ANY_ID,
6190 PCI_ANY_ID, PCI_ANY_ID,
6191 PCI_CLASS_COMMUNICATION_MODEM << 8,
6192 0xffff00, pbn_default },
6193 { PCI_ANY_ID, PCI_ANY_ID,
6194 PCI_ANY_ID, PCI_ANY_ID,
6195 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6196 0xffff00, pbn_default },
6197 { 0, }
6198 };
6199
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6200 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6201 pci_channel_state_t state)
6202 {
6203 struct serial_private *priv = pci_get_drvdata(dev);
6204
6205 if (state == pci_channel_io_perm_failure)
6206 return PCI_ERS_RESULT_DISCONNECT;
6207
6208 if (priv)
6209 pciserial_detach_ports(priv);
6210
6211 pci_disable_device(dev);
6212
6213 return PCI_ERS_RESULT_NEED_RESET;
6214 }
6215
serial8250_io_slot_reset(struct pci_dev * dev)6216 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6217 {
6218 int rc;
6219
6220 rc = pci_enable_device(dev);
6221
6222 if (rc)
6223 return PCI_ERS_RESULT_DISCONNECT;
6224
6225 pci_restore_state(dev);
6226
6227 return PCI_ERS_RESULT_RECOVERED;
6228 }
6229
serial8250_io_resume(struct pci_dev * dev)6230 static void serial8250_io_resume(struct pci_dev *dev)
6231 {
6232 struct serial_private *priv = pci_get_drvdata(dev);
6233 struct serial_private *new;
6234
6235 if (!priv)
6236 return;
6237
6238 new = pciserial_init_ports(dev, priv->board);
6239 if (!IS_ERR(new)) {
6240 pci_set_drvdata(dev, new);
6241 kfree(priv);
6242 }
6243 }
6244
6245 static const struct pci_error_handlers serial8250_err_handler = {
6246 .error_detected = serial8250_io_error_detected,
6247 .slot_reset = serial8250_io_slot_reset,
6248 .resume = serial8250_io_resume,
6249 };
6250
6251 static struct pci_driver serial_pci_driver = {
6252 .name = "serial",
6253 .probe = pciserial_init_one,
6254 .remove = pciserial_remove_one,
6255 .driver = {
6256 .pm = &pciserial_pm_ops,
6257 },
6258 .id_table = serial_pci_tbl,
6259 .err_handler = &serial8250_err_handler,
6260 };
6261
6262 module_pci_driver(serial_pci_driver);
6263
6264 MODULE_LICENSE("GPL");
6265 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6266 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6267 MODULE_IMPORT_NS("SERIAL_8250_PCI");
6268