xref: /linux/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c (revision be54f8c558027a218423134dd9b8c7c46d92204a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * c8sectpfe-core.c - C8SECTPFE STi DVB driver
4  *
5  * Copyright (c) STMicroelectronics 2015
6  *
7  *   Author:Peter Bennett <peter.bennett@st.com>
8  *	    Peter Griffin <peter.griffin@linaro.org>
9  *
10  */
11 #include <linux/atomic.h>
12 #include <linux/clk.h>
13 #include <linux/completion.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dvb/dmx.h>
18 #include <linux/dvb/frontend.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/firmware.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/time.h>
33 #include <linux/usb.h>
34 #include <linux/wait.h>
35 
36 #include "c8sectpfe-common.h"
37 #include "c8sectpfe-core.h"
38 #include "c8sectpfe-debugfs.h"
39 
40 #include <media/dmxdev.h>
41 #include <media/dvb_demux.h>
42 #include <media/dvb_frontend.h>
43 #include <media/dvb_net.h>
44 
45 #define FIRMWARE_MEMDMA "pti_memdma_h407.elf"
46 MODULE_FIRMWARE(FIRMWARE_MEMDMA);
47 
48 #define PID_TABLE_SIZE 1024
49 #define POLL_MSECS 50
50 
51 static int load_c8sectpfe_fw(struct c8sectpfei *fei);
52 
53 #define TS_PKT_SIZE 188
54 #define HEADER_SIZE (4)
55 #define PACKET_SIZE (TS_PKT_SIZE+HEADER_SIZE)
56 
57 #define FEI_ALIGNMENT (32)
58 /* hw requires minimum of 8*PACKET_SIZE and padded to 8byte boundary */
59 #define FEI_BUFFER_SIZE (8*PACKET_SIZE*340)
60 
61 #define FIFO_LEN 1024
62 
c8sectpfe_timer_interrupt(struct timer_list * t)63 static void c8sectpfe_timer_interrupt(struct timer_list *t)
64 {
65 	struct c8sectpfei *fei = timer_container_of(fei, t, timer);
66 	struct channel_info *channel;
67 	int chan_num;
68 
69 	/* iterate through input block channels */
70 	for (chan_num = 0; chan_num < fei->tsin_count; chan_num++) {
71 		channel = fei->channel_data[chan_num];
72 
73 		/* is this descriptor initialised and TP enabled */
74 		if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE))
75 			queue_work(system_bh_wq, &channel->bh_work);
76 	}
77 
78 	fei->timer.expires = jiffies +	msecs_to_jiffies(POLL_MSECS);
79 	add_timer(&fei->timer);
80 }
81 
channel_swdemux_bh_work(struct work_struct * t)82 static void channel_swdemux_bh_work(struct work_struct *t)
83 {
84 	struct channel_info *channel = from_work(channel, t, bh_work);
85 	struct c8sectpfei *fei;
86 	unsigned long wp, rp;
87 	int pos, num_packets, n, size;
88 	u8 *buf;
89 
90 	if (unlikely(!channel || !channel->irec))
91 		return;
92 
93 	fei = channel->fei;
94 
95 	wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0));
96 	rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0));
97 
98 	pos = rp - channel->back_buffer_busaddr;
99 
100 	/* has it wrapped */
101 	if (wp < rp)
102 		wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE;
103 
104 	size = wp - rp;
105 	num_packets = size / PACKET_SIZE;
106 
107 	/* manage cache so data is visible to CPU */
108 	dma_sync_single_for_cpu(fei->dev,
109 				rp,
110 				size,
111 				DMA_FROM_DEVICE);
112 
113 	buf = channel->back_buffer_aligned;
114 
115 	dev_dbg(fei->dev,
116 		"chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n",
117 		channel->tsin_id, channel, num_packets, buf, pos, rp, wp);
118 
119 	for (n = 0; n < num_packets; n++) {
120 		dvb_dmx_swfilter_packets(
121 			&fei->c8sectpfe[0]->
122 				demux[channel->demux_mapping].dvb_demux,
123 			&buf[pos], 1);
124 
125 		pos += PACKET_SIZE;
126 	}
127 
128 	/* advance the read pointer */
129 	if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE))
130 		writel(channel->back_buffer_busaddr, channel->irec +
131 			DMA_PRDS_BUSRP_TP(0));
132 	else
133 		writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0));
134 }
135 
c8sectpfe_start_feed(struct dvb_demux_feed * dvbdmxfeed)136 static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed)
137 {
138 	struct dvb_demux *demux = dvbdmxfeed->demux;
139 	struct stdemux *stdemux = demux->priv;
140 	struct c8sectpfei *fei = stdemux->c8sectpfei;
141 	struct channel_info *channel;
142 	u32 tmp;
143 	unsigned long *bitmap;
144 	int ret;
145 
146 	switch (dvbdmxfeed->type) {
147 	case DMX_TYPE_TS:
148 		break;
149 	case DMX_TYPE_SEC:
150 		break;
151 	default:
152 		dev_err(fei->dev, "%s:%d Error bailing\n"
153 			, __func__, __LINE__);
154 		return -EINVAL;
155 	}
156 
157 	if (dvbdmxfeed->type == DMX_TYPE_TS) {
158 		switch (dvbdmxfeed->pes_type) {
159 		case DMX_PES_VIDEO:
160 		case DMX_PES_AUDIO:
161 		case DMX_PES_TELETEXT:
162 		case DMX_PES_PCR:
163 		case DMX_PES_OTHER:
164 			break;
165 		default:
166 			dev_err(fei->dev, "%s:%d Error bailing\n"
167 				, __func__, __LINE__);
168 			return -EINVAL;
169 		}
170 	}
171 
172 	if (!atomic_read(&fei->fw_loaded)) {
173 		ret = load_c8sectpfe_fw(fei);
174 		if (ret)
175 			return ret;
176 	}
177 
178 	mutex_lock(&fei->lock);
179 
180 	channel = fei->channel_data[stdemux->tsin_index];
181 
182 	bitmap = channel->pid_buffer_aligned;
183 
184 	/* 8192 is a special PID */
185 	if (dvbdmxfeed->pid == 8192) {
186 		tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
187 		tmp &= ~C8SECTPFE_PID_ENABLE;
188 		writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
189 
190 	} else {
191 		bitmap_set(bitmap, dvbdmxfeed->pid, 1);
192 	}
193 
194 	/* manage cache so PID bitmap is visible to HW */
195 	dma_sync_single_for_device(fei->dev,
196 					channel->pid_buffer_busaddr,
197 					PID_TABLE_SIZE,
198 					DMA_TO_DEVICE);
199 
200 	channel->active = 1;
201 
202 	if (fei->global_feed_count == 0) {
203 		fei->timer.expires = jiffies +
204 			msecs_to_jiffies(msecs_to_jiffies(POLL_MSECS));
205 
206 		add_timer(&fei->timer);
207 	}
208 
209 	if (stdemux->running_feed_count == 0) {
210 
211 		dev_dbg(fei->dev, "Starting channel=%p\n", channel);
212 
213 		INIT_WORK(&channel->bh_work, channel_swdemux_bh_work);
214 
215 		/* Reset the internal inputblock sram pointers */
216 		writel(channel->fifo,
217 			fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id));
218 		writel(channel->fifo + FIFO_LEN - 1,
219 			fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id));
220 
221 		writel(channel->fifo,
222 			fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id));
223 		writel(channel->fifo,
224 			fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id));
225 
226 
227 		/* reset read / write memdma ptrs for this channel */
228 		writel(channel->back_buffer_busaddr, channel->irec +
229 			DMA_PRDS_BUSBASE_TP(0));
230 
231 		tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
232 		writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
233 
234 		writel(channel->back_buffer_busaddr, channel->irec +
235 			DMA_PRDS_BUSWP_TP(0));
236 
237 		/* Issue a reset and enable InputBlock */
238 		writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET
239 			, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
240 
241 		/* and enable the tp */
242 		writel(0x1, channel->irec + DMA_PRDS_TPENABLE);
243 
244 		dev_dbg(fei->dev, "%s:%d Starting DMA feed on stdemux=%p\n"
245 			, __func__, __LINE__, stdemux);
246 	}
247 
248 	stdemux->running_feed_count++;
249 	fei->global_feed_count++;
250 
251 	mutex_unlock(&fei->lock);
252 
253 	return 0;
254 }
255 
c8sectpfe_stop_feed(struct dvb_demux_feed * dvbdmxfeed)256 static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
257 {
258 
259 	struct dvb_demux *demux = dvbdmxfeed->demux;
260 	struct stdemux *stdemux = demux->priv;
261 	struct c8sectpfei *fei = stdemux->c8sectpfei;
262 	struct channel_info *channel;
263 	int idlereq;
264 	u32 tmp;
265 	int ret;
266 	unsigned long *bitmap;
267 
268 	if (!atomic_read(&fei->fw_loaded)) {
269 		ret = load_c8sectpfe_fw(fei);
270 		if (ret)
271 			return ret;
272 	}
273 
274 	mutex_lock(&fei->lock);
275 
276 	channel = fei->channel_data[stdemux->tsin_index];
277 
278 	bitmap = channel->pid_buffer_aligned;
279 
280 	if (dvbdmxfeed->pid == 8192) {
281 		tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
282 		tmp |= C8SECTPFE_PID_ENABLE;
283 		writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
284 	} else {
285 		bitmap_clear(bitmap, dvbdmxfeed->pid, 1);
286 	}
287 
288 	/* manage cache so data is visible to HW */
289 	dma_sync_single_for_device(fei->dev,
290 					channel->pid_buffer_busaddr,
291 					PID_TABLE_SIZE,
292 					DMA_TO_DEVICE);
293 
294 	if (--stdemux->running_feed_count == 0) {
295 
296 		channel = fei->channel_data[stdemux->tsin_index];
297 
298 		/* TP re-configuration on page 168 of functional spec */
299 
300 		/* disable IB (prevents more TS data going to memdma) */
301 		writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
302 
303 		/* disable this channels descriptor */
304 		writel(0,  channel->irec + DMA_PRDS_TPENABLE);
305 
306 		disable_work_sync(&channel->bh_work);
307 
308 		/* now request memdma channel goes idle */
309 		idlereq = (1 << channel->tsin_id) | IDLEREQ;
310 		writel(idlereq, fei->io + DMA_IDLE_REQ);
311 
312 		/* wait for idle irq handler to signal completion */
313 		ret = wait_for_completion_timeout(&channel->idle_completion,
314 						msecs_to_jiffies(100));
315 
316 		if (ret == 0)
317 			dev_warn(fei->dev,
318 				"Timeout waiting for idle irq on tsin%d\n",
319 				channel->tsin_id);
320 
321 		reinit_completion(&channel->idle_completion);
322 
323 		/* reset read / write ptrs for this channel */
324 
325 		writel(channel->back_buffer_busaddr,
326 			channel->irec + DMA_PRDS_BUSBASE_TP(0));
327 
328 		tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
329 		writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
330 
331 		writel(channel->back_buffer_busaddr,
332 			channel->irec + DMA_PRDS_BUSWP_TP(0));
333 
334 		dev_dbg(fei->dev,
335 			"%s:%d stopping DMA feed on stdemux=%p channel=%d\n",
336 			__func__, __LINE__, stdemux, channel->tsin_id);
337 
338 		/* turn off all PIDS in the bitmap */
339 		memset(channel->pid_buffer_aligned, 0, PID_TABLE_SIZE);
340 
341 		/* manage cache so data is visible to HW */
342 		dma_sync_single_for_device(fei->dev,
343 					channel->pid_buffer_busaddr,
344 					PID_TABLE_SIZE,
345 					DMA_TO_DEVICE);
346 
347 		channel->active = 0;
348 	}
349 
350 	if (--fei->global_feed_count == 0) {
351 		dev_dbg(fei->dev, "%s:%d global_feed_count=%d\n"
352 			, __func__, __LINE__, fei->global_feed_count);
353 
354 		timer_delete(&fei->timer);
355 	}
356 
357 	mutex_unlock(&fei->lock);
358 
359 	return 0;
360 }
361 
find_channel(struct c8sectpfei * fei,int tsin_num)362 static struct channel_info *find_channel(struct c8sectpfei *fei, int tsin_num)
363 {
364 	int i;
365 
366 	for (i = 0; i < C8SECTPFE_MAX_TSIN_CHAN; i++) {
367 		if (!fei->channel_data[i])
368 			continue;
369 
370 		if (fei->channel_data[i]->tsin_id == tsin_num)
371 			return fei->channel_data[i];
372 	}
373 
374 	return NULL;
375 }
376 
c8sectpfe_getconfig(struct c8sectpfei * fei)377 static void c8sectpfe_getconfig(struct c8sectpfei *fei)
378 {
379 	struct c8sectpfe_hw *hw = &fei->hw_stats;
380 
381 	hw->num_ib = readl(fei->io + SYS_CFG_NUM_IB);
382 	hw->num_mib = readl(fei->io + SYS_CFG_NUM_MIB);
383 	hw->num_swts = readl(fei->io + SYS_CFG_NUM_SWTS);
384 	hw->num_tsout = readl(fei->io + SYS_CFG_NUM_TSOUT);
385 	hw->num_ccsc = readl(fei->io + SYS_CFG_NUM_CCSC);
386 	hw->num_ram = readl(fei->io + SYS_CFG_NUM_RAM);
387 	hw->num_tp = readl(fei->io + SYS_CFG_NUM_TP);
388 
389 	dev_info(fei->dev, "C8SECTPFE hw supports the following:\n");
390 	dev_info(fei->dev, "Input Blocks: %d\n", hw->num_ib);
391 	dev_info(fei->dev, "Merged Input Blocks: %d\n", hw->num_mib);
392 	dev_info(fei->dev, "Software Transport Stream Inputs: %d\n"
393 				, hw->num_swts);
394 	dev_info(fei->dev, "Transport Stream Output: %d\n", hw->num_tsout);
395 	dev_info(fei->dev, "Cable Card Converter: %d\n", hw->num_ccsc);
396 	dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram);
397 	dev_info(fei->dev, "Tango TPs supported by C8SECTPFE: %d\n"
398 			, hw->num_tp);
399 }
400 
c8sectpfe_idle_irq_handler(int irq,void * priv)401 static irqreturn_t c8sectpfe_idle_irq_handler(int irq, void *priv)
402 {
403 	struct c8sectpfei *fei = priv;
404 	struct channel_info *chan;
405 	int bit;
406 	unsigned long tmp = readl(fei->io + DMA_IDLE_REQ);
407 
408 	/* page 168 of functional spec: Clear the idle request
409 	   by writing 0 to the C8SECTPFE_DMA_IDLE_REQ register. */
410 
411 	/* signal idle completion */
412 	for_each_set_bit(bit, &tmp, fei->hw_stats.num_ib) {
413 
414 		chan = find_channel(fei, bit);
415 
416 		if (chan)
417 			complete(&chan->idle_completion);
418 	}
419 
420 	writel(0, fei->io + DMA_IDLE_REQ);
421 
422 	return IRQ_HANDLED;
423 }
424 
425 
free_input_block(struct c8sectpfei * fei,struct channel_info * tsin)426 static void free_input_block(struct c8sectpfei *fei, struct channel_info *tsin)
427 {
428 	if (!fei || !tsin)
429 		return;
430 
431 	if (tsin->back_buffer_busaddr)
432 		if (!dma_mapping_error(fei->dev, tsin->back_buffer_busaddr))
433 			dma_unmap_single(fei->dev, tsin->back_buffer_busaddr,
434 				FEI_BUFFER_SIZE, DMA_BIDIRECTIONAL);
435 
436 	kfree(tsin->back_buffer_start);
437 
438 	if (tsin->pid_buffer_busaddr)
439 		if (!dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr))
440 			dma_unmap_single(fei->dev, tsin->pid_buffer_busaddr,
441 				PID_TABLE_SIZE, DMA_BIDIRECTIONAL);
442 
443 	kfree(tsin->pid_buffer_start);
444 }
445 
446 #define MAX_NAME 20
447 
configure_memdma_and_inputblock(struct c8sectpfei * fei,struct channel_info * tsin)448 static int configure_memdma_and_inputblock(struct c8sectpfei *fei,
449 				struct channel_info *tsin)
450 {
451 	int ret;
452 	u32 tmp;
453 	char tsin_pin_name[MAX_NAME];
454 
455 	if (!fei || !tsin)
456 		return -EINVAL;
457 
458 	dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n"
459 		, __func__, __LINE__, tsin, tsin->tsin_id);
460 
461 	init_completion(&tsin->idle_completion);
462 
463 	tsin->back_buffer_start = kzalloc(FEI_BUFFER_SIZE + FEI_ALIGNMENT, GFP_KERNEL);
464 	if (!tsin->back_buffer_start) {
465 		ret = -ENOMEM;
466 		goto err_unmap;
467 	}
468 
469 	/* Ensure backbuffer is 32byte aligned */
470 	tsin->back_buffer_aligned = tsin->back_buffer_start + FEI_ALIGNMENT;
471 
472 	tsin->back_buffer_aligned = PTR_ALIGN(tsin->back_buffer_aligned, FEI_ALIGNMENT);
473 
474 	tsin->back_buffer_busaddr = dma_map_single(fei->dev,
475 					tsin->back_buffer_aligned,
476 					FEI_BUFFER_SIZE,
477 					DMA_BIDIRECTIONAL);
478 
479 	if (dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) {
480 		dev_err(fei->dev, "failed to map back_buffer\n");
481 		ret = -EFAULT;
482 		goto err_unmap;
483 	}
484 
485 	/*
486 	 * The pid buffer can be configured (in hw) for byte or bit
487 	 * per pid. By powers of deduction we conclude stih407 family
488 	 * is configured (at SoC design stage) for bit per pid.
489 	 */
490 	tsin->pid_buffer_start = kzalloc(PID_TABLE_SIZE + PID_TABLE_SIZE, GFP_KERNEL);
491 	if (!tsin->pid_buffer_start) {
492 		ret = -ENOMEM;
493 		goto err_unmap;
494 	}
495 
496 	/*
497 	 * PID buffer needs to be aligned to size of the pid table
498 	 * which at bit per pid is 1024 bytes (8192 pids / 8).
499 	 * PIDF_BASE register enforces this alignment when writing
500 	 * the register.
501 	 */
502 
503 	tsin->pid_buffer_aligned = tsin->pid_buffer_start + PID_TABLE_SIZE;
504 
505 	tsin->pid_buffer_aligned = PTR_ALIGN(tsin->pid_buffer_aligned, PID_TABLE_SIZE);
506 
507 	tsin->pid_buffer_busaddr = dma_map_single(fei->dev,
508 						tsin->pid_buffer_aligned,
509 						PID_TABLE_SIZE,
510 						DMA_BIDIRECTIONAL);
511 
512 	if (dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) {
513 		dev_err(fei->dev, "failed to map pid_bitmap\n");
514 		ret = -EFAULT;
515 		goto err_unmap;
516 	}
517 
518 	/* manage cache so pid bitmap is visible to HW */
519 	dma_sync_single_for_device(fei->dev,
520 				tsin->pid_buffer_busaddr,
521 				PID_TABLE_SIZE,
522 				DMA_TO_DEVICE);
523 
524 	snprintf(tsin_pin_name, MAX_NAME, "tsin%d-%s", tsin->tsin_id,
525 		(tsin->serial_not_parallel ? "serial" : "parallel"));
526 
527 	tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name);
528 	if (IS_ERR(tsin->pstate)) {
529 		dev_err(fei->dev, "%s: pinctrl_lookup_state couldn't find %s state\n"
530 			, __func__, tsin_pin_name);
531 		ret = PTR_ERR(tsin->pstate);
532 		goto err_unmap;
533 	}
534 
535 	ret = pinctrl_select_state(fei->pinctrl, tsin->pstate);
536 
537 	if (ret) {
538 		dev_err(fei->dev, "%s: pinctrl_select_state failed\n"
539 			, __func__);
540 		goto err_unmap;
541 	}
542 
543 	/* Enable this input block */
544 	tmp = readl(fei->io + SYS_INPUT_CLKEN);
545 	tmp |= BIT(tsin->tsin_id);
546 	writel(tmp, fei->io + SYS_INPUT_CLKEN);
547 
548 	if (tsin->serial_not_parallel)
549 		tmp |= C8SECTPFE_SERIAL_NOT_PARALLEL;
550 
551 	if (tsin->invert_ts_clk)
552 		tmp |= C8SECTPFE_INVERT_TSCLK;
553 
554 	if (tsin->async_not_sync)
555 		tmp |= C8SECTPFE_ASYNC_NOT_SYNC;
556 
557 	tmp |= C8SECTPFE_ALIGN_BYTE_SOP | C8SECTPFE_BYTE_ENDIANNESS_MSB;
558 
559 	writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id));
560 
561 	writel(C8SECTPFE_SYNC(0x9) |
562 		C8SECTPFE_DROP(0x9) |
563 		C8SECTPFE_TOKEN(0x47),
564 		fei->io + C8SECTPFE_IB_SYNCLCKDRP_CFG(tsin->tsin_id));
565 
566 	writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id));
567 
568 	/* Place the FIFO's at the end of the irec descriptors */
569 
570 	tsin->fifo = (tsin->tsin_id * FIFO_LEN);
571 
572 	writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id));
573 	writel(tsin->fifo + FIFO_LEN - 1,
574 		fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id));
575 
576 	writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id));
577 	writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id));
578 
579 	writel(tsin->pid_buffer_busaddr,
580 		fei->io + PIDF_BASE(tsin->tsin_id));
581 
582 	dev_dbg(fei->dev, "chan=%d PIDF_BASE=0x%x pid_bus_addr=%pad\n",
583 		tsin->tsin_id, readl(fei->io + PIDF_BASE(tsin->tsin_id)),
584 		&tsin->pid_buffer_busaddr);
585 
586 	/* Configure and enable HW PID filtering */
587 
588 	/*
589 	 * The PID value is created by assembling the first 8 bytes of
590 	 * the TS packet into a 64-bit word in big-endian format. A
591 	 * slice of that 64-bit word is taken from
592 	 * (PID_OFFSET+PID_NUM_BITS-1) to PID_OFFSET.
593 	 */
594 	tmp = (C8SECTPFE_PID_ENABLE | C8SECTPFE_PID_NUMBITS(13)
595 		| C8SECTPFE_PID_OFFSET(40));
596 
597 	writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id));
598 
599 	dev_dbg(fei->dev, "chan=%d setting wp: %d, rp: %d, buf: %d-%d\n",
600 		tsin->tsin_id,
601 		readl(fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)),
602 		readl(fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)),
603 		readl(fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)),
604 		readl(fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id)));
605 
606 	/* Get base addpress of pointer record block from DMEM */
607 	tsin->irec = fei->io + DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET +
608 			readl(fei->io + DMA_PTRREC_BASE);
609 
610 	/* fill out pointer record data structure */
611 
612 	/* advance pointer record block to our channel */
613 	tsin->irec += (tsin->tsin_id * DMA_PRDS_SIZE);
614 
615 	writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE);
616 
617 	writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP);
618 
619 	writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE);
620 
621 	writel(0x1, tsin->irec + DMA_PRDS_TPENABLE);
622 
623 	/* read/write pointers with physical bus address */
624 
625 	writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0));
626 
627 	tmp = tsin->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
628 	writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0));
629 
630 	writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0));
631 	writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0));
632 
633 	/* initialize bh work */
634 	INIT_WORK(&tsin->bh_work, channel_swdemux_bh_work);
635 
636 	return 0;
637 
638 err_unmap:
639 	free_input_block(fei, tsin);
640 	return ret;
641 }
642 
c8sectpfe_error_irq_handler(int irq,void * priv)643 static irqreturn_t c8sectpfe_error_irq_handler(int irq, void *priv)
644 {
645 	struct c8sectpfei *fei = priv;
646 
647 	dev_err(fei->dev, "%s: error handling not yet implemented\n"
648 		, __func__);
649 
650 	/*
651 	 * TODO FIXME we should detect some error conditions here
652 	 * and ideally do something about them!
653 	 */
654 
655 	return IRQ_HANDLED;
656 }
657 
c8sectpfe_probe(struct platform_device * pdev)658 static int c8sectpfe_probe(struct platform_device *pdev)
659 {
660 	struct device *dev = &pdev->dev;
661 	struct device_node *child, *np = dev->of_node;
662 	struct c8sectpfei *fei;
663 	struct resource *res;
664 	int ret, index = 0;
665 	struct channel_info *tsin;
666 
667 	/* Allocate the c8sectpfei structure */
668 	fei = devm_kzalloc(dev, sizeof(struct c8sectpfei), GFP_KERNEL);
669 	if (!fei)
670 		return -ENOMEM;
671 
672 	fei->dev = dev;
673 
674 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "c8sectpfe");
675 	fei->io = devm_ioremap_resource(dev, res);
676 	if (IS_ERR(fei->io))
677 		return PTR_ERR(fei->io);
678 
679 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
680 					"c8sectpfe-ram");
681 	fei->sram = devm_ioremap_resource(dev, res);
682 	if (IS_ERR(fei->sram))
683 		return PTR_ERR(fei->sram);
684 
685 	fei->sram_size = resource_size(res);
686 
687 	fei->idle_irq = platform_get_irq_byname(pdev, "c8sectpfe-idle-irq");
688 	if (fei->idle_irq < 0)
689 		return fei->idle_irq;
690 
691 	fei->error_irq = platform_get_irq_byname(pdev, "c8sectpfe-error-irq");
692 	if (fei->error_irq < 0)
693 		return fei->error_irq;
694 
695 	platform_set_drvdata(pdev, fei);
696 
697 	fei->c8sectpfeclk = devm_clk_get_enabled(dev, "c8sectpfe");
698 	if (IS_ERR(fei->c8sectpfeclk)) {
699 		dev_err(dev, "Failed to enable c8sectpfe clock\n");
700 		return PTR_ERR(fei->c8sectpfeclk);
701 	}
702 
703 	/* to save power disable all IP's (on by default) */
704 	writel(0, fei->io + SYS_INPUT_CLKEN);
705 
706 	/* Enable memdma clock */
707 	writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN);
708 
709 	/* clear internal sram */
710 	memset_io(fei->sram, 0x0, fei->sram_size);
711 
712 	c8sectpfe_getconfig(fei);
713 
714 	ret = devm_request_irq(dev, fei->idle_irq, c8sectpfe_idle_irq_handler,
715 			0, "c8sectpfe-idle-irq", fei);
716 	if (ret) {
717 		dev_err(dev, "Can't register c8sectpfe-idle-irq IRQ.\n");
718 		return ret;
719 	}
720 
721 	ret = devm_request_irq(dev, fei->error_irq,
722 				c8sectpfe_error_irq_handler, 0,
723 				"c8sectpfe-error-irq", fei);
724 	if (ret) {
725 		dev_err(dev, "Can't register c8sectpfe-error-irq IRQ.\n");
726 		return ret;
727 	}
728 
729 	fei->tsin_count = of_get_child_count(np);
730 
731 	if (fei->tsin_count > C8SECTPFE_MAX_TSIN_CHAN ||
732 		fei->tsin_count > fei->hw_stats.num_ib) {
733 
734 		dev_err(dev, "More tsin declared than exist on SoC!\n");
735 		return -EINVAL;
736 	}
737 
738 	fei->pinctrl = devm_pinctrl_get(dev);
739 
740 	if (IS_ERR(fei->pinctrl)) {
741 		dev_err(dev, "Error getting tsin pins\n");
742 		return PTR_ERR(fei->pinctrl);
743 	}
744 
745 	for_each_child_of_node(np, child) {
746 		struct device_node *i2c_bus;
747 
748 		fei->channel_data[index] = devm_kzalloc(dev,
749 						sizeof(struct channel_info),
750 						GFP_KERNEL);
751 
752 		if (!fei->channel_data[index]) {
753 			ret = -ENOMEM;
754 			goto err_node_put;
755 		}
756 
757 		tsin = fei->channel_data[index];
758 
759 		tsin->fei = fei;
760 
761 		ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id);
762 		if (ret) {
763 			dev_err(&pdev->dev, "No tsin_num found\n");
764 			goto err_node_put;
765 		}
766 
767 		/* sanity check value */
768 		if (tsin->tsin_id > fei->hw_stats.num_ib) {
769 			dev_err(&pdev->dev,
770 				"tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)",
771 				tsin->tsin_id, fei->hw_stats.num_ib);
772 			ret = -EINVAL;
773 			goto err_node_put;
774 		}
775 
776 		tsin->invert_ts_clk = of_property_read_bool(child,
777 							"invert-ts-clk");
778 
779 		tsin->serial_not_parallel = of_property_read_bool(child,
780 							"serial-not-parallel");
781 
782 		tsin->async_not_sync = of_property_read_bool(child,
783 							"async-not-sync");
784 
785 		ret = of_property_read_u32(child, "dvb-card",
786 					&tsin->dvb_card);
787 		if (ret) {
788 			dev_err(&pdev->dev, "No dvb-card found\n");
789 			goto err_node_put;
790 		}
791 
792 		i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
793 		if (!i2c_bus) {
794 			dev_err(&pdev->dev, "No i2c-bus found\n");
795 			ret = -ENODEV;
796 			goto err_node_put;
797 		}
798 		tsin->i2c_adapter =
799 			of_find_i2c_adapter_by_node(i2c_bus);
800 		of_node_put(i2c_bus);
801 		if (!tsin->i2c_adapter) {
802 			dev_err(&pdev->dev, "No i2c adapter found\n");
803 			ret = -ENODEV;
804 			goto err_node_put;
805 		}
806 
807 		/* Acquire reset GPIO and activate it */
808 		tsin->rst_gpio = devm_fwnode_gpiod_get(dev,
809 						       of_fwnode_handle(child),
810 						       "reset", GPIOD_OUT_HIGH,
811 						       "NIM reset");
812 		ret = PTR_ERR_OR_ZERO(tsin->rst_gpio);
813 		if (ret && ret != -EBUSY) {
814 			dev_err(dev, "Can't request tsin%d reset gpio\n",
815 				fei->channel_data[index]->tsin_id);
816 			goto err_node_put;
817 		}
818 
819 		if (!ret) {
820 			/* wait for the chip to reset */
821 			usleep_range(3500, 5000);
822 			/* release the reset line */
823 			gpiod_set_value_cansleep(tsin->rst_gpio, 0);
824 			usleep_range(3000, 5000);
825 		}
826 
827 		tsin->demux_mapping = index;
828 
829 		dev_dbg(fei->dev,
830 			"channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
831 			fei->channel_data[index], index,
832 			tsin->tsin_id, tsin->invert_ts_clk,
833 			tsin->serial_not_parallel, tsin->async_not_sync,
834 			tsin->dvb_card);
835 
836 		index++;
837 	}
838 
839 	/* Setup timer interrupt */
840 	timer_setup(&fei->timer, c8sectpfe_timer_interrupt, 0);
841 
842 	mutex_init(&fei->lock);
843 
844 	/* Get the configuration information about the tuners */
845 	ret = c8sectpfe_tuner_register_frontend(&fei->c8sectpfe[0],
846 					(void *)fei,
847 					c8sectpfe_start_feed,
848 					c8sectpfe_stop_feed);
849 	if (ret) {
850 		dev_err(dev, "c8sectpfe_tuner_register_frontend failed (%d)\n",
851 			ret);
852 		return ret;
853 	}
854 
855 	c8sectpfe_debugfs_init(fei);
856 
857 	return 0;
858 
859 err_node_put:
860 	of_node_put(child);
861 	return ret;
862 }
863 
c8sectpfe_remove(struct platform_device * pdev)864 static void c8sectpfe_remove(struct platform_device *pdev)
865 {
866 	struct c8sectpfei *fei = platform_get_drvdata(pdev);
867 	struct channel_info *channel;
868 	int i;
869 
870 	wait_for_completion(&fei->fw_ack);
871 
872 	c8sectpfe_tuner_unregister_frontend(fei->c8sectpfe[0], fei);
873 
874 	/*
875 	 * Now loop through and un-configure each of the InputBlock resources
876 	 */
877 	for (i = 0; i < fei->tsin_count; i++) {
878 		channel = fei->channel_data[i];
879 		free_input_block(fei, channel);
880 	}
881 
882 	c8sectpfe_debugfs_exit(fei);
883 
884 	dev_info(fei->dev, "Stopping memdma SLIM core\n");
885 	if (readl(fei->io + DMA_CPU_RUN))
886 		writel(0x0,  fei->io + DMA_CPU_RUN);
887 
888 	/* unclock all internal IP's */
889 	if (readl(fei->io + SYS_INPUT_CLKEN))
890 		writel(0, fei->io + SYS_INPUT_CLKEN);
891 
892 	if (readl(fei->io + SYS_OTHER_CLKEN))
893 		writel(0, fei->io + SYS_OTHER_CLKEN);
894 }
895 
896 
configure_channels(struct c8sectpfei * fei)897 static int configure_channels(struct c8sectpfei *fei)
898 {
899 	int index = 0, ret;
900 	struct device_node *child, *np = fei->dev->of_node;
901 
902 	/* iterate round each tsin and configure memdma descriptor and IB hw */
903 	for_each_child_of_node(np, child) {
904 		ret = configure_memdma_and_inputblock(fei,
905 						fei->channel_data[index]);
906 		if (ret) {
907 			dev_err(fei->dev,
908 				"configure_memdma_and_inputblock failed\n");
909 			of_node_put(child);
910 			goto err_unmap;
911 		}
912 		index++;
913 	}
914 
915 	return 0;
916 
917 err_unmap:
918 	while (--index >= 0)
919 		free_input_block(fei, fei->channel_data[index]);
920 
921 	return ret;
922 }
923 
924 static int
c8sectpfe_elf_sanity_check(struct c8sectpfei * fei,const struct firmware * fw)925 c8sectpfe_elf_sanity_check(struct c8sectpfei *fei, const struct firmware *fw)
926 {
927 	struct elf32_hdr *ehdr;
928 	char class;
929 
930 	if (!fw) {
931 		dev_err(fei->dev, "failed to load %s\n", FIRMWARE_MEMDMA);
932 		return -EINVAL;
933 	}
934 
935 	if (fw->size < sizeof(struct elf32_hdr)) {
936 		dev_err(fei->dev, "Image is too small\n");
937 		return -EINVAL;
938 	}
939 
940 	ehdr = (struct elf32_hdr *)fw->data;
941 
942 	/* We only support ELF32 at this point */
943 	class = ehdr->e_ident[EI_CLASS];
944 	if (class != ELFCLASS32) {
945 		dev_err(fei->dev, "Unsupported class: %d\n", class);
946 		return -EINVAL;
947 	}
948 
949 	if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
950 		dev_err(fei->dev, "Unsupported firmware endianness\n");
951 		return -EINVAL;
952 	}
953 
954 	if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) {
955 		dev_err(fei->dev, "Image is too small\n");
956 		return -EINVAL;
957 	}
958 
959 	if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
960 		dev_err(fei->dev, "Image is corrupted (bad magic)\n");
961 		return -EINVAL;
962 	}
963 
964 	/* Check ELF magic */
965 	ehdr = (Elf32_Ehdr *)fw->data;
966 	if (ehdr->e_ident[EI_MAG0] != ELFMAG0 ||
967 	    ehdr->e_ident[EI_MAG1] != ELFMAG1 ||
968 	    ehdr->e_ident[EI_MAG2] != ELFMAG2 ||
969 	    ehdr->e_ident[EI_MAG3] != ELFMAG3) {
970 		dev_err(fei->dev, "Invalid ELF magic\n");
971 		return -EINVAL;
972 	}
973 
974 	if (ehdr->e_type != ET_EXEC) {
975 		dev_err(fei->dev, "Unsupported ELF header type\n");
976 		return -EINVAL;
977 	}
978 
979 	if (ehdr->e_phoff > fw->size) {
980 		dev_err(fei->dev, "Firmware size is too small\n");
981 		return -EINVAL;
982 	}
983 
984 	return 0;
985 }
986 
987 
load_imem_segment(struct c8sectpfei * fei,Elf32_Phdr * phdr,const struct firmware * fw,u8 __iomem * dest,int seg_num)988 static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
989 			const struct firmware *fw, u8 __iomem *dest,
990 			int seg_num)
991 {
992 	const u8 *imem_src = fw->data + phdr->p_offset;
993 	int i;
994 
995 	/*
996 	 * For IMEM segments, the segment contains 24-bit
997 	 * instructions which must be padded to 32-bit
998 	 * instructions before being written. The written
999 	 * segment is padded with NOP instructions.
1000 	 */
1001 
1002 	dev_dbg(fei->dev,
1003 		"Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n",
1004 		seg_num, phdr->p_paddr, phdr->p_filesz, dest,
1005 		phdr->p_memsz + phdr->p_memsz / 3);
1006 
1007 	for (i = 0; i < phdr->p_filesz; i++) {
1008 
1009 		writeb(readb((void __iomem *)imem_src), (void __iomem *)dest);
1010 
1011 		/* Every 3 bytes, add an additional
1012 		 * padding zero in destination */
1013 		if (i % 3 == 2) {
1014 			dest++;
1015 			writeb(0x00, (void __iomem *)dest);
1016 		}
1017 
1018 		dest++;
1019 		imem_src++;
1020 	}
1021 }
1022 
load_dmem_segment(struct c8sectpfei * fei,Elf32_Phdr * phdr,const struct firmware * fw,u8 __iomem * dst,int seg_num)1023 static void load_dmem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1024 			const struct firmware *fw, u8 __iomem *dst, int seg_num)
1025 {
1026 	/*
1027 	 * For DMEM segments copy the segment data from the ELF
1028 	 * file and pad segment with zeroes
1029 	 */
1030 
1031 	dev_dbg(fei->dev,
1032 		"Loading DMEM segment %d 0x%08x\n\t(0x%x bytes) -> 0x%p (0x%x bytes)\n",
1033 		seg_num, phdr->p_paddr, phdr->p_filesz,
1034 		dst, phdr->p_memsz);
1035 
1036 	memcpy((void __force *)dst, (void *)fw->data + phdr->p_offset,
1037 		phdr->p_filesz);
1038 
1039 	memset((void __force *)dst + phdr->p_filesz, 0,
1040 		phdr->p_memsz - phdr->p_filesz);
1041 }
1042 
load_slim_core_fw(const struct firmware * fw,struct c8sectpfei * fei)1043 static int load_slim_core_fw(const struct firmware *fw, struct c8sectpfei *fei)
1044 {
1045 	Elf32_Ehdr *ehdr;
1046 	Elf32_Phdr *phdr;
1047 	u8 __iomem *dst;
1048 	int err = 0, i;
1049 
1050 	if (!fw || !fei)
1051 		return -EINVAL;
1052 
1053 	ehdr = (Elf32_Ehdr *)fw->data;
1054 	phdr = (Elf32_Phdr *)(fw->data + ehdr->e_phoff);
1055 
1056 	/* go through the available ELF segments */
1057 	for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
1058 
1059 		/* Only consider LOAD segments */
1060 		if (phdr->p_type != PT_LOAD)
1061 			continue;
1062 
1063 		/*
1064 		 * Check segment is contained within the fw->data buffer
1065 		 */
1066 		if (phdr->p_offset + phdr->p_filesz > fw->size) {
1067 			dev_err(fei->dev,
1068 				"Segment %d is outside of firmware file\n", i);
1069 			err = -EINVAL;
1070 			break;
1071 		}
1072 
1073 		/*
1074 		 * MEMDMA IMEM has executable flag set, otherwise load
1075 		 * this segment into DMEM.
1076 		 *
1077 		 */
1078 
1079 		if (phdr->p_flags & PF_X) {
1080 			dst = (u8 __iomem *) fei->io + DMA_MEMDMA_IMEM;
1081 			/*
1082 			 * The Slim ELF file uses 32-bit word addressing for
1083 			 * load offsets.
1084 			 */
1085 			dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1086 			load_imem_segment(fei, phdr, fw, dst, i);
1087 		} else {
1088 			dst = (u8 __iomem *) fei->io + DMA_MEMDMA_DMEM;
1089 			/*
1090 			 * The Slim ELF file uses 32-bit word addressing for
1091 			 * load offsets.
1092 			 */
1093 			dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1094 			load_dmem_segment(fei, phdr, fw, dst, i);
1095 		}
1096 	}
1097 
1098 	return err;
1099 }
1100 
load_c8sectpfe_fw(struct c8sectpfei * fei)1101 static int load_c8sectpfe_fw(struct c8sectpfei *fei)
1102 {
1103 	const struct firmware *fw;
1104 	int err;
1105 
1106 	dev_info(fei->dev, "Loading firmware: %s\n", FIRMWARE_MEMDMA);
1107 
1108 	err = request_firmware(&fw, FIRMWARE_MEMDMA, fei->dev);
1109 	if (err)
1110 		return err;
1111 
1112 	err = c8sectpfe_elf_sanity_check(fei, fw);
1113 	if (err) {
1114 		dev_err(fei->dev, "c8sectpfe_elf_sanity_check failed err=(%d)\n"
1115 			, err);
1116 		release_firmware(fw);
1117 		return err;
1118 	}
1119 
1120 	err = load_slim_core_fw(fw, fei);
1121 	release_firmware(fw);
1122 	if (err) {
1123 		dev_err(fei->dev, "load_slim_core_fw failed err=(%d)\n", err);
1124 		return err;
1125 	}
1126 
1127 	/* now the firmware is loaded configure the input blocks */
1128 	err = configure_channels(fei);
1129 	if (err) {
1130 		dev_err(fei->dev, "configure_channels failed err=(%d)\n", err);
1131 		return err;
1132 	}
1133 
1134 	/*
1135 	 * STBus target port can access IMEM and DMEM ports
1136 	 * without waiting for CPU
1137 	 */
1138 	writel(0x1, fei->io + DMA_PER_STBUS_SYNC);
1139 
1140 	dev_info(fei->dev, "Boot the memdma SLIM core\n");
1141 	writel(0x1,  fei->io + DMA_CPU_RUN);
1142 
1143 	atomic_set(&fei->fw_loaded, 1);
1144 
1145 	return 0;
1146 }
1147 
1148 static const struct of_device_id c8sectpfe_match[] = {
1149 	{ .compatible = "st,stih407-c8sectpfe" },
1150 	{ /* sentinel */ },
1151 };
1152 MODULE_DEVICE_TABLE(of, c8sectpfe_match);
1153 
1154 static struct platform_driver c8sectpfe_driver = {
1155 	.driver = {
1156 		.name = "c8sectpfe",
1157 		.of_match_table = c8sectpfe_match,
1158 	},
1159 	.probe	= c8sectpfe_probe,
1160 	.remove = c8sectpfe_remove,
1161 };
1162 
1163 module_platform_driver(c8sectpfe_driver);
1164 
1165 MODULE_AUTHOR("Peter Bennett <peter.bennett@st.com>");
1166 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
1167 MODULE_DESCRIPTION("C8SECTPFE STi DVB Driver");
1168 MODULE_LICENSE("GPL");
1169