1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU_13_0_6_PMFW_H 24 #define SMU_13_0_6_PMFW_H 25 26 #define NUM_VCLK_DPM_LEVELS 4 27 #define NUM_DCLK_DPM_LEVELS 4 28 #define NUM_SOCCLK_DPM_LEVELS 4 29 #define NUM_LCLK_DPM_LEVELS 4 30 #define NUM_UCLK_DPM_LEVELS 4 31 #define NUM_FCLK_DPM_LEVELS 4 32 #define NUM_XGMI_DPM_LEVELS 2 33 #define NUM_CXL_BITRATES 4 34 #define NUM_PCIE_BITRATES 4 35 #define NUM_XGMI_BITRATES 4 36 #define NUM_XGMI_WIDTHS 3 37 38 typedef enum { 39 /*0*/ FEATURE_DATA_CALCULATION = 0, 40 /*1*/ FEATURE_DPM_CCLK = 1, 41 /*2*/ FEATURE_DPM_FCLK = 2, 42 /*3*/ FEATURE_DPM_GFXCLK = 3, 43 /*4*/ FEATURE_DPM_LCLK = 4, 44 /*5*/ FEATURE_DPM_SOCCLK = 5, 45 /*6*/ FEATURE_DPM_UCLK = 6, 46 /*7*/ FEATURE_DPM_VCN = 7, 47 /*8*/ FEATURE_DPM_XGMI = 8, 48 /*9*/ FEATURE_DS_FCLK = 9, 49 /*10*/ FEATURE_DS_GFXCLK = 10, 50 /*11*/ FEATURE_DS_LCLK = 11, 51 /*12*/ FEATURE_DS_MP0CLK = 12, 52 /*13*/ FEATURE_DS_MP1CLK = 13, 53 /*14*/ FEATURE_DS_MPIOCLK = 14, 54 /*15*/ FEATURE_DS_SOCCLK = 15, 55 /*16*/ FEATURE_DS_VCN = 16, 56 /*17*/ FEATURE_APCC_DFLL = 17, 57 /*18*/ FEATURE_APCC_PLUS = 18, 58 /*19*/ FEATURE_DF_CSTATE = 19, 59 /*20*/ FEATURE_CC6 = 20, 60 /*21*/ FEATURE_PC6 = 21, 61 /*22*/ FEATURE_CPPC = 22, 62 /*23*/ FEATURE_PPT = 23, 63 /*24*/ FEATURE_TDC = 24, 64 /*25*/ FEATURE_THERMAL = 25, 65 /*26*/ FEATURE_SOC_PCC = 26, 66 /*27*/ FEATURE_CCD_PCC = 27, 67 /*28*/ FEATURE_CCD_EDC = 28, 68 /*29*/ FEATURE_PROCHOT = 29, 69 /*30*/ FEATURE_DVO_CCLK = 30, 70 /*31*/ FEATURE_FDD_AID_HBM = 31, 71 /*32*/ FEATURE_FDD_AID_SOC = 32, 72 /*33*/ FEATURE_FDD_XCD_EDC = 33, 73 /*34*/ FEATURE_FDD_XCD_XVMIN = 34, 74 /*35*/ FEATURE_FW_CTF = 35, 75 /*36*/ FEATURE_GFXOFF = 36, 76 /*37*/ FEATURE_SMU_CG = 37, 77 /*38*/ FEATURE_PSI7 = 38, 78 /*39*/ FEATURE_CSTATE_BOOST = 39, 79 /*40*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 40, 80 /*41*/ FEATURE_CXL_QOS = 41, 81 /*42*/ FEATURE_SOC_DC_RTC = 42, 82 /*43*/ FEATURE_GFX_DC_RTC = 43, 83 84 /*44*/ NUM_FEATURES = 44 85 } FEATURE_LIST_e; 86 87 //enum for MPIO PCIe gen speed msgs 88 typedef enum { 89 PCIE_LINK_SPEED_INDEX_TABLE_GEN1, 90 PCIE_LINK_SPEED_INDEX_TABLE_GEN2, 91 PCIE_LINK_SPEED_INDEX_TABLE_GEN3, 92 PCIE_LINK_SPEED_INDEX_TABLE_GEN4, 93 PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM, 94 PCIE_LINK_SPEED_INDEX_TABLE_GEN5, 95 PCIE_LINK_SPEED_INDEX_TABLE_COUNT 96 } PCIE_LINK_SPEED_INDEX_TABLE_e; 97 98 typedef enum { 99 VOLTAGE_COLD_0, 100 VOLTAGE_COLD_1, 101 VOLTAGE_COLD_2, 102 VOLTAGE_COLD_3, 103 VOLTAGE_COLD_4, 104 VOLTAGE_COLD_5, 105 VOLTAGE_COLD_6, 106 VOLTAGE_COLD_7, 107 VOLTAGE_MID_0, 108 VOLTAGE_MID_1, 109 VOLTAGE_MID_2, 110 VOLTAGE_MID_3, 111 VOLTAGE_MID_4, 112 VOLTAGE_MID_5, 113 VOLTAGE_MID_6, 114 VOLTAGE_MID_7, 115 VOLTAGE_HOT_0, 116 VOLTAGE_HOT_1, 117 VOLTAGE_HOT_2, 118 VOLTAGE_HOT_3, 119 VOLTAGE_HOT_4, 120 VOLTAGE_HOT_5, 121 VOLTAGE_HOT_6, 122 VOLTAGE_HOT_7, 123 VOLTAGE_GUARDBAND_COUNT 124 } GFX_GUARDBAND_e; 125 126 #define SMU_METRICS_TABLE_VERSION 0xD 127 128 typedef struct __attribute__((packed, aligned(4))) { 129 uint32_t AccumulationCounter; 130 131 //TEMPERATURE 132 uint32_t MaxSocketTemperature; 133 uint32_t MaxVrTemperature; 134 uint32_t MaxHbmTemperature; 135 uint64_t MaxSocketTemperatureAcc; 136 uint64_t MaxVrTemperatureAcc; 137 uint64_t MaxHbmTemperatureAcc; 138 139 //POWER 140 uint32_t SocketPowerLimit; 141 uint32_t MaxSocketPowerLimit; 142 uint32_t SocketPower; 143 144 //ENERGY 145 uint64_t Timestamp; 146 uint64_t SocketEnergyAcc; 147 uint64_t CcdEnergyAcc; 148 uint64_t XcdEnergyAcc; 149 uint64_t AidEnergyAcc; 150 uint64_t HbmEnergyAcc; 151 152 //FREQUENCY 153 uint32_t CclkFrequencyLimit; 154 uint32_t GfxclkFrequencyLimit; 155 uint32_t FclkFrequency; 156 uint32_t UclkFrequency; 157 uint32_t SocclkFrequency[4]; 158 uint32_t VclkFrequency[4]; 159 uint32_t DclkFrequency[4]; 160 uint32_t LclkFrequency[4]; 161 uint64_t GfxclkFrequencyAcc[8]; 162 uint64_t CclkFrequencyAcc[96]; 163 164 //FREQUENCY RANGE 165 uint32_t MaxCclkFrequency; 166 uint32_t MinCclkFrequency; 167 uint32_t MaxGfxclkFrequency; 168 uint32_t MinGfxclkFrequency; 169 uint32_t FclkFrequencyTable[4]; 170 uint32_t UclkFrequencyTable[4]; 171 uint32_t SocclkFrequencyTable[4]; 172 uint32_t VclkFrequencyTable[4]; 173 uint32_t DclkFrequencyTable[4]; 174 uint32_t LclkFrequencyTable[4]; 175 uint32_t MaxLclkDpmRange; 176 uint32_t MinLclkDpmRange; 177 178 //XGMI 179 uint32_t XgmiWidth; 180 uint32_t XgmiBitrate; 181 uint64_t XgmiReadBandwidthAcc[8]; 182 uint64_t XgmiWriteBandwidthAcc[8]; 183 184 //ACTIVITY 185 uint32_t SocketC0Residency; 186 uint32_t SocketGfxBusy; 187 uint32_t DramBandwidthUtilization; 188 uint64_t SocketC0ResidencyAcc; 189 uint64_t SocketGfxBusyAcc; 190 uint64_t DramBandwidthAcc; 191 uint32_t MaxDramBandwidth; 192 uint64_t DramBandwidthUtilizationAcc; 193 uint64_t PcieBandwidthAcc[4]; 194 195 //THROTTLERS 196 uint32_t ProchotResidencyAcc; 197 uint32_t PptResidencyAcc; 198 uint32_t SocketThmResidencyAcc; 199 uint32_t VrThmResidencyAcc; 200 uint32_t HbmThmResidencyAcc; 201 uint32_t GfxLockXCDMak; 202 203 // New Items at end to maintain driver compatibility 204 uint32_t GfxclkFrequency[8]; 205 206 //PSNs 207 uint64_t PublicSerialNumber_AID[4]; 208 uint64_t PublicSerialNumber_XCD[8]; 209 uint64_t PublicSerialNumber_CCD[12]; 210 211 //XGMI Data tranfser size 212 uint64_t XgmiReadDataSizeAcc[8];//in KByte 213 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 214 215 //PCIE BW Data and error count 216 uint32_t PcieBandwidth[4]; 217 uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated 218 uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated 219 uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated 220 uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated 221 uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated 222 223 // VCN/JPEG ACTIVITY 224 uint32_t VcnBusy[4]; 225 uint32_t JpegBusy[32]; 226 227 // PCIE LINK Speed and width 228 uint32_t PCIeLinkSpeed; 229 uint32_t PCIeLinkWidth; 230 231 // PER XCD ACTIVITY 232 uint32_t GfxBusy[8]; 233 uint64_t GfxBusyAcc[8]; 234 } MetricsTableX_t; 235 236 typedef struct __attribute__((packed, aligned(4))) { 237 uint32_t AccumulationCounter; 238 239 //TEMPERATURE 240 uint32_t MaxSocketTemperature; 241 uint32_t MaxVrTemperature; 242 uint32_t MaxHbmTemperature; 243 uint64_t MaxSocketTemperatureAcc; 244 uint64_t MaxVrTemperatureAcc; 245 uint64_t MaxHbmTemperatureAcc; 246 247 //POWER 248 uint32_t SocketPowerLimit; 249 uint32_t MaxSocketPowerLimit; 250 uint32_t SocketPower; 251 252 //ENERGY 253 uint64_t Timestamp; 254 uint64_t SocketEnergyAcc; 255 uint64_t CcdEnergyAcc; 256 uint64_t XcdEnergyAcc; 257 uint64_t AidEnergyAcc; 258 uint64_t HbmEnergyAcc; 259 260 //FREQUENCY 261 uint32_t CclkFrequencyLimit; 262 uint32_t GfxclkFrequencyLimit; 263 uint32_t FclkFrequency; 264 uint32_t UclkFrequency; 265 uint32_t SocclkFrequency[4]; 266 uint32_t VclkFrequency[4]; 267 uint32_t DclkFrequency[4]; 268 uint32_t LclkFrequency[4]; 269 uint64_t GfxclkFrequencyAcc[8]; 270 uint64_t CclkFrequencyAcc[96]; 271 272 //FREQUENCY RANGE 273 uint32_t MaxCclkFrequency; 274 uint32_t MinCclkFrequency; 275 uint32_t MaxGfxclkFrequency; 276 uint32_t MinGfxclkFrequency; 277 uint32_t FclkFrequencyTable[4]; 278 uint32_t UclkFrequencyTable[4]; 279 uint32_t SocclkFrequencyTable[4]; 280 uint32_t VclkFrequencyTable[4]; 281 uint32_t DclkFrequencyTable[4]; 282 uint32_t LclkFrequencyTable[4]; 283 uint32_t MaxLclkDpmRange; 284 uint32_t MinLclkDpmRange; 285 286 //XGMI 287 uint32_t XgmiWidth; 288 uint32_t XgmiBitrate; 289 uint64_t XgmiReadBandwidthAcc[8]; 290 uint64_t XgmiWriteBandwidthAcc[8]; 291 292 //ACTIVITY 293 uint32_t SocketC0Residency; 294 uint32_t SocketGfxBusy; 295 uint32_t DramBandwidthUtilization; 296 uint64_t SocketC0ResidencyAcc; 297 uint64_t SocketGfxBusyAcc; 298 uint64_t DramBandwidthAcc; 299 uint32_t MaxDramBandwidth; 300 uint64_t DramBandwidthUtilizationAcc; 301 uint64_t PcieBandwidthAcc[4]; 302 303 //THROTTLERS 304 uint32_t ProchotResidencyAcc; 305 uint32_t PptResidencyAcc; 306 uint32_t SocketThmResidencyAcc; 307 uint32_t VrThmResidencyAcc; 308 uint32_t HbmThmResidencyAcc; 309 uint32_t GfxLockXCDMak; 310 311 // New Items at end to maintain driver compatibility 312 uint32_t GfxclkFrequency[8]; 313 314 //PSNs 315 uint64_t PublicSerialNumber_AID[4]; 316 uint64_t PublicSerialNumber_XCD[8]; 317 uint64_t PublicSerialNumber_CCD[12]; 318 319 //XGMI Data tranfser size 320 uint64_t XgmiReadDataSizeAcc[8];//in KByte 321 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 322 323 // VCN/JPEG ACTIVITY 324 uint32_t VcnBusy[4]; 325 uint32_t JpegBusy[32]; 326 } MetricsTableA_t; 327 328 #define SMU_VF_METRICS_TABLE_VERSION 0x3 329 330 typedef struct __attribute__((packed, aligned(4))) { 331 uint32_t AccumulationCounter; 332 uint32_t InstGfxclk_TargFreq; 333 uint64_t AccGfxclk_TargFreq; 334 uint64_t AccGfxRsmuDpm_Busy; 335 } VfMetricsTable_t; 336 337 #endif 338