1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes
83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes
84 * Panther Lake-H (SOC) 0xe322 32 hard yes yes yes
85 * Panther Lake-P (SOC) 0xe422 32 hard yes yes yes
86 * Wildcat Lake-U (SOC) 0x4d22 32 hard yes yes yes
87 * Diamond Rapids (SOC) 0x5827 32 hard yes yes yes
88 *
89 * Features supported by this driver:
90 * Software PEC no
91 * Hardware PEC yes
92 * Block buffer yes
93 * Block process call transaction yes
94 * I2C block read transaction yes (doesn't use the block buffer)
95 * Target mode no
96 * SMBus Host Notify yes
97 * Interrupt processing yes
98 *
99 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
100 */
101
102 #define DRV_NAME "i801_smbus"
103
104 #include <linux/interrupt.h>
105 #include <linux/module.h>
106 #include <linux/pci.h>
107 #include <linux/kernel.h>
108 #include <linux/stddef.h>
109 #include <linux/delay.h>
110 #include <linux/ioport.h>
111 #include <linux/init.h>
112 #include <linux/i2c.h>
113 #include <linux/i2c-mux.h>
114 #include <linux/i2c-smbus.h>
115 #include <linux/acpi.h>
116 #include <linux/io.h>
117 #include <linux/dmi.h>
118 #include <linux/slab.h>
119 #include <linux/string.h>
120 #include <linux/completion.h>
121 #include <linux/err.h>
122 #include <linux/platform_device.h>
123 #include <linux/platform_data/itco_wdt.h>
124 #include <linux/platform_data/x86/p2sb.h>
125 #include <linux/pm_runtime.h>
126 #include <linux/mutex.h>
127
128 #ifdef CONFIG_I2C_I801_MUX
129 #include <linux/gpio/machine.h>
130 #include <linux/platform_data/i2c-mux-gpio.h>
131 #endif
132
133 /* I801 SMBus address offsets */
134 #define SMBHSTSTS(p) (0 + (p)->smba)
135 #define SMBHSTCNT(p) (2 + (p)->smba)
136 #define SMBHSTCMD(p) (3 + (p)->smba)
137 #define SMBHSTADD(p) (4 + (p)->smba)
138 #define SMBHSTDAT0(p) (5 + (p)->smba)
139 #define SMBHSTDAT1(p) (6 + (p)->smba)
140 #define SMBBLKDAT(p) (7 + (p)->smba)
141 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
142 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
143 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
144 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
145 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
146 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
147
148 /* PCI Address Constants */
149 #define SMBBAR_MMIO 0
150 #define SMBBAR 4
151 #define SMBHSTCFG 0x040
152 #define TCOBASE 0x050
153 #define TCOCTL 0x054
154
155 #define SBREG_SMBCTRL 0xc6000c
156 #define SBREG_SMBCTRL_DNV 0xcf000c
157
158 /* Host configuration bits for SMBHSTCFG */
159 #define SMBHSTCFG_HST_EN BIT(0)
160 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
161 #define SMBHSTCFG_I2C_EN BIT(2)
162 #define SMBHSTCFG_SPD_WD BIT(4)
163
164 /* TCO configuration bits for TCOCTL */
165 #define TCOCTL_EN BIT(8)
166
167 /* Auxiliary status register bits, ICH4+ only */
168 #define SMBAUXSTS_CRCE BIT(0)
169 #define SMBAUXSTS_STCO BIT(1)
170
171 /* Auxiliary control register bits, ICH4+ only */
172 #define SMBAUXCTL_CRC BIT(0)
173 #define SMBAUXCTL_E32B BIT(1)
174
175 /* I801 command constants */
176 #define I801_QUICK 0x00
177 #define I801_BYTE 0x04
178 #define I801_BYTE_DATA 0x08
179 #define I801_WORD_DATA 0x0C
180 #define I801_PROC_CALL 0x10
181 #define I801_BLOCK_DATA 0x14
182 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
183 #define I801_BLOCK_PROC_CALL 0x1C
184
185 /* I801 Host Control register bits */
186 #define SMBHSTCNT_INTREN BIT(0)
187 #define SMBHSTCNT_KILL BIT(1)
188 #define SMBHSTCNT_LAST_BYTE BIT(5)
189 #define SMBHSTCNT_START BIT(6)
190 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
191
192 /* I801 Hosts Status register bits */
193 #define SMBHSTSTS_BYTE_DONE BIT(7)
194 #define SMBHSTSTS_INUSE_STS BIT(6)
195 #define SMBHSTSTS_SMBALERT_STS BIT(5)
196 #define SMBHSTSTS_FAILED BIT(4)
197 #define SMBHSTSTS_BUS_ERR BIT(3)
198 #define SMBHSTSTS_DEV_ERR BIT(2)
199 #define SMBHSTSTS_INTR BIT(1)
200 #define SMBHSTSTS_HOST_BUSY BIT(0)
201
202 /* Host Notify Status register bits */
203 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
204
205 /* Host Notify Command register bits */
206 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
207 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
208
209 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
210 SMBHSTSTS_DEV_ERR)
211
212 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
213 STATUS_ERROR_FLAGS)
214
215 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1)
216
217 /* Older devices have their ID defined in <linux/pci_ids.h> */
218 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
219 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
220 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
221 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
222 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
223 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
224 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
225 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
226 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
227 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
228 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
229 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
230 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
231 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
232 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
233 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
234 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
235 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
236 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
237 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
238 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
239 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
240 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
241 #define PCI_DEVICE_ID_INTEL_WILDCAT_LAKE_U_SMBUS 0x4d22
242 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
243 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
244 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
245 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796
246 #define PCI_DEVICE_ID_INTEL_DIAMOND_RAPIDS_SMBUS 0x5827
247 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
248 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722
249 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
250 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
251 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
252 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
253 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
254 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
255 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
256 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
257 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
258 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
259 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
260 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
261 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
262 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
263 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
264 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
265 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
266 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
267 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
268 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
269 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
270 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
271 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS 0xe322
272 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS 0xe422
273
274 struct i801_mux_config {
275 char *gpio_chip;
276 unsigned values[3];
277 int n_values;
278 unsigned gpios[2]; /* Relative to gpio_chip->base */
279 int n_gpios;
280 };
281
282 struct i801_priv {
283 struct i2c_adapter adapter;
284 void __iomem *smba;
285 unsigned char original_hstcfg;
286 unsigned char original_hstcnt;
287 unsigned char original_slvcmd;
288 struct pci_dev *pci_dev;
289 unsigned int features;
290
291 /* isr processing */
292 struct completion done;
293 u8 status;
294
295 /* Command state used by isr for byte-by-byte block transactions */
296 u8 cmd;
297 bool is_read;
298 int count;
299 int len;
300 u8 *data;
301
302 #ifdef CONFIG_I2C_I801_MUX
303 struct platform_device *mux_pdev;
304 struct gpiod_lookup_table *lookup;
305 struct notifier_block mux_notifier_block;
306 #endif
307 struct platform_device *tco_pdev;
308
309 /*
310 * If set to true the host controller registers are reserved for
311 * ACPI AML use.
312 */
313 bool acpi_reserved;
314 };
315
316 #define FEATURE_SMBUS_PEC BIT(0)
317 #define FEATURE_BLOCK_BUFFER BIT(1)
318 #define FEATURE_BLOCK_PROC BIT(2)
319 #define FEATURE_I2C_BLOCK_READ BIT(3)
320 #define FEATURE_IRQ BIT(4)
321 #define FEATURE_HOST_NOTIFY BIT(5)
322 /* Not really a feature, but it's convenient to handle it as such */
323 #define FEATURE_IDF BIT(15)
324 #define FEATURE_TCO_SPT BIT(16)
325 #define FEATURE_TCO_CNL BIT(17)
326
327 static const char *i801_feature_names[] = {
328 "SMBus PEC",
329 "Block buffer",
330 "Block process call",
331 "I2C block read",
332 "Interrupt",
333 "SMBus Host Notify",
334 };
335
336 static unsigned int disable_features;
337 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
338 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
339 "\t\t 0x01 disable SMBus PEC\n"
340 "\t\t 0x02 disable the block buffer\n"
341 "\t\t 0x08 disable the I2C block read functionality\n"
342 "\t\t 0x10 don't use interrupts\n"
343 "\t\t 0x20 disable SMBus Host Notify ");
344
345 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)346 static int i801_wait_intr(struct i801_priv *priv)
347 {
348 unsigned long timeout = jiffies + priv->adapter.timeout;
349 int status, busy;
350
351 do {
352 usleep_range(250, 500);
353 status = ioread8(SMBHSTSTS(priv));
354 busy = status & SMBHSTSTS_HOST_BUSY;
355 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
356 if (!busy && status)
357 return status & STATUS_ERROR_FLAGS;
358 } while (time_is_after_eq_jiffies(timeout));
359
360 return -ETIMEDOUT;
361 }
362
363 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)364 static int i801_wait_byte_done(struct i801_priv *priv)
365 {
366 unsigned long timeout = jiffies + priv->adapter.timeout;
367 int status;
368
369 do {
370 usleep_range(250, 500);
371 status = ioread8(SMBHSTSTS(priv));
372 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
373 return status & STATUS_ERROR_FLAGS;
374 } while (time_is_after_eq_jiffies(timeout));
375
376 return -ETIMEDOUT;
377 }
378
i801_get_block_len(struct i801_priv * priv)379 static int i801_get_block_len(struct i801_priv *priv)
380 {
381 u8 len = ioread8(SMBHSTDAT0(priv));
382
383 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
384 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len);
385 return -EPROTO;
386 }
387
388 return len;
389 }
390
i801_check_and_clear_pec_error(struct i801_priv * priv)391 static int i801_check_and_clear_pec_error(struct i801_priv *priv)
392 {
393 u8 status;
394
395 if (!(priv->features & FEATURE_SMBUS_PEC))
396 return 0;
397
398 status = ioread8(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
399 if (status) {
400 iowrite8(status, SMBAUXSTS(priv));
401 return -EBADMSG;
402 }
403
404 return 0;
405 }
406
407 /* Make sure the SMBus host is ready to start transmitting.
408 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)409 static int i801_check_pre(struct i801_priv *priv)
410 {
411 int status, result;
412
413 status = ioread8(SMBHSTSTS(priv));
414 if (status & SMBHSTSTS_HOST_BUSY) {
415 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
416 return -EBUSY;
417 }
418
419 status &= STATUS_FLAGS;
420 if (status) {
421 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
422 iowrite8(status, SMBHSTSTS(priv));
423 }
424
425 /*
426 * Clear CRC status if needed.
427 * During normal operation, i801_check_post() takes care
428 * of it after every operation. We do it here only in case
429 * the hardware was already in this state when the driver
430 * started.
431 */
432 result = i801_check_and_clear_pec_error(priv);
433 if (result)
434 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n");
435
436 return 0;
437 }
438
i801_check_post(struct i801_priv * priv,int status)439 static int i801_check_post(struct i801_priv *priv, int status)
440 {
441 int result = 0;
442
443 /*
444 * If the SMBus is still busy, we give up
445 */
446 if (unlikely(status < 0)) {
447 /* try to stop the current command */
448 iowrite8(SMBHSTCNT_KILL, SMBHSTCNT(priv));
449 status = i801_wait_intr(priv);
450 iowrite8(0, SMBHSTCNT(priv));
451
452 /* Check if it worked */
453 if (status < 0 || !(status & SMBHSTSTS_FAILED))
454 pci_dbg(priv->pci_dev, "Failed terminating the transaction\n");
455 return -ETIMEDOUT;
456 }
457
458 if (status & SMBHSTSTS_FAILED) {
459 result = -EIO;
460 pci_err(priv->pci_dev, "Transaction failed\n");
461 }
462 if (status & SMBHSTSTS_DEV_ERR) {
463 /*
464 * This may be a PEC error, check and clear it.
465 *
466 * AUXSTS is handled differently from HSTSTS.
467 * For HSTSTS, i801_isr() or i801_wait_intr()
468 * has already cleared the error bits in hardware,
469 * and we are passed a copy of the original value
470 * in "status".
471 * For AUXSTS, the hardware register is left
472 * for us to handle here.
473 * This is asymmetric, slightly iffy, but safe,
474 * since all this code is serialized and the CRCE
475 * bit is harmless as long as it's cleared before
476 * the next operation.
477 */
478 result = i801_check_and_clear_pec_error(priv);
479 if (result) {
480 pci_dbg(priv->pci_dev, "PEC error\n");
481 } else {
482 result = -ENXIO;
483 pci_dbg(priv->pci_dev, "No response\n");
484 }
485 }
486 if (status & SMBHSTSTS_BUS_ERR) {
487 result = -EAGAIN;
488 pci_dbg(priv->pci_dev, "Lost arbitration\n");
489 }
490
491 return result;
492 }
493
i801_transaction(struct i801_priv * priv,int xact)494 static int i801_transaction(struct i801_priv *priv, int xact)
495 {
496 unsigned long result;
497 const struct i2c_adapter *adap = &priv->adapter;
498
499 if (priv->features & FEATURE_IRQ) {
500 reinit_completion(&priv->done);
501 iowrite8(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
502 SMBHSTCNT(priv));
503 result = wait_for_completion_timeout(&priv->done, adap->timeout);
504 return result ? priv->status : -ETIMEDOUT;
505 }
506
507 iowrite8(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
508
509 return i801_wait_intr(priv);
510 }
511
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)512 static int i801_block_transaction_by_block(struct i801_priv *priv,
513 union i2c_smbus_data *data,
514 char read_write, int command)
515 {
516 int len, status, xact;
517
518 switch (command) {
519 case I2C_SMBUS_BLOCK_PROC_CALL:
520 xact = I801_BLOCK_PROC_CALL;
521 break;
522 case I2C_SMBUS_BLOCK_DATA:
523 xact = I801_BLOCK_DATA;
524 break;
525 default:
526 return -EOPNOTSUPP;
527 }
528
529 /* Set block buffer mode */
530 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
531
532 if (read_write == I2C_SMBUS_WRITE) {
533 len = data->block[0];
534 iowrite8(len, SMBHSTDAT0(priv));
535 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */
536 iowrite8_rep(SMBBLKDAT(priv), data->block + 1, len);
537 }
538
539 status = i801_transaction(priv, xact);
540 if (status)
541 goto out;
542
543 if (read_write == I2C_SMBUS_READ ||
544 command == I2C_SMBUS_BLOCK_PROC_CALL) {
545 len = i801_get_block_len(priv);
546 if (len < 0) {
547 status = len;
548 goto out;
549 }
550
551 data->block[0] = len;
552 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */
553 ioread8_rep(SMBBLKDAT(priv), data->block + 1, len);
554 }
555 out:
556 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
557 return status;
558 }
559
i801_isr_byte_done(struct i801_priv * priv)560 static void i801_isr_byte_done(struct i801_priv *priv)
561 {
562 if (priv->is_read) {
563 /*
564 * At transfer start i801_smbus_block_transaction() marks
565 * the block length as invalid. Check for this sentinel value
566 * and read the block length from SMBHSTDAT0.
567 */
568 if (priv->len == SMBUS_LEN_SENTINEL) {
569 priv->len = i801_get_block_len(priv);
570 if (priv->len < 0)
571 /* FIXME: Recover */
572 priv->len = I2C_SMBUS_BLOCK_MAX;
573
574 priv->data[-1] = priv->len;
575 }
576
577 /* Read next byte */
578 if (priv->count < priv->len)
579 priv->data[priv->count++] = ioread8(SMBBLKDAT(priv));
580 else
581 pci_dbg(priv->pci_dev, "Discarding extra byte on block read\n");
582
583 /* Set LAST_BYTE for last byte of read transaction */
584 if (priv->count == priv->len - 1)
585 iowrite8(priv->cmd | SMBHSTCNT_LAST_BYTE,
586 SMBHSTCNT(priv));
587 } else if (priv->count < priv->len - 1) {
588 /* Write next byte, except for IRQ after last byte */
589 iowrite8(priv->data[++priv->count], SMBBLKDAT(priv));
590 }
591 }
592
i801_host_notify_isr(struct i801_priv * priv)593 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
594 {
595 unsigned short addr;
596
597 addr = ioread8(SMBNTFDADD(priv)) >> 1;
598
599 /*
600 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
601 * always returns 0. Our current implementation doesn't provide
602 * data, so we just ignore it.
603 */
604 i2c_handle_smbus_host_notify(&priv->adapter, addr);
605
606 /* clear Host Notify bit and return */
607 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
608 return IRQ_HANDLED;
609 }
610
611 /*
612 * There are three kinds of interrupts:
613 *
614 * 1) i801 signals transaction completion with one of these interrupts:
615 * INTR - Success
616 * DEV_ERR - Invalid command, NAK or communication timeout
617 * BUS_ERR - SMI# transaction collision
618 * FAILED - transaction was canceled due to a KILL request
619 * When any of these occur, update ->status and signal completion.
620 *
621 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
622 * occurs for each byte of a byte-by-byte to prepare the next byte.
623 *
624 * 3) Host Notify interrupts
625 */
i801_isr(int irq,void * dev_id)626 static irqreturn_t i801_isr(int irq, void *dev_id)
627 {
628 struct i801_priv *priv = dev_id;
629 u16 pcists;
630 u8 status;
631
632 /* Confirm this is our interrupt */
633 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
634 if (!(pcists & PCI_STATUS_INTERRUPT))
635 return IRQ_NONE;
636
637 if (priv->features & FEATURE_HOST_NOTIFY) {
638 status = ioread8(SMBSLVSTS(priv));
639 if (status & SMBSLVSTS_HST_NTFY_STS)
640 return i801_host_notify_isr(priv);
641 }
642
643 status = ioread8(SMBHSTSTS(priv));
644 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
645 i801_isr_byte_done(priv);
646
647 /*
648 * Clear IRQ sources: SMB_ALERT status is set after signal assertion
649 * independently of the interrupt generation being blocked or not
650 * so clear it always when the status is set.
651 */
652 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
653 iowrite8(status, SMBHSTSTS(priv));
654
655 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
656 if (status) {
657 priv->status = status & STATUS_ERROR_FLAGS;
658 complete(&priv->done);
659 }
660
661 return IRQ_HANDLED;
662 }
663
664 /*
665 * For "byte-by-byte" block transactions:
666 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
667 * I2C read uses cmd=I801_I2C_BLOCK_DATA
668 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)669 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
670 union i2c_smbus_data *data,
671 char read_write, int command)
672 {
673 int i, len;
674 int smbcmd;
675 int status;
676 unsigned long result;
677 const struct i2c_adapter *adap = &priv->adapter;
678
679 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
680 return -EOPNOTSUPP;
681
682 len = data->block[0];
683
684 if (read_write == I2C_SMBUS_WRITE) {
685 iowrite8(len, SMBHSTDAT0(priv));
686 iowrite8(data->block[1], SMBBLKDAT(priv));
687 }
688
689 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
690 read_write == I2C_SMBUS_READ)
691 smbcmd = I801_I2C_BLOCK_DATA;
692 else
693 smbcmd = I801_BLOCK_DATA;
694
695 if (priv->features & FEATURE_IRQ) {
696 priv->is_read = (read_write == I2C_SMBUS_READ);
697 if (len == 1 && priv->is_read)
698 smbcmd |= SMBHSTCNT_LAST_BYTE;
699 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
700 priv->len = len;
701 priv->count = 0;
702 priv->data = &data->block[1];
703
704 reinit_completion(&priv->done);
705 iowrite8(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
706 result = wait_for_completion_timeout(&priv->done, adap->timeout);
707 return result ? priv->status : -ETIMEDOUT;
708 }
709
710 if (len == 1 && read_write == I2C_SMBUS_READ)
711 smbcmd |= SMBHSTCNT_LAST_BYTE;
712 iowrite8(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
713
714 for (i = 1; i <= len; i++) {
715 status = i801_wait_byte_done(priv);
716 if (status)
717 return status;
718
719 /*
720 * At transfer start i801_smbus_block_transaction() marks
721 * the block length as invalid. Check for this sentinel value
722 * and read the block length from SMBHSTDAT0.
723 */
724 if (len == SMBUS_LEN_SENTINEL) {
725 len = i801_get_block_len(priv);
726 if (len < 0) {
727 /* Recover */
728 while (ioread8(SMBHSTSTS(priv)) &
729 SMBHSTSTS_HOST_BUSY)
730 iowrite8(SMBHSTSTS_BYTE_DONE,
731 SMBHSTSTS(priv));
732 iowrite8(SMBHSTSTS_INTR, SMBHSTSTS(priv));
733 return -EPROTO;
734 }
735 data->block[0] = len;
736 }
737
738 if (read_write == I2C_SMBUS_READ) {
739 data->block[i] = ioread8(SMBBLKDAT(priv));
740 if (i == len - 1)
741 iowrite8(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
742 }
743
744 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
745 iowrite8(data->block[i+1], SMBBLKDAT(priv));
746
747 /* signals SMBBLKDAT ready */
748 iowrite8(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
749 }
750
751 return i801_wait_intr(priv);
752 }
753
i801_set_hstadd(struct i801_priv * priv,u8 addr,char read_write)754 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
755 {
756 iowrite8((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
757 }
758
759 /* Single value transaction function */
i801_simple_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)760 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
761 u8 addr, u8 hstcmd, char read_write, int command)
762 {
763 int xact, ret;
764
765 switch (command) {
766 case I2C_SMBUS_QUICK:
767 i801_set_hstadd(priv, addr, read_write);
768 xact = I801_QUICK;
769 break;
770 case I2C_SMBUS_BYTE:
771 i801_set_hstadd(priv, addr, read_write);
772 if (read_write == I2C_SMBUS_WRITE)
773 iowrite8(hstcmd, SMBHSTCMD(priv));
774 xact = I801_BYTE;
775 break;
776 case I2C_SMBUS_BYTE_DATA:
777 i801_set_hstadd(priv, addr, read_write);
778 if (read_write == I2C_SMBUS_WRITE)
779 iowrite8(data->byte, SMBHSTDAT0(priv));
780 iowrite8(hstcmd, SMBHSTCMD(priv));
781 xact = I801_BYTE_DATA;
782 break;
783 case I2C_SMBUS_WORD_DATA:
784 i801_set_hstadd(priv, addr, read_write);
785 if (read_write == I2C_SMBUS_WRITE) {
786 iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
787 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
788 }
789 iowrite8(hstcmd, SMBHSTCMD(priv));
790 xact = I801_WORD_DATA;
791 break;
792 case I2C_SMBUS_PROC_CALL:
793 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
794 iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
795 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
796 iowrite8(hstcmd, SMBHSTCMD(priv));
797 read_write = I2C_SMBUS_READ;
798 xact = I801_PROC_CALL;
799 break;
800 default:
801 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
802 return -EOPNOTSUPP;
803 }
804
805 ret = i801_transaction(priv, xact);
806 if (ret || read_write == I2C_SMBUS_WRITE)
807 return ret;
808
809 switch (command) {
810 case I2C_SMBUS_BYTE:
811 case I2C_SMBUS_BYTE_DATA:
812 data->byte = ioread8(SMBHSTDAT0(priv));
813 break;
814 case I2C_SMBUS_WORD_DATA:
815 case I2C_SMBUS_PROC_CALL:
816 data->word = ioread8(SMBHSTDAT0(priv)) +
817 (ioread8(SMBHSTDAT1(priv)) << 8);
818 break;
819 }
820
821 return 0;
822 }
823
i801_smbus_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)824 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
825 u8 addr, u8 hstcmd, char read_write, int command)
826 {
827 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
828 /* Mark block length as invalid */
829 data->block[0] = SMBUS_LEN_SENTINEL;
830 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
831 return -EPROTO;
832
833 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
834 /* Needs to be flagged as write transaction */
835 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
836 else
837 i801_set_hstadd(priv, addr, read_write);
838 iowrite8(hstcmd, SMBHSTCMD(priv));
839
840 if (priv->features & FEATURE_BLOCK_BUFFER)
841 return i801_block_transaction_by_block(priv, data, read_write, command);
842 else
843 return i801_block_transaction_byte_by_byte(priv, data, read_write, command);
844 }
845
i801_i2c_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)846 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
847 u8 addr, u8 hstcmd, char read_write, int command)
848 {
849 int result;
850 u8 hostc;
851
852 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
853 return -EPROTO;
854 /*
855 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here,
856 * even when reading. However if SPD Write Disable is set (Lynx Point and later),
857 * the read will fail if we don't set the R/#W bit.
858 */
859 i801_set_hstadd(priv, addr,
860 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE);
861
862 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */
863 if (read_write == I2C_SMBUS_READ)
864 iowrite8(hstcmd, SMBHSTDAT1(priv));
865 else
866 iowrite8(hstcmd, SMBHSTCMD(priv));
867
868 if (read_write == I2C_SMBUS_WRITE) {
869 /* set I2C_EN bit in configuration register */
870 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
871 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN);
872 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
873 pci_err(priv->pci_dev, "I2C block read is unsupported!\n");
874 return -EOPNOTSUPP;
875 }
876
877 /* Block buffer isn't supported for I2C block transactions */
878 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command);
879
880 /* restore saved configuration register value */
881 if (read_write == I2C_SMBUS_WRITE)
882 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
883
884 return result;
885 }
886
887 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)888 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
889 unsigned short flags, char read_write, u8 command,
890 int size, union i2c_smbus_data *data)
891 {
892 int hwpec, ret;
893 struct i801_priv *priv = i2c_get_adapdata(adap);
894
895 if (priv->acpi_reserved)
896 return -EBUSY;
897
898 pm_runtime_get_sync(&priv->pci_dev->dev);
899
900 ret = i801_check_pre(priv);
901 if (ret)
902 goto out;
903
904 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
905 && size != I2C_SMBUS_QUICK
906 && size != I2C_SMBUS_I2C_BLOCK_DATA;
907
908 if (hwpec) /* enable/disable hardware PEC */
909 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
910 else
911 iowrite8(ioread8(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
912 SMBAUXCTL(priv));
913
914 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL)
915 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size);
916 else if (size == I2C_SMBUS_I2C_BLOCK_DATA)
917 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size);
918 else
919 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
920
921 ret = i801_check_post(priv, ret);
922
923 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
924 * time, so we forcibly disable it after every transaction.
925 */
926 if (hwpec)
927 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
928 out:
929 /*
930 * Unlock the SMBus device for use by BIOS/ACPI,
931 * and clear status flags if not done already.
932 */
933 iowrite8(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
934
935 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
936 return ret;
937 }
938
939
i801_func(struct i2c_adapter * adapter)940 static u32 i801_func(struct i2c_adapter *adapter)
941 {
942 struct i801_priv *priv = i2c_get_adapdata(adapter);
943
944 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
945 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
946 I2C_FUNC_SMBUS_PROC_CALL |
947 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
948 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
949 ((priv->features & FEATURE_BLOCK_PROC) ?
950 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
951 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
952 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
953 ((priv->features & FEATURE_HOST_NOTIFY) ?
954 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
955 }
956
i801_enable_host_notify(struct i2c_adapter * adapter)957 static void i801_enable_host_notify(struct i2c_adapter *adapter)
958 {
959 struct i801_priv *priv = i2c_get_adapdata(adapter);
960
961 if (!(priv->features & FEATURE_HOST_NOTIFY))
962 return;
963
964 /*
965 * Enable host notify interrupt and block the generation of interrupt
966 * from the SMB_ALERT signal because the driver does not support
967 * SMBus Alert.
968 */
969 iowrite8(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
970 priv->original_slvcmd, SMBSLVCMD(priv));
971
972 /* clear Host Notify bit to allow a new notification */
973 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
974 }
975
i801_disable_host_notify(struct i801_priv * priv)976 static void i801_disable_host_notify(struct i801_priv *priv)
977 {
978 if (!(priv->features & FEATURE_HOST_NOTIFY))
979 return;
980
981 iowrite8(priv->original_slvcmd, SMBSLVCMD(priv));
982 }
983
984 static const struct i2c_algorithm smbus_algorithm = {
985 .smbus_xfer = i801_access,
986 .functionality = i801_func,
987 };
988
989 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
990 FEATURE_HOST_NOTIFY)
991 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \
992 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ)
993
994 static const struct pci_device_id i801_ids[] = {
995 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
996 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
997 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
998 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
999 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
1000 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
1001 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
1002 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
1003 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
1004 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
1005 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
1006 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
1007 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
1008 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
1009 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
1010 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
1011 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
1013 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
1014 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
1015 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
1016 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
1017 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
1018 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
1019 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
1020 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
1022 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
1023 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
1024 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
1025 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
1026 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
1027 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
1028 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
1029 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
1030 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
1031 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1032 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1033 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1034 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1035 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1036 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
1037 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1038 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1039 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1040 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1047 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5) },
1059 { PCI_DEVICE_DATA(INTEL, DIAMOND_RAPIDS_SMBUS, FEATURES_ICH5) },
1060 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1061 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1062 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1063 { PCI_DEVICE_DATA(INTEL, WILDCAT_LAKE_U_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1064 { 0, }
1065 };
1066
1067 MODULE_DEVICE_TABLE(pci, i801_ids);
1068
1069 #if defined CONFIG_X86 && defined CONFIG_DMI
1070 static unsigned char apanel_addr __ro_after_init;
1071
1072 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1073 static __init const void __iomem *bios_signature(const void __iomem *bios)
1074 {
1075 ssize_t offset;
1076 const unsigned char signature[] = "FJKEYINF";
1077
1078 for (offset = 0; offset < 0x10000; offset += 0x10) {
1079 if (check_signature(bios + offset, signature,
1080 sizeof(signature)-1))
1081 return bios + offset;
1082 }
1083 return NULL;
1084 }
1085
input_apanel_init(void)1086 static void __init input_apanel_init(void)
1087 {
1088 void __iomem *bios;
1089 const void __iomem *p;
1090
1091 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1092 p = bios_signature(bios);
1093 if (p) {
1094 /* just use the first address */
1095 apanel_addr = readb(p + 8 + 3) >> 1;
1096 }
1097 iounmap(bios);
1098 }
1099
1100 struct dmi_onboard_device_info {
1101 const char *name;
1102 u8 type;
1103 unsigned short i2c_addr;
1104 const char *i2c_type;
1105 };
1106
1107 static const struct dmi_onboard_device_info dmi_devices[] = {
1108 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1109 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1110 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1111 };
1112
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1113 static void dmi_check_onboard_device(u8 type, const char *name,
1114 struct i2c_adapter *adap)
1115 {
1116 int i;
1117 struct i2c_board_info info;
1118
1119 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1120 /* & ~0x80, ignore enabled/disabled bit */
1121 if ((type & ~0x80) != dmi_devices[i].type)
1122 continue;
1123 if (strcasecmp(name, dmi_devices[i].name))
1124 continue;
1125
1126 memset(&info, 0, sizeof(struct i2c_board_info));
1127 info.addr = dmi_devices[i].i2c_addr;
1128 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1129 i2c_new_client_device(adap, &info);
1130 break;
1131 }
1132 }
1133
1134 /* We use our own function to check for onboard devices instead of
1135 dmi_find_device() as some buggy BIOS's have the devices we are interested
1136 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1137 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1138 {
1139 int i, count;
1140
1141 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE)
1142 return;
1143
1144 count = (dm->length - sizeof(struct dmi_header)) / 2;
1145 for (i = 0; i < count; i++) {
1146 const u8 *d = (char *)(dm + 1) + (i * 2);
1147 const char *name = ((char *) dm) + dm->length;
1148 u8 type = d[0];
1149 u8 s = d[1];
1150
1151 if (!s)
1152 continue;
1153 s--;
1154 while (s > 0 && name[0]) {
1155 name += strlen(name) + 1;
1156 s--;
1157 }
1158 if (name[0] == 0) /* Bogus string reference */
1159 continue;
1160
1161 dmi_check_onboard_device(type, name, adap);
1162 }
1163 }
1164
1165 /* Register optional targets */
i801_probe_optional_targets(struct i801_priv * priv)1166 static void i801_probe_optional_targets(struct i801_priv *priv)
1167 {
1168 /* Only register targets on main SMBus channel */
1169 if (priv->features & FEATURE_IDF)
1170 return;
1171
1172 if (apanel_addr) {
1173 struct i2c_board_info info = {
1174 .addr = apanel_addr,
1175 .type = "fujitsu_apanel",
1176 };
1177
1178 i2c_new_client_device(&priv->adapter, &info);
1179 }
1180
1181 if (dmi_name_in_vendors("FUJITSU"))
1182 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1183
1184 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1185 #ifdef CONFIG_I2C_I801_MUX
1186 if (!priv->mux_pdev)
1187 #endif
1188 i2c_register_spd_write_enable(&priv->adapter);
1189 }
1190 #else
input_apanel_init(void)1191 static void __init input_apanel_init(void) {}
i801_probe_optional_targets(struct i801_priv * priv)1192 static void i801_probe_optional_targets(struct i801_priv *priv) {}
1193 #endif /* CONFIG_X86 && CONFIG_DMI */
1194
1195 #ifdef CONFIG_I2C_I801_MUX
1196 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1197 .gpio_chip = "gpio_ich",
1198 .values = { 0x02, 0x03 },
1199 .n_values = 2,
1200 .gpios = { 52, 53 },
1201 .n_gpios = 2,
1202 };
1203
1204 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1205 .gpio_chip = "gpio_ich",
1206 .values = { 0x02, 0x03, 0x01 },
1207 .n_values = 3,
1208 .gpios = { 52, 53 },
1209 .n_gpios = 2,
1210 };
1211
1212 static const struct dmi_system_id mux_dmi_table[] = {
1213 {
1214 .matches = {
1215 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1216 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1217 },
1218 .driver_data = &i801_mux_config_asus_z8_d12,
1219 },
1220 {
1221 .matches = {
1222 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1223 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1224 },
1225 .driver_data = &i801_mux_config_asus_z8_d12,
1226 },
1227 {
1228 .matches = {
1229 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1230 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1231 },
1232 .driver_data = &i801_mux_config_asus_z8_d12,
1233 },
1234 {
1235 .matches = {
1236 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1237 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1238 },
1239 .driver_data = &i801_mux_config_asus_z8_d12,
1240 },
1241 {
1242 .matches = {
1243 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1244 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1245 },
1246 .driver_data = &i801_mux_config_asus_z8_d12,
1247 },
1248 {
1249 .matches = {
1250 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1251 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1252 },
1253 .driver_data = &i801_mux_config_asus_z8_d12,
1254 },
1255 {
1256 .matches = {
1257 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1258 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1259 },
1260 .driver_data = &i801_mux_config_asus_z8_d18,
1261 },
1262 {
1263 .matches = {
1264 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1265 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1266 },
1267 .driver_data = &i801_mux_config_asus_z8_d18,
1268 },
1269 {
1270 .matches = {
1271 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1272 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1273 },
1274 .driver_data = &i801_mux_config_asus_z8_d12,
1275 },
1276 { }
1277 };
1278
i801_notifier_call(struct notifier_block * nb,unsigned long action,void * data)1279 static int i801_notifier_call(struct notifier_block *nb, unsigned long action,
1280 void *data)
1281 {
1282 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block);
1283 struct device *dev = data;
1284
1285 if (action != BUS_NOTIFY_ADD_DEVICE ||
1286 dev->type != &i2c_adapter_type ||
1287 i2c_root_adapter(dev) != &priv->adapter)
1288 return NOTIFY_DONE;
1289
1290 /* Call i2c_register_spd for muxed child segments */
1291 i2c_register_spd_write_enable(to_i2c_adapter(dev));
1292
1293 return NOTIFY_OK;
1294 }
1295
1296 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1297 static void i801_add_mux(struct i801_priv *priv)
1298 {
1299 struct device *dev = &priv->adapter.dev;
1300 const struct i801_mux_config *mux_config;
1301 struct i2c_mux_gpio_platform_data gpio_data;
1302 struct gpiod_lookup_table *lookup;
1303 const struct dmi_system_id *id;
1304 int i;
1305
1306 id = dmi_first_match(mux_dmi_table);
1307 if (!id)
1308 return;
1309
1310 mux_config = id->driver_data;
1311
1312 /* Prepare the platform data */
1313 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1314 gpio_data.parent = priv->adapter.nr;
1315 gpio_data.values = mux_config->values;
1316 gpio_data.n_values = mux_config->n_values;
1317 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1318
1319 /* Register GPIO descriptor lookup table */
1320 lookup = devm_kzalloc(dev,
1321 struct_size(lookup, table, mux_config->n_gpios + 1),
1322 GFP_KERNEL);
1323 if (!lookup)
1324 return;
1325 lookup->dev_id = "i2c-mux-gpio";
1326 for (i = 0; i < mux_config->n_gpios; i++)
1327 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1328 mux_config->gpios[i], "mux", 0);
1329 gpiod_add_lookup_table(lookup);
1330
1331 priv->mux_notifier_block.notifier_call = i801_notifier_call;
1332 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block))
1333 return;
1334 /*
1335 * Register the mux device, we use PLATFORM_DEVID_NONE here
1336 * because since we are referring to the GPIO chip by name we are
1337 * anyways in deep trouble if there is more than one of these
1338 * devices, and there should likely only be one platform controller
1339 * hub.
1340 */
1341 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1342 PLATFORM_DEVID_NONE, &gpio_data,
1343 sizeof(struct i2c_mux_gpio_platform_data));
1344 if (IS_ERR(priv->mux_pdev)) {
1345 gpiod_remove_lookup_table(lookup);
1346 devm_kfree(dev, lookup);
1347 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1348 } else {
1349 priv->lookup = lookup;
1350 }
1351 }
1352
i801_del_mux(struct i801_priv * priv)1353 static void i801_del_mux(struct i801_priv *priv)
1354 {
1355 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block);
1356 platform_device_unregister(priv->mux_pdev);
1357 gpiod_remove_lookup_table(priv->lookup);
1358 }
1359 #else
i801_add_mux(struct i801_priv * priv)1360 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1361 static inline void i801_del_mux(struct i801_priv *priv) { }
1362 #endif
1363
1364 static struct platform_device *
i801_add_tco_spt(struct pci_dev * pci_dev,struct resource * tco_res)1365 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res)
1366 {
1367 static const struct itco_wdt_platform_data pldata = {
1368 .name = "Intel PCH",
1369 .version = 4,
1370 };
1371 struct resource *res;
1372 int ret;
1373
1374 /*
1375 * We must access the NO_REBOOT bit over the Primary to Sideband
1376 * (P2SB) bridge.
1377 */
1378
1379 res = &tco_res[1];
1380 ret = p2sb_bar(pci_dev->bus, 0, res);
1381 if (ret)
1382 return ERR_PTR(ret);
1383
1384 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1385 res->start += SBREG_SMBCTRL_DNV;
1386 else
1387 res->start += SBREG_SMBCTRL;
1388
1389 res->end = res->start + 3;
1390
1391 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1392 tco_res, 2, &pldata, sizeof(pldata));
1393 }
1394
1395 static struct platform_device *
i801_add_tco_cnl(struct pci_dev * pci_dev,struct resource * tco_res)1396 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res)
1397 {
1398 static const struct itco_wdt_platform_data pldata = {
1399 .name = "Intel PCH",
1400 .version = 6,
1401 };
1402
1403 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1404 tco_res, 1, &pldata, sizeof(pldata));
1405 }
1406
i801_add_tco(struct i801_priv * priv)1407 static void i801_add_tco(struct i801_priv *priv)
1408 {
1409 struct pci_dev *pci_dev = priv->pci_dev;
1410 struct resource tco_res[2], *res;
1411 u32 tco_base, tco_ctl;
1412
1413 /* If we have ACPI based watchdog use that instead */
1414 if (acpi_has_watchdog())
1415 return;
1416
1417 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1418 return;
1419
1420 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1421 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1422 if (!(tco_ctl & TCOCTL_EN))
1423 return;
1424
1425 memset(tco_res, 0, sizeof(tco_res));
1426 /*
1427 * Always populate the main iTCO IO resource here. The second entry
1428 * for NO_REBOOT MMIO is filled by the SPT specific function.
1429 */
1430 res = &tco_res[0];
1431 res->start = tco_base & ~1;
1432 res->end = res->start + 32 - 1;
1433 res->flags = IORESOURCE_IO;
1434
1435 if (priv->features & FEATURE_TCO_CNL)
1436 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res);
1437 else
1438 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res);
1439
1440 if (IS_ERR(priv->tco_pdev))
1441 pci_warn(pci_dev, "failed to create iTCO device\n");
1442 }
1443
1444 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1445 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1446 acpi_physical_address address)
1447 {
1448 return address >= pci_resource_start(priv->pci_dev, SMBBAR) &&
1449 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1450 }
1451
1452 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1453 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1454 u64 *value, void *handler_context, void *region_context)
1455 {
1456 struct i801_priv *priv = handler_context;
1457 struct pci_dev *pdev = priv->pci_dev;
1458 acpi_status status;
1459
1460 /*
1461 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1462 * further access from the driver itself. This device is now owned
1463 * by the system firmware.
1464 */
1465 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1466
1467 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1468 priv->acpi_reserved = true;
1469
1470 pci_warn(pdev, "BIOS is accessing SMBus registers\n");
1471 pci_warn(pdev, "Driver SMBus register access inhibited\n");
1472
1473 /*
1474 * BIOS is accessing the host controller so prevent it from
1475 * suspending automatically from now on.
1476 */
1477 pm_runtime_get_sync(&pdev->dev);
1478 }
1479
1480 if ((function & ACPI_IO_MASK) == ACPI_READ)
1481 status = acpi_os_read_port(address, (u32 *)value, bits);
1482 else
1483 status = acpi_os_write_port(address, (u32)*value, bits);
1484
1485 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1486
1487 return status;
1488 }
1489
i801_acpi_probe(struct i801_priv * priv)1490 static int i801_acpi_probe(struct i801_priv *priv)
1491 {
1492 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1493 acpi_status status;
1494
1495 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1496 i801_acpi_io_handler, NULL, priv);
1497 if (ACPI_SUCCESS(status))
1498 return 0;
1499
1500 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1501 }
1502
i801_acpi_remove(struct i801_priv * priv)1503 static void i801_acpi_remove(struct i801_priv *priv)
1504 {
1505 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1506
1507 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1508 }
1509 #else
i801_acpi_probe(struct i801_priv * priv)1510 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1511 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1512 #endif
1513
i801_setup_hstcfg(struct i801_priv * priv)1514 static void i801_setup_hstcfg(struct i801_priv *priv)
1515 {
1516 unsigned char hstcfg = priv->original_hstcfg;
1517
1518 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1519 hstcfg |= SMBHSTCFG_HST_EN;
1520 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1521 }
1522
i801_restore_regs(struct i801_priv * priv)1523 static void i801_restore_regs(struct i801_priv *priv)
1524 {
1525 iowrite8(priv->original_hstcnt, SMBHSTCNT(priv));
1526 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1527 }
1528
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1529 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1530 {
1531 int err, i, bar = SMBBAR;
1532 struct i801_priv *priv;
1533
1534 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1535 if (!priv)
1536 return -ENOMEM;
1537
1538 i2c_set_adapdata(&priv->adapter, priv);
1539 priv->adapter.owner = THIS_MODULE;
1540 priv->adapter.class = I2C_CLASS_HWMON;
1541 priv->adapter.algo = &smbus_algorithm;
1542 priv->adapter.dev.parent = &dev->dev;
1543 acpi_use_parent_companion(&priv->adapter.dev);
1544 priv->adapter.retries = 3;
1545
1546 priv->pci_dev = dev;
1547 priv->features = id->driver_data;
1548
1549 /* Disable features on user request */
1550 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1551 if (priv->features & disable_features & (1 << i))
1552 pci_notice(dev, "%s disabled by user\n", i801_feature_names[i]);
1553 }
1554 priv->features &= ~disable_features;
1555
1556 /* The block process call uses block buffer mode */
1557 if (!(priv->features & FEATURE_BLOCK_BUFFER))
1558 priv->features &= ~FEATURE_BLOCK_PROC;
1559
1560 /*
1561 * Do not call pcim_enable_device(), because the device has to remain
1562 * enabled on driver detach. See i801_remove() for the reasoning.
1563 */
1564 err = pci_enable_device(dev);
1565 if (err) {
1566 pci_err(dev, "Failed to enable SMBus PCI device (%d)\n", err);
1567 return err;
1568 }
1569
1570 /* Determine the address of the SMBus area */
1571 if (!pci_resource_start(dev, SMBBAR)) {
1572 pci_err(dev, "SMBus base address uninitialized, upgrade BIOS\n");
1573 return -ENODEV;
1574 }
1575
1576 if (i801_acpi_probe(priv))
1577 return -ENODEV;
1578
1579 if (pci_resource_flags(dev, SMBBAR_MMIO) & IORESOURCE_MEM)
1580 bar = SMBBAR_MMIO;
1581
1582 priv->smba = pcim_iomap_region(dev, bar, DRV_NAME);
1583 if (IS_ERR(priv->smba)) {
1584 pci_err(dev, "Failed to request SMBus region %pr\n",
1585 pci_resource_n(dev, bar));
1586 i801_acpi_remove(priv);
1587 return PTR_ERR(priv->smba);
1588 }
1589
1590 pci_read_config_byte(dev, SMBHSTCFG, &priv->original_hstcfg);
1591 i801_setup_hstcfg(priv);
1592 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1593 pci_info(dev, "Enabling SMBus device\n");
1594
1595 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1596 pci_dbg(dev, "SMBus using interrupt SMI#\n");
1597 /* Disable SMBus interrupt feature if SMBus using SMI# */
1598 priv->features &= ~FEATURE_IRQ;
1599 }
1600 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1601 pci_info(dev, "SPD Write Disable is set\n");
1602
1603 /* Clear special mode bits */
1604 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1605 iowrite8(ioread8(SMBAUXCTL(priv)) &
1606 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1607
1608 /* Default timeout in interrupt mode: 200 ms */
1609 priv->adapter.timeout = HZ / 5;
1610
1611 if (dev->irq == IRQ_NOTCONNECTED)
1612 priv->features &= ~FEATURE_IRQ;
1613
1614 if (priv->features & FEATURE_IRQ) {
1615 u16 pcists;
1616
1617 /* Complain if an interrupt is already pending */
1618 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1619 if (pcists & PCI_STATUS_INTERRUPT)
1620 pci_warn(dev, "An interrupt is pending!\n");
1621 }
1622
1623 if (priv->features & FEATURE_IRQ) {
1624 init_completion(&priv->done);
1625
1626 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1627 IRQF_SHARED, DRV_NAME, priv);
1628 if (err) {
1629 pci_err(dev, "Failed to allocate irq %d: %d\n", dev->irq, err);
1630 priv->features &= ~FEATURE_IRQ;
1631 }
1632 }
1633 pci_info(dev, "SMBus using %s\n",
1634 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1635
1636 /* Host notification uses an interrupt */
1637 if (!(priv->features & FEATURE_IRQ))
1638 priv->features &= ~FEATURE_HOST_NOTIFY;
1639
1640 /* Remember original Interrupt and Host Notify settings */
1641 priv->original_hstcnt = ioread8(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1642 if (priv->features & FEATURE_HOST_NOTIFY)
1643 priv->original_slvcmd = ioread8(SMBSLVCMD(priv));
1644
1645 i801_add_tco(priv);
1646
1647 /*
1648 * adapter.name is used by platform code to find the main I801 adapter
1649 * to instantiante i2c_clients, do not change.
1650 */
1651 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1652 "SMBus %s adapter at %s",
1653 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1654 pci_name(dev));
1655
1656 err = i2c_add_adapter(&priv->adapter);
1657 if (err) {
1658 platform_device_unregister(priv->tco_pdev);
1659 i801_acpi_remove(priv);
1660 i801_restore_regs(priv);
1661 return err;
1662 }
1663
1664 i801_enable_host_notify(&priv->adapter);
1665
1666 /* We ignore errors - multiplexing is optional */
1667 i801_add_mux(priv);
1668 i801_probe_optional_targets(priv);
1669
1670 pci_set_drvdata(dev, priv);
1671
1672 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1673 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1674 pm_runtime_use_autosuspend(&dev->dev);
1675 pm_runtime_put_autosuspend(&dev->dev);
1676 pm_runtime_allow(&dev->dev);
1677
1678 return 0;
1679 }
1680
i801_remove(struct pci_dev * dev)1681 static void i801_remove(struct pci_dev *dev)
1682 {
1683 struct i801_priv *priv = pci_get_drvdata(dev);
1684
1685 i801_disable_host_notify(priv);
1686 i801_del_mux(priv);
1687 i2c_del_adapter(&priv->adapter);
1688 i801_acpi_remove(priv);
1689
1690 platform_device_unregister(priv->tco_pdev);
1691
1692 /* if acpi_reserved is set then usage_count is incremented already */
1693 if (!priv->acpi_reserved)
1694 pm_runtime_get_noresume(&dev->dev);
1695
1696 i801_restore_regs(priv);
1697
1698 /*
1699 * do not call pci_disable_device(dev) since it can cause hard hangs on
1700 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1701 */
1702 }
1703
i801_shutdown(struct pci_dev * dev)1704 static void i801_shutdown(struct pci_dev *dev)
1705 {
1706 struct i801_priv *priv = pci_get_drvdata(dev);
1707
1708 i801_disable_host_notify(priv);
1709 /* Restore config registers to avoid hard hang on some systems */
1710 i801_restore_regs(priv);
1711 }
1712
i801_suspend(struct device * dev)1713 static int i801_suspend(struct device *dev)
1714 {
1715 struct i801_priv *priv = dev_get_drvdata(dev);
1716
1717 i2c_mark_adapter_suspended(&priv->adapter);
1718 i801_restore_regs(priv);
1719
1720 return 0;
1721 }
1722
i801_resume(struct device * dev)1723 static int i801_resume(struct device *dev)
1724 {
1725 struct i801_priv *priv = dev_get_drvdata(dev);
1726
1727 i801_setup_hstcfg(priv);
1728 i801_enable_host_notify(&priv->adapter);
1729 i2c_mark_adapter_resumed(&priv->adapter);
1730
1731 return 0;
1732 }
1733
1734 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1735
1736 static struct pci_driver i801_driver = {
1737 .name = DRV_NAME,
1738 .id_table = i801_ids,
1739 .probe = i801_probe,
1740 .remove = i801_remove,
1741 .shutdown = i801_shutdown,
1742 .driver = {
1743 .pm = pm_sleep_ptr(&i801_pm_ops),
1744 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1745 },
1746 };
1747
i2c_i801_init(struct pci_driver * drv)1748 static int __init i2c_i801_init(struct pci_driver *drv)
1749 {
1750 if (dmi_name_in_vendors("FUJITSU"))
1751 input_apanel_init();
1752 return pci_register_driver(drv);
1753 }
1754
1755 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1756 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1757 MODULE_DESCRIPTION("I801 SMBus driver");
1758 MODULE_LICENSE("GPL");
1759
1760 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver);
1761