1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU_13_0_6_PMFW_H 24 #define SMU_13_0_6_PMFW_H 25 26 #define NUM_VCLK_DPM_LEVELS 4 27 #define NUM_DCLK_DPM_LEVELS 4 28 #define NUM_SOCCLK_DPM_LEVELS 4 29 #define NUM_LCLK_DPM_LEVELS 4 30 #define NUM_UCLK_DPM_LEVELS 4 31 #define NUM_FCLK_DPM_LEVELS 4 32 #define NUM_XGMI_DPM_LEVELS 2 33 #define NUM_CXL_BITRATES 4 34 #define NUM_PCIE_BITRATES 4 35 #define NUM_XGMI_BITRATES 4 36 #define NUM_XGMI_WIDTHS 3 37 #define NUM_SOC_P2S_TABLES 3 38 #define NUM_TDP_GROUPS 4 39 40 typedef enum { 41 /*0*/ FEATURE_DATA_CALCULATION = 0, 42 /*1*/ FEATURE_DPM_CCLK = 1, 43 /*2*/ FEATURE_DPM_FCLK = 2, 44 /*3*/ FEATURE_DPM_GFXCLK = 3, 45 /*4*/ FEATURE_DPM_LCLK = 4, 46 /*5*/ FEATURE_DPM_SOCCLK = 5, 47 /*6*/ FEATURE_DPM_UCLK = 6, 48 /*7*/ FEATURE_DPM_VCN = 7, 49 /*8*/ FEATURE_DPM_XGMI = 8, 50 /*9*/ FEATURE_DS_FCLK = 9, 51 /*10*/ FEATURE_DS_GFXCLK = 10, 52 /*11*/ FEATURE_DS_LCLK = 11, 53 /*12*/ FEATURE_DS_MP0CLK = 12, 54 /*13*/ FEATURE_DS_MP1CLK = 13, 55 /*14*/ FEATURE_DS_MPIOCLK = 14, 56 /*15*/ FEATURE_DS_SOCCLK = 15, 57 /*16*/ FEATURE_DS_VCN = 16, 58 /*17*/ FEATURE_APCC_DFLL = 17, 59 /*18*/ FEATURE_APCC_PLUS = 18, 60 /*19*/ FEATURE_DF_CSTATE = 19, 61 /*20*/ FEATURE_CC6 = 20, 62 /*21*/ FEATURE_PC6 = 21, 63 /*22*/ FEATURE_CPPC = 22, 64 /*23*/ FEATURE_PPT = 23, 65 /*24*/ FEATURE_TDC = 24, 66 /*25*/ FEATURE_THERMAL = 25, 67 /*26*/ FEATURE_SOC_PCC = 26, 68 /*27*/ FEATURE_CCD_PCC = 27, 69 /*28*/ FEATURE_CCD_EDC = 28, 70 /*29*/ FEATURE_PROCHOT = 29, 71 /*30*/ FEATURE_DVO_CCLK = 30, 72 /*31*/ FEATURE_FDD_AID_HBM = 31, 73 /*32*/ FEATURE_FDD_AID_SOC = 32, 74 /*33*/ FEATURE_FDD_XCD_EDC = 33, 75 /*34*/ FEATURE_FDD_XCD_XVMIN = 34, 76 /*35*/ FEATURE_FW_CTF = 35, 77 /*36*/ FEATURE_GFXOFF = 36, 78 /*37*/ FEATURE_SMU_CG = 37, 79 /*38*/ FEATURE_PSI7 = 38, 80 /*39*/ FEATURE_CSTATE_BOOST = 39, 81 /*40*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 40, 82 /*41*/ FEATURE_CXL_QOS = 41, 83 /*42*/ FEATURE_SOC_DC_RTC = 42, 84 /*43*/ FEATURE_GFX_DC_RTC = 43, 85 /*44*/ FEATURE_DVM_MIN_PSM = 44, 86 /*45*/ FEATURE_PRC = 45, 87 88 /*46*/ NUM_FEATURES = 46 89 } FEATURE_LIST_e; 90 91 //enum for MPIO PCIe gen speed msgs 92 typedef enum { 93 PCIE_LINK_SPEED_INDEX_TABLE_GEN1, 94 PCIE_LINK_SPEED_INDEX_TABLE_GEN2, 95 PCIE_LINK_SPEED_INDEX_TABLE_GEN3, 96 PCIE_LINK_SPEED_INDEX_TABLE_GEN4, 97 PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM, 98 PCIE_LINK_SPEED_INDEX_TABLE_GEN5, 99 PCIE_LINK_SPEED_INDEX_TABLE_COUNT 100 } PCIE_LINK_SPEED_INDEX_TABLE_e; 101 102 typedef enum { 103 VOLTAGE_COLD_0, 104 VOLTAGE_COLD_1, 105 VOLTAGE_COLD_2, 106 VOLTAGE_COLD_3, 107 VOLTAGE_COLD_4, 108 VOLTAGE_COLD_5, 109 VOLTAGE_COLD_6, 110 VOLTAGE_COLD_7, 111 VOLTAGE_MID_0, 112 VOLTAGE_MID_1, 113 VOLTAGE_MID_2, 114 VOLTAGE_MID_3, 115 VOLTAGE_MID_4, 116 VOLTAGE_MID_5, 117 VOLTAGE_MID_6, 118 VOLTAGE_MID_7, 119 VOLTAGE_HOT_0, 120 VOLTAGE_HOT_1, 121 VOLTAGE_HOT_2, 122 VOLTAGE_HOT_3, 123 VOLTAGE_HOT_4, 124 VOLTAGE_HOT_5, 125 VOLTAGE_HOT_6, 126 VOLTAGE_HOT_7, 127 VOLTAGE_GUARDBAND_COUNT 128 } GFX_GUARDBAND_e; 129 130 #define SMU_METRICS_TABLE_VERSION 0x11 131 132 // Unified metrics table for smu_v13_0_6 133 typedef struct __attribute__((packed, aligned(4))) { 134 uint32_t AccumulationCounter; 135 136 //TEMPERATURE 137 uint32_t MaxSocketTemperature; 138 uint32_t MaxVrTemperature; 139 uint32_t MaxHbmTemperature; 140 uint64_t MaxSocketTemperatureAcc; 141 uint64_t MaxVrTemperatureAcc; 142 uint64_t MaxHbmTemperatureAcc; 143 144 //POWER 145 uint32_t SocketPowerLimit; 146 uint32_t MaxSocketPowerLimit; 147 uint32_t SocketPower; 148 149 //ENERGY 150 uint64_t Timestamp; 151 uint64_t SocketEnergyAcc; 152 uint64_t CcdEnergyAcc; 153 uint64_t XcdEnergyAcc; 154 uint64_t AidEnergyAcc; 155 uint64_t HbmEnergyAcc; 156 157 //FREQUENCY 158 uint32_t CclkFrequencyLimit; 159 uint32_t GfxclkFrequencyLimit; 160 uint32_t FclkFrequency; 161 uint32_t UclkFrequency; 162 uint32_t SocclkFrequency[4]; 163 uint32_t VclkFrequency[4]; 164 uint32_t DclkFrequency[4]; 165 uint32_t LclkFrequency[4]; 166 uint64_t GfxclkFrequencyAcc[8]; 167 uint64_t CclkFrequencyAcc[96]; 168 169 //FREQUENCY RANGE 170 uint32_t MaxCclkFrequency; 171 uint32_t MinCclkFrequency; 172 uint32_t MaxGfxclkFrequency; 173 uint32_t MinGfxclkFrequency; 174 uint32_t FclkFrequencyTable[4]; 175 uint32_t UclkFrequencyTable[4]; 176 uint32_t SocclkFrequencyTable[4]; 177 uint32_t VclkFrequencyTable[4]; 178 uint32_t DclkFrequencyTable[4]; 179 uint32_t LclkFrequencyTable[4]; 180 uint32_t MaxLclkDpmRange; 181 uint32_t MinLclkDpmRange; 182 183 //XGMI 184 uint32_t XgmiWidth; 185 uint32_t XgmiBitrate; 186 uint64_t XgmiReadBandwidthAcc[8]; 187 uint64_t XgmiWriteBandwidthAcc[8]; 188 189 //ACTIVITY 190 uint32_t SocketC0Residency; 191 uint32_t SocketGfxBusy; 192 uint32_t DramBandwidthUtilization; 193 uint64_t SocketC0ResidencyAcc; 194 uint64_t SocketGfxBusyAcc; 195 uint64_t DramBandwidthAcc; 196 uint32_t MaxDramBandwidth; 197 uint64_t DramBandwidthUtilizationAcc; 198 uint64_t PcieBandwidthAcc[4]; 199 200 //THROTTLERS 201 uint32_t ProchotResidencyAcc; 202 uint32_t PptResidencyAcc; 203 uint32_t SocketThmResidencyAcc; 204 uint32_t VrThmResidencyAcc; 205 uint32_t HbmThmResidencyAcc; 206 uint32_t GfxLockXCDMak; 207 208 // New Items at end to maintain driver compatibility 209 uint32_t GfxclkFrequency[8]; 210 211 //PSNs 212 uint64_t PublicSerialNumber_AID[4]; 213 uint64_t PublicSerialNumber_XCD[8]; 214 uint64_t PublicSerialNumber_CCD[12]; 215 216 //XGMI Data tranfser size 217 uint64_t XgmiReadDataSizeAcc[8];//in KByte 218 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 219 220 //PCIE BW Data and error count 221 uint32_t PcieBandwidth[4]; 222 uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated 223 uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated 224 uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated 225 uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated 226 uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated 227 228 // VCN/JPEG ACTIVITY 229 uint32_t VcnBusy[4]; 230 uint32_t JpegBusy[32]; 231 232 // PCIE LINK Speed and width 233 uint32_t PCIeLinkSpeed; 234 uint32_t PCIeLinkWidth; 235 236 // PER XCD ACTIVITY 237 uint32_t GfxBusy[8]; 238 uint64_t GfxBusyAcc[8]; 239 240 //PCIE BW Data and error count 241 uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated 242 243 //Total App Clock Counter 244 uint64_t GfxclkBelowHostLimitPptAcc[8]; 245 uint64_t GfxclkBelowHostLimitThmAcc[8]; 246 uint64_t GfxclkBelowHostLimitTotalAcc[8]; 247 uint64_t GfxclkLowUtilizationAcc[8]; 248 } MetricsTableV0_t; 249 250 // Metrics table for smu_v13_0_6 APUS 251 typedef struct __attribute__((packed, aligned(4))) { 252 uint32_t AccumulationCounter; 253 254 //TEMPERATURE 255 uint32_t MaxSocketTemperature; 256 uint32_t MaxVrTemperature; 257 uint32_t MaxHbmTemperature; 258 uint64_t MaxSocketTemperatureAcc; 259 uint64_t MaxVrTemperatureAcc; 260 uint64_t MaxHbmTemperatureAcc; 261 262 //POWER 263 uint32_t SocketPowerLimit; 264 uint32_t MaxSocketPowerLimit; 265 uint32_t SocketPower; 266 267 //ENERGY 268 uint64_t Timestamp; 269 uint64_t SocketEnergyAcc; 270 uint64_t CcdEnergyAcc; 271 uint64_t XcdEnergyAcc; 272 uint64_t AidEnergyAcc; 273 uint64_t HbmEnergyAcc; 274 275 //FREQUENCY 276 uint32_t CclkFrequencyLimit; 277 uint32_t GfxclkFrequencyLimit; 278 uint32_t FclkFrequency; 279 uint32_t UclkFrequency; 280 uint32_t SocclkFrequency[4]; 281 uint32_t VclkFrequency[4]; 282 uint32_t DclkFrequency[4]; 283 uint32_t LclkFrequency[4]; 284 uint64_t GfxclkFrequencyAcc[8]; 285 uint64_t CclkFrequencyAcc[96]; 286 287 //FREQUENCY RANGE 288 uint32_t MaxCclkFrequency; 289 uint32_t MinCclkFrequency; 290 uint32_t MaxGfxclkFrequency; 291 uint32_t MinGfxclkFrequency; 292 uint32_t FclkFrequencyTable[4]; 293 uint32_t UclkFrequencyTable[4]; 294 uint32_t SocclkFrequencyTable[4]; 295 uint32_t VclkFrequencyTable[4]; 296 uint32_t DclkFrequencyTable[4]; 297 uint32_t LclkFrequencyTable[4]; 298 uint32_t MaxLclkDpmRange; 299 uint32_t MinLclkDpmRange; 300 301 //XGMI 302 uint32_t XgmiWidth; 303 uint32_t XgmiBitrate; 304 uint64_t XgmiReadBandwidthAcc[8]; 305 uint64_t XgmiWriteBandwidthAcc[8]; 306 307 //ACTIVITY 308 uint32_t SocketC0Residency; 309 uint32_t SocketGfxBusy; 310 uint32_t DramBandwidthUtilization; 311 uint64_t SocketC0ResidencyAcc; 312 uint64_t SocketGfxBusyAcc; 313 uint64_t DramBandwidthAcc; 314 uint32_t MaxDramBandwidth; 315 uint64_t DramBandwidthUtilizationAcc; 316 uint64_t PcieBandwidthAcc[4]; 317 318 //THROTTLERS 319 uint32_t ProchotResidencyAcc; 320 uint32_t PptResidencyAcc; 321 uint32_t SocketThmResidencyAcc; 322 uint32_t VrThmResidencyAcc; 323 uint32_t HbmThmResidencyAcc; 324 uint32_t GfxLockXCDMak; 325 326 // New Items at end to maintain driver compatibility 327 uint32_t GfxclkFrequency[8]; 328 329 //PSNs 330 uint64_t PublicSerialNumber_AID[4]; 331 uint64_t PublicSerialNumber_XCD[8]; 332 uint64_t PublicSerialNumber_CCD[12]; 333 334 //XGMI Data tranfser size 335 uint64_t XgmiReadDataSizeAcc[8];//in KByte 336 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 337 338 // VCN/JPEG ACTIVITY 339 uint32_t VcnBusy[4]; 340 uint32_t JpegBusy[32]; 341 } MetricsTableV1_t; 342 343 // Metrics table for smu_v13_0_12 344 typedef struct __attribute__((packed, aligned(4))) { 345 uint64_t AccumulationCounter; 346 347 //TEMPERATURE 348 uint32_t MaxSocketTemperature; 349 uint32_t MaxVrTemperature; 350 uint32_t MaxHbmTemperature; 351 uint64_t MaxSocketTemperatureAcc; 352 uint64_t MaxVrTemperatureAcc; 353 uint64_t MaxHbmTemperatureAcc; 354 355 //POWER 356 uint32_t SocketPowerLimit; 357 uint32_t MaxSocketPowerLimit; 358 uint32_t SocketPower; 359 360 //ENERGY 361 uint64_t Timestamp; 362 uint64_t SocketEnergyAcc; 363 uint64_t CcdEnergyAcc; 364 uint64_t XcdEnergyAcc; 365 uint64_t AidEnergyAcc; 366 uint64_t HbmEnergyAcc; 367 368 //FREQUENCY 369 uint32_t GfxclkFrequencyLimit; 370 uint32_t FclkFrequency; 371 uint32_t UclkFrequency; 372 uint32_t SocclkFrequency[4]; 373 uint32_t VclkFrequency[4]; 374 uint32_t DclkFrequency[4]; 375 uint32_t LclkFrequency[4]; 376 uint64_t GfxclkFrequencyAcc[8]; 377 378 //FREQUENCY RANGE 379 uint32_t MaxGfxclkFrequency; 380 uint32_t MinGfxclkFrequency; 381 uint32_t FclkFrequencyTable[4]; 382 uint32_t UclkFrequencyTable[4]; 383 uint32_t SocclkFrequencyTable[4]; 384 uint32_t VclkFrequencyTable[4]; 385 uint32_t DclkFrequencyTable[4]; 386 uint32_t LclkFrequencyTable[4]; 387 uint32_t MaxLclkDpmRange; 388 uint32_t MinLclkDpmRange; 389 390 //XGMI 391 uint32_t XgmiWidth; 392 uint32_t XgmiBitrate; 393 uint64_t XgmiReadBandwidthAcc[8]; 394 uint64_t XgmiWriteBandwidthAcc[8]; 395 396 //ACTIVITY 397 uint32_t SocketGfxBusy; 398 uint32_t DramBandwidthUtilization; 399 uint64_t SocketC0ResidencyAcc; 400 uint64_t SocketGfxBusyAcc; 401 uint64_t DramBandwidthAcc; 402 uint32_t MaxDramBandwidth; 403 uint64_t DramBandwidthUtilizationAcc; 404 uint64_t PcieBandwidthAcc[4]; 405 406 //THROTTLERS 407 uint32_t ProchotResidencyAcc; 408 uint32_t PptResidencyAcc; 409 uint32_t SocketThmResidencyAcc; 410 uint32_t VrThmResidencyAcc; 411 uint32_t HbmThmResidencyAcc; 412 uint32_t GfxLockXCDMak; 413 414 // New Items at end to maintain driver compatibility 415 uint32_t GfxclkFrequency[8]; 416 417 //PSNs 418 uint64_t PublicSerialNumber_AID[4]; 419 uint64_t PublicSerialNumber_XCD[8]; 420 421 //XGMI Data tranfser size 422 uint64_t XgmiReadDataSizeAcc[8];//in KByte 423 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 424 425 //PCIE BW Data and error count 426 uint32_t PcieBandwidth[4]; 427 uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated 428 uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated 429 uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated 430 uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated 431 uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated 432 433 // VCN/JPEG ACTIVITY 434 uint32_t VcnBusy[4]; 435 uint32_t JpegBusy[32]; 436 437 // PCIE LINK Speed and width 438 uint32_t PCIeLinkSpeed; 439 uint32_t PCIeLinkWidth; 440 441 // PER XCD ACTIVITY 442 uint32_t GfxBusy[8]; 443 uint64_t GfxBusyAcc[8]; 444 445 //PCIE BW Data and error count 446 uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated 447 448 //Total App Clock Counter 449 uint64_t GfxclkBelowHostLimitAcc[8]; 450 } MetricsTableV2_t; 451 452 #define SMU_VF_METRICS_TABLE_VERSION 0x5 453 454 typedef struct __attribute__((packed, aligned(4))) { 455 uint32_t AccumulationCounter; 456 uint32_t InstGfxclk_TargFreq; 457 uint64_t AccGfxclk_TargFreq; 458 uint64_t AccGfxRsmuDpm_Busy; 459 uint64_t AccGfxclkBelowHostLimit; 460 } VfMetricsTable_t; 461 462 #pragma pack(push, 4) 463 typedef struct { 464 // Telemetry 465 uint32_t InputTelemetryVoltageInmV; 466 // General info 467 uint32_t pldmVersion[2]; 468 } StaticMetricsTable_t; 469 #pragma pack(pop) 470 471 #endif 472