1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RNG driver for Exynos TRNGs
4 *
5 * Author: Łukasz Stelmach <l.stelmach@samsung.com>
6 *
7 * Copyright 2017 (c) Samsung Electronics Software, Inc.
8 *
9 * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by
10 * Krzysztof Kozłowski <krzk@kernel.org>
11 */
12
13 #include <linux/arm-smccc.h>
14 #include <linux/clk.h>
15 #include <linux/crypto.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/hw_random.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/property.h>
26
27 #define EXYNOS_TRNG_CLKDIV 0x0
28
29 #define EXYNOS_TRNG_CTRL 0x20
30 #define EXYNOS_TRNG_CTRL_RNGEN BIT(31)
31
32 #define EXYNOS_TRNG_POST_CTRL 0x30
33 #define EXYNOS_TRNG_ONLINE_CTRL 0x40
34 #define EXYNOS_TRNG_ONLINE_STAT 0x44
35 #define EXYNOS_TRNG_ONLINE_MAXCHI2 0x48
36 #define EXYNOS_TRNG_FIFO_CTRL 0x50
37 #define EXYNOS_TRNG_FIFO_0 0x80
38 #define EXYNOS_TRNG_FIFO_1 0x84
39 #define EXYNOS_TRNG_FIFO_2 0x88
40 #define EXYNOS_TRNG_FIFO_3 0x8c
41 #define EXYNOS_TRNG_FIFO_4 0x90
42 #define EXYNOS_TRNG_FIFO_5 0x94
43 #define EXYNOS_TRNG_FIFO_6 0x98
44 #define EXYNOS_TRNG_FIFO_7 0x9c
45 #define EXYNOS_TRNG_FIFO_LEN 8
46 #define EXYNOS_TRNG_CLOCK_RATE 500000
47
48 /* Driver feature flags */
49 #define EXYNOS_SMC BIT(0)
50
51 #define EXYNOS_SMC_CALL_VAL(func_num) \
52 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
53 ARM_SMCCC_SMC_32, \
54 ARM_SMCCC_OWNER_SIP, \
55 func_num)
56
57 /* SMC command for DTRNG access */
58 #define SMC_CMD_RANDOM EXYNOS_SMC_CALL_VAL(0x1012)
59
60 /* SMC_CMD_RANDOM: arguments */
61 #define HWRNG_INIT 0x0
62 #define HWRNG_EXIT 0x1
63 #define HWRNG_GET_DATA 0x2
64 #define HWRNG_RESUME 0x3
65
66 /* SMC_CMD_RANDOM: return values */
67 #define HWRNG_RET_OK 0x0
68 #define HWRNG_RET_RETRY_ERROR 0x2
69
70 #define HWRNG_MAX_TRIES 100
71
72 struct exynos_trng_dev {
73 struct device *dev;
74 void __iomem *mem;
75 struct clk *clk; /* operating clock */
76 struct clk *pclk; /* bus clock */
77 struct hwrng rng;
78 unsigned long flags;
79 };
80
exynos_trng_do_read_reg(struct hwrng * rng,void * data,size_t max,bool wait)81 static int exynos_trng_do_read_reg(struct hwrng *rng, void *data, size_t max,
82 bool wait)
83 {
84 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
85 int val;
86
87 max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4));
88 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
89 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
90 val == 0, 200, 1000000);
91 if (val < 0)
92 return val;
93
94 memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max);
95
96 return max;
97 }
98
exynos_trng_do_read_smc(struct hwrng * rng,void * data,size_t max,bool wait)99 static int exynos_trng_do_read_smc(struct hwrng *rng, void *data, size_t max,
100 bool wait)
101 {
102 struct arm_smccc_res res;
103 unsigned int copied = 0;
104 u32 *buf = data;
105 int tries = 0;
106
107 while (copied < max) {
108 arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_GET_DATA, 0, 0, 0, 0, 0, 0,
109 &res);
110 switch (res.a0) {
111 case HWRNG_RET_OK:
112 *buf++ = res.a2;
113 *buf++ = res.a3;
114 copied += 8;
115 tries = 0;
116 break;
117 case HWRNG_RET_RETRY_ERROR:
118 if (!wait)
119 return copied;
120 if (++tries >= HWRNG_MAX_TRIES)
121 return copied;
122 cond_resched();
123 break;
124 default:
125 return -EIO;
126 }
127 }
128
129 return copied;
130 }
131
exynos_trng_init_reg(struct hwrng * rng)132 static int exynos_trng_init_reg(struct hwrng *rng)
133 {
134 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
135 unsigned long sss_rate;
136 u32 val;
137
138 sss_rate = clk_get_rate(trng->clk);
139
140 /*
141 * For most TRNG circuits the clock frequency of under 500 kHz
142 * is safe.
143 */
144 val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2);
145 if (val > 0x7fff) {
146 dev_err(trng->dev, "clock divider too large: %d\n", val);
147 return -ERANGE;
148 }
149 val = val << 1;
150 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
151
152 /* Enable the generator. */
153 val = EXYNOS_TRNG_CTRL_RNGEN;
154 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);
155
156 /*
157 * Disable post-processing. /dev/hwrng is supposed to deliver
158 * unprocessed data.
159 */
160 writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
161
162 return 0;
163 }
164
exynos_trng_init_smc(struct hwrng * rng)165 static int exynos_trng_init_smc(struct hwrng *rng)
166 {
167 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
168 struct arm_smccc_res res;
169 int ret = 0;
170
171 arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_INIT, 0, 0, 0, 0, 0, 0, &res);
172 if (res.a0 != HWRNG_RET_OK) {
173 dev_err(trng->dev, "SMC command for TRNG init failed (%d)\n",
174 (int)res.a0);
175 ret = -EIO;
176 }
177 if ((int)res.a0 == -1)
178 dev_info(trng->dev, "Make sure LDFW is loaded by your BL\n");
179
180 return ret;
181 }
182
exynos_trng_probe(struct platform_device * pdev)183 static int exynos_trng_probe(struct platform_device *pdev)
184 {
185 struct exynos_trng_dev *trng;
186 int ret = -ENOMEM;
187
188 trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
189 if (!trng)
190 return ret;
191
192 platform_set_drvdata(pdev, trng);
193 trng->dev = &pdev->dev;
194
195 trng->flags = (unsigned long)device_get_match_data(&pdev->dev);
196
197 trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev),
198 GFP_KERNEL);
199 if (!trng->rng.name)
200 return ret;
201
202 trng->rng.priv = (unsigned long)trng;
203
204 if (trng->flags & EXYNOS_SMC) {
205 trng->rng.init = exynos_trng_init_smc;
206 trng->rng.read = exynos_trng_do_read_smc;
207 } else {
208 trng->rng.init = exynos_trng_init_reg;
209 trng->rng.read = exynos_trng_do_read_reg;
210
211 trng->mem = devm_platform_ioremap_resource(pdev, 0);
212 if (IS_ERR(trng->mem))
213 return PTR_ERR(trng->mem);
214 }
215
216 pm_runtime_enable(&pdev->dev);
217 ret = pm_runtime_resume_and_get(&pdev->dev);
218 if (ret < 0) {
219 dev_err(&pdev->dev, "Could not get runtime PM.\n");
220 goto err_pm_get;
221 }
222
223 trng->clk = devm_clk_get_enabled(&pdev->dev, "secss");
224 if (IS_ERR(trng->clk)) {
225 ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->clk),
226 "Could not get clock\n");
227 goto err_clock;
228 }
229
230 trng->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
231 if (IS_ERR(trng->pclk)) {
232 ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->pclk),
233 "Could not get pclk\n");
234 goto err_clock;
235 }
236
237 ret = devm_hwrng_register(&pdev->dev, &trng->rng);
238 if (ret) {
239 dev_err(&pdev->dev, "Could not register hwrng device.\n");
240 goto err_clock;
241 }
242
243 dev_info(&pdev->dev, "Exynos True Random Number Generator.\n");
244
245 return 0;
246
247 err_clock:
248 pm_runtime_put_noidle(&pdev->dev);
249
250 err_pm_get:
251 pm_runtime_disable(&pdev->dev);
252
253 return ret;
254 }
255
exynos_trng_remove(struct platform_device * pdev)256 static void exynos_trng_remove(struct platform_device *pdev)
257 {
258 struct exynos_trng_dev *trng = platform_get_drvdata(pdev);
259
260 if (trng->flags & EXYNOS_SMC) {
261 struct arm_smccc_res res;
262
263 arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_EXIT, 0, 0, 0, 0, 0, 0,
264 &res);
265 }
266
267 pm_runtime_put_sync(&pdev->dev);
268 pm_runtime_disable(&pdev->dev);
269 }
270
exynos_trng_suspend(struct device * dev)271 static int exynos_trng_suspend(struct device *dev)
272 {
273 struct exynos_trng_dev *trng = dev_get_drvdata(dev);
274 struct arm_smccc_res res;
275
276 if (trng->flags & EXYNOS_SMC) {
277 arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_EXIT, 0, 0, 0, 0, 0, 0,
278 &res);
279 if (res.a0 != HWRNG_RET_OK)
280 return -EIO;
281 }
282
283 pm_runtime_put_sync(dev);
284
285 return 0;
286 }
287
exynos_trng_resume(struct device * dev)288 static int exynos_trng_resume(struct device *dev)
289 {
290 struct exynos_trng_dev *trng = dev_get_drvdata(dev);
291 int ret;
292
293 ret = pm_runtime_resume_and_get(dev);
294 if (ret < 0) {
295 dev_err(dev, "Could not get runtime PM.\n");
296 return ret;
297 }
298
299 if (trng->flags & EXYNOS_SMC) {
300 struct arm_smccc_res res;
301
302 arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_RESUME, 0, 0, 0, 0, 0, 0,
303 &res);
304 if (res.a0 != HWRNG_RET_OK)
305 return -EIO;
306
307 arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_INIT, 0, 0, 0, 0, 0, 0,
308 &res);
309 if (res.a0 != HWRNG_RET_OK)
310 return -EIO;
311 }
312
313 return 0;
314 }
315
316 static DEFINE_SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend,
317 exynos_trng_resume);
318
319 static const struct of_device_id exynos_trng_dt_match[] = {
320 {
321 .compatible = "samsung,exynos5250-trng",
322 }, {
323 .compatible = "samsung,exynos850-trng",
324 .data = (void *)EXYNOS_SMC,
325 },
326 { },
327 };
328 MODULE_DEVICE_TABLE(of, exynos_trng_dt_match);
329
330 static struct platform_driver exynos_trng_driver = {
331 .driver = {
332 .name = "exynos-trng",
333 .pm = pm_sleep_ptr(&exynos_trng_pm_ops),
334 .of_match_table = exynos_trng_dt_match,
335 },
336 .probe = exynos_trng_probe,
337 .remove = exynos_trng_remove,
338 };
339
340 module_platform_driver(exynos_trng_driver);
341
342 MODULE_AUTHOR("Łukasz Stelmach");
343 MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips");
344 MODULE_LICENSE("GPL v2");
345