1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2010-2015 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Exynos - Power management unit definition 7 * 8 * Notice: 9 * This is not a list of all Exynos Power Management Unit SFRs. 10 * There are too many of them, not mentioning subtle differences 11 * between SoCs. For now, put here only the used registers. 12 */ 13 14 #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H 15 #define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__ 16 17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 18 19 #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 20 21 #define S5P_CENTRAL_SEQ_OPTION 0x0208 22 23 #define S5P_USE_STANDBY_WFI0 (1 << 16) 24 #define S5P_USE_STANDBY_WFI1 (1 << 17) 25 #define S5P_USE_STANDBY_WFI2 (1 << 19) 26 #define S5P_USE_STANDBY_WFI3 (1 << 20) 27 #define S5P_USE_STANDBY_WFE0 (1 << 24) 28 #define S5P_USE_STANDBY_WFE1 (1 << 25) 29 #define S5P_USE_STANDBY_WFE2 (1 << 27) 30 #define S5P_USE_STANDBY_WFE3 (1 << 28) 31 32 #define S5P_USE_STANDBY_WFI_ALL \ 33 (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \ 34 S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \ 35 S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \ 36 S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3) 37 38 #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) 39 40 #define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n) 41 #define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28) 42 #define EXYNOS_SWRESET 0x0400 43 44 #define S5P_WAKEUP_STAT 0x0600 45 /* Value for EXYNOS_EINT_WAKEUP_MASK disabling all external wakeup interrupts */ 46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff 47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604 48 #define S5P_WAKEUP_MASK 0x0608 49 #define S5P_WAKEUP_MASK2 0x0614 50 51 /* MIPI_PHYn_CONTROL, valid for Exynos3250, Exynos4, Exynos5250 and Exynos5433 */ 52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4) 53 /* Phy enable bit, common for all phy registers, not only MIPI */ 54 #define EXYNOS4_PHY_ENABLE (1 << 0) 55 #define EXYNOS4_MIPI_PHY_SRESETN (1 << 1) 56 #define EXYNOS4_MIPI_PHY_MRESETN (1 << 2) 57 #define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1) 58 /* USB PHY enable bit, valid for Exynos7870 */ 59 #define EXYNOS7870_USB2PHY_ENABLE (1 << 1) 60 61 #define S5P_INFORM0 0x0800 62 #define S5P_INFORM1 0x0804 63 #define S5P_INFORM5 0x0814 64 #define S5P_INFORM6 0x0818 65 #define S5P_INFORM7 0x081C 66 #define S5P_PMU_SPARE2 0x0908 67 #define S5P_PMU_SPARE3 0x090C 68 69 #define EXYNOS_IROM_DATA2 0x0988 70 #define S5P_ARM_CORE0_LOWPWR 0x1000 71 #define S5P_DIS_IRQ_CORE0 0x1004 72 #define S5P_DIS_IRQ_CENTRAL0 0x1008 73 #define S5P_ARM_CORE1_LOWPWR 0x1010 74 #define S5P_DIS_IRQ_CORE1 0x1014 75 #define S5P_DIS_IRQ_CENTRAL1 0x1018 76 #define S5P_ARM_COMMON_LOWPWR 0x1080 77 #define S5P_L2_0_LOWPWR 0x10C0 78 #define S5P_L2_1_LOWPWR 0x10C4 79 #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 80 #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 81 #define S5P_CMU_RESET_LOWPWR 0x110C 82 #define S5P_APLL_SYSCLK_LOWPWR 0x1120 83 #define S5P_MPLL_SYSCLK_LOWPWR 0x1124 84 #define S5P_VPLL_SYSCLK_LOWPWR 0x1128 85 #define S5P_EPLL_SYSCLK_LOWPWR 0x112C 86 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 87 #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C 88 #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 89 #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 90 #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 91 #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C 92 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 93 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 94 #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C 95 #define S5P_CMU_RESET_CAM_LOWPWR 0x1160 96 #define S5P_CMU_RESET_TV_LOWPWR 0x1164 97 #define S5P_CMU_RESET_MFC_LOWPWR 0x1168 98 #define S5P_CMU_RESET_G3D_LOWPWR 0x116C 99 #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 100 #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 101 #define S5P_CMU_RESET_GPS_LOWPWR 0x117C 102 #define S5P_TOP_BUS_LOWPWR 0x1180 103 #define S5P_TOP_RETENTION_LOWPWR 0x1184 104 #define S5P_TOP_PWR_LOWPWR 0x1188 105 #define S5P_LOGIC_RESET_LOWPWR 0x11A0 106 #define S5P_ONENAND_MEM_LOWPWR 0x11C0 107 #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 108 #define S5P_USBOTG_MEM_LOWPWR 0x11CC 109 #define S5P_HSMMC_MEM_LOWPWR 0x11D0 110 #define S5P_CSSYS_MEM_LOWPWR 0x11D4 111 #define S5P_SECSS_MEM_LOWPWR 0x11D8 112 #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 113 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 114 #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 115 #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 116 #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 117 #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C 118 #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 119 #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 120 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 121 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 122 #define S5P_XUSBXTI_LOWPWR 0x1280 123 #define S5P_XXTI_LOWPWR 0x1284 124 #define S5P_EXT_REGULATOR_LOWPWR 0x12C0 125 #define S5P_GPIO_MODE_LOWPWR 0x1300 126 #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 127 #define S5P_CAM_LOWPWR 0x1380 128 #define S5P_TV_LOWPWR 0x1384 129 #define S5P_MFC_LOWPWR 0x1388 130 #define S5P_G3D_LOWPWR 0x138C 131 #define S5P_LCD0_LOWPWR 0x1390 132 #define S5P_MAUDIO_LOWPWR 0x1398 133 #define S5P_GPS_LOWPWR 0x139C 134 #define S5P_GPS_ALIVE_LOWPWR 0x13A0 135 136 #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 137 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 138 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 139 #define EXYNOS_ARM_CORE_STATUS(_nr) \ 140 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 141 #define EXYNOS_ARM_CORE_OPTION(_nr) \ 142 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) 143 144 #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 145 #define EXYNOS_COMMON_CONFIGURATION(_nr) \ 146 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 147 #define EXYNOS_COMMON_STATUS(_nr) \ 148 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) 149 #define EXYNOS_COMMON_OPTION(_nr) \ 150 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 151 152 #define EXYNOS_ARM_L2_CONFIGURATION 0x2600 153 #define EXYNOS_L2_CONFIGURATION(_nr) \ 154 (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) 155 #define EXYNOS_L2_STATUS(_nr) \ 156 (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) 157 #define EXYNOS_L2_OPTION(_nr) \ 158 (EXYNOS_L2_CONFIGURATION(_nr) + 0x8) 159 160 #define EXYNOS_L2_USE_RETENTION BIT(4) 161 162 #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 163 #define S5P_PAD_RET_MMC2_OPTION 0x30c8 164 #define S5P_PAD_RET_GPIO_OPTION 0x3108 165 #define S5P_PAD_RET_UART_OPTION 0x3128 166 #define S5P_PAD_RET_MMCA_OPTION 0x3148 167 #define S5P_PAD_RET_MMCB_OPTION 0x3168 168 #define S5P_PAD_RET_EBIA_OPTION 0x3188 169 #define S5P_PAD_RET_EBIB_OPTION 0x31A8 170 #define S5P_PAD_RET_SPI_OPTION 0x31c8 171 172 #define S5P_PS_HOLD_CONTROL 0x330C 173 #define S5P_PS_HOLD_EN (1 << 31) 174 #define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8) 175 176 #define S5P_CAM_OPTION 0x3C08 177 #define S5P_MFC_OPTION 0x3C48 178 #define S5P_G3D_OPTION 0x3C68 179 #define S5P_LCD0_OPTION 0x3C88 180 #define S5P_LCD1_OPTION 0x3CA8 181 #define S5P_ISP_OPTION S5P_LCD1_OPTION 182 183 #define S5P_CORE_LOCAL_PWR_EN 0x3 184 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) 185 #define S5P_CORE_AUTOWAKEUP_EN (1 << 31) 186 187 /* Only for S5Pv210 */ 188 #define S5PV210_EINT_WAKEUP_MASK 0xC004 189 190 /* Only for Exynos2200 */ 191 #define EXYNOS2200_PHY_CTRL_USB20 0x72C 192 193 /* Only for Exynos4210 */ 194 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 195 #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 196 #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 197 #define S5P_PCIE_MEM_LOWPWR 0x11E0 198 #define S5P_SATA_MEM_LOWPWR 0x11E4 199 #define S5P_LCD1_LOWPWR 0x1394 200 201 /* Only for Exynos4x12 */ 202 #define S5P_ISP_ARM_LOWPWR 0x1050 203 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 204 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 205 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 206 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 207 #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C 208 #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 209 #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 210 #define S5P_CMU_RESET_ISP_LOWPWR 0x1174 211 #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 212 #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 213 #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 214 #define S5P_OSCCLK_GATE_LOWPWR 0x11A4 215 #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 216 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 217 #define S5P_HSI_MEM_LOWPWR 0x11C4 218 #define S5P_ROTATOR_MEM_LOWPWR 0x11DC 219 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C 220 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 221 #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 222 #define S5P_TOP_ASB_RESET_LOWPWR 0x1344 223 #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 224 #define S5P_ISP_LOWPWR 0x1394 225 #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 226 #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 227 #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 228 #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC 229 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 230 231 #define S5P_ARM_L2_0_OPTION 0x2608 232 #define S5P_ARM_L2_1_OPTION 0x2628 233 #define S5P_ONENAND_MEM_OPTION 0x2E08 234 #define S5P_HSI_MEM_OPTION 0x2E28 235 #define S5P_G2D_ACP_MEM_OPTION 0x2E48 236 #define S5P_USBOTG_MEM_OPTION 0x2E68 237 #define S5P_HSMMC_MEM_OPTION 0x2E88 238 #define S5P_CSSYS_MEM_OPTION 0x2EA8 239 #define S5P_SECSS_MEM_OPTION 0x2EC8 240 #define S5P_ROTATOR_MEM_OPTION 0x2F48 241 242 /* Only for Exynos4412 */ 243 #define S5P_ARM_CORE2_LOWPWR 0x1020 244 #define S5P_DIS_IRQ_CORE2 0x1024 245 #define S5P_DIS_IRQ_CENTRAL2 0x1028 246 #define S5P_ARM_CORE3_LOWPWR 0x1030 247 #define S5P_DIS_IRQ_CORE3 0x1034 248 #define S5P_DIS_IRQ_CENTRAL3 0x1038 249 250 /* Only for Exynos3XXX */ 251 #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000 252 #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 253 #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 254 #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010 255 #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 256 #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 257 #define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050 258 #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 259 #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 260 #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080 261 #define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0 262 #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 263 #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 264 #define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C 265 #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110 266 #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114 267 #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C 268 #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120 269 #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124 270 #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128 271 #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C 272 #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130 273 #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134 274 #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138 275 #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 276 #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 277 #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C 278 #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 279 #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154 280 #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 281 #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160 282 #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168 283 #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C 284 #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170 285 #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174 286 #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 287 #define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180 288 #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184 289 #define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188 290 #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190 291 #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194 292 #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198 293 #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0 294 #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4 295 #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0 296 #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4 297 #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 298 #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 299 #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208 300 #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218 301 #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 302 #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 303 #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228 304 #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C 305 #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 306 #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 307 #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238 308 #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240 309 #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260 310 #define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280 311 #define EXYNOS3_XXTI_SYS_PWR_REG 0x1284 312 #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0 313 #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4 314 #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300 315 #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 316 #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344 317 #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 318 #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350 319 #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354 320 #define EXYNOS3_CAM_SYS_PWR_REG 0x1380 321 #define EXYNOS3_MFC_SYS_PWR_REG 0x1388 322 #define EXYNOS3_G3D_SYS_PWR_REG 0x138C 323 #define EXYNOS3_LCD0_SYS_PWR_REG 0x1390 324 #define EXYNOS3_ISP_SYS_PWR_REG 0x1394 325 #define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398 326 #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0 327 #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4 328 #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8 329 #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0 330 #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4 331 #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8 332 333 #define EXYNOS3_ARM_CORE0_OPTION 0x2008 334 #define EXYNOS3_ARM_CORE_OPTION(_nr) \ 335 (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80)) 336 337 #define EXYNOS3_ARM_COMMON_OPTION 0x2408 338 #define EXYNOS3_ARM_L2_OPTION 0x2608 339 #define EXYNOS3_TOP_PWR_OPTION 0x2C48 340 #define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8 341 #define EXYNOS3_XUSBXTI_DURATION 0x341C 342 #define EXYNOS3_XXTI_DURATION 0x343C 343 #define EXYNOS3_EXT_REGULATOR_DURATION 0x361C 344 #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C 345 #define XUSBXTI_DURATION 0x00000BB8 346 #define XXTI_DURATION XUSBXTI_DURATION 347 #define EXT_REGULATOR_DURATION 0x00001D4C 348 #define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION 349 350 /* for XXX_OPTION */ 351 #define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0) 352 #define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1) 353 #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) 354 355 /* For Exynos5 */ 356 357 #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 358 #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C 359 #define EXYNOS5_USBDRD_PHY_CONTROL 0x0704 360 #define EXYNOS5_DPTX_PHY_CONTROL 0x0720 361 362 #define EXYNOS5_USE_RETENTION BIT(4) 363 #define EXYNOS5_SYS_WDTRESET (1 << 20) 364 365 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 366 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 367 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 368 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 369 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 370 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 371 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 372 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 373 #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 374 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 375 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 376 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 377 #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 378 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 379 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 380 #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C 381 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 382 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 383 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C 384 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 385 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 386 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 387 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 388 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 389 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 390 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C 391 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 392 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 393 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 394 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 395 #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 396 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 397 #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 398 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 399 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 400 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 401 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 402 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 403 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 404 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 405 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 406 #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 407 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC 408 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 409 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 410 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 411 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC 412 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 413 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 414 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 415 #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC 416 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 417 #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC 418 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 419 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 420 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 421 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 422 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 423 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C 424 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 425 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 426 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 427 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C 428 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 429 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 430 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 431 #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 432 #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 433 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 434 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 435 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 436 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 437 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 438 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 439 #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 440 #define EXYNOS5_ISP_SYS_PWR_REG 0x1404 441 #define EXYNOS5_MFC_SYS_PWR_REG 0x1408 442 #define EXYNOS5_G3D_SYS_PWR_REG 0x140C 443 #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 444 #define EXYNOS5_MAU_SYS_PWR_REG 0x1418 445 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 446 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 447 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 448 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C 449 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 450 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 451 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 452 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 453 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 454 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC 455 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 456 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 457 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 458 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 459 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 460 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C 461 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 462 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 463 464 #define EXYNOS5_ARM_CORE0_OPTION 0x2008 465 #define EXYNOS5_ARM_CORE1_OPTION 0x2088 466 #define EXYNOS5_FSYS_ARM_OPTION 0x2208 467 #define EXYNOS5_ISP_ARM_OPTION 0x2288 468 #define EXYNOS5_ARM_COMMON_OPTION 0x2408 469 #define EXYNOS5_ARM_L2_OPTION 0x2608 470 #define EXYNOS5_TOP_PWR_OPTION 0x2C48 471 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 472 #define EXYNOS5_JPEG_MEM_OPTION 0x2F48 473 #define EXYNOS5_GSCL_OPTION 0x4008 474 #define EXYNOS5_ISP_OPTION 0x4028 475 #define EXYNOS5_MFC_OPTION 0x4048 476 #define EXYNOS5_G3D_OPTION 0x4068 477 #define EXYNOS5_DISP1_OPTION 0x40A8 478 #define EXYNOS5_MAU_OPTION 0x40C8 479 480 #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 481 #define EXYNOS5_USE_SC_COUNTER (1 << 0) 482 483 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) 484 485 #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) 486 #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) 487 488 #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) 489 490 #define EXYNOS5420_SWRESET_KFC_SEL 0x3 491 492 /* Only for Exynos5420 */ 493 #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) 494 495 #define EXYNOS5420_LPI_MASK 0x0004 496 #define EXYNOS5420_LPI_MASK1 0x0008 497 #define EXYNOS5420_UFS BIT(8) 498 #define EXYNOS5420_ATB_KFC BIT(13) 499 #define EXYNOS5420_ATB_ISP_ARM BIT(19) 500 #define EXYNOS5420_EMULATION BIT(31) 501 502 #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100 503 #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104 504 #define EXYNOS5420_UP_SCHEDULER 0x0120 505 #define SPREAD_ENABLE 0xF 506 #define SPREAD_USE_STANDWFI 0xF 507 508 #define EXYNOS5420_KFC_CORE_RESET0 BIT(8) 509 #define EXYNOS5420_KFC_ETM_RESET0 BIT(20) 510 511 #define EXYNOS5420_KFC_CORE_RESET(_nr) \ 512 ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) 513 514 #define EXYNOS5420_USBDRD1_PHY_CONTROL 0x0708 515 #define EXYNOS5420_MIPI_PHY_CONTROL(n) (0x0714 + (n) * 4) 516 #define EXYNOS5420_DPTX_PHY_CONTROL 0x0728 517 #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020 518 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024 519 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028 520 #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030 521 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034 522 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038 523 #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040 524 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044 525 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 526 #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050 527 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054 528 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 529 #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060 530 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064 531 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 532 #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070 533 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074 534 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 535 #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090 536 #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094 537 #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098 538 #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0 539 #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0 540 #define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0 541 #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158 542 #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C 543 #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160 544 #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174 545 #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178 546 #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8 547 #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC 548 #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 549 #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210 550 #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214 551 #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218 552 #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C 553 #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220 554 #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224 555 #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228 556 #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C 557 #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230 558 #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234 559 #define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410 560 #define EXYNOS5420_MAU_SYS_PWR_REG 0x1414 561 #define EXYNOS5420_G2D_SYS_PWR_REG 0x1418 562 #define EXYNOS5420_MSC_SYS_PWR_REG 0x141C 563 #define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420 564 #define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424 565 #define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428 566 #define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C 567 #define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430 568 #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490 569 #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494 570 #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498 571 #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C 572 #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0 573 #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4 574 #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8 575 #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC 576 #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0 577 #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC 578 #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0 579 #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4 580 #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8 581 #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC 582 #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0 583 #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4 584 #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8 585 #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC 586 #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0 587 #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4 588 #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570 589 #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574 590 #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578 591 #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C 592 #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590 593 #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594 594 #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598 595 #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C 596 #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0 597 #define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4 598 #define EXYNOS5420_ARM_COMMON_OPTION 0x2508 599 #define EXYNOS5420_KFC_COMMON_OPTION 0x2588 600 #define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C 601 602 #define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8 603 #define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8 604 #define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108 605 #define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128 606 #define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148 607 #define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168 608 #define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8 609 #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8 610 #define EXYNOS_PAD_RET_DRAM_OPTION 0x3008 611 #define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028 612 #define EXYNOS_PAD_RET_JTAG_OPTION 0x3048 613 #define EXYNOS_PAD_RET_EBIA_OPTION 0x3188 614 #define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8 615 616 #define EXYNOS5420_FSYS2_OPTION 0x4168 617 #define EXYNOS5420_PSGEN_OPTION 0x4188 618 619 #define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) 620 #define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) 621 #define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) 622 #define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) 623 #define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) 624 #define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) 625 #define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) 626 #define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) 627 #define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) 628 #define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) 629 #define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) 630 #define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) 631 #define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) 632 #define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) 633 #define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) 634 #define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) 635 636 #define DUR_WAIT_RESET 0xF 637 638 #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \ 639 | EXYNOS5420_ARM_USE_STANDBY_WFI1 \ 640 | EXYNOS5420_ARM_USE_STANDBY_WFI2 \ 641 | EXYNOS5420_ARM_USE_STANDBY_WFI3 \ 642 | EXYNOS5420_KFC_USE_STANDBY_WFI0 \ 643 | EXYNOS5420_KFC_USE_STANDBY_WFI1 \ 644 | EXYNOS5420_KFC_USE_STANDBY_WFI2 \ 645 | EXYNOS5420_KFC_USE_STANDBY_WFI3) 646 647 /* For Exynos5433 */ 648 #define EXYNOS5433_EINT_WAKEUP_MASK (0x060C) 649 #define EXYNOS5433_USBHOST30_PHY_CONTROL (0x0728) 650 #define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028) 651 #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION (0x30C8) 652 #define EXYNOS5433_PAD_RETENTION_TOP_OPTION (0x3108) 653 #define EXYNOS5433_PAD_RETENTION_UART_OPTION (0x3128) 654 #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION (0x3148) 655 #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION (0x3168) 656 #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION (0x3188) 657 #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION (0x31A8) 658 #define EXYNOS5433_PAD_RETENTION_SPI_OPTION (0x31C8) 659 #define EXYNOS5433_PAD_RETENTION_MIF_OPTION (0x31E8) 660 #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION (0x3228) 661 #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION (0x3248) 662 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268) 663 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) 664 665 /* For Tensor GS101 */ 666 /* PMU ALIVE */ 667 #define GS101_SYSIP_DAT0 (0x810) 668 #define GS101_CPU0_INFORM (0x860) 669 #define GS101_CPU_INFORM(cpu) \ 670 (GS101_CPU0_INFORM + (cpu*4)) 671 #define GS101_SYSTEM_CONFIGURATION (0x3A00) 672 #define GS101_PHY_CTRL_USB20 (0x3EB0) 673 #define GS101_PHY_CTRL_USBDP (0x3EB4) 674 675 /* PMU INTR GEN */ 676 #define GS101_GRP1_INTR_BID_UPEND (0x0108) 677 #define GS101_GRP1_INTR_BID_CLEAR (0x010c) 678 #define GS101_GRP2_INTR_BID_ENABLE (0x0200) 679 #define GS101_GRP2_INTR_BID_UPEND (0x0208) 680 #define GS101_GRP2_INTR_BID_CLEAR (0x020c) 681 682 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ 683