xref: /linux/arch/arm/mach-exynos/common.h (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4  *		http://www.samsung.com
5  *
6  * Common Header for Exynos machines
7  */
8 
9 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
10 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
11 
12 #include <linux/platform_data/cpuidle-exynos.h>
13 
14 #define EXYNOS3250_SOC_ID	0xE3472000
15 #define EXYNOS3_SOC_MASK	0xFFFFF000
16 
17 #define EXYNOS4210_CPU_ID	0x43210000
18 #define EXYNOS4212_CPU_ID	0x43220000
19 #define EXYNOS4412_CPU_ID	0xE4412200
20 #define EXYNOS4_CPU_MASK	0xFFFE0000
21 
22 #define EXYNOS5250_SOC_ID	0x43520000
23 #define EXYNOS5410_SOC_ID	0xE5410000
24 #define EXYNOS5420_SOC_ID	0xE5420000
25 #define EXYNOS5800_SOC_ID	0xE5422000
26 #define EXYNOS5_SOC_MASK	0xFFFFF000
27 
28 extern unsigned long exynos_cpu_id;
29 
30 #define IS_SAMSUNG_CPU(name, id, mask)		\
31 static inline int is_samsung_##name(void)	\
32 {						\
33 	return ((exynos_cpu_id & mask) == (id & mask));	\
34 }
35 
36 IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
37 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
38 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
39 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
40 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
41 IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
42 IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
43 IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
44 
45 #if defined(CONFIG_SOC_EXYNOS3250)
46 # define soc_is_exynos3250()	is_samsung_exynos3250()
47 #else
48 # define soc_is_exynos3250()	0
49 #endif
50 
51 #if defined(CONFIG_CPU_EXYNOS4210)
52 # define soc_is_exynos4210()	is_samsung_exynos4210()
53 #else
54 # define soc_is_exynos4210()	0
55 #endif
56 
57 #if defined(CONFIG_SOC_EXYNOS4212)
58 # define soc_is_exynos4212()	is_samsung_exynos4212()
59 #else
60 # define soc_is_exynos4212()	0
61 #endif
62 
63 #if defined(CONFIG_SOC_EXYNOS4412)
64 # define soc_is_exynos4412()	is_samsung_exynos4412()
65 #else
66 # define soc_is_exynos4412()	0
67 #endif
68 
69 #define EXYNOS4210_REV_0	(0x0)
70 #define EXYNOS4210_REV_1_0	(0x10)
71 #define EXYNOS4210_REV_1_1	(0x11)
72 
73 #if defined(CONFIG_SOC_EXYNOS5250)
74 # define soc_is_exynos5250()	is_samsung_exynos5250()
75 #else
76 # define soc_is_exynos5250()	0
77 #endif
78 
79 #if defined(CONFIG_SOC_EXYNOS5410)
80 # define soc_is_exynos5410()	is_samsung_exynos5410()
81 #else
82 # define soc_is_exynos5410()	0
83 #endif
84 
85 #if defined(CONFIG_SOC_EXYNOS5420)
86 # define soc_is_exynos5420()	is_samsung_exynos5420()
87 #else
88 # define soc_is_exynos5420()	0
89 #endif
90 
91 #if defined(CONFIG_SOC_EXYNOS5800)
92 # define soc_is_exynos5800()	is_samsung_exynos5800()
93 #else
94 # define soc_is_exynos5800()	0
95 #endif
96 
97 extern u32 cp15_save_diag;
98 extern u32 cp15_save_power;
99 
100 extern void __iomem *sysram_ns_base_addr;
101 extern void __iomem *sysram_base_addr;
102 extern phys_addr_t sysram_base_phys;
103 extern void __iomem *pmu_base_addr;
104 void exynos_sysram_init(void);
105 
106 enum {
107 	FW_DO_IDLE_SLEEP,
108 	FW_DO_IDLE_AFTR,
109 };
110 
111 void exynos_firmware_init(void);
112 
113 /* CPU BOOT mode flag for Exynos3250 SoC bootloader */
114 #define C2_STATE	(1 << 3)
115 /*
116  * Magic values for bootloader indicating chosen low power mode.
117  * See also Documentation/arch/arm/samsung/bootloader-interface.rst
118  */
119 #define EXYNOS_SLEEP_MAGIC	0x00000bad
120 #define EXYNOS_AFTR_MAGIC	0xfcba0d10
121 
122 bool __init exynos_secure_firmware_available(void);
123 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
124 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
125 
126 #ifdef CONFIG_PM_SLEEP
127 extern void __init exynos_pm_init(void);
128 #else
exynos_pm_init(void)129 static inline void exynos_pm_init(void) {}
130 #endif
131 
132 extern void exynos_cpu_resume(void);
133 extern void exynos_cpu_resume_ns(void);
134 
135 extern const struct smp_operations exynos_smp_ops;
136 
137 extern void exynos_cpu_power_down(int cpu);
138 extern void exynos_cpu_power_up(int cpu);
139 extern int  exynos_cpu_power_state(int cpu);
140 extern void exynos_cluster_power_down(int cluster);
141 extern void exynos_cluster_power_up(int cluster);
142 extern int  exynos_cluster_power_state(int cluster);
143 extern void exynos_cpu_save_register(void);
144 extern void exynos_cpu_restore_register(void);
145 extern void exynos_pm_central_suspend(void);
146 extern int exynos_pm_central_resume(void);
147 extern void exynos_enter_aftr(void);
148 #ifdef CONFIG_SMP
149 extern void exynos_scu_enable(void);
150 #else
exynos_scu_enable(void)151 static inline void exynos_scu_enable(void) { }
152 #endif
153 
154 extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
155 
156 extern void exynos_set_delayed_reset_assertion(bool enable);
157 
158 extern unsigned int exynos_rev(void);
159 extern void exynos_core_restart(u32 core_id);
160 extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
161 extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
162 
pmu_raw_writel(u32 val,u32 offset)163 static inline void pmu_raw_writel(u32 val, u32 offset)
164 {
165 	writel_relaxed(val, pmu_base_addr + offset);
166 }
167 
pmu_raw_readl(u32 offset)168 static inline u32 pmu_raw_readl(u32 offset)
169 {
170 	return readl_relaxed(pmu_base_addr + offset);
171 }
172 
173 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
174