1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 #include "dc_ddc_types.h" 31 32 enum dc_lane_count { 33 LANE_COUNT_UNKNOWN = 0, 34 LANE_COUNT_ONE = 1, 35 LANE_COUNT_TWO = 2, 36 LANE_COUNT_FOUR = 4, 37 LANE_COUNT_EIGHT = 8, 38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 39 }; 40 41 /* This is actually a reference clock (27MHz) multiplier 42 * 162MBps bandwidth for 1.62GHz like rate, 43 * 270MBps for 2.70GHz, 44 * 324MBps for 3.24Ghz, 45 * 540MBps for 5.40GHz 46 * 810MBps for 8.10GHz 47 */ 48 enum dc_link_rate { 49 LINK_RATE_UNKNOWN = 0, 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane 57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane 59 /* Starting from DP2.0 link rate enum directly represents actual 60 * link rate value in unit of 10 mbps 61 */ 62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 63 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 64 LINK_RATE_UHBR20 = 2000, // UHBR20 - 20.0 Gbps/Lane 65 }; 66 67 enum dc_link_spread { 68 LINK_SPREAD_DISABLED = 0x00, 69 /* 0.5 % downspread 30 kHz */ 70 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 71 /* 0.5 % downspread 33 kHz */ 72 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 73 }; 74 75 enum dc_voltage_swing { 76 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 77 VOLTAGE_SWING_LEVEL1, 78 VOLTAGE_SWING_LEVEL2, 79 VOLTAGE_SWING_LEVEL3, 80 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 81 }; 82 83 enum dc_pre_emphasis { 84 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 85 PRE_EMPHASIS_LEVEL1, 86 PRE_EMPHASIS_LEVEL2, 87 PRE_EMPHASIS_LEVEL3, 88 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 89 }; 90 /* Post Cursor 2 is optional for transmitter 91 * and it applies only to the main link operating at HBR2 92 */ 93 enum dc_post_cursor2 { 94 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 95 POST_CURSOR2_LEVEL1, 96 POST_CURSOR2_LEVEL2, 97 POST_CURSOR2_LEVEL3, 98 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 99 }; 100 101 enum dc_dp_ffe_preset_level { 102 DP_FFE_PRESET_LEVEL0 = 0, 103 DP_FFE_PRESET_LEVEL1, 104 DP_FFE_PRESET_LEVEL2, 105 DP_FFE_PRESET_LEVEL3, 106 DP_FFE_PRESET_LEVEL4, 107 DP_FFE_PRESET_LEVEL5, 108 DP_FFE_PRESET_LEVEL6, 109 DP_FFE_PRESET_LEVEL7, 110 DP_FFE_PRESET_LEVEL8, 111 DP_FFE_PRESET_LEVEL9, 112 DP_FFE_PRESET_LEVEL10, 113 DP_FFE_PRESET_LEVEL11, 114 DP_FFE_PRESET_LEVEL12, 115 DP_FFE_PRESET_LEVEL13, 116 DP_FFE_PRESET_LEVEL14, 117 DP_FFE_PRESET_LEVEL15, 118 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 119 }; 120 121 enum dc_dp_training_pattern { 122 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 123 DP_TRAINING_PATTERN_SEQUENCE_2, 124 DP_TRAINING_PATTERN_SEQUENCE_3, 125 DP_TRAINING_PATTERN_SEQUENCE_4, 126 DP_TRAINING_PATTERN_VIDEOIDLE, 127 DP_128b_132b_TPS1, 128 DP_128b_132b_TPS2, 129 DP_128b_132b_TPS2_CDS, 130 }; 131 132 enum dp_link_encoding { 133 DP_UNKNOWN_ENCODING = 0, 134 DP_8b_10b_ENCODING = 1, 135 DP_128b_132b_ENCODING = 2, 136 }; 137 138 enum dp_test_link_rate { 139 DP_TEST_LINK_RATE_RBR = 0x06, 140 DP_TEST_LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 141 DP_TEST_LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 142 DP_TEST_LINK_RATE_HBR = 0x0A, 143 DP_TEST_LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 144 DP_TEST_LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 145 DP_TEST_LINK_RATE_HBR2 = 0x14, 146 DP_TEST_LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 147 DP_TEST_LINK_RATE_HBR3 = 0x1E, 148 DP_TEST_LINK_RATE_UHBR10 = 0x01, 149 DP_TEST_LINK_RATE_UHBR20 = 0x02, 150 DP_TEST_LINK_RATE_UHBR13_5_LEGACY = 0x03, /* For backward compatibility*/ 151 DP_TEST_LINK_RATE_UHBR13_5 = 0x04, 152 }; 153 154 struct dc_link_settings { 155 enum dc_lane_count lane_count; 156 enum dc_link_rate link_rate; 157 enum dc_link_spread link_spread; 158 bool use_link_rate_set; 159 uint8_t link_rate_set; 160 }; 161 162 union dc_dp_ffe_preset { 163 struct { 164 uint8_t level : 4; 165 uint8_t reserved : 1; 166 uint8_t no_preshoot : 1; 167 uint8_t no_deemphasis : 1; 168 uint8_t method2 : 1; 169 } settings; 170 uint8_t raw; 171 }; 172 173 struct dc_lane_settings { 174 enum dc_voltage_swing VOLTAGE_SWING; 175 enum dc_pre_emphasis PRE_EMPHASIS; 176 enum dc_post_cursor2 POST_CURSOR2; 177 union dc_dp_ffe_preset FFE_PRESET; 178 }; 179 180 struct dc_link_training_overrides { 181 enum dc_voltage_swing *voltage_swing; 182 enum dc_pre_emphasis *pre_emphasis; 183 enum dc_post_cursor2 *post_cursor2; 184 union dc_dp_ffe_preset *ffe_preset; 185 186 uint16_t *cr_pattern_time; 187 uint16_t *eq_pattern_time; 188 enum dc_dp_training_pattern *pattern_for_cr; 189 enum dc_dp_training_pattern *pattern_for_eq; 190 191 enum dc_link_spread *downspread; 192 bool *alternate_scrambler_reset; 193 bool *enhanced_framing; 194 bool *mst_enable; 195 bool *fec_enable; 196 }; 197 198 union payload_table_update_status { 199 struct { 200 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 201 uint8_t ACT_HANDLED:1; 202 } bits; 203 uint8_t raw; 204 }; 205 206 union dpcd_rev { 207 struct { 208 uint8_t MINOR:4; 209 uint8_t MAJOR:4; 210 } bits; 211 uint8_t raw; 212 }; 213 214 union max_lane_count { 215 struct { 216 uint8_t MAX_LANE_COUNT:5; 217 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 218 uint8_t TPS3_SUPPORTED:1; 219 uint8_t ENHANCED_FRAME_CAP:1; 220 } bits; 221 uint8_t raw; 222 }; 223 224 union max_down_spread { 225 struct { 226 uint8_t MAX_DOWN_SPREAD:1; 227 uint8_t RESERVED:5; 228 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 229 uint8_t TPS4_SUPPORTED:1; 230 } bits; 231 uint8_t raw; 232 }; 233 234 union mstm_cap { 235 struct { 236 uint8_t MST_CAP:1; 237 uint8_t RESERVED:7; 238 } bits; 239 uint8_t raw; 240 }; 241 242 union lane_count_set { 243 struct { 244 uint8_t LANE_COUNT_SET:5; 245 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 246 uint8_t RESERVED:1; 247 uint8_t ENHANCED_FRAMING:1; 248 } bits; 249 uint8_t raw; 250 }; 251 252 union lane_status { 253 struct { 254 uint8_t CR_DONE_0:1; 255 uint8_t CHANNEL_EQ_DONE_0:1; 256 uint8_t SYMBOL_LOCKED_0:1; 257 uint8_t RESERVED0:1; 258 uint8_t CR_DONE_1:1; 259 uint8_t CHANNEL_EQ_DONE_1:1; 260 uint8_t SYMBOL_LOCKED_1:1; 261 uint8_t RESERVED_1:1; 262 } bits; 263 uint8_t raw; 264 }; 265 266 union device_service_irq { 267 struct { 268 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 269 uint8_t AUTOMATED_TEST:1; 270 uint8_t CP_IRQ:1; 271 uint8_t MCCS_IRQ:1; 272 uint8_t DOWN_REP_MSG_RDY:1; 273 uint8_t UP_REQ_MSG_RDY:1; 274 uint8_t SINK_SPECIFIC:1; 275 uint8_t reserved:1; 276 } bits; 277 uint8_t raw; 278 }; 279 280 union sink_count { 281 struct { 282 uint8_t SINK_COUNT:6; 283 uint8_t CPREADY:1; 284 uint8_t RESERVED:1; 285 } bits; 286 uint8_t raw; 287 }; 288 289 union lane_align_status_updated { 290 struct { 291 uint8_t INTERLANE_ALIGN_DONE:1; 292 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 293 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 294 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 295 uint8_t LT_FAILED_128b_132b:1; 296 uint8_t RESERVED:1; 297 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 298 uint8_t LINK_STATUS_UPDATED:1; 299 } bits; 300 uint8_t raw; 301 }; 302 303 union link_service_irq_vector_esi0 { 304 struct { 305 uint8_t DP_LINK_RX_CAP_CHANGED:1; 306 uint8_t DP_LINK_STATUS_CHANGED:1; 307 uint8_t DP_LINK_STREAM_STATUS_CHANGED:1; 308 uint8_t DP_LINK_HDMI_LINK_STATUS_CHANGED:1; 309 uint8_t DP_LINK_CONNECTED_OFF_ENTRY_REQUESTED:1; 310 uint8_t DP_LINK_TUNNELING_IRQ:1; 311 uint8_t reserved:2; 312 } bits; 313 uint8_t raw; 314 }; 315 316 union lane_adjust { 317 struct { 318 uint8_t VOLTAGE_SWING_LANE:2; 319 uint8_t PRE_EMPHASIS_LANE:2; 320 uint8_t RESERVED:4; 321 } bits; 322 struct { 323 uint8_t PRESET_VALUE :4; 324 uint8_t RESERVED :4; 325 } tx_ffe; 326 uint8_t raw; 327 }; 328 329 union dpcd_training_pattern { 330 struct { 331 uint8_t TRAINING_PATTERN_SET:4; 332 uint8_t RECOVERED_CLOCK_OUT_EN:1; 333 uint8_t SCRAMBLING_DISABLE:1; 334 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 335 } v1_4; 336 struct { 337 uint8_t TRAINING_PATTERN_SET:2; 338 uint8_t LINK_QUAL_PATTERN_SET:2; 339 uint8_t RESERVED:4; 340 } v1_3; 341 uint8_t raw; 342 }; 343 344 /* Training Lane is used to configure downstream DP device's voltage swing 345 and pre-emphasis levels*/ 346 /* The DPCD addresses are from 0x103 to 0x106*/ 347 union dpcd_training_lane { 348 struct { 349 uint8_t VOLTAGE_SWING_SET:2; 350 uint8_t MAX_SWING_REACHED:1; 351 uint8_t PRE_EMPHASIS_SET:2; 352 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 353 uint8_t RESERVED:2; 354 } bits; 355 struct { 356 uint8_t PRESET_VALUE :4; 357 uint8_t RESERVED :4; 358 } tx_ffe; 359 uint8_t raw; 360 }; 361 362 /* TMDS-converter related */ 363 union dwnstream_port_caps_byte0 { 364 struct { 365 uint8_t DWN_STRM_PORTX_TYPE:3; 366 uint8_t DWN_STRM_PORTX_HPD:1; 367 uint8_t RESERVERD:4; 368 } bits; 369 uint8_t raw; 370 }; 371 372 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 373 enum dpcd_downstream_port_detailed_type { 374 DOWN_STREAM_DETAILED_DP = 0, 375 DOWN_STREAM_DETAILED_VGA, 376 DOWN_STREAM_DETAILED_DVI, 377 DOWN_STREAM_DETAILED_HDMI, 378 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 379 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 380 }; 381 382 union dwnstream_port_caps_byte2 { 383 struct { 384 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 385 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 386 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 387 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 388 uint8_t RESERVED:1; 389 } bits; 390 uint8_t raw; 391 }; 392 393 union dp_downstream_port_present { 394 uint8_t byte; 395 struct { 396 uint8_t PORT_PRESENT:1; 397 uint8_t PORT_TYPE:2; 398 uint8_t FMT_CONVERSION:1; 399 uint8_t DETAILED_CAPS:1; 400 uint8_t RESERVED:3; 401 } fields; 402 }; 403 404 union dwnstream_port_caps_byte3_dvi { 405 struct { 406 uint8_t RESERVED1:1; 407 uint8_t DUAL_LINK:1; 408 uint8_t HIGH_COLOR_DEPTH:1; 409 uint8_t RESERVED2:5; 410 } bits; 411 uint8_t raw; 412 }; 413 414 union dwnstream_port_caps_byte3_hdmi { 415 struct { 416 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 417 uint8_t YCrCr422_PASS_THROUGH:1; 418 uint8_t YCrCr420_PASS_THROUGH:1; 419 uint8_t YCrCr422_CONVERSION:1; 420 uint8_t YCrCr420_CONVERSION:1; 421 uint8_t RESERVED:3; 422 } bits; 423 uint8_t raw; 424 }; 425 426 union hdmi_encoded_link_bw { 427 struct { 428 uint8_t FRL_MODE:1; // Bit 0 429 uint8_t BW_9Gbps:1; 430 uint8_t BW_18Gbps:1; 431 uint8_t BW_24Gbps:1; 432 uint8_t BW_32Gbps:1; 433 uint8_t BW_40Gbps:1; 434 uint8_t BW_48Gbps:1; 435 uint8_t FRL_LINK_TRAINING_FINISHED:1; // Bit 7 436 } bits; 437 uint8_t raw; 438 }; 439 440 union hdmi_tx_link_status { 441 struct { 442 uint8_t HDMI_TX_LINK_ACTIVE_STATUS:1; 443 uint8_t HDMI_TX_READY_STATUS:1; 444 uint8_t RESERVED:6; 445 } bits; 446 uint8_t raw; 447 }; 448 449 union autonomous_mode_and_frl_link_status { 450 struct { 451 uint8_t FRL_LT_IN_PROGRESS_STATUS:1; 452 uint8_t FRL_LT_LINK_CONFIG_IN_PROGRESS:3; 453 uint8_t RESERVED:1; 454 uint8_t FALLBACK_POLICY:1; 455 uint8_t FALLBACK_POLICY_VALID:1; 456 uint8_t REGULATED_AUTONOMOUS_MODE_SUPPORTED:1; 457 } bits; 458 uint8_t raw; 459 }; 460 461 /*4-byte structure for detailed capabilities of a down-stream port 462 (DP-to-TMDS converter).*/ 463 union dwnstream_portxcaps { 464 struct { 465 union dwnstream_port_caps_byte0 byte0; 466 unsigned char max_TMDS_clock; //byte1 467 union dwnstream_port_caps_byte2 byte2; 468 469 union { 470 union dwnstream_port_caps_byte3_dvi byteDVI; 471 union dwnstream_port_caps_byte3_hdmi byteHDMI; 472 } byte3; 473 } bytes; 474 475 unsigned char raw[4]; 476 }; 477 478 union downstream_port { 479 struct { 480 unsigned char present:1; 481 unsigned char type:2; 482 unsigned char format_conv:1; 483 unsigned char detailed_caps:1; 484 unsigned char reserved:3; 485 } bits; 486 unsigned char raw; 487 }; 488 489 490 union sink_status { 491 struct { 492 uint8_t RX_PORT0_STATUS:1; 493 uint8_t RX_PORT1_STATUS:1; 494 uint8_t RESERVED:6; 495 } bits; 496 uint8_t raw; 497 }; 498 499 /* 7-byte structure corresponding to 6 registers (200h-205h) 500 * and LINK_SERVICE_IRQ_ESI0 (2005h) for tunneling IRQ 501 * read during handling of HPD-IRQ 502 */ 503 union hpd_irq_data { 504 struct { 505 union sink_count sink_cnt;/* 200h */ 506 union device_service_irq device_service_irq;/* 201h */ 507 union lane_status lane01_status;/* 202h */ 508 union lane_status lane23_status;/* 203h */ 509 union lane_align_status_updated lane_status_updated;/* 204h */ 510 union sink_status sink_status;/* 205h */ 511 union link_service_irq_vector_esi0 link_service_irq_esi0;/* 2005h */ 512 } bytes; 513 uint8_t raw[7]; 514 }; 515 516 union down_stream_port_count { 517 struct { 518 uint8_t DOWN_STR_PORT_COUNT:4; 519 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 520 /*Bit 6 = MSA_TIMING_PAR_IGNORED 521 0 = Sink device requires the MSA timing parameters 522 1 = Sink device is capable of rendering incoming video 523 stream without MSA timing parameters*/ 524 uint8_t IGNORE_MSA_TIMING_PARAM:1; 525 /*Bit 7 = OUI Support 526 0 = OUI not supported 527 1 = OUI supported 528 (OUI and Device Identification mandatory for DP 1.2)*/ 529 uint8_t OUI_SUPPORT:1; 530 } bits; 531 uint8_t raw; 532 }; 533 534 union down_spread_ctrl { 535 struct { 536 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 537 /* Bits 4 = SPREAD_AMP. Spreading amplitude 538 0 = Main link signal is not downspread 539 1 = Main link signal is downspread <= 0.5% 540 with frequency in the range of 30kHz ~ 33kHz*/ 541 uint8_t SPREAD_AMP:1; 542 uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/ 543 /* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE. 544 0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default) 545 1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */ 546 uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1; 547 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 548 0 = Source device will send valid data for the MSA Timing Params 549 1 = Source device may send invalid data for these MSA Timing Params*/ 550 uint8_t IGNORE_MSA_TIMING_PARAM:1; 551 } bits; 552 uint8_t raw; 553 }; 554 555 union dpcd_edp_config { 556 struct { 557 uint8_t PANEL_MODE_EDP:1; 558 uint8_t FRAMING_CHANGE_ENABLE:1; 559 uint8_t RESERVED:5; 560 uint8_t PANEL_SELF_TEST_ENABLE:1; 561 } bits; 562 uint8_t raw; 563 }; 564 565 struct dp_device_vendor_id { 566 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 567 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 568 }; 569 570 struct dp_sink_hw_fw_revision { 571 uint8_t ieee_hw_rev; 572 uint8_t ieee_fw_rev[2]; 573 }; 574 575 struct dpcd_vendor_signature { 576 bool is_valid; 577 578 union dpcd_ieee_vendor_signature { 579 struct { 580 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 581 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 582 uint8_t ieee_hw_rev; 583 uint8_t ieee_fw_rev[2]; 584 }; 585 uint8_t raw[12]; 586 } data; 587 }; 588 589 struct dpcd_amd_signature { 590 uint8_t AMD_IEEE_TxSignature_byte1; 591 uint8_t AMD_IEEE_TxSignature_byte2; 592 uint8_t AMD_IEEE_TxSignature_byte3; 593 }; 594 595 struct dpcd_amd_device_id { 596 uint8_t device_id_byte1; 597 uint8_t device_id_byte2; 598 uint8_t zero[4]; 599 uint8_t dce_version; 600 uint8_t dal_version_byte1; 601 uint8_t dal_version_byte2; 602 }; 603 604 struct target_luminance_value { 605 uint8_t byte0; 606 uint8_t byte1; 607 uint8_t byte2; 608 }; 609 610 struct dpcd_source_backlight_set { 611 struct { 612 uint8_t byte0; 613 uint8_t byte1; 614 uint8_t byte2; 615 uint8_t byte3; 616 } backlight_level_millinits; 617 618 struct { 619 uint8_t byte0; 620 uint8_t byte1; 621 } backlight_transition_time_ms; 622 }; 623 624 union dpcd_source_backlight_get { 625 struct { 626 uint32_t backlight_millinits_peak; /* 326h */ 627 uint32_t backlight_millinits_avg; /* 32Ah */ 628 } bytes; 629 uint8_t raw[8]; 630 }; 631 632 /*DPCD register of DP receiver capability field bits-*/ 633 union edp_configuration_cap { 634 struct { 635 uint8_t ALT_SCRAMBLER_RESET:1; 636 uint8_t FRAMING_CHANGE:1; 637 uint8_t RESERVED:1; 638 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 639 uint8_t RESERVED2:4; 640 } bits; 641 uint8_t raw; 642 }; 643 644 union dprx_feature { 645 struct { 646 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 647 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 648 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 649 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 650 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 651 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 652 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 653 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 654 } bits; 655 uint8_t raw; 656 }; 657 658 union training_aux_rd_interval { 659 struct { 660 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 661 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 662 } bits; 663 uint8_t raw; 664 }; 665 666 /* Automated test structures */ 667 union test_request { 668 struct { 669 uint8_t LINK_TRAINING :1; 670 uint8_t LINK_TEST_PATTRN :1; 671 uint8_t EDID_READ :1; 672 uint8_t PHY_TEST_PATTERN :1; 673 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2; 674 uint8_t AUDIO_TEST_PATTERN :1; 675 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 676 } bits; 677 uint8_t raw; 678 }; 679 680 union test_response { 681 struct { 682 uint8_t ACK :1; 683 uint8_t NO_ACK :1; 684 uint8_t EDID_CHECKSUM_WRITE:1; 685 uint8_t RESERVED :5; 686 } bits; 687 uint8_t raw; 688 }; 689 690 union phy_test_pattern { 691 struct { 692 /* This field is 7 bits for DP2.0 */ 693 uint8_t PATTERN :7; 694 uint8_t RESERVED :1; 695 } bits; 696 uint8_t raw; 697 }; 698 699 /* States of Compliance Test Specification (CTS DP1.2). */ 700 union compliance_test_state { 701 struct { 702 unsigned char STEREO_3D_RUNNING : 1; 703 unsigned char RESERVED : 7; 704 } bits; 705 unsigned char raw; 706 }; 707 708 union link_test_pattern { 709 struct { 710 /* dpcd_link_test_patterns */ 711 unsigned char PATTERN :2; 712 unsigned char RESERVED:6; 713 } bits; 714 unsigned char raw; 715 }; 716 717 union test_misc { 718 struct dpcd_test_misc_bits { 719 unsigned char SYNC_CLOCK :1; 720 /* dpcd_test_color_format */ 721 unsigned char CLR_FORMAT :2; 722 /* dpcd_test_dyn_range */ 723 unsigned char DYN_RANGE :1; 724 unsigned char YCBCR_COEFS :1; 725 /* dpcd_test_bit_depth */ 726 unsigned char BPC :3; 727 } bits; 728 unsigned char raw; 729 }; 730 731 union audio_test_mode { 732 struct { 733 unsigned char sampling_rate :4; 734 unsigned char channel_count :4; 735 } bits; 736 unsigned char raw; 737 }; 738 739 union audio_test_pattern_period { 740 struct { 741 unsigned char pattern_period :4; 742 unsigned char reserved :4; 743 } bits; 744 unsigned char raw; 745 }; 746 747 struct audio_test_pattern_type { 748 unsigned char value; 749 }; 750 751 struct dp_audio_test_data_flags { 752 uint8_t test_requested :1; 753 uint8_t disable_video :1; 754 }; 755 756 struct dp_audio_test_data { 757 758 struct dp_audio_test_data_flags flags; 759 uint8_t sampling_rate; 760 uint8_t channel_count; 761 uint8_t pattern_type; 762 uint8_t pattern_period[8]; 763 }; 764 765 /* FEC capability DPCD register field bits-*/ 766 union dpcd_fec_capability { 767 struct { 768 uint8_t FEC_CAPABLE:1; 769 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 770 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 771 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 772 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 773 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 774 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 775 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 776 } bits; 777 uint8_t raw; 778 }; 779 780 /* DSC capability DPCD register field bits-*/ 781 struct dpcd_dsc_support { 782 uint8_t DSC_SUPPORT :1; 783 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 784 uint8_t RESERVED :6; 785 }; 786 787 struct dpcd_dsc_algorithm_revision { 788 uint8_t DSC_VERSION_MAJOR :4; 789 uint8_t DSC_VERSION_MINOR :4; 790 }; 791 792 struct dpcd_dsc_rc_buffer_block_size { 793 uint8_t RC_BLOCK_BUFFER_SIZE :2; 794 uint8_t RESERVED :6; 795 }; 796 797 struct dpcd_dsc_slice_capability1 { 798 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 799 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 800 uint8_t RESERVED :1; 801 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 802 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 803 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 804 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 805 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 806 }; 807 808 struct dpcd_dsc_line_buffer_bit_depth { 809 uint8_t LINE_BUFFER_BIT_DEPTH :4; 810 uint8_t RESERVED :4; 811 }; 812 813 struct dpcd_dsc_block_prediction_support { 814 uint8_t BLOCK_PREDICTION_SUPPORT:1; 815 uint8_t RESERVED :7; 816 }; 817 818 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 819 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 820 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 821 uint8_t RESERVED :2; 822 }; 823 824 struct dpcd_dsc_decoder_color_format_capabilities { 825 uint8_t RGB_SUPPORT :1; 826 uint8_t Y_CB_CR_444_SUPPORT :1; 827 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 828 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 829 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 830 uint8_t RESERVED :3; 831 }; 832 833 struct dpcd_dsc_decoder_color_depth_capabilities { 834 uint8_t RESERVED0 :1; 835 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 836 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 837 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 838 uint8_t RESERVED1 :4; 839 }; 840 841 struct dpcd_peak_dsc_throughput_dsc_sink { 842 uint8_t THROUGHPUT_MODE_0:4; 843 uint8_t THROUGHPUT_MODE_1:4; 844 }; 845 846 struct dpcd_dsc_slice_capabilities_2 { 847 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 848 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 849 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 850 uint8_t RESERVED :5; 851 }; 852 853 struct dpcd_bits_per_pixel_increment{ 854 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 855 uint8_t RESERVED :5; 856 }; 857 union dpcd_dsc_basic_capabilities { 858 struct { 859 struct dpcd_dsc_support dsc_support; 860 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 861 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 862 uint8_t dsc_rc_buffer_size; 863 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 864 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 865 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 866 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 867 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 868 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 869 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 870 uint8_t dsc_maximum_slice_width; 871 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 872 uint8_t reserved; 873 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 874 } fields; 875 uint8_t raw[16]; 876 }; 877 878 union dpcd_dsc_branch_decoder_capabilities { 879 struct { 880 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 881 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 882 uint8_t BRANCH_MAX_LINE_WIDTH; 883 } fields; 884 uint8_t raw[3]; 885 }; 886 887 struct dpcd_dsc_capabilities { 888 union dpcd_dsc_basic_capabilities dsc_basic_caps; 889 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 890 }; 891 892 /* These parameters are from PSR capabilities reported by Sink DPCD */ 893 struct psr_caps { 894 unsigned char psr_version; 895 unsigned int psr_rfb_setup_time; 896 bool psr_exit_link_training_required; 897 unsigned char edp_revision; 898 unsigned char support_ver; 899 bool su_granularity_required; 900 bool y_coordinate_required; 901 uint8_t su_y_granularity; 902 bool alpm_cap; 903 bool standby_support; 904 uint8_t rate_control_caps; 905 unsigned int psr_power_opt_flag; 906 }; 907 908 union dpcd_dprx_feature_enumeration_list_cont_1 { 909 struct { 910 uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1; 911 uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1; 912 uint8_t RESERVED0: 2; 913 uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1; 914 uint8_t RESERVED1: 3; 915 } bits; 916 uint8_t raw; 917 }; 918 919 struct adaptive_sync_caps { 920 union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps; 921 }; 922 923 /* Length of router topology ID read from DPCD in bytes. */ 924 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 925 926 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 927 union dp_tun_cap_support { 928 struct { 929 uint8_t dp_tunneling :1; 930 uint8_t rsvd :5; 931 uint8_t panel_replay_tun_opt :1; 932 uint8_t dpia_bw_alloc :1; 933 } bits; 934 uint8_t raw; 935 }; 936 937 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 938 union dpia_info { 939 struct { 940 uint8_t dpia_num :5; 941 uint8_t rsvd :3; 942 } bits; 943 uint8_t raw; 944 }; 945 946 /* DP Tunneling over USB4 */ 947 struct dpcd_usb4_dp_tunneling_info { 948 union dp_tun_cap_support dp_tun_cap; 949 union dpia_info dpia_info; 950 uint8_t usb4_driver_id; 951 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 952 }; 953 954 union dp_main_line_channel_coding_cap { 955 struct { 956 uint8_t DP_8b_10b_SUPPORTED :1; 957 uint8_t DP_128b_132b_SUPPORTED :1; 958 uint8_t RESERVED :6; 959 } bits; 960 uint8_t raw; 961 }; 962 963 union dp_main_link_channel_coding_lttpr_cap { 964 struct { 965 uint8_t DP_128b_132b_SUPPORTED :1; 966 uint8_t RESERVED :7; 967 } bits; 968 uint8_t raw; 969 }; 970 971 union dp_128b_132b_supported_link_rates { 972 struct { 973 uint8_t UHBR10 :1; 974 uint8_t UHBR20 :1; 975 uint8_t UHBR13_5:1; 976 uint8_t RESERVED:5; 977 } bits; 978 uint8_t raw; 979 }; 980 981 union dp_128b_132b_supported_lttpr_link_rates { 982 struct { 983 uint8_t UHBR10 :1; 984 uint8_t UHBR20 :1; 985 uint8_t UHBR13_5:1; 986 uint8_t RESERVED:5; 987 } bits; 988 uint8_t raw; 989 }; 990 991 union dp_alpm_lttpr_cap { 992 struct { 993 uint8_t AUX_LESS_ALPM_SUPPORTED :1; 994 uint8_t RESERVED :7; 995 } bits; 996 uint8_t raw; 997 }; 998 999 union dp_sink_video_fallback_formats { 1000 struct { 1001 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1002 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1003 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1004 uint8_t RESERVED :5; 1005 } bits; 1006 uint8_t raw; 1007 }; 1008 1009 union dp_receive_port0_cap { 1010 struct { 1011 uint8_t RESERVED :1; 1012 uint8_t LOCAL_EDID_PRESENT :1; 1013 uint8_t ASSOCIATED_TO_PRECEDING_PORT:1; 1014 uint8_t HBLANK_EXPANSION_CAPABLE :1; 1015 uint8_t BUFFER_SIZE_UNIT :1; 1016 uint8_t BUFFER_SIZE_PER_PORT :1; 1017 uint8_t HBLANK_REDUCTION_CAPABLE :1; 1018 uint8_t RESERVED2:1; 1019 uint8_t BUFFER_SIZE:8; 1020 } bits; 1021 uint8_t raw[2]; 1022 }; 1023 1024 union dpcd_max_uncompressed_pixel_rate_cap { 1025 struct { 1026 uint16_t max_uncompressed_pixel_rate_cap :15; 1027 uint16_t valid :1; 1028 } bits; 1029 uint8_t raw[2]; 1030 }; 1031 1032 union dp_fec_capability1 { 1033 struct { 1034 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1035 uint8_t RESERVED :7; 1036 } bits; 1037 uint8_t raw; 1038 }; 1039 1040 union dp_cable_id { 1041 struct { 1042 uint8_t UHBR10_20_CAPABILITY :2; 1043 uint8_t UHBR13_5_CAPABILITY :1; 1044 uint8_t CABLE_TYPE :3; 1045 uint8_t RESERVED :2; 1046 } bits; 1047 uint8_t raw; 1048 }; 1049 1050 struct dp_color_depth_caps { 1051 uint8_t support_6bpc :1; 1052 uint8_t support_8bpc :1; 1053 uint8_t support_10bpc :1; 1054 uint8_t support_12bpc :1; 1055 uint8_t support_16bpc :1; 1056 uint8_t RESERVED :3; 1057 }; 1058 1059 struct dp_encoding_format_caps { 1060 uint8_t support_rgb :1; 1061 uint8_t support_ycbcr444:1; 1062 uint8_t support_ycbcr422:1; 1063 uint8_t support_ycbcr420:1; 1064 uint8_t RESERVED :4; 1065 }; 1066 1067 union dp_dfp_cap_ext { 1068 struct { 1069 uint8_t supported; 1070 uint8_t max_pixel_rate_in_mps[2]; 1071 uint8_t max_video_h_active_width[2]; 1072 uint8_t max_video_v_active_height[2]; 1073 struct dp_encoding_format_caps encoding_format_caps; 1074 struct dp_color_depth_caps rgb_color_depth_caps; 1075 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1076 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1077 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1078 } fields; 1079 uint8_t raw[12]; 1080 }; 1081 1082 union dp_128b_132b_training_aux_rd_interval { 1083 struct { 1084 uint8_t VALUE :7; 1085 uint8_t UNIT :1; 1086 } bits; 1087 uint8_t raw; 1088 }; 1089 1090 union edp_alpm_caps { 1091 struct { 1092 uint8_t AUX_WAKE_ALPM_CAP :1; 1093 uint8_t PM_STATE_2A_SUPPORT :1; 1094 uint8_t AUX_LESS_ALPM_CAP :1; 1095 uint8_t RESERVED :5; 1096 } bits; 1097 uint8_t raw; 1098 }; 1099 1100 union edp_psr_dpcd_caps { 1101 struct { 1102 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1103 uint8_t PSR_SETUP_TIME :3; 1104 uint8_t Y_COORDINATE_REQUIRED :1; 1105 uint8_t SU_GRANULARITY_REQUIRED :1; 1106 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1107 uint8_t RESERVED :1; 1108 } bits; 1109 uint8_t raw; 1110 }; 1111 1112 struct edp_psr_info { 1113 uint8_t psr_version; 1114 union edp_psr_dpcd_caps psr_dpcd_caps; 1115 uint8_t psr2_su_y_granularity_cap; 1116 uint8_t force_psrsu_cap; 1117 }; 1118 1119 struct replay_info { 1120 uint8_t pixel_deviation_per_line; 1121 uint8_t max_deviation_line; 1122 }; 1123 1124 struct dprx_states { 1125 bool cable_id_written; 1126 }; 1127 1128 enum dpcd_downstream_port_max_bpc { 1129 DOWN_STREAM_MAX_8BPC = 0, 1130 DOWN_STREAM_MAX_10BPC, 1131 DOWN_STREAM_MAX_12BPC, 1132 DOWN_STREAM_MAX_16BPC 1133 }; 1134 1135 enum link_training_offset { 1136 DPRX = 0, 1137 LTTPR_PHY_REPEATER1 = 1, 1138 LTTPR_PHY_REPEATER2 = 2, 1139 LTTPR_PHY_REPEATER3 = 3, 1140 LTTPR_PHY_REPEATER4 = 4, 1141 LTTPR_PHY_REPEATER5 = 5, 1142 LTTPR_PHY_REPEATER6 = 6, 1143 LTTPR_PHY_REPEATER7 = 7, 1144 LTTPR_PHY_REPEATER8 = 8 1145 }; 1146 1147 #define MAX_REPEATER_CNT 8 1148 1149 struct dc_lttpr_caps { 1150 union dpcd_rev revision; 1151 uint8_t mode; 1152 uint8_t max_lane_count; 1153 uint8_t max_link_rate; 1154 uint8_t phy_repeater_cnt; 1155 uint8_t max_ext_timeout; 1156 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 1157 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 1158 union dp_alpm_lttpr_cap alpm; 1159 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 1160 uint8_t lttpr_ieee_oui[3]; 1161 uint8_t lttpr_device_id[6]; 1162 }; 1163 1164 struct dc_dongle_dfp_cap_ext { 1165 bool supported; 1166 uint16_t max_pixel_rate_in_mps; 1167 uint16_t max_video_h_active_width; 1168 uint16_t max_video_v_active_height; 1169 struct dp_encoding_format_caps encoding_format_caps; 1170 struct dp_color_depth_caps rgb_color_depth_caps; 1171 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1172 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1173 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1174 }; 1175 1176 struct dc_dongle_caps { 1177 /* dongle type (DP converter, CV smart dongle) */ 1178 enum display_dongle_type dongle_type; 1179 bool extendedCapValid; 1180 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1181 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1182 bool is_dp_hdmi_s3d_converter; 1183 bool is_dp_hdmi_ycbcr422_pass_through; 1184 bool is_dp_hdmi_ycbcr420_pass_through; 1185 bool is_dp_hdmi_ycbcr422_converter; 1186 bool is_dp_hdmi_ycbcr420_converter; 1187 uint32_t dp_hdmi_max_bpc; 1188 uint32_t dp_hdmi_max_pixel_clk_in_khz; 1189 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 1190 uint32_t dp_hdmi_regulated_autonomous_mode_support; 1191 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 1192 }; 1193 1194 struct dpcd_caps { 1195 union dpcd_rev dpcd_rev; 1196 union max_lane_count max_ln_count; 1197 union max_down_spread max_down_spread; 1198 union dprx_feature dprx_feature; 1199 1200 /* valid only for eDP v1.4 or higher*/ 1201 uint8_t edp_supported_link_rates_count; 1202 enum dc_link_rate edp_supported_link_rates[8]; 1203 1204 /* dongle type (DP converter, CV smart dongle) */ 1205 enum display_dongle_type dongle_type; 1206 bool is_dongle_type_one; 1207 /* branch device or sink device */ 1208 bool is_branch_dev; 1209 /* Dongle's downstream count. */ 1210 union sink_count sink_count; 1211 bool is_mst_capable; 1212 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1213 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1214 struct dc_dongle_caps dongle_caps; 1215 1216 uint32_t sink_dev_id; 1217 int8_t sink_dev_id_str[6]; 1218 int8_t sink_hw_revision; 1219 int8_t sink_fw_revision[2]; 1220 1221 uint32_t branch_dev_id; 1222 int8_t branch_dev_name[6]; 1223 int8_t branch_hw_revision; 1224 int8_t branch_fw_revision[2]; 1225 int8_t branch_vendor_specific_data[4]; 1226 1227 bool allow_invalid_MSA_timing_param; 1228 bool panel_mode_edp; 1229 bool dpcd_display_control_capable; 1230 bool ext_receiver_cap_field_present; 1231 bool set_power_state_capable_edp; 1232 bool dynamic_backlight_capable_edp; 1233 union dpcd_fec_capability fec_cap; 1234 struct dpcd_dsc_capabilities dsc_caps; 1235 struct dc_lttpr_caps lttpr_caps; 1236 struct adaptive_sync_caps adaptive_sync_caps; 1237 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1238 union dpcd_max_uncompressed_pixel_rate_cap max_uncompressed_pixel_rate_cap; 1239 1240 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1241 union dp_main_line_channel_coding_cap channel_coding_cap; 1242 union dp_sink_video_fallback_formats fallback_formats; 1243 union dp_fec_capability1 fec_cap1; 1244 bool panel_luminance_control; 1245 union dp_cable_id cable_id; 1246 uint8_t edp_rev; 1247 union edp_alpm_caps alpm_caps; 1248 struct edp_psr_info psr_info; 1249 1250 struct replay_info pr_info; 1251 uint16_t edp_oled_emission_rate; 1252 union dp_receive_port0_cap receive_port0_cap; 1253 /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ 1254 uint8_t mso_cap_sst_links_supported; 1255 }; 1256 1257 union dpcd_sink_ext_caps { 1258 struct { 1259 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1260 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1261 */ 1262 uint8_t sdr_aux_backlight_control : 1; 1263 uint8_t hdr_aux_backlight_control : 1; 1264 uint8_t reserved_1 : 2; 1265 uint8_t oled : 1; 1266 uint8_t reserved_2 : 1; 1267 uint8_t miniled : 1; 1268 uint8_t emission_output : 1; 1269 } bits; 1270 uint8_t raw; 1271 }; 1272 1273 enum dc_link_fec_state { 1274 dc_link_fec_not_ready, 1275 dc_link_fec_ready, 1276 dc_link_fec_enabled 1277 }; 1278 1279 union dpcd_psr_configuration { 1280 struct { 1281 unsigned char ENABLE : 1; 1282 unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1; 1283 unsigned char CRC_VERIFICATION : 1; 1284 unsigned char FRAME_CAPTURE_INDICATION : 1; 1285 /* For eDP 1.4, PSR v2*/ 1286 unsigned char LINE_CAPTURE_INDICATION : 1; 1287 /* For eDP 1.4, PSR v2*/ 1288 unsigned char IRQ_HPD_WITH_CRC_ERROR : 1; 1289 unsigned char ENABLE_PSR2 : 1; 1290 unsigned char EARLY_TRANSPORT_ENABLE : 1; 1291 } bits; 1292 unsigned char raw; 1293 }; 1294 1295 union replay_enable_and_configuration { 1296 struct { 1297 unsigned char FREESYNC_PANEL_REPLAY_MODE :1; 1298 unsigned char TIMING_DESYNC_ERROR_VERIFICATION :1; 1299 unsigned char STATE_TRANSITION_ERROR_DETECTION :1; 1300 unsigned char RESERVED :5; 1301 } bits; 1302 unsigned char raw; 1303 }; 1304 1305 union dpcd_replay_configuration { 1306 struct { 1307 unsigned char STATE_TRANSITION_ERROR_STATUS : 1; 1308 unsigned char DESYNC_ERROR_STATUS : 1; 1309 unsigned char SINK_DEVICE_REPLAY_STATUS : 3; 1310 unsigned char SINK_FRAME_LOCKED : 2; 1311 unsigned char RESERVED : 1; 1312 } bits; 1313 unsigned char raw; 1314 }; 1315 1316 union dpcd_alpm_configuration { 1317 struct { 1318 unsigned char ENABLE : 1; 1319 unsigned char IRQ_HPD_ENABLE : 1; 1320 unsigned char RESERVED : 6; 1321 } bits; 1322 unsigned char raw; 1323 }; 1324 1325 union dpcd_sink_active_vtotal_control_mode { 1326 struct { 1327 unsigned char ENABLE : 1; 1328 unsigned char RESERVED : 7; 1329 } bits; 1330 unsigned char raw; 1331 }; 1332 1333 union psr_error_status { 1334 struct { 1335 unsigned char LINK_CRC_ERROR :1; 1336 unsigned char RFB_STORAGE_ERROR :1; 1337 unsigned char VSC_SDP_ERROR :1; 1338 unsigned char RESERVED :5; 1339 } bits; 1340 unsigned char raw; 1341 }; 1342 1343 union psr_sink_psr_status { 1344 struct { 1345 unsigned char SINK_SELF_REFRESH_STATUS :3; 1346 unsigned char RESERVED :5; 1347 } bits; 1348 unsigned char raw; 1349 }; 1350 1351 struct edp_trace_power_timestamps { 1352 uint64_t poweroff; 1353 uint64_t poweron; 1354 }; 1355 1356 struct dp_trace_lt_counts { 1357 unsigned int total; 1358 unsigned int fail; 1359 }; 1360 1361 enum link_training_result { 1362 LINK_TRAINING_SUCCESS, 1363 LINK_TRAINING_CR_FAIL_LANE0, 1364 LINK_TRAINING_CR_FAIL_LANE1, 1365 LINK_TRAINING_CR_FAIL_LANE23, 1366 /* CR DONE bit is cleared during EQ step */ 1367 LINK_TRAINING_EQ_FAIL_CR, 1368 /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ 1369 LINK_TRAINING_EQ_FAIL_CR_PARTIAL, 1370 /* other failure during EQ step */ 1371 LINK_TRAINING_EQ_FAIL_EQ, 1372 LINK_TRAINING_LQA_FAIL, 1373 /* one of the CR,EQ or symbol lock is dropped */ 1374 LINK_TRAINING_LINK_LOSS, 1375 /* Abort link training (because sink unplugged) */ 1376 LINK_TRAINING_ABORT, 1377 DP_128b_132b_LT_FAILED, 1378 DP_128b_132b_MAX_LOOP_COUNT_REACHED, 1379 DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, 1380 DP_128b_132b_CDS_DONE_TIMEOUT, 1381 }; 1382 1383 struct dp_trace_lt { 1384 struct dp_trace_lt_counts counts; 1385 struct dp_trace_timestamps { 1386 unsigned long long start; 1387 unsigned long long end; 1388 } timestamps; 1389 enum link_training_result result; 1390 bool is_logged; 1391 }; 1392 1393 struct dp_trace { 1394 struct dp_trace_lt detect_lt_trace; 1395 struct dp_trace_lt commit_lt_trace; 1396 unsigned int link_loss_count; 1397 bool is_initialized; 1398 struct edp_trace_power_timestamps edp_trace_power_timestamps; 1399 }; 1400 1401 /* TODO - This is a temporary location for any new DPCD definitions. 1402 * We should move these to drm_dp header. 1403 */ 1404 #ifndef DP_LINK_SQUARE_PATTERN 1405 #define DP_LINK_SQUARE_PATTERN 0x10F 1406 #endif 1407 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 1408 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 1409 #endif 1410 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 1411 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 1412 #endif 1413 #ifndef DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 1414 #define DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 0x221c 1415 #endif 1416 #ifndef DP_LTTPR_ALPM_CAPABILITIES 1417 #define DP_LTTPR_ALPM_CAPABILITIES 0xF0009 1418 #endif 1419 #ifndef DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 1420 #define DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 0x303C 1421 #endif 1422 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 1423 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 1424 #endif 1425 #ifndef DP_TUNNELING_IRQ 1426 #define DP_TUNNELING_IRQ (1 << 5) 1427 #endif 1428 #ifndef DP_BRANCH_VENDOR_SPECIFIC_START 1429 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C 1430 #endif 1431 #ifndef DP_LTTPR_IEEE_OUI 1432 #define DP_LTTPR_IEEE_OUI 0xF003D 1433 #endif 1434 #ifndef DP_LTTPR_DEVICE_ID 1435 #define DP_LTTPR_DEVICE_ID 0xF0040 1436 #endif 1437 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/ 1438 #ifndef DP_TUNNELING_CAPABILITIES 1439 #define DP_TUNNELING_CAPABILITIES 0xE000D /* 1.4a */ 1440 #endif 1441 #ifndef USB4_DRIVER_ID 1442 #define USB4_DRIVER_ID 0xE000F /* 1.4a */ 1443 #endif 1444 #ifndef USB4_DRIVER_BW_CAPABILITY 1445 #define USB4_DRIVER_BW_CAPABILITY 0xE0020 /* 1.4a */ 1446 #endif 1447 #ifndef DP_IN_ADAPTER_TUNNEL_INFO 1448 #define DP_IN_ADAPTER_TUNNEL_INFO 0xE0021 /* 1.4a */ 1449 #endif 1450 #ifndef DP_BW_GRANULALITY 1451 #define DP_BW_GRANULALITY 0xE0022 /* 1.4a */ 1452 #endif 1453 #ifndef ESTIMATED_BW 1454 #define ESTIMATED_BW 0xE0023 /* 1.4a */ 1455 #endif 1456 #ifndef ALLOCATED_BW 1457 #define ALLOCATED_BW 0xE0024 /* 1.4a */ 1458 #endif 1459 #ifndef DP_TUNNELING_STATUS 1460 #define DP_TUNNELING_STATUS 0xE0025 /* 1.4a */ 1461 #endif 1462 #ifndef DP_TUNNELING_MAX_LINK_RATE 1463 #define DP_TUNNELING_MAX_LINK_RATE 0xE0028 /* 1.4a */ 1464 #endif 1465 #ifndef DP_TUNNELING_MAX_LANE_COUNT 1466 #define DP_TUNNELING_MAX_LANE_COUNT 0xE0029 /* 1.4a */ 1467 #endif 1468 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL 1469 #define DPTX_BW_ALLOCATION_MODE_CONTROL 0xE0030 /* 1.4a */ 1470 #endif 1471 #ifndef REQUESTED_BW 1472 #define REQUESTED_BW 0xE0031 /* 1.4a */ 1473 #endif 1474 # ifndef DP_TUNNELING_BW_ALLOC_BITS_MASK 1475 # define DP_TUNNELING_BW_ALLOC_BITS_MASK (0x0F << 0) 1476 # endif 1477 # ifndef DP_TUNNELING_BW_REQUEST_FAILED 1478 # define DP_TUNNELING_BW_REQUEST_FAILED (1 << 0) 1479 # endif 1480 # ifndef DP_TUNNELING_BW_REQUEST_SUCCEEDED 1481 # define DP_TUNNELING_BW_REQUEST_SUCCEEDED (1 << 1) 1482 # endif 1483 # ifndef DP_TUNNELING_ESTIMATED_BW_CHANGED 1484 # define DP_TUNNELING_ESTIMATED_BW_CHANGED (1 << 2) 1485 # endif 1486 # ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED 1487 # define DP_TUNNELING_BW_ALLOC_CAP_CHANGED (1 << 3) 1488 # endif 1489 1490 #endif /* DC_DP_TYPES_H */ 1491