1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef SELFTEST_KVM_PROCESSOR_H
4 #define SELFTEST_KVM_PROCESSOR_H
5
6 #ifndef __ASSEMBLER__
7 #include "ucall_common.h"
8
9 #else
10 /* general registers */
11 #define zero $r0
12 #define ra $r1
13 #define tp $r2
14 #define sp $r3
15 #define a0 $r4
16 #define a1 $r5
17 #define a2 $r6
18 #define a3 $r7
19 #define a4 $r8
20 #define a5 $r9
21 #define a6 $r10
22 #define a7 $r11
23 #define t0 $r12
24 #define t1 $r13
25 #define t2 $r14
26 #define t3 $r15
27 #define t4 $r16
28 #define t5 $r17
29 #define t6 $r18
30 #define t7 $r19
31 #define t8 $r20
32 #define u0 $r21
33 #define fp $r22
34 #define s0 $r23
35 #define s1 $r24
36 #define s2 $r25
37 #define s3 $r26
38 #define s4 $r27
39 #define s5 $r28
40 #define s6 $r29
41 #define s7 $r30
42 #define s8 $r31
43 #endif
44
45 /*
46 * LoongArch page table entry definition
47 * Original header file arch/loongarch/include/asm/loongarch.h
48 */
49 #define _PAGE_VALID_SHIFT 0
50 #define _PAGE_DIRTY_SHIFT 1
51 #define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */
52 #define PLV_KERN 0
53 #define PLV_USER 3
54 #define PLV_MASK 0x3
55 #define _CACHE_SHIFT 4 /* 4~5, two bits */
56 #define _PAGE_PRESENT_SHIFT 7
57 #define _PAGE_WRITE_SHIFT 8
58
59 #define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT)
60 #define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT)
61 #define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT)
62 #define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT)
63 #define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT)
64 #define __READABLE (_PAGE_VALID)
65 #define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE)
66 /* Coherent Cached */
67 #define _CACHE_CC BIT_ULL(_CACHE_SHIFT)
68 #define PS_4K 0x0000000c
69 #define PS_16K 0x0000000e
70 #define PS_64K 0x00000010
71 #define PS_DEFAULT_SIZE PS_16K
72
73 /* LoongArch Basic CSR registers */
74 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
75 #define CSR_CRMD_PG_SHIFT 4
76 #define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT)
77 #define CSR_CRMD_IE_SHIFT 2
78 #define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT)
79 #define CSR_CRMD_PLV_SHIFT 0
80 #define CSR_CRMD_PLV_WIDTH 2
81 #define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT)
82 #define PLV_MASK 0x3
83 #define LOONGARCH_CSR_PRMD 0x1
84 #define LOONGARCH_CSR_EUEN 0x2
85 #define LOONGARCH_CSR_ECFG 0x4
86 #define ECFGB_TIMER 11
87 #define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER))
88 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
89 #define CSR_ESTAT_EXC_SHIFT 16
90 #define CSR_ESTAT_EXC_WIDTH 6
91 #define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT)
92 #define EXCCODE_INT 0 /* Interrupt */
93 #define INT_TI 11 /* Timer interrupt*/
94 #define LOONGARCH_CSR_ERA 0x6 /* ERA */
95 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
96 #define LOONGARCH_CSR_EENTRY 0xc
97 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */
98 #define CSR_TLBIDX_PS_SHIFT 24
99 #define CSR_TLBIDX_PS_WIDTH 6
100 #define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT)
101 #define CSR_TLBIDX_SIZEM 0x3f000000
102 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
103 #define LOONGARCH_CSR_ASID 0x18 /* ASID */
104 #define LOONGARCH_CSR_PGDL 0x19
105 #define LOONGARCH_CSR_PGDH 0x1a
106 /* Page table base */
107 #define LOONGARCH_CSR_PGD 0x1b
108 #define LOONGARCH_CSR_PWCTL0 0x1c
109 #define LOONGARCH_CSR_PWCTL1 0x1d
110 #define LOONGARCH_CSR_STLBPGSIZE 0x1e
111 #define LOONGARCH_CSR_CPUID 0x20
112 #define LOONGARCH_CSR_KS0 0x30
113 #define LOONGARCH_CSR_KS1 0x31
114 #define LOONGARCH_CSR_TMID 0x40
115 #define LOONGARCH_CSR_TCFG 0x41
116 #define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2))
117 #define CSR_TCFG_PERIOD_SHIFT 1
118 #define CSR_TCFG_PERIOD (0x1UL << CSR_TCFG_PERIOD_SHIFT)
119 #define CSR_TCFG_EN (0x1UL)
120 #define LOONGARCH_CSR_TVAL 0x42
121 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
122 #define CSR_TINTCLR_TI_SHIFT 0
123 #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT)
124 /* TLB refill exception entry */
125 #define LOONGARCH_CSR_TLBRENTRY 0x88
126 #define LOONGARCH_CSR_TLBRSAVE 0x8b
127 #define LOONGARCH_CSR_TLBREHI 0x8e
128 #define CSR_TLBREHI_PS_SHIFT 0
129 #define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT)
130
131 #define csr_read(csr) \
132 ({ \
133 register unsigned long __v; \
134 __asm__ __volatile__( \
135 "csrrd %[val], %[reg]\n\t" \
136 : [val] "=r" (__v) \
137 : [reg] "i" (csr) \
138 : "memory"); \
139 __v; \
140 })
141
142 #define csr_write(v, csr) \
143 ({ \
144 register unsigned long __v = v; \
145 __asm__ __volatile__ ( \
146 "csrwr %[val], %[reg]\n\t" \
147 : [val] "+r" (__v) \
148 : [reg] "i" (csr) \
149 : "memory"); \
150 __v; \
151 })
152
153 #define EXREGS_GPRS (32)
154
155 #ifndef __ASSEMBLER__
156 void handle_tlb_refill(void);
157 void handle_exception(void);
158
159 struct ex_regs {
160 unsigned long regs[EXREGS_GPRS];
161 unsigned long pc;
162 unsigned long estat;
163 unsigned long badv;
164 unsigned long prmd;
165 };
166
167 #define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc)
168 #define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat)
169 #define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv)
170 #define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd)
171 #define EXREGS_SIZE sizeof(struct ex_regs)
172
173 #define VECTOR_NUM 64
174
175 typedef void(*handler_fn)(struct ex_regs *);
176
177 struct handlers {
178 handler_fn exception_handlers[VECTOR_NUM];
179 };
180
181 void vm_init_descriptor_tables(struct kvm_vm *vm);
182 void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn handler);
183
cpu_relax(void)184 static inline void cpu_relax(void)
185 {
186 asm volatile("nop" ::: "memory");
187 }
188
local_irq_enable(void)189 static inline void local_irq_enable(void)
190 {
191 unsigned int flags = CSR_CRMD_IE;
192 register unsigned int mask asm("$t0") = CSR_CRMD_IE;
193
194 __asm__ __volatile__(
195 "csrxchg %[val], %[mask], %[reg]\n\t"
196 : [val] "+r" (flags)
197 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
198 : "memory");
199 }
200
local_irq_disable(void)201 static inline void local_irq_disable(void)
202 {
203 unsigned int flags = 0;
204 register unsigned int mask asm("$t0") = CSR_CRMD_IE;
205
206 __asm__ __volatile__(
207 "csrxchg %[val], %[mask], %[reg]\n\t"
208 : [val] "+r" (flags)
209 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
210 : "memory");
211 }
212 #else
213 #define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8)
214 #define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8)
215 #define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8)
216 #define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8)
217 #define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8)
218 #endif
219
220 #endif /* SELFTEST_KVM_PROCESSOR_H */
221