1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_VMX_H 7 #define SELFTEST_KVM_VMX_H 8 9 #include <asm/vmx.h> 10 11 #include <stdint.h> 12 #include "processor.h" 13 #include "apic.h" 14 15 /* 16 * Definitions of Primary Processor-Based VM-Execution Controls. 17 */ 18 #define CPU_BASED_INTR_WINDOW_EXITING 0x00000004 19 #define CPU_BASED_USE_TSC_OFFSETTING 0x00000008 20 #define CPU_BASED_HLT_EXITING 0x00000080 21 #define CPU_BASED_INVLPG_EXITING 0x00000200 22 #define CPU_BASED_MWAIT_EXITING 0x00000400 23 #define CPU_BASED_RDPMC_EXITING 0x00000800 24 #define CPU_BASED_RDTSC_EXITING 0x00001000 25 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 26 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 27 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 28 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 29 #define CPU_BASED_TPR_SHADOW 0x00200000 30 #define CPU_BASED_NMI_WINDOW_EXITING 0x00400000 31 #define CPU_BASED_MOV_DR_EXITING 0x00800000 32 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 33 #define CPU_BASED_USE_IO_BITMAPS 0x02000000 34 #define CPU_BASED_MONITOR_TRAP 0x08000000 35 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 36 #define CPU_BASED_MONITOR_EXITING 0x20000000 37 #define CPU_BASED_PAUSE_EXITING 0x40000000 38 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 39 40 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172 41 42 /* 43 * Definitions of Secondary Processor-Based VM-Execution Controls. 44 */ 45 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 46 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 47 #define SECONDARY_EXEC_DESC 0x00000004 48 #define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008 49 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 50 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 51 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 52 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 53 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 54 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 55 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 56 #define SECONDARY_EXEC_RDRAND_EXITING 0x00000800 57 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 58 #define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 59 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 60 #define SECONDARY_EXEC_RDSEED_EXITING 0x00010000 61 #define SECONDARY_EXEC_ENABLE_PML 0x00020000 62 #define SECONDARY_EPT_VE 0x00040000 63 #define SECONDARY_ENABLE_XSAV_RESTORE 0x00100000 64 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 65 66 #define PIN_BASED_EXT_INTR_MASK 0x00000001 67 #define PIN_BASED_NMI_EXITING 0x00000008 68 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 69 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 70 #define PIN_BASED_POSTED_INTR 0x00000080 71 72 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 73 74 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 75 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 76 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 77 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 78 #define VM_EXIT_SAVE_IA32_PAT 0x00040000 79 #define VM_EXIT_LOAD_IA32_PAT 0x00080000 80 #define VM_EXIT_SAVE_IA32_EFER 0x00100000 81 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 82 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 83 84 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 85 86 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 87 #define VM_ENTRY_IA32E_MODE 0x00000200 88 #define VM_ENTRY_SMM 0x00000400 89 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 90 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 91 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 92 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 93 94 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 95 96 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 97 #define VMX_MISC_SAVE_EFER_LMA 0x00000020 98 99 #define VMX_EPT_VPID_CAP_1G_PAGES 0x00020000 100 #define VMX_EPT_VPID_CAP_AD_BITS 0x00200000 101 102 #define EXIT_REASON_FAILED_VMENTRY 0x80000000 103 104 enum vmcs_field { 105 VIRTUAL_PROCESSOR_ID = 0x00000000, 106 POSTED_INTR_NV = 0x00000002, 107 GUEST_ES_SELECTOR = 0x00000800, 108 GUEST_CS_SELECTOR = 0x00000802, 109 GUEST_SS_SELECTOR = 0x00000804, 110 GUEST_DS_SELECTOR = 0x00000806, 111 GUEST_FS_SELECTOR = 0x00000808, 112 GUEST_GS_SELECTOR = 0x0000080a, 113 GUEST_LDTR_SELECTOR = 0x0000080c, 114 GUEST_TR_SELECTOR = 0x0000080e, 115 GUEST_INTR_STATUS = 0x00000810, 116 GUEST_PML_INDEX = 0x00000812, 117 HOST_ES_SELECTOR = 0x00000c00, 118 HOST_CS_SELECTOR = 0x00000c02, 119 HOST_SS_SELECTOR = 0x00000c04, 120 HOST_DS_SELECTOR = 0x00000c06, 121 HOST_FS_SELECTOR = 0x00000c08, 122 HOST_GS_SELECTOR = 0x00000c0a, 123 HOST_TR_SELECTOR = 0x00000c0c, 124 IO_BITMAP_A = 0x00002000, 125 IO_BITMAP_A_HIGH = 0x00002001, 126 IO_BITMAP_B = 0x00002002, 127 IO_BITMAP_B_HIGH = 0x00002003, 128 MSR_BITMAP = 0x00002004, 129 MSR_BITMAP_HIGH = 0x00002005, 130 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 131 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 132 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 133 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 134 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 135 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 136 PML_ADDRESS = 0x0000200e, 137 PML_ADDRESS_HIGH = 0x0000200f, 138 TSC_OFFSET = 0x00002010, 139 TSC_OFFSET_HIGH = 0x00002011, 140 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 141 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 142 APIC_ACCESS_ADDR = 0x00002014, 143 APIC_ACCESS_ADDR_HIGH = 0x00002015, 144 POSTED_INTR_DESC_ADDR = 0x00002016, 145 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 146 EPT_POINTER = 0x0000201a, 147 EPT_POINTER_HIGH = 0x0000201b, 148 EOI_EXIT_BITMAP0 = 0x0000201c, 149 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 150 EOI_EXIT_BITMAP1 = 0x0000201e, 151 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 152 EOI_EXIT_BITMAP2 = 0x00002020, 153 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 154 EOI_EXIT_BITMAP3 = 0x00002022, 155 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 156 VMREAD_BITMAP = 0x00002026, 157 VMREAD_BITMAP_HIGH = 0x00002027, 158 VMWRITE_BITMAP = 0x00002028, 159 VMWRITE_BITMAP_HIGH = 0x00002029, 160 XSS_EXIT_BITMAP = 0x0000202C, 161 XSS_EXIT_BITMAP_HIGH = 0x0000202D, 162 ENCLS_EXITING_BITMAP = 0x0000202E, 163 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F, 164 TSC_MULTIPLIER = 0x00002032, 165 TSC_MULTIPLIER_HIGH = 0x00002033, 166 GUEST_PHYSICAL_ADDRESS = 0x00002400, 167 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 168 VMCS_LINK_POINTER = 0x00002800, 169 VMCS_LINK_POINTER_HIGH = 0x00002801, 170 GUEST_IA32_DEBUGCTL = 0x00002802, 171 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 172 GUEST_IA32_PAT = 0x00002804, 173 GUEST_IA32_PAT_HIGH = 0x00002805, 174 GUEST_IA32_EFER = 0x00002806, 175 GUEST_IA32_EFER_HIGH = 0x00002807, 176 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 177 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 178 GUEST_PDPTR0 = 0x0000280a, 179 GUEST_PDPTR0_HIGH = 0x0000280b, 180 GUEST_PDPTR1 = 0x0000280c, 181 GUEST_PDPTR1_HIGH = 0x0000280d, 182 GUEST_PDPTR2 = 0x0000280e, 183 GUEST_PDPTR2_HIGH = 0x0000280f, 184 GUEST_PDPTR3 = 0x00002810, 185 GUEST_PDPTR3_HIGH = 0x00002811, 186 GUEST_BNDCFGS = 0x00002812, 187 GUEST_BNDCFGS_HIGH = 0x00002813, 188 HOST_IA32_PAT = 0x00002c00, 189 HOST_IA32_PAT_HIGH = 0x00002c01, 190 HOST_IA32_EFER = 0x00002c02, 191 HOST_IA32_EFER_HIGH = 0x00002c03, 192 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 193 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 194 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 195 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 196 EXCEPTION_BITMAP = 0x00004004, 197 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 198 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 199 CR3_TARGET_COUNT = 0x0000400a, 200 VM_EXIT_CONTROLS = 0x0000400c, 201 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 202 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 203 VM_ENTRY_CONTROLS = 0x00004012, 204 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 205 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 206 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 207 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 208 TPR_THRESHOLD = 0x0000401c, 209 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 210 PLE_GAP = 0x00004020, 211 PLE_WINDOW = 0x00004022, 212 VM_INSTRUCTION_ERROR = 0x00004400, 213 VM_EXIT_REASON = 0x00004402, 214 VM_EXIT_INTR_INFO = 0x00004404, 215 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 216 IDT_VECTORING_INFO_FIELD = 0x00004408, 217 IDT_VECTORING_ERROR_CODE = 0x0000440a, 218 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 219 VMX_INSTRUCTION_INFO = 0x0000440e, 220 GUEST_ES_LIMIT = 0x00004800, 221 GUEST_CS_LIMIT = 0x00004802, 222 GUEST_SS_LIMIT = 0x00004804, 223 GUEST_DS_LIMIT = 0x00004806, 224 GUEST_FS_LIMIT = 0x00004808, 225 GUEST_GS_LIMIT = 0x0000480a, 226 GUEST_LDTR_LIMIT = 0x0000480c, 227 GUEST_TR_LIMIT = 0x0000480e, 228 GUEST_GDTR_LIMIT = 0x00004810, 229 GUEST_IDTR_LIMIT = 0x00004812, 230 GUEST_ES_AR_BYTES = 0x00004814, 231 GUEST_CS_AR_BYTES = 0x00004816, 232 GUEST_SS_AR_BYTES = 0x00004818, 233 GUEST_DS_AR_BYTES = 0x0000481a, 234 GUEST_FS_AR_BYTES = 0x0000481c, 235 GUEST_GS_AR_BYTES = 0x0000481e, 236 GUEST_LDTR_AR_BYTES = 0x00004820, 237 GUEST_TR_AR_BYTES = 0x00004822, 238 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 239 GUEST_ACTIVITY_STATE = 0X00004826, 240 GUEST_SYSENTER_CS = 0x0000482A, 241 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 242 HOST_IA32_SYSENTER_CS = 0x00004c00, 243 CR0_GUEST_HOST_MASK = 0x00006000, 244 CR4_GUEST_HOST_MASK = 0x00006002, 245 CR0_READ_SHADOW = 0x00006004, 246 CR4_READ_SHADOW = 0x00006006, 247 CR3_TARGET_VALUE0 = 0x00006008, 248 CR3_TARGET_VALUE1 = 0x0000600a, 249 CR3_TARGET_VALUE2 = 0x0000600c, 250 CR3_TARGET_VALUE3 = 0x0000600e, 251 EXIT_QUALIFICATION = 0x00006400, 252 GUEST_LINEAR_ADDRESS = 0x0000640a, 253 GUEST_CR0 = 0x00006800, 254 GUEST_CR3 = 0x00006802, 255 GUEST_CR4 = 0x00006804, 256 GUEST_ES_BASE = 0x00006806, 257 GUEST_CS_BASE = 0x00006808, 258 GUEST_SS_BASE = 0x0000680a, 259 GUEST_DS_BASE = 0x0000680c, 260 GUEST_FS_BASE = 0x0000680e, 261 GUEST_GS_BASE = 0x00006810, 262 GUEST_LDTR_BASE = 0x00006812, 263 GUEST_TR_BASE = 0x00006814, 264 GUEST_GDTR_BASE = 0x00006816, 265 GUEST_IDTR_BASE = 0x00006818, 266 GUEST_DR7 = 0x0000681a, 267 GUEST_RSP = 0x0000681c, 268 GUEST_RIP = 0x0000681e, 269 GUEST_RFLAGS = 0x00006820, 270 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 271 GUEST_SYSENTER_ESP = 0x00006824, 272 GUEST_SYSENTER_EIP = 0x00006826, 273 HOST_CR0 = 0x00006c00, 274 HOST_CR3 = 0x00006c02, 275 HOST_CR4 = 0x00006c04, 276 HOST_FS_BASE = 0x00006c06, 277 HOST_GS_BASE = 0x00006c08, 278 HOST_TR_BASE = 0x00006c0a, 279 HOST_GDTR_BASE = 0x00006c0c, 280 HOST_IDTR_BASE = 0x00006c0e, 281 HOST_IA32_SYSENTER_ESP = 0x00006c10, 282 HOST_IA32_SYSENTER_EIP = 0x00006c12, 283 HOST_RSP = 0x00006c14, 284 HOST_RIP = 0x00006c16, 285 }; 286 287 struct vmx_msr_entry { 288 u32 index; 289 u32 reserved; 290 u64 value; 291 } __attribute__ ((aligned(16))); 292 293 #define VMX_SWITCH_GPRS_ASM \ 294 GUEST_SWITCH_GPR_ASM(rax) \ 295 GUEST_SWITCH_GPR_ASM(rbx) \ 296 GUEST_SWITCH_GPR_ASM(rcx) \ 297 GUEST_SWITCH_GPR_ASM(rdx) \ 298 GUEST_SWITCH_GPR_ASM(rbp) \ 299 GUEST_SWITCH_GPR_ASM(rsi) \ 300 GUEST_SWITCH_GPR_ASM(rdi) \ 301 GUEST_SWITCH_GPR_ASM(r8) \ 302 GUEST_SWITCH_GPR_ASM(r9) \ 303 GUEST_SWITCH_GPR_ASM(r10) \ 304 GUEST_SWITCH_GPR_ASM(r11) \ 305 GUEST_SWITCH_GPR_ASM(r12) \ 306 GUEST_SWITCH_GPR_ASM(r13) \ 307 GUEST_SWITCH_GPR_ASM(r14) \ 308 GUEST_SWITCH_GPR_ASM(r15) 309 310 #include "evmcs.h" 311 312 #define GUEST_ASSERT_VMX_INSN_SUCCEEDED(insn, __r, __pa) \ 313 __GUEST_ASSERT(!__r, __stringify(insn) "[0x%lx] hit %s", \ 314 __pa, __r < 0 ? "VM-Fail" : ex_str(__r)) 315 316 #define BUILD_VMCS_ASM_HELPERS(insn) \ 317 static inline int __##insn(u64 vmcs_pa) \ 318 { \ 319 u64 error_code; \ 320 u8 vector; \ 321 u8 failed; \ 322 \ 323 asm volatile(KVM_ASM_SAFE(__stringify(insn) " %[pa]") \ 324 "\n\tsetna %[failed]" \ 325 : KVM_ASM_SAFE_OUTPUTS(vector, error_code), \ 326 [failed]"=qm"(failed) \ 327 : [pa]"m"(vmcs_pa) \ 328 : "cc", "memory", KVM_ASM_SAFE_CLOBBERS); \ 329 \ 330 return vector ? vector : failed ? -EINVAL : 0; \ 331 } \ 332 \ 333 static inline void insn(u64 vmcs_pa) \ 334 { \ 335 int ret = __##insn(vmcs_pa); \ 336 \ 337 GUEST_ASSERT_VMX_INSN_SUCCEEDED(insn, ret, vmcs_pa); \ 338 } 339 340 BUILD_VMCS_ASM_HELPERS(vmxon) 341 BUILD_VMCS_ASM_HELPERS(vmptrld) 342 BUILD_VMCS_ASM_HELPERS(vmclear) 343 344 static inline void vmxoff(void) 345 { 346 __asm__ __volatile__("vmxoff"); 347 } 348 349 static inline u64 vmptrst(void) 350 { 351 u64 value = 0; 352 u8 ret; 353 354 __asm__ __volatile__("vmptrst %[value]; setna %[ret]" 355 : [value]"=m"(value), [ret]"=rm"(ret) 356 : : "cc", "memory"); 357 358 __GUEST_ASSERT(!ret, "vmptrst failed"); 359 return value; 360 } 361 362 int __vmlaunch(void); 363 int __vmresume(void); 364 365 static inline void vmlaunch(void) 366 { 367 __GUEST_ASSERT(!__vmlaunch(), "vmlaunch hit VM-Fail"); 368 } 369 370 static inline void vmresume(void) 371 { 372 __GUEST_ASSERT(!__vmresume(), "vmresume hit VM-Fail"); 373 } 374 375 static inline void vmcall(void) 376 { 377 /* 378 * Stuff RAX and RCX with "safe" values to make sure L0 doesn't handle 379 * it as a valid hypercall (e.g. Hyper-V L2 TLB flush) as the intended 380 * use of this function is to exit to L1 from L2. Clobber all other 381 * GPRs as L1 doesn't correctly preserve them during vmexits. 382 */ 383 __asm__ __volatile__("push %%rbp; vmcall; pop %%rbp" 384 : : "a"(0xdeadbeef), "c"(0xbeefdead) 385 : "rbx", "rdx", "rsi", "rdi", "r8", "r9", 386 "r10", "r11", "r12", "r13", "r14", "r15"); 387 } 388 389 static inline int __vmread(u64 encoding, u64 *value) 390 { 391 u64 tmp; 392 u8 ret; 393 394 if (enable_evmcs) 395 return evmcs_vmread(encoding, value); 396 397 __asm__ __volatile__("vmread %[encoding], %[value]; setna %[ret]" 398 : [value]"=rm"(tmp), [ret]"=rm"(ret) 399 : [encoding]"r"(encoding) 400 : "cc", "memory"); 401 402 if (!ret) 403 *value = tmp; 404 return ret; 405 } 406 407 static inline u64 vmread(u64 encoding) 408 { 409 u64 value = 0; 410 411 __GUEST_ASSERT(!__vmread(encoding, &value), 412 "vmread[0x%lx] hit VM-Fail", encoding); 413 return value; 414 } 415 416 static __always_inline int __vmwrite(u64 encoding, u64 value) 417 { 418 u8 ret; 419 420 if (enable_evmcs) 421 return evmcs_vmwrite(encoding, value); 422 423 __asm__ __volatile__ ("vmwrite %[value], %[encoding]; setna %[ret]" 424 : [ret]"=rm"(ret) 425 : [value]"rm"(value), [encoding]"r"(encoding) 426 : "cc", "memory"); 427 428 return ret; 429 } 430 431 static inline void vmwrite(u64 encoding, u64 value) 432 { 433 __GUEST_ASSERT(!__vmwrite(encoding, value), 434 "vmwrite[0x%lx] = 0x%lx hit VM-Fail", encoding, value); 435 } 436 437 static inline u32 vmcs_revision(void) 438 { 439 return rdmsr(MSR_IA32_VMX_BASIC); 440 } 441 442 struct vmx_pages { 443 void *vmxon_hva; 444 u64 vmxon_gpa; 445 void *vmxon; 446 447 void *vmcs_hva; 448 u64 vmcs_gpa; 449 void *vmcs; 450 451 void *msr_hva; 452 u64 msr_gpa; 453 void *msr; 454 455 void *shadow_vmcs_hva; 456 u64 shadow_vmcs_gpa; 457 void *shadow_vmcs; 458 459 void *vmread_hva; 460 u64 vmread_gpa; 461 void *vmread; 462 463 void *vmwrite_hva; 464 u64 vmwrite_gpa; 465 void *vmwrite; 466 467 void *apic_access_hva; 468 u64 apic_access_gpa; 469 void *apic_access; 470 471 void *stack; 472 473 u64 eptp_gpa; 474 }; 475 476 union vmx_basic { 477 u64 val; 478 struct { 479 u32 revision; 480 u32 size:13, 481 reserved1:3, 482 width:1, 483 dual:1, 484 type:4, 485 insouts:1, 486 ctrl:1, 487 vm_entry_exception_ctrl:1, 488 reserved2:7; 489 }; 490 }; 491 492 union vmx_ctrl_msr { 493 u64 val; 494 struct { 495 u32 set, clr; 496 }; 497 }; 498 499 struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva); 500 void prepare_for_vmx_operation(struct vmx_pages *vmx); 501 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip); 502 void load_vmcs(struct vmx_pages *vmx); 503 504 bool ept_1g_pages_supported(void); 505 506 bool kvm_cpu_has_secondary_exec_control(u32 ctrl); 507 508 static inline bool kvm_cpu_has_ept(void) 509 { 510 return kvm_cpu_has_secondary_exec_control(SECONDARY_EXEC_ENABLE_EPT); 511 } 512 513 static inline bool kvm_cpu_has_vmx_virtualize_apic_accesses(void) 514 { 515 return kvm_cpu_has_secondary_exec_control(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); 516 } 517 518 void vm_enable_ept(struct kvm_vm *vm); 519 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm); 520 521 #endif /* SELFTEST_KVM_VMX_H */ 522