1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * TI EDMA definitions 4 * 5 * Copyright (C) 2006-2013 Texas Instruments. 6 */ 7 8 /* 9 * This EDMA3 programming framework exposes two basic kinds of resource: 10 * 11 * Channel Triggers transfers, usually from a hardware event but 12 * also manually or by "chaining" from DMA completions. 13 * Each channel is coupled to a Parameter RAM (PaRAM) slot. 14 * 15 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM 16 * "set"), source and destination addresses, a link to a 17 * next PaRAM slot (if any), options for the transfer, and 18 * instructions for updating those addresses. There are 19 * more than twice as many slots as event channels. 20 * 21 * Each PaRAM set describes a sequence of transfers, either for one large 22 * buffer or for several discontiguous smaller buffers. An EDMA transfer 23 * is driven only from a channel, which performs the transfers specified 24 * in its PaRAM slot until there are no more transfers. When that last 25 * transfer completes, the "link" field may be used to reload the channel's 26 * PaRAM slot with a new transfer descriptor. 27 * 28 * The EDMA Channel Controller (CC) maps requests from channels into physical 29 * Transfer Controller (TC) requests when the channel triggers (by hardware 30 * or software events, or by chaining). The two physical DMA channels provided 31 * by the TCs are thus shared by many logical channels. 32 * 33 * DaVinci hardware also has a "QDMA" mechanism which is not currently 34 * supported through this interface. (DSP firmware uses it though.) 35 */ 36 37 #ifndef EDMA_H_ 38 #define EDMA_H_ 39 40 enum dma_event_q { 41 EVENTQ_0 = 0, 42 EVENTQ_1 = 1, 43 EVENTQ_2 = 2, 44 EVENTQ_3 = 3, 45 EVENTQ_DEFAULT = -1 46 }; 47 48 #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) 49 #define EDMA_CTLR(i) ((i) >> 16) 50 #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) 51 52 #define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) }) 53 54 struct edma_rsv_info { 55 56 const s16 (*rsv_chans)[2]; 57 const s16 (*rsv_slots)[2]; 58 }; 59 60 struct dma_slave_map; 61 62 /* platform_data for EDMA driver */ 63 struct edma_soc_info { 64 /* 65 * Default queue is expected to be a low-priority queue. 66 * This way, long transfers on the default queue started 67 * by the codec engine will not cause audio defects. 68 */ 69 enum dma_event_q default_queue; 70 71 /* Resource reservation for other cores */ 72 struct edma_rsv_info *rsv; 73 74 /* List of channels allocated for memcpy, terminated with -1 */ 75 s32 *memcpy_channels; 76 77 s8 (*queue_priority_mapping)[2]; 78 const s16 (*xbar_chans)[2]; 79 80 const struct dma_slave_map *slave_map; 81 int slavecnt; 82 }; 83 84 #endif 85