1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI eTDM Control 4 * 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 #include <sound/pcm_params.h> 14 #include "mt8195-afe-clk.h" 15 #include "mt8195-afe-common.h" 16 #include "mt8195-reg.h" 17 18 #define MT8195_ETDM_MAX_CHANNELS 24 19 #define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000 20 #define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START) 21 #define ENUM_TO_STR(x) #x 22 23 enum { 24 MTK_DAI_ETDM_FORMAT_I2S = 0, 25 MTK_DAI_ETDM_FORMAT_LJ, 26 MTK_DAI_ETDM_FORMAT_RJ, 27 MTK_DAI_ETDM_FORMAT_EIAJ, 28 MTK_DAI_ETDM_FORMAT_DSPA, 29 MTK_DAI_ETDM_FORMAT_DSPB, 30 }; 31 32 enum { 33 MTK_DAI_ETDM_DATA_ONE_PIN = 0, 34 MTK_DAI_ETDM_DATA_MULTI_PIN, 35 }; 36 37 enum { 38 ETDM_IN, 39 ETDM_OUT, 40 }; 41 42 enum { 43 ETDM_IN_FROM_PAD, 44 ETDM_IN_FROM_ETDM_OUT1, 45 ETDM_IN_FROM_ETDM_OUT2, 46 }; 47 48 enum { 49 ETDM_IN_SLAVE_FROM_PAD, 50 ETDM_IN_SLAVE_FROM_ETDM_OUT1, 51 ETDM_IN_SLAVE_FROM_ETDM_OUT2, 52 }; 53 54 enum { 55 ETDM_OUT_SLAVE_FROM_PAD, 56 ETDM_OUT_SLAVE_FROM_ETDM_IN1, 57 ETDM_OUT_SLAVE_FROM_ETDM_IN2, 58 }; 59 60 enum { 61 COWORK_ETDM_NONE = 0, 62 COWORK_ETDM_IN1_M = 2, 63 COWORK_ETDM_IN1_S = 3, 64 COWORK_ETDM_IN2_M = 4, 65 COWORK_ETDM_IN2_S = 5, 66 COWORK_ETDM_OUT1_M = 10, 67 COWORK_ETDM_OUT1_S = 11, 68 COWORK_ETDM_OUT2_M = 12, 69 COWORK_ETDM_OUT2_S = 13, 70 COWORK_ETDM_OUT3_M = 14, 71 COWORK_ETDM_OUT3_S = 15, 72 }; 73 74 enum { 75 ETDM_RELATCH_TIMING_A1A2SYS, 76 ETDM_RELATCH_TIMING_A3SYS, 77 ETDM_RELATCH_TIMING_A4SYS, 78 }; 79 80 enum { 81 ETDM_SYNC_NONE, 82 ETDM_SYNC_FROM_IN1, 83 ETDM_SYNC_FROM_IN2, 84 ETDM_SYNC_FROM_OUT1, 85 ETDM_SYNC_FROM_OUT2, 86 ETDM_SYNC_FROM_OUT3, 87 }; 88 89 struct etdm_con_reg { 90 unsigned int con0; 91 unsigned int con1; 92 unsigned int con2; 93 unsigned int con3; 94 unsigned int con4; 95 unsigned int con5; 96 }; 97 98 struct mtk_dai_etdm_rate { 99 unsigned int rate; 100 unsigned int reg_value; 101 }; 102 103 struct mtk_dai_etdm_priv { 104 unsigned int clock_mode; 105 unsigned int data_mode; 106 bool slave_mode; 107 bool lrck_inv; 108 bool bck_inv; 109 unsigned int format; 110 unsigned int slots; 111 unsigned int lrck_width; 112 unsigned int mclk_freq; 113 unsigned int mclk_apll; 114 unsigned int mclk_dir; 115 int cowork_source_id; //dai id 116 unsigned int cowork_slv_count; 117 int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id 118 bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS]; 119 unsigned int en_ref_cnt; 120 }; 121 122 static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = { 123 { .rate = 8000, .reg_value = 0, }, 124 { .rate = 12000, .reg_value = 1, }, 125 { .rate = 16000, .reg_value = 2, }, 126 { .rate = 24000, .reg_value = 3, }, 127 { .rate = 32000, .reg_value = 4, }, 128 { .rate = 48000, .reg_value = 5, }, 129 { .rate = 96000, .reg_value = 7, }, 130 { .rate = 192000, .reg_value = 9, }, 131 { .rate = 384000, .reg_value = 11, }, 132 { .rate = 11025, .reg_value = 16, }, 133 { .rate = 22050, .reg_value = 17, }, 134 { .rate = 44100, .reg_value = 18, }, 135 { .rate = 88200, .reg_value = 19, }, 136 { .rate = 176400, .reg_value = 20, }, 137 { .rate = 352800, .reg_value = 21, }, 138 }; 139 140 static bool mt8195_afe_etdm_is_valid(int id) 141 { 142 switch (id) { 143 case MT8195_AFE_IO_ETDM1_IN: 144 fallthrough; 145 case MT8195_AFE_IO_ETDM2_IN: 146 fallthrough; 147 case MT8195_AFE_IO_ETDM1_OUT: 148 fallthrough; 149 case MT8195_AFE_IO_ETDM2_OUT: 150 fallthrough; 151 case MT8195_AFE_IO_DPTX: 152 fallthrough; 153 case MT8195_AFE_IO_ETDM3_OUT: 154 return true; 155 default: 156 return false; 157 } 158 } 159 160 static bool mt8195_afe_hdmitx_dptx_is_valid(int id) 161 { 162 switch (id) { 163 case MT8195_AFE_IO_DPTX: 164 fallthrough; 165 case MT8195_AFE_IO_ETDM3_OUT: 166 return true; 167 default: 168 return false; 169 } 170 } 171 172 static int get_etdm_fs_timing(unsigned int rate) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++) 177 if (mt8195_etdm_rates[i].rate == rate) 178 return mt8195_etdm_rates[i].reg_value; 179 180 return -EINVAL; 181 } 182 183 static unsigned int get_etdm_ch_fixup(unsigned int channels) 184 { 185 if (channels > 16) 186 return 24; 187 else if (channels > 8) 188 return 16; 189 else if (channels > 4) 190 return 8; 191 else if (channels > 2) 192 return 4; 193 else 194 return 2; 195 } 196 197 static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 198 { 199 switch (dai_id) { 200 case MT8195_AFE_IO_ETDM1_IN: 201 etdm_reg->con0 = ETDM_IN1_CON0; 202 etdm_reg->con1 = ETDM_IN1_CON1; 203 etdm_reg->con2 = ETDM_IN1_CON2; 204 etdm_reg->con3 = ETDM_IN1_CON3; 205 etdm_reg->con4 = ETDM_IN1_CON4; 206 etdm_reg->con5 = ETDM_IN1_CON5; 207 break; 208 case MT8195_AFE_IO_ETDM2_IN: 209 etdm_reg->con0 = ETDM_IN2_CON0; 210 etdm_reg->con1 = ETDM_IN2_CON1; 211 etdm_reg->con2 = ETDM_IN2_CON2; 212 etdm_reg->con3 = ETDM_IN2_CON3; 213 etdm_reg->con4 = ETDM_IN2_CON4; 214 etdm_reg->con5 = ETDM_IN2_CON5; 215 break; 216 case MT8195_AFE_IO_ETDM1_OUT: 217 etdm_reg->con0 = ETDM_OUT1_CON0; 218 etdm_reg->con1 = ETDM_OUT1_CON1; 219 etdm_reg->con2 = ETDM_OUT1_CON2; 220 etdm_reg->con3 = ETDM_OUT1_CON3; 221 etdm_reg->con4 = ETDM_OUT1_CON4; 222 etdm_reg->con5 = ETDM_OUT1_CON5; 223 break; 224 case MT8195_AFE_IO_ETDM2_OUT: 225 etdm_reg->con0 = ETDM_OUT2_CON0; 226 etdm_reg->con1 = ETDM_OUT2_CON1; 227 etdm_reg->con2 = ETDM_OUT2_CON2; 228 etdm_reg->con3 = ETDM_OUT2_CON3; 229 etdm_reg->con4 = ETDM_OUT2_CON4; 230 etdm_reg->con5 = ETDM_OUT2_CON5; 231 break; 232 case MT8195_AFE_IO_ETDM3_OUT: 233 case MT8195_AFE_IO_DPTX: 234 etdm_reg->con0 = ETDM_OUT3_CON0; 235 etdm_reg->con1 = ETDM_OUT3_CON1; 236 etdm_reg->con2 = ETDM_OUT3_CON2; 237 etdm_reg->con3 = ETDM_OUT3_CON3; 238 etdm_reg->con4 = ETDM_OUT3_CON4; 239 etdm_reg->con5 = ETDM_OUT3_CON5; 240 break; 241 default: 242 return -EINVAL; 243 } 244 return 0; 245 } 246 247 static int get_etdm_dir(unsigned int dai_id) 248 { 249 switch (dai_id) { 250 case MT8195_AFE_IO_ETDM1_IN: 251 case MT8195_AFE_IO_ETDM2_IN: 252 return ETDM_IN; 253 case MT8195_AFE_IO_ETDM1_OUT: 254 case MT8195_AFE_IO_ETDM2_OUT: 255 case MT8195_AFE_IO_ETDM3_OUT: 256 return ETDM_OUT; 257 default: 258 return -EINVAL; 259 } 260 } 261 262 static int get_etdm_wlen(unsigned int bitwidth) 263 { 264 return bitwidth <= 16 ? 16 : 32; 265 } 266 267 static int is_cowork_mode(struct snd_soc_dai *dai) 268 { 269 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 270 struct mt8195_afe_private *afe_priv = afe->platform_priv; 271 struct mtk_dai_etdm_priv *etdm_data; 272 273 if (!mt8195_afe_etdm_is_valid(dai->id)) 274 return -EINVAL; 275 276 etdm_data = afe_priv->dai_priv[dai->id]; 277 return (etdm_data->cowork_slv_count > 0 || 278 etdm_data->cowork_source_id != COWORK_ETDM_NONE); 279 } 280 281 static int sync_to_dai_id(int source_sel) 282 { 283 switch (source_sel) { 284 case ETDM_SYNC_FROM_IN1: 285 return MT8195_AFE_IO_ETDM1_IN; 286 case ETDM_SYNC_FROM_IN2: 287 return MT8195_AFE_IO_ETDM2_IN; 288 case ETDM_SYNC_FROM_OUT1: 289 return MT8195_AFE_IO_ETDM1_OUT; 290 case ETDM_SYNC_FROM_OUT2: 291 return MT8195_AFE_IO_ETDM2_OUT; 292 case ETDM_SYNC_FROM_OUT3: 293 return MT8195_AFE_IO_ETDM3_OUT; 294 default: 295 return 0; 296 } 297 } 298 299 static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 300 { 301 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 302 struct mt8195_afe_private *afe_priv = afe->platform_priv; 303 struct mtk_dai_etdm_priv *etdm_data; 304 int dai_id; 305 306 if (!mt8195_afe_etdm_is_valid(dai->id)) 307 return -EINVAL; 308 309 etdm_data = afe_priv->dai_priv[dai->id]; 310 dai_id = etdm_data->cowork_source_id; 311 312 if (dai_id == COWORK_ETDM_NONE) 313 dai_id = dai->id; 314 315 return dai_id; 316 } 317 318 static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 319 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 320 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 321 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 322 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 323 }; 324 325 static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 326 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 327 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 328 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 329 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 330 }; 331 332 static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 333 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 334 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 335 }; 336 337 static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 338 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 339 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 340 }; 341 342 static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 343 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 344 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 345 }; 346 347 static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 348 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 349 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 350 }; 351 352 static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 353 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 354 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 355 }; 356 357 static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 358 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 359 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 360 }; 361 362 static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 363 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 364 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 365 }; 366 367 static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 368 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 369 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 370 }; 371 372 static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 373 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 374 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 375 }; 376 377 static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 378 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 379 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 380 }; 381 382 static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 383 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 384 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 385 }; 386 387 static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 388 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 389 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 390 }; 391 392 static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 393 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 394 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 395 }; 396 397 static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 398 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 399 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 400 }; 401 402 static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = { 403 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0), 404 SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0), 405 }; 406 407 static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = { 408 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0), 409 SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0), 410 }; 411 412 static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = { 413 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0), 414 SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0), 415 }; 416 417 static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = { 418 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0), 419 SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0), 420 }; 421 422 static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = { 423 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0), 424 SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0), 425 }; 426 427 static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = { 428 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0), 429 SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0), 430 }; 431 432 static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = { 433 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0), 434 SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0), 435 }; 436 437 static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = { 438 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0), 439 SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0), 440 }; 441 442 static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 443 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 444 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 445 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 446 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 447 }; 448 449 static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 450 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 451 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 452 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 453 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 454 }; 455 456 static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 457 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 458 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 459 }; 460 461 static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 462 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 463 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 464 }; 465 466 static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 467 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 468 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 469 }; 470 471 static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 472 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 473 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 474 }; 475 476 static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 477 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 478 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 479 }; 480 481 static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 482 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 483 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 484 }; 485 486 static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 487 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 488 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 489 }; 490 491 static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 492 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 493 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 494 }; 495 496 static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 497 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 498 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 499 }; 500 501 static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 502 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 503 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 504 }; 505 506 static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 507 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 508 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 509 }; 510 511 static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 512 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 513 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 514 }; 515 516 static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 517 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 518 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 519 }; 520 521 static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 522 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 523 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 524 }; 525 526 static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = { 527 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0), 528 SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0), 529 }; 530 531 static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = { 532 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0), 533 SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0), 534 }; 535 536 static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = { 537 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0), 538 SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0), 539 }; 540 541 static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = { 542 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0), 543 SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0), 544 }; 545 546 static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = { 547 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0), 548 SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0), 549 }; 550 551 static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = { 552 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0), 553 SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0), 554 }; 555 556 static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = { 557 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0), 558 SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0), 559 }; 560 561 static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = { 562 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0), 563 SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0), 564 }; 565 566 static const char * const mt8195_etdm_clk_src_sel_text[] = { 567 "26m", 568 "a1sys_a2sys", 569 "a3sys", 570 "a4sys", 571 }; 572 573 static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 574 mt8195_etdm_clk_src_sel_text); 575 576 static const char * const hdmitx_dptx_mux_map[] = { 577 "Disconnect", "Connect", 578 }; 579 580 static int hdmitx_dptx_mux_map_value[] = { 581 0, 1, 582 }; 583 584 /* HDMI_OUT_MUX */ 585 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 586 SND_SOC_NOPM, 587 0, 588 1, 589 hdmitx_dptx_mux_map, 590 hdmitx_dptx_mux_map_value); 591 592 static const struct snd_kcontrol_new hdmi_out_mux_control = 593 SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 594 595 /* DPTX_OUT_MUX */ 596 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 597 SND_SOC_NOPM, 598 0, 599 1, 600 hdmitx_dptx_mux_map, 601 hdmitx_dptx_mux_map_value); 602 603 static const struct snd_kcontrol_new dptx_out_mux_control = 604 SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 605 606 /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 607 static const char *const afe_conn_hdmi_mux_map[] = { 608 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 609 }; 610 611 static int afe_conn_hdmi_mux_map_value[] = { 612 0, 1, 2, 3, 4, 5, 6, 7, 613 }; 614 615 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 616 AFE_TDMOUT_CONN0, 617 0, 618 0xf, 619 afe_conn_hdmi_mux_map, 620 afe_conn_hdmi_mux_map_value); 621 622 static const struct snd_kcontrol_new hdmi_ch0_mux_control = 623 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 624 625 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 626 AFE_TDMOUT_CONN0, 627 4, 628 0xf, 629 afe_conn_hdmi_mux_map, 630 afe_conn_hdmi_mux_map_value); 631 632 static const struct snd_kcontrol_new hdmi_ch1_mux_control = 633 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 634 635 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 636 AFE_TDMOUT_CONN0, 637 8, 638 0xf, 639 afe_conn_hdmi_mux_map, 640 afe_conn_hdmi_mux_map_value); 641 642 static const struct snd_kcontrol_new hdmi_ch2_mux_control = 643 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 644 645 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 646 AFE_TDMOUT_CONN0, 647 12, 648 0xf, 649 afe_conn_hdmi_mux_map, 650 afe_conn_hdmi_mux_map_value); 651 652 static const struct snd_kcontrol_new hdmi_ch3_mux_control = 653 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 654 655 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 656 AFE_TDMOUT_CONN0, 657 16, 658 0xf, 659 afe_conn_hdmi_mux_map, 660 afe_conn_hdmi_mux_map_value); 661 662 static const struct snd_kcontrol_new hdmi_ch4_mux_control = 663 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 664 665 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 666 AFE_TDMOUT_CONN0, 667 20, 668 0xf, 669 afe_conn_hdmi_mux_map, 670 afe_conn_hdmi_mux_map_value); 671 672 static const struct snd_kcontrol_new hdmi_ch5_mux_control = 673 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 674 675 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 676 AFE_TDMOUT_CONN0, 677 24, 678 0xf, 679 afe_conn_hdmi_mux_map, 680 afe_conn_hdmi_mux_map_value); 681 682 static const struct snd_kcontrol_new hdmi_ch6_mux_control = 683 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 684 685 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 686 AFE_TDMOUT_CONN0, 687 28, 688 0xf, 689 afe_conn_hdmi_mux_map, 690 afe_conn_hdmi_mux_map_value); 691 692 static const struct snd_kcontrol_new hdmi_ch7_mux_control = 693 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 694 695 static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 696 struct snd_ctl_elem_value *ucontrol) 697 { 698 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 699 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 700 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 701 unsigned int source = ucontrol->value.enumerated.item[0]; 702 unsigned int val; 703 unsigned int mask; 704 unsigned int reg; 705 706 if (source >= e->items) 707 return -EINVAL; 708 709 reg = 0; 710 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 711 reg = ETDM_OUT1_CON4; 712 mask = ETDM_OUT_CON4_CLOCK_MASK; 713 val = ETDM_OUT_CON4_CLOCK(source); 714 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 715 reg = ETDM_OUT2_CON4; 716 mask = ETDM_OUT_CON4_CLOCK_MASK; 717 val = ETDM_OUT_CON4_CLOCK(source); 718 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 719 reg = ETDM_OUT3_CON4; 720 mask = ETDM_OUT_CON4_CLOCK_MASK; 721 val = ETDM_OUT_CON4_CLOCK(source); 722 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 723 reg = ETDM_IN1_CON2; 724 mask = ETDM_IN_CON2_CLOCK_MASK; 725 val = ETDM_IN_CON2_CLOCK(source); 726 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 727 reg = ETDM_IN2_CON2; 728 mask = ETDM_IN_CON2_CLOCK_MASK; 729 val = ETDM_IN_CON2_CLOCK(source); 730 } 731 732 if (reg) 733 regmap_update_bits(afe->regmap, reg, mask, val); 734 735 return 0; 736 } 737 738 static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 739 struct snd_ctl_elem_value *ucontrol) 740 { 741 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 742 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 743 unsigned int value = 0; 744 unsigned int reg = 0; 745 unsigned int mask = 0; 746 unsigned int shift = 0; 747 748 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 749 reg = ETDM_OUT1_CON4; 750 mask = ETDM_OUT_CON4_CLOCK_MASK; 751 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 752 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 753 reg = ETDM_OUT2_CON4; 754 mask = ETDM_OUT_CON4_CLOCK_MASK; 755 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 756 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 757 reg = ETDM_OUT3_CON4; 758 mask = ETDM_OUT_CON4_CLOCK_MASK; 759 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 760 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 761 reg = ETDM_IN1_CON2; 762 mask = ETDM_IN_CON2_CLOCK_MASK; 763 shift = ETDM_IN_CON2_CLOCK_SHIFT; 764 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 765 reg = ETDM_IN2_CON2; 766 mask = ETDM_IN_CON2_CLOCK_MASK; 767 shift = ETDM_IN_CON2_CLOCK_SHIFT; 768 } 769 770 if (reg) 771 regmap_read(afe->regmap, reg, &value); 772 773 value &= mask; 774 value >>= shift; 775 ucontrol->value.enumerated.item[0] = value; 776 return 0; 777 } 778 779 static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 780 SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", 781 etdmout_clk_src_enum, 782 mt8195_etdm_clk_src_sel_get, 783 mt8195_etdm_clk_src_sel_put), 784 SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", 785 etdmout_clk_src_enum, 786 mt8195_etdm_clk_src_sel_get, 787 mt8195_etdm_clk_src_sel_put), 788 SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", 789 etdmout_clk_src_enum, 790 mt8195_etdm_clk_src_sel_get, 791 mt8195_etdm_clk_src_sel_put), 792 SOC_ENUM_EXT("ETDM_IN1_Clock_Source", 793 etdmout_clk_src_enum, 794 mt8195_etdm_clk_src_sel_get, 795 mt8195_etdm_clk_src_sel_put), 796 SOC_ENUM_EXT("ETDM_IN2_Clock_Source", 797 etdmout_clk_src_enum, 798 mt8195_etdm_clk_src_sel_get, 799 mt8195_etdm_clk_src_sel_put), 800 }; 801 802 static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 803 /* eTDM_IN2 */ 804 SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 805 SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 806 SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 807 SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 808 SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 809 SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 810 SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 811 SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 812 813 /* eTDM_IN1 */ 814 SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 815 SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 816 SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 817 SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 818 SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 819 SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 820 SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 821 SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 822 SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 823 SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 824 SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 825 SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 826 SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 827 SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 828 SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 829 SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 830 SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0), 831 SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0), 832 SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0), 833 SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0), 834 SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0), 835 SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0), 836 SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0), 837 SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0), 838 839 /* eTDM_OUT2 */ 840 SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 841 mtk_dai_etdm_o048_mix, 842 ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 843 SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 844 mtk_dai_etdm_o049_mix, 845 ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 846 SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 847 mtk_dai_etdm_o050_mix, 848 ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 849 SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 850 mtk_dai_etdm_o051_mix, 851 ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 852 SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 853 mtk_dai_etdm_o052_mix, 854 ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 855 SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 856 mtk_dai_etdm_o053_mix, 857 ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 858 SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 859 mtk_dai_etdm_o054_mix, 860 ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 861 SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 862 mtk_dai_etdm_o055_mix, 863 ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 864 SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 865 mtk_dai_etdm_o056_mix, 866 ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 867 SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 868 mtk_dai_etdm_o057_mix, 869 ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 870 SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 871 mtk_dai_etdm_o058_mix, 872 ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 873 SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 874 mtk_dai_etdm_o059_mix, 875 ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 876 SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 877 mtk_dai_etdm_o060_mix, 878 ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 879 SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 880 mtk_dai_etdm_o061_mix, 881 ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 882 SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 883 mtk_dai_etdm_o062_mix, 884 ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 885 SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 886 mtk_dai_etdm_o063_mix, 887 ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 888 SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0, 889 mtk_dai_etdm_o064_mix, 890 ARRAY_SIZE(mtk_dai_etdm_o064_mix)), 891 SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0, 892 mtk_dai_etdm_o065_mix, 893 ARRAY_SIZE(mtk_dai_etdm_o065_mix)), 894 SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0, 895 mtk_dai_etdm_o066_mix, 896 ARRAY_SIZE(mtk_dai_etdm_o066_mix)), 897 SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0, 898 mtk_dai_etdm_o067_mix, 899 ARRAY_SIZE(mtk_dai_etdm_o067_mix)), 900 SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0, 901 mtk_dai_etdm_o068_mix, 902 ARRAY_SIZE(mtk_dai_etdm_o068_mix)), 903 SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0, 904 mtk_dai_etdm_o069_mix, 905 ARRAY_SIZE(mtk_dai_etdm_o069_mix)), 906 SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0, 907 mtk_dai_etdm_o070_mix, 908 ARRAY_SIZE(mtk_dai_etdm_o070_mix)), 909 SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0, 910 mtk_dai_etdm_o071_mix, 911 ARRAY_SIZE(mtk_dai_etdm_o071_mix)), 912 913 /* eTDM_OUT1 */ 914 SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 915 mtk_dai_etdm_o072_mix, 916 ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 917 SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 918 mtk_dai_etdm_o073_mix, 919 ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 920 SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 921 mtk_dai_etdm_o074_mix, 922 ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 923 SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 924 mtk_dai_etdm_o075_mix, 925 ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 926 SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 927 mtk_dai_etdm_o076_mix, 928 ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 929 SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 930 mtk_dai_etdm_o077_mix, 931 ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 932 SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 933 mtk_dai_etdm_o078_mix, 934 ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 935 SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 936 mtk_dai_etdm_o079_mix, 937 ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 938 SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 939 mtk_dai_etdm_o080_mix, 940 ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 941 SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 942 mtk_dai_etdm_o081_mix, 943 ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 944 SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 945 mtk_dai_etdm_o082_mix, 946 ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 947 SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 948 mtk_dai_etdm_o083_mix, 949 ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 950 SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 951 mtk_dai_etdm_o084_mix, 952 ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 953 SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 954 mtk_dai_etdm_o085_mix, 955 ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 956 SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 957 mtk_dai_etdm_o086_mix, 958 ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 959 SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 960 mtk_dai_etdm_o087_mix, 961 ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 962 SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0, 963 mtk_dai_etdm_o088_mix, 964 ARRAY_SIZE(mtk_dai_etdm_o088_mix)), 965 SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0, 966 mtk_dai_etdm_o089_mix, 967 ARRAY_SIZE(mtk_dai_etdm_o089_mix)), 968 SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0, 969 mtk_dai_etdm_o090_mix, 970 ARRAY_SIZE(mtk_dai_etdm_o090_mix)), 971 SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0, 972 mtk_dai_etdm_o091_mix, 973 ARRAY_SIZE(mtk_dai_etdm_o091_mix)), 974 SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0, 975 mtk_dai_etdm_o092_mix, 976 ARRAY_SIZE(mtk_dai_etdm_o092_mix)), 977 SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0, 978 mtk_dai_etdm_o093_mix, 979 ARRAY_SIZE(mtk_dai_etdm_o093_mix)), 980 SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0, 981 mtk_dai_etdm_o094_mix, 982 ARRAY_SIZE(mtk_dai_etdm_o094_mix)), 983 SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0, 984 mtk_dai_etdm_o095_mix, 985 ARRAY_SIZE(mtk_dai_etdm_o095_mix)), 986 987 /* eTDM_OUT3 */ 988 SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 989 &hdmi_out_mux_control), 990 SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 991 &dptx_out_mux_control), 992 993 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 994 &hdmi_ch0_mux_control), 995 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 996 &hdmi_ch1_mux_control), 997 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 998 &hdmi_ch2_mux_control), 999 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 1000 &hdmi_ch3_mux_control), 1001 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 1002 &hdmi_ch4_mux_control), 1003 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 1004 &hdmi_ch5_mux_control), 1005 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 1006 &hdmi_ch6_mux_control), 1007 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 1008 &hdmi_ch7_mux_control), 1009 1010 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 1011 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 1012 }; 1013 1014 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 1015 {"I012", NULL, "ETDM2 Capture"}, 1016 {"I013", NULL, "ETDM2 Capture"}, 1017 {"I014", NULL, "ETDM2 Capture"}, 1018 {"I015", NULL, "ETDM2 Capture"}, 1019 {"I016", NULL, "ETDM2 Capture"}, 1020 {"I017", NULL, "ETDM2 Capture"}, 1021 {"I018", NULL, "ETDM2 Capture"}, 1022 {"I019", NULL, "ETDM2 Capture"}, 1023 1024 {"I072", NULL, "ETDM1 Capture"}, 1025 {"I073", NULL, "ETDM1 Capture"}, 1026 {"I074", NULL, "ETDM1 Capture"}, 1027 {"I075", NULL, "ETDM1 Capture"}, 1028 {"I076", NULL, "ETDM1 Capture"}, 1029 {"I077", NULL, "ETDM1 Capture"}, 1030 {"I078", NULL, "ETDM1 Capture"}, 1031 {"I079", NULL, "ETDM1 Capture"}, 1032 {"I080", NULL, "ETDM1 Capture"}, 1033 {"I081", NULL, "ETDM1 Capture"}, 1034 {"I082", NULL, "ETDM1 Capture"}, 1035 {"I083", NULL, "ETDM1 Capture"}, 1036 {"I084", NULL, "ETDM1 Capture"}, 1037 {"I085", NULL, "ETDM1 Capture"}, 1038 {"I086", NULL, "ETDM1 Capture"}, 1039 {"I087", NULL, "ETDM1 Capture"}, 1040 {"I088", NULL, "ETDM1 Capture"}, 1041 {"I089", NULL, "ETDM1 Capture"}, 1042 {"I090", NULL, "ETDM1 Capture"}, 1043 {"I091", NULL, "ETDM1 Capture"}, 1044 {"I092", NULL, "ETDM1 Capture"}, 1045 {"I093", NULL, "ETDM1 Capture"}, 1046 {"I094", NULL, "ETDM1 Capture"}, 1047 {"I095", NULL, "ETDM1 Capture"}, 1048 1049 {"UL8", NULL, "ETDM1 Capture"}, 1050 {"UL3", NULL, "ETDM2 Capture"}, 1051 1052 {"ETDM2 Playback", NULL, "O048"}, 1053 {"ETDM2 Playback", NULL, "O049"}, 1054 {"ETDM2 Playback", NULL, "O050"}, 1055 {"ETDM2 Playback", NULL, "O051"}, 1056 {"ETDM2 Playback", NULL, "O052"}, 1057 {"ETDM2 Playback", NULL, "O053"}, 1058 {"ETDM2 Playback", NULL, "O054"}, 1059 {"ETDM2 Playback", NULL, "O055"}, 1060 {"ETDM2 Playback", NULL, "O056"}, 1061 {"ETDM2 Playback", NULL, "O057"}, 1062 {"ETDM2 Playback", NULL, "O058"}, 1063 {"ETDM2 Playback", NULL, "O059"}, 1064 {"ETDM2 Playback", NULL, "O060"}, 1065 {"ETDM2 Playback", NULL, "O061"}, 1066 {"ETDM2 Playback", NULL, "O062"}, 1067 {"ETDM2 Playback", NULL, "O063"}, 1068 {"ETDM2 Playback", NULL, "O064"}, 1069 {"ETDM2 Playback", NULL, "O065"}, 1070 {"ETDM2 Playback", NULL, "O066"}, 1071 {"ETDM2 Playback", NULL, "O067"}, 1072 {"ETDM2 Playback", NULL, "O068"}, 1073 {"ETDM2 Playback", NULL, "O069"}, 1074 {"ETDM2 Playback", NULL, "O070"}, 1075 {"ETDM2 Playback", NULL, "O071"}, 1076 1077 {"ETDM1 Playback", NULL, "O072"}, 1078 {"ETDM1 Playback", NULL, "O073"}, 1079 {"ETDM1 Playback", NULL, "O074"}, 1080 {"ETDM1 Playback", NULL, "O075"}, 1081 {"ETDM1 Playback", NULL, "O076"}, 1082 {"ETDM1 Playback", NULL, "O077"}, 1083 {"ETDM1 Playback", NULL, "O078"}, 1084 {"ETDM1 Playback", NULL, "O079"}, 1085 {"ETDM1 Playback", NULL, "O080"}, 1086 {"ETDM1 Playback", NULL, "O081"}, 1087 {"ETDM1 Playback", NULL, "O082"}, 1088 {"ETDM1 Playback", NULL, "O083"}, 1089 {"ETDM1 Playback", NULL, "O084"}, 1090 {"ETDM1 Playback", NULL, "O085"}, 1091 {"ETDM1 Playback", NULL, "O086"}, 1092 {"ETDM1 Playback", NULL, "O087"}, 1093 {"ETDM1 Playback", NULL, "O088"}, 1094 {"ETDM1 Playback", NULL, "O089"}, 1095 {"ETDM1 Playback", NULL, "O090"}, 1096 {"ETDM1 Playback", NULL, "O091"}, 1097 {"ETDM1 Playback", NULL, "O092"}, 1098 {"ETDM1 Playback", NULL, "O093"}, 1099 {"ETDM1 Playback", NULL, "O094"}, 1100 {"ETDM1 Playback", NULL, "O095"}, 1101 1102 {"O048", "I020 Switch", "I020"}, 1103 {"O049", "I021 Switch", "I021"}, 1104 1105 {"O048", "I022 Switch", "I022"}, 1106 {"O049", "I023 Switch", "I023"}, 1107 {"O050", "I024 Switch", "I024"}, 1108 {"O051", "I025 Switch", "I025"}, 1109 {"O052", "I026 Switch", "I026"}, 1110 {"O053", "I027 Switch", "I027"}, 1111 {"O054", "I028 Switch", "I028"}, 1112 {"O055", "I029 Switch", "I029"}, 1113 {"O056", "I030 Switch", "I030"}, 1114 {"O057", "I031 Switch", "I031"}, 1115 {"O058", "I032 Switch", "I032"}, 1116 {"O059", "I033 Switch", "I033"}, 1117 {"O060", "I034 Switch", "I034"}, 1118 {"O061", "I035 Switch", "I035"}, 1119 {"O062", "I036 Switch", "I036"}, 1120 {"O063", "I037 Switch", "I037"}, 1121 {"O064", "I038 Switch", "I038"}, 1122 {"O065", "I039 Switch", "I039"}, 1123 {"O066", "I040 Switch", "I040"}, 1124 {"O067", "I041 Switch", "I041"}, 1125 {"O068", "I042 Switch", "I042"}, 1126 {"O069", "I043 Switch", "I043"}, 1127 {"O070", "I044 Switch", "I044"}, 1128 {"O071", "I045 Switch", "I045"}, 1129 1130 {"O048", "I046 Switch", "I046"}, 1131 {"O049", "I047 Switch", "I047"}, 1132 {"O050", "I048 Switch", "I048"}, 1133 {"O051", "I049 Switch", "I049"}, 1134 {"O052", "I050 Switch", "I050"}, 1135 {"O053", "I051 Switch", "I051"}, 1136 {"O054", "I052 Switch", "I052"}, 1137 {"O055", "I053 Switch", "I053"}, 1138 {"O056", "I054 Switch", "I054"}, 1139 {"O057", "I055 Switch", "I055"}, 1140 {"O058", "I056 Switch", "I056"}, 1141 {"O059", "I057 Switch", "I057"}, 1142 {"O060", "I058 Switch", "I058"}, 1143 {"O061", "I059 Switch", "I059"}, 1144 {"O062", "I060 Switch", "I060"}, 1145 {"O063", "I061 Switch", "I061"}, 1146 {"O064", "I062 Switch", "I062"}, 1147 {"O065", "I063 Switch", "I063"}, 1148 {"O066", "I064 Switch", "I064"}, 1149 {"O067", "I065 Switch", "I065"}, 1150 {"O068", "I066 Switch", "I066"}, 1151 {"O069", "I067 Switch", "I067"}, 1152 {"O070", "I068 Switch", "I068"}, 1153 {"O071", "I069 Switch", "I069"}, 1154 1155 {"O048", "I070 Switch", "I070"}, 1156 {"O049", "I071 Switch", "I071"}, 1157 1158 {"O072", "I020 Switch", "I020"}, 1159 {"O073", "I021 Switch", "I021"}, 1160 1161 {"O072", "I022 Switch", "I022"}, 1162 {"O073", "I023 Switch", "I023"}, 1163 {"O074", "I024 Switch", "I024"}, 1164 {"O075", "I025 Switch", "I025"}, 1165 {"O076", "I026 Switch", "I026"}, 1166 {"O077", "I027 Switch", "I027"}, 1167 {"O078", "I028 Switch", "I028"}, 1168 {"O079", "I029 Switch", "I029"}, 1169 {"O080", "I030 Switch", "I030"}, 1170 {"O081", "I031 Switch", "I031"}, 1171 {"O082", "I032 Switch", "I032"}, 1172 {"O083", "I033 Switch", "I033"}, 1173 {"O084", "I034 Switch", "I034"}, 1174 {"O085", "I035 Switch", "I035"}, 1175 {"O086", "I036 Switch", "I036"}, 1176 {"O087", "I037 Switch", "I037"}, 1177 {"O088", "I038 Switch", "I038"}, 1178 {"O089", "I039 Switch", "I039"}, 1179 {"O090", "I040 Switch", "I040"}, 1180 {"O091", "I041 Switch", "I041"}, 1181 {"O092", "I042 Switch", "I042"}, 1182 {"O093", "I043 Switch", "I043"}, 1183 {"O094", "I044 Switch", "I044"}, 1184 {"O095", "I045 Switch", "I045"}, 1185 1186 {"O072", "I046 Switch", "I046"}, 1187 {"O073", "I047 Switch", "I047"}, 1188 {"O074", "I048 Switch", "I048"}, 1189 {"O075", "I049 Switch", "I049"}, 1190 {"O076", "I050 Switch", "I050"}, 1191 {"O077", "I051 Switch", "I051"}, 1192 {"O078", "I052 Switch", "I052"}, 1193 {"O079", "I053 Switch", "I053"}, 1194 {"O080", "I054 Switch", "I054"}, 1195 {"O081", "I055 Switch", "I055"}, 1196 {"O082", "I056 Switch", "I056"}, 1197 {"O083", "I057 Switch", "I057"}, 1198 {"O084", "I058 Switch", "I058"}, 1199 {"O085", "I059 Switch", "I059"}, 1200 {"O086", "I060 Switch", "I060"}, 1201 {"O087", "I061 Switch", "I061"}, 1202 {"O088", "I062 Switch", "I062"}, 1203 {"O089", "I063 Switch", "I063"}, 1204 {"O090", "I064 Switch", "I064"}, 1205 {"O091", "I065 Switch", "I065"}, 1206 {"O092", "I066 Switch", "I066"}, 1207 {"O093", "I067 Switch", "I067"}, 1208 {"O094", "I068 Switch", "I068"}, 1209 {"O095", "I069 Switch", "I069"}, 1210 1211 {"O072", "I070 Switch", "I070"}, 1212 {"O073", "I071 Switch", "I071"}, 1213 1214 {"HDMI_CH0_MUX", "CH0", "DL10"}, 1215 {"HDMI_CH0_MUX", "CH1", "DL10"}, 1216 {"HDMI_CH0_MUX", "CH2", "DL10"}, 1217 {"HDMI_CH0_MUX", "CH3", "DL10"}, 1218 {"HDMI_CH0_MUX", "CH4", "DL10"}, 1219 {"HDMI_CH0_MUX", "CH5", "DL10"}, 1220 {"HDMI_CH0_MUX", "CH6", "DL10"}, 1221 {"HDMI_CH0_MUX", "CH7", "DL10"}, 1222 1223 {"HDMI_CH1_MUX", "CH0", "DL10"}, 1224 {"HDMI_CH1_MUX", "CH1", "DL10"}, 1225 {"HDMI_CH1_MUX", "CH2", "DL10"}, 1226 {"HDMI_CH1_MUX", "CH3", "DL10"}, 1227 {"HDMI_CH1_MUX", "CH4", "DL10"}, 1228 {"HDMI_CH1_MUX", "CH5", "DL10"}, 1229 {"HDMI_CH1_MUX", "CH6", "DL10"}, 1230 {"HDMI_CH1_MUX", "CH7", "DL10"}, 1231 1232 {"HDMI_CH2_MUX", "CH0", "DL10"}, 1233 {"HDMI_CH2_MUX", "CH1", "DL10"}, 1234 {"HDMI_CH2_MUX", "CH2", "DL10"}, 1235 {"HDMI_CH2_MUX", "CH3", "DL10"}, 1236 {"HDMI_CH2_MUX", "CH4", "DL10"}, 1237 {"HDMI_CH2_MUX", "CH5", "DL10"}, 1238 {"HDMI_CH2_MUX", "CH6", "DL10"}, 1239 {"HDMI_CH2_MUX", "CH7", "DL10"}, 1240 1241 {"HDMI_CH3_MUX", "CH0", "DL10"}, 1242 {"HDMI_CH3_MUX", "CH1", "DL10"}, 1243 {"HDMI_CH3_MUX", "CH2", "DL10"}, 1244 {"HDMI_CH3_MUX", "CH3", "DL10"}, 1245 {"HDMI_CH3_MUX", "CH4", "DL10"}, 1246 {"HDMI_CH3_MUX", "CH5", "DL10"}, 1247 {"HDMI_CH3_MUX", "CH6", "DL10"}, 1248 {"HDMI_CH3_MUX", "CH7", "DL10"}, 1249 1250 {"HDMI_CH4_MUX", "CH0", "DL10"}, 1251 {"HDMI_CH4_MUX", "CH1", "DL10"}, 1252 {"HDMI_CH4_MUX", "CH2", "DL10"}, 1253 {"HDMI_CH4_MUX", "CH3", "DL10"}, 1254 {"HDMI_CH4_MUX", "CH4", "DL10"}, 1255 {"HDMI_CH4_MUX", "CH5", "DL10"}, 1256 {"HDMI_CH4_MUX", "CH6", "DL10"}, 1257 {"HDMI_CH4_MUX", "CH7", "DL10"}, 1258 1259 {"HDMI_CH5_MUX", "CH0", "DL10"}, 1260 {"HDMI_CH5_MUX", "CH1", "DL10"}, 1261 {"HDMI_CH5_MUX", "CH2", "DL10"}, 1262 {"HDMI_CH5_MUX", "CH3", "DL10"}, 1263 {"HDMI_CH5_MUX", "CH4", "DL10"}, 1264 {"HDMI_CH5_MUX", "CH5", "DL10"}, 1265 {"HDMI_CH5_MUX", "CH6", "DL10"}, 1266 {"HDMI_CH5_MUX", "CH7", "DL10"}, 1267 1268 {"HDMI_CH6_MUX", "CH0", "DL10"}, 1269 {"HDMI_CH6_MUX", "CH1", "DL10"}, 1270 {"HDMI_CH6_MUX", "CH2", "DL10"}, 1271 {"HDMI_CH6_MUX", "CH3", "DL10"}, 1272 {"HDMI_CH6_MUX", "CH4", "DL10"}, 1273 {"HDMI_CH6_MUX", "CH5", "DL10"}, 1274 {"HDMI_CH6_MUX", "CH6", "DL10"}, 1275 {"HDMI_CH6_MUX", "CH7", "DL10"}, 1276 1277 {"HDMI_CH7_MUX", "CH0", "DL10"}, 1278 {"HDMI_CH7_MUX", "CH1", "DL10"}, 1279 {"HDMI_CH7_MUX", "CH2", "DL10"}, 1280 {"HDMI_CH7_MUX", "CH3", "DL10"}, 1281 {"HDMI_CH7_MUX", "CH4", "DL10"}, 1282 {"HDMI_CH7_MUX", "CH5", "DL10"}, 1283 {"HDMI_CH7_MUX", "CH6", "DL10"}, 1284 {"HDMI_CH7_MUX", "CH7", "DL10"}, 1285 1286 {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1287 {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1288 {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1289 {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1290 {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1291 {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1292 {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1293 {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1294 1295 {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1296 {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1297 {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1298 {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1299 {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1300 {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1301 {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1302 {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1303 1304 {"ETDM3 Playback", NULL, "HDMI_OUT_MUX"}, 1305 {"DPTX Playback", NULL, "DPTX_OUT_MUX"}, 1306 1307 {"ETDM_OUTPUT", NULL, "DPTX Playback"}, 1308 {"ETDM_OUTPUT", NULL, "ETDM1 Playback"}, 1309 {"ETDM_OUTPUT", NULL, "ETDM2 Playback"}, 1310 {"ETDM_OUTPUT", NULL, "ETDM3 Playback"}, 1311 {"ETDM1 Capture", NULL, "ETDM_INPUT"}, 1312 {"ETDM2 Capture", NULL, "ETDM_INPUT"}, 1313 }; 1314 1315 static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1316 { 1317 int ret = 0; 1318 struct etdm_con_reg etdm_reg; 1319 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1320 struct mtk_dai_etdm_priv *etdm_data; 1321 1322 if (!mt8195_afe_etdm_is_valid(dai_id)) 1323 return -EINVAL; 1324 1325 etdm_data = afe_priv->dai_priv[dai_id]; 1326 guard(spinlock_irqsave)(&afe_priv->afe_ctrl_lock); 1327 etdm_data->en_ref_cnt++; 1328 if (etdm_data->en_ref_cnt == 1) { 1329 ret = get_etdm_reg(dai_id, &etdm_reg); 1330 if (ret < 0) 1331 return ret; 1332 1333 regmap_update_bits(afe->regmap, etdm_reg.con0, 1334 ETDM_CON0_EN, ETDM_CON0_EN); 1335 } 1336 1337 return ret; 1338 } 1339 1340 static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1341 { 1342 int ret = 0; 1343 struct etdm_con_reg etdm_reg; 1344 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1345 struct mtk_dai_etdm_priv *etdm_data; 1346 1347 if (!mt8195_afe_etdm_is_valid(dai_id)) 1348 return -EINVAL; 1349 1350 etdm_data = afe_priv->dai_priv[dai_id]; 1351 guard(spinlock_irqsave)(&afe_priv->afe_ctrl_lock); 1352 if (etdm_data->en_ref_cnt > 0) { 1353 etdm_data->en_ref_cnt--; 1354 if (etdm_data->en_ref_cnt == 0) { 1355 ret = get_etdm_reg(dai_id, &etdm_reg); 1356 if (ret < 0) 1357 return ret; 1358 1359 regmap_update_bits(afe->regmap, etdm_reg.con0, 1360 ETDM_CON0_EN, 0); 1361 } 1362 } 1363 1364 return ret; 1365 } 1366 1367 static int etdm_cowork_slv_sel(int id, int slave_mode) 1368 { 1369 if (slave_mode) { 1370 switch (id) { 1371 case MT8195_AFE_IO_ETDM1_IN: 1372 return COWORK_ETDM_IN1_S; 1373 case MT8195_AFE_IO_ETDM2_IN: 1374 return COWORK_ETDM_IN2_S; 1375 case MT8195_AFE_IO_ETDM1_OUT: 1376 return COWORK_ETDM_OUT1_S; 1377 case MT8195_AFE_IO_ETDM2_OUT: 1378 return COWORK_ETDM_OUT2_S; 1379 case MT8195_AFE_IO_ETDM3_OUT: 1380 return COWORK_ETDM_OUT3_S; 1381 default: 1382 return -EINVAL; 1383 } 1384 } else { 1385 switch (id) { 1386 case MT8195_AFE_IO_ETDM1_IN: 1387 return COWORK_ETDM_IN1_M; 1388 case MT8195_AFE_IO_ETDM2_IN: 1389 return COWORK_ETDM_IN2_M; 1390 case MT8195_AFE_IO_ETDM1_OUT: 1391 return COWORK_ETDM_OUT1_M; 1392 case MT8195_AFE_IO_ETDM2_OUT: 1393 return COWORK_ETDM_OUT2_M; 1394 case MT8195_AFE_IO_ETDM3_OUT: 1395 return COWORK_ETDM_OUT3_M; 1396 default: 1397 return -EINVAL; 1398 } 1399 } 1400 } 1401 1402 static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1403 { 1404 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1405 struct mtk_dai_etdm_priv *etdm_data; 1406 unsigned int reg = 0; 1407 unsigned int mask; 1408 unsigned int val; 1409 int cowork_source_sel; 1410 1411 if (!mt8195_afe_etdm_is_valid(dai_id)) 1412 return -EINVAL; 1413 1414 etdm_data = afe_priv->dai_priv[dai_id]; 1415 if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1416 return 0; 1417 1418 cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1419 etdm_data->slave_mode); 1420 if (cowork_source_sel < 0) 1421 return cowork_source_sel; 1422 1423 switch (dai_id) { 1424 case MT8195_AFE_IO_ETDM1_IN: 1425 reg = ETDM_COWORK_CON1; 1426 mask = ETDM_IN1_SLAVE_SEL_MASK; 1427 val = ETDM_IN1_SLAVE_SEL(cowork_source_sel); 1428 break; 1429 case MT8195_AFE_IO_ETDM2_IN: 1430 reg = ETDM_COWORK_CON2; 1431 mask = ETDM_IN2_SLAVE_SEL_MASK; 1432 val = ETDM_IN2_SLAVE_SEL(cowork_source_sel); 1433 break; 1434 case MT8195_AFE_IO_ETDM1_OUT: 1435 reg = ETDM_COWORK_CON0; 1436 mask = ETDM_OUT1_SLAVE_SEL_MASK; 1437 val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel); 1438 break; 1439 case MT8195_AFE_IO_ETDM2_OUT: 1440 reg = ETDM_COWORK_CON2; 1441 mask = ETDM_OUT2_SLAVE_SEL_MASK; 1442 val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel); 1443 break; 1444 case MT8195_AFE_IO_ETDM3_OUT: 1445 reg = ETDM_COWORK_CON2; 1446 mask = ETDM_OUT3_SLAVE_SEL_MASK; 1447 val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel); 1448 break; 1449 default: 1450 return 0; 1451 } 1452 1453 regmap_update_bits(afe->regmap, reg, mask, val); 1454 1455 return 0; 1456 } 1457 1458 static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 1459 { 1460 int cg_id = -1; 1461 1462 switch (dai_id) { 1463 case MT8195_AFE_IO_DPTX: 1464 cg_id = MT8195_CLK_AUD_HDMI_OUT; 1465 break; 1466 case MT8195_AFE_IO_ETDM1_IN: 1467 cg_id = MT8195_CLK_AUD_TDM_IN; 1468 break; 1469 case MT8195_AFE_IO_ETDM2_IN: 1470 cg_id = MT8195_CLK_AUD_I2SIN; 1471 break; 1472 case MT8195_AFE_IO_ETDM1_OUT: 1473 cg_id = MT8195_CLK_AUD_TDM_OUT; 1474 break; 1475 case MT8195_AFE_IO_ETDM2_OUT: 1476 cg_id = MT8195_CLK_AUD_I2S_OUT; 1477 break; 1478 case MT8195_AFE_IO_ETDM3_OUT: 1479 cg_id = MT8195_CLK_AUD_HDMI_OUT; 1480 break; 1481 default: 1482 break; 1483 } 1484 1485 return cg_id; 1486 } 1487 1488 static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 1489 { 1490 int clk_id = -1; 1491 1492 switch (dai_id) { 1493 case MT8195_AFE_IO_DPTX: 1494 clk_id = MT8195_CLK_TOP_DPTX_M_SEL; 1495 break; 1496 case MT8195_AFE_IO_ETDM1_IN: 1497 clk_id = MT8195_CLK_TOP_I2SI1_M_SEL; 1498 break; 1499 case MT8195_AFE_IO_ETDM2_IN: 1500 clk_id = MT8195_CLK_TOP_I2SI2_M_SEL; 1501 break; 1502 case MT8195_AFE_IO_ETDM1_OUT: 1503 clk_id = MT8195_CLK_TOP_I2SO1_M_SEL; 1504 break; 1505 case MT8195_AFE_IO_ETDM2_OUT: 1506 clk_id = MT8195_CLK_TOP_I2SO2_M_SEL; 1507 break; 1508 case MT8195_AFE_IO_ETDM3_OUT: 1509 default: 1510 break; 1511 } 1512 1513 return clk_id; 1514 } 1515 1516 static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 1517 { 1518 int clk_id = -1; 1519 1520 switch (dai_id) { 1521 case MT8195_AFE_IO_DPTX: 1522 clk_id = MT8195_CLK_TOP_APLL12_DIV9; 1523 break; 1524 case MT8195_AFE_IO_ETDM1_IN: 1525 clk_id = MT8195_CLK_TOP_APLL12_DIV0; 1526 break; 1527 case MT8195_AFE_IO_ETDM2_IN: 1528 clk_id = MT8195_CLK_TOP_APLL12_DIV1; 1529 break; 1530 case MT8195_AFE_IO_ETDM1_OUT: 1531 clk_id = MT8195_CLK_TOP_APLL12_DIV2; 1532 break; 1533 case MT8195_AFE_IO_ETDM2_OUT: 1534 clk_id = MT8195_CLK_TOP_APLL12_DIV3; 1535 break; 1536 case MT8195_AFE_IO_ETDM3_OUT: 1537 default: 1538 break; 1539 } 1540 1541 return clk_id; 1542 } 1543 1544 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 1545 { 1546 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1547 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1548 1549 if (clkdiv_id < 0) 1550 return -EINVAL; 1551 1552 mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 1553 1554 return 0; 1555 } 1556 1557 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 1558 { 1559 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1560 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1561 1562 if (clkdiv_id < 0) 1563 return -EINVAL; 1564 1565 mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 1566 1567 return 0; 1568 } 1569 1570 /* dai ops */ 1571 static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1572 struct snd_soc_dai *dai) 1573 { 1574 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1575 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1576 struct mtk_dai_etdm_priv *mst_etdm_data; 1577 int cg_id; 1578 int mst_dai_id; 1579 int slv_dai_id; 1580 int i; 1581 1582 if (is_cowork_mode(dai)) { 1583 mst_dai_id = get_etdm_cowork_master_id(dai); 1584 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 1585 return -EINVAL; 1586 1587 mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1588 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1589 if (cg_id >= 0) 1590 mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1591 1592 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1593 1594 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1595 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1596 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1597 if (cg_id >= 0) 1598 mt8195_afe_enable_clk(afe, 1599 afe_priv->clk[cg_id]); 1600 } 1601 } else { 1602 mtk_dai_etdm_enable_mclk(afe, dai->id); 1603 1604 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1605 if (cg_id >= 0) 1606 mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1607 } 1608 1609 return 0; 1610 } 1611 1612 static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1613 struct snd_soc_dai *dai) 1614 { 1615 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1616 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1617 struct mtk_dai_etdm_priv *mst_etdm_data; 1618 int cg_id; 1619 int mst_dai_id; 1620 int slv_dai_id; 1621 int i; 1622 1623 if (is_cowork_mode(dai)) { 1624 mst_dai_id = get_etdm_cowork_master_id(dai); 1625 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 1626 return; 1627 1628 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1629 if (cg_id >= 0) 1630 mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1631 1632 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1633 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1634 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1635 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1636 if (cg_id >= 0) 1637 mt8195_afe_disable_clk(afe, 1638 afe_priv->clk[cg_id]); 1639 } 1640 mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1641 } else { 1642 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1643 if (cg_id >= 0) 1644 mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1645 1646 mtk_dai_etdm_disable_mclk(afe, dai->id); 1647 } 1648 } 1649 1650 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1651 int dai_id, unsigned int rate) 1652 { 1653 unsigned int mode = 0; 1654 unsigned int reg = 0; 1655 unsigned int val = 0; 1656 unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1657 1658 if (rate != 0) 1659 mode = mt8195_afe_fs_timing(rate); 1660 1661 switch (dai_id) { 1662 case MT8195_AFE_IO_ETDM1_IN: 1663 reg = ETDM_IN1_AFIFO_CON; 1664 if (rate == 0) 1665 mode = MT8195_ETDM_IN1_1X_EN; 1666 break; 1667 case MT8195_AFE_IO_ETDM2_IN: 1668 reg = ETDM_IN2_AFIFO_CON; 1669 if (rate == 0) 1670 mode = MT8195_ETDM_IN2_1X_EN; 1671 break; 1672 default: 1673 return -EINVAL; 1674 } 1675 1676 val = (mode | ETDM_IN_USE_AFIFO); 1677 1678 regmap_update_bits(afe->regmap, reg, mask, val); 1679 return 0; 1680 } 1681 1682 static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1683 unsigned int rate, 1684 unsigned int channels, 1685 int dai_id) 1686 { 1687 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1688 struct mtk_dai_etdm_priv *etdm_data; 1689 struct etdm_con_reg etdm_reg; 1690 bool slave_mode; 1691 unsigned int data_mode; 1692 unsigned int lrck_width; 1693 unsigned int val = 0; 1694 unsigned int mask = 0; 1695 int i; 1696 int ret; 1697 1698 if (!mt8195_afe_etdm_is_valid(dai_id)) 1699 return -EINVAL; 1700 1701 etdm_data = afe_priv->dai_priv[dai_id]; 1702 slave_mode = etdm_data->slave_mode; 1703 data_mode = etdm_data->data_mode; 1704 lrck_width = etdm_data->lrck_width; 1705 1706 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1707 __func__, rate, channels, dai_id); 1708 1709 ret = get_etdm_reg(dai_id, &etdm_reg); 1710 if (ret < 0) 1711 return ret; 1712 1713 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1714 slave_mode = true; 1715 1716 /* afifo */ 1717 if (slave_mode) 1718 mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1719 else 1720 mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1721 1722 /* con1 */ 1723 if (lrck_width > 0) { 1724 mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1725 ETDM_IN_CON1_LRCK_WIDTH_MASK); 1726 val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width); 1727 } 1728 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1729 1730 mask = 0; 1731 val = 0; 1732 1733 /* con2 */ 1734 if (!slave_mode) { 1735 mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1736 if (rate == 352800 || rate == 384000) 1737 val |= ETDM_IN_CON2_UPDATE_GAP(4); 1738 else 1739 val |= ETDM_IN_CON2_UPDATE_GAP(3); 1740 } 1741 mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1742 ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1743 if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1744 val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1745 ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels); 1746 } 1747 regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1748 1749 mask = 0; 1750 val = 0; 1751 1752 /* con3 */ 1753 mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1754 for (i = 0; i < channels; i += 2) { 1755 if (etdm_data->in_disable_ch[i] && 1756 etdm_data->in_disable_ch[i + 1]) 1757 val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1758 } 1759 if (!slave_mode) { 1760 mask |= ETDM_IN_CON3_FS_MASK; 1761 val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate)); 1762 } 1763 regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1764 1765 mask = 0; 1766 val = 0; 1767 1768 /* con4 */ 1769 mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1770 ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1771 if (slave_mode) { 1772 if (etdm_data->lrck_inv) 1773 val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1774 if (etdm_data->bck_inv) 1775 val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1776 } else { 1777 if (etdm_data->lrck_inv) 1778 val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1779 if (etdm_data->bck_inv) 1780 val |= ETDM_IN_CON4_MASTER_BCK_INV; 1781 } 1782 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1783 1784 mask = 0; 1785 val = 0; 1786 1787 /* con5 */ 1788 mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1789 mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1790 for (i = 0; i < channels; i += 2) { 1791 if (etdm_data->in_disable_ch[i] && 1792 !etdm_data->in_disable_ch[i + 1]) { 1793 if (i == (channels - 2)) 1794 val |= ETDM_IN_CON5_LR_SWAP(15); 1795 else 1796 val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1797 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1798 } else if (!etdm_data->in_disable_ch[i] && 1799 etdm_data->in_disable_ch[i + 1]) { 1800 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1801 } 1802 } 1803 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1804 return 0; 1805 } 1806 1807 static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1808 unsigned int rate, 1809 unsigned int channels, 1810 int dai_id) 1811 { 1812 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1813 struct mtk_dai_etdm_priv *etdm_data; 1814 struct etdm_con_reg etdm_reg; 1815 bool slave_mode; 1816 unsigned int lrck_width; 1817 unsigned int val = 0; 1818 unsigned int mask = 0; 1819 int ret; 1820 int fs = 0; 1821 1822 if (!mt8195_afe_etdm_is_valid(dai_id)) 1823 return -EINVAL; 1824 1825 etdm_data = afe_priv->dai_priv[dai_id]; 1826 slave_mode = etdm_data->slave_mode; 1827 lrck_width = etdm_data->lrck_width; 1828 1829 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1830 __func__, rate, channels, dai_id); 1831 1832 ret = get_etdm_reg(dai_id, &etdm_reg); 1833 if (ret < 0) 1834 return ret; 1835 1836 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1837 slave_mode = true; 1838 1839 /* con0 */ 1840 mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1841 val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS); 1842 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1843 1844 mask = 0; 1845 val = 0; 1846 1847 /* con1 */ 1848 if (lrck_width > 0) { 1849 mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1850 ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1851 val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width); 1852 } 1853 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1854 1855 mask = 0; 1856 val = 0; 1857 1858 if (slave_mode) { 1859 /* con2 */ 1860 mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 1861 ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 1862 val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 1863 ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 1864 regmap_update_bits(afe->regmap, etdm_reg.con2, 1865 mask, val); 1866 mask = 0; 1867 val = 0; 1868 } else { 1869 /* con4 */ 1870 mask |= ETDM_OUT_CON4_FS_MASK; 1871 val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate)); 1872 } 1873 1874 mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1875 if (dai_id == MT8195_AFE_IO_ETDM1_OUT) 1876 fs = MT8195_ETDM_OUT1_1X_EN; 1877 else if (dai_id == MT8195_AFE_IO_ETDM2_OUT) 1878 fs = MT8195_ETDM_OUT2_1X_EN; 1879 1880 val |= ETDM_OUT_CON4_RELATCH_EN(fs); 1881 1882 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1883 1884 mask = 0; 1885 val = 0; 1886 1887 /* con5 */ 1888 mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1889 ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1890 if (slave_mode) { 1891 if (etdm_data->lrck_inv) 1892 val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1893 if (etdm_data->bck_inv) 1894 val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1895 } else { 1896 if (etdm_data->lrck_inv) 1897 val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1898 if (etdm_data->bck_inv) 1899 val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1900 } 1901 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1902 1903 return 0; 1904 } 1905 1906 static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 1907 { 1908 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1909 struct mtk_dai_etdm_priv *etdm_data; 1910 int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 1911 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1912 int apll; 1913 int apll_clk_id; 1914 struct etdm_con_reg etdm_reg; 1915 unsigned int val = 0; 1916 unsigned int mask = 0; 1917 int ret = 0; 1918 1919 if (clk_id < 0 || clkdiv_id < 0) 1920 return 0; 1921 1922 if (!mt8195_afe_etdm_is_valid(dai_id)) 1923 return -EINVAL; 1924 1925 etdm_data = afe_priv->dai_priv[dai_id]; 1926 ret = get_etdm_reg(dai_id, &etdm_reg); 1927 if (ret < 0) 1928 return ret; 1929 1930 mask |= ETDM_CON1_MCLK_OUTPUT; 1931 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1932 val |= ETDM_CON1_MCLK_OUTPUT; 1933 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1934 1935 if (etdm_data->mclk_freq) { 1936 apll = etdm_data->mclk_apll; 1937 apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 1938 if (apll_clk_id < 0) 1939 return apll_clk_id; 1940 1941 /* select apll */ 1942 ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 1943 afe_priv->clk[apll_clk_id]); 1944 if (ret) 1945 return ret; 1946 1947 /* set rate */ 1948 ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 1949 etdm_data->mclk_freq); 1950 } else { 1951 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1952 dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 1953 } 1954 return ret; 1955 } 1956 1957 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1958 unsigned int rate, 1959 unsigned int channels, 1960 unsigned int bit_width, 1961 int dai_id) 1962 { 1963 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1964 struct mtk_dai_etdm_priv *etdm_data; 1965 struct etdm_con_reg etdm_reg; 1966 bool slave_mode; 1967 unsigned int etdm_channels; 1968 unsigned int val = 0; 1969 unsigned int mask = 0; 1970 unsigned int bck; 1971 unsigned int wlen = get_etdm_wlen(bit_width); 1972 int ret; 1973 1974 if (!mt8195_afe_etdm_is_valid(dai_id)) 1975 return -EINVAL; 1976 1977 etdm_data = afe_priv->dai_priv[dai_id]; 1978 slave_mode = etdm_data->slave_mode; 1979 ret = get_etdm_reg(dai_id, &etdm_reg); 1980 if (ret < 0) 1981 return ret; 1982 1983 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1984 slave_mode = true; 1985 1986 dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1987 __func__, etdm_data->format, etdm_data->data_mode, 1988 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 1989 etdm_data->clock_mode, etdm_data->slave_mode); 1990 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 1991 __func__, rate, channels, bit_width, dai_id); 1992 1993 etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 1994 get_etdm_ch_fixup(channels) : 2; 1995 1996 bck = rate * etdm_channels * wlen; 1997 if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) { 1998 dev_info(afe->dev, "%s bck rate %u not support\n", 1999 __func__, bck); 2000 return -EINVAL; 2001 } 2002 2003 /* con0 */ 2004 mask |= ETDM_CON0_BIT_LEN_MASK; 2005 val |= ETDM_CON0_BIT_LEN(bit_width); 2006 mask |= ETDM_CON0_WORD_LEN_MASK; 2007 val |= ETDM_CON0_WORD_LEN(wlen); 2008 mask |= ETDM_CON0_FORMAT_MASK; 2009 val |= ETDM_CON0_FORMAT(etdm_data->format); 2010 mask |= ETDM_CON0_CH_NUM_MASK; 2011 val |= ETDM_CON0_CH_NUM(etdm_channels); 2012 2013 mask |= ETDM_CON0_SLAVE_MODE; 2014 if (slave_mode) { 2015 if (dai_id == MT8195_AFE_IO_ETDM1_OUT && 2016 etdm_data->cowork_source_id == COWORK_ETDM_NONE) { 2017 dev_info(afe->dev, "%s id %d only support master mode\n", 2018 __func__, dai_id); 2019 return -EINVAL; 2020 } 2021 val |= ETDM_CON0_SLAVE_MODE; 2022 } 2023 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 2024 2025 if (get_etdm_dir(dai_id) == ETDM_IN) 2026 mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 2027 else 2028 mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 2029 2030 return 0; 2031 } 2032 2033 static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 2034 struct snd_pcm_hw_params *params, 2035 struct snd_soc_dai *dai) 2036 { 2037 int ret = 0; 2038 unsigned int rate = params_rate(params); 2039 unsigned int bit_width = params_width(params); 2040 unsigned int channels = params_channels(params); 2041 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2042 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2043 struct mtk_dai_etdm_priv *mst_etdm_data; 2044 int mst_dai_id; 2045 int slv_dai_id; 2046 int i; 2047 2048 dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 2049 __func__, snd_pcm_stream_str(substream), 2050 params_period_size(params), params_periods(params)); 2051 2052 if (is_cowork_mode(dai)) { 2053 mst_dai_id = get_etdm_cowork_master_id(dai); 2054 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 2055 return -EINVAL; 2056 2057 ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 2058 if (ret) 2059 return ret; 2060 2061 ret = mtk_dai_etdm_configure(afe, rate, channels, 2062 bit_width, mst_dai_id); 2063 if (ret) 2064 return ret; 2065 2066 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2067 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2068 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2069 ret = mtk_dai_etdm_configure(afe, rate, channels, 2070 bit_width, slv_dai_id); 2071 if (ret) 2072 return ret; 2073 2074 ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id); 2075 if (ret) 2076 return ret; 2077 } 2078 } else { 2079 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2080 if (ret) 2081 return ret; 2082 2083 ret = mtk_dai_etdm_configure(afe, rate, channels, 2084 bit_width, dai->id); 2085 } 2086 2087 return ret; 2088 } 2089 2090 static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, 2091 struct snd_soc_dai *dai) 2092 { 2093 int ret = 0; 2094 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2095 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2096 struct mtk_dai_etdm_priv *mst_etdm_data; 2097 int mst_dai_id; 2098 int slv_dai_id; 2099 int i; 2100 2101 dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 2102 switch (cmd) { 2103 case SNDRV_PCM_TRIGGER_START: 2104 case SNDRV_PCM_TRIGGER_RESUME: 2105 if (is_cowork_mode(dai)) { 2106 mst_dai_id = get_etdm_cowork_master_id(dai); 2107 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 2108 return -EINVAL; 2109 2110 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2111 2112 //open master first 2113 ret |= mt8195_afe_enable_etdm(afe, mst_dai_id); 2114 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2115 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2116 ret |= mt8195_afe_enable_etdm(afe, slv_dai_id); 2117 } 2118 } else { 2119 ret = mt8195_afe_enable_etdm(afe, dai->id); 2120 } 2121 break; 2122 case SNDRV_PCM_TRIGGER_STOP: 2123 case SNDRV_PCM_TRIGGER_SUSPEND: 2124 if (is_cowork_mode(dai)) { 2125 mst_dai_id = get_etdm_cowork_master_id(dai); 2126 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) 2127 return -EINVAL; 2128 2129 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2130 2131 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2132 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2133 ret |= mt8195_afe_disable_etdm(afe, slv_dai_id); 2134 } 2135 // close master at last 2136 ret |= mt8195_afe_disable_etdm(afe, mst_dai_id); 2137 } else { 2138 ret = mt8195_afe_disable_etdm(afe, dai->id); 2139 } 2140 break; 2141 default: 2142 break; 2143 } 2144 return ret; 2145 } 2146 2147 static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2148 { 2149 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2150 struct mtk_dai_etdm_priv *etdm_data; 2151 int apll; 2152 int apll_rate; 2153 2154 if (!mt8195_afe_etdm_is_valid(dai_id)) 2155 return -EINVAL; 2156 2157 etdm_data = afe_priv->dai_priv[dai_id]; 2158 if (freq == 0) { 2159 etdm_data->mclk_freq = freq; 2160 return 0; 2161 } 2162 2163 apll = mt8195_afe_get_default_mclk_source_by_rate(freq); 2164 apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll); 2165 2166 if (freq > apll_rate) { 2167 dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2168 return -EINVAL; 2169 } 2170 2171 if (apll_rate % freq != 0) { 2172 dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2173 return -EINVAL; 2174 } 2175 2176 etdm_data->mclk_apll = apll; 2177 etdm_data->mclk_freq = freq; 2178 2179 return 0; 2180 } 2181 2182 static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2183 int clk_id, unsigned int freq, int dir) 2184 { 2185 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2186 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2187 struct mtk_dai_etdm_priv *etdm_data; 2188 int dai_id; 2189 2190 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2191 __func__, dai->id, freq, dir); 2192 if (is_cowork_mode(dai)) 2193 dai_id = get_etdm_cowork_master_id(dai); 2194 else 2195 dai_id = dai->id; 2196 2197 if (!mt8195_afe_etdm_is_valid(dai_id)) 2198 return -EINVAL; 2199 2200 etdm_data = afe_priv->dai_priv[dai_id]; 2201 etdm_data->mclk_dir = dir; 2202 return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2203 } 2204 2205 static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2206 unsigned int tx_mask, unsigned int rx_mask, 2207 int slots, int slot_width) 2208 { 2209 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2210 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2211 struct mtk_dai_etdm_priv *etdm_data; 2212 2213 if (!mt8195_afe_etdm_is_valid(dai->id)) 2214 return -EINVAL; 2215 2216 etdm_data = afe_priv->dai_priv[dai->id]; 2217 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2218 __func__, dai->id, slot_width); 2219 2220 etdm_data->slots = slots; 2221 etdm_data->lrck_width = slot_width; 2222 return 0; 2223 } 2224 2225 static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2226 { 2227 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2228 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2229 struct mtk_dai_etdm_priv *etdm_data; 2230 2231 if (!mt8195_afe_etdm_is_valid(dai->id)) 2232 return -EINVAL; 2233 2234 etdm_data = afe_priv->dai_priv[dai->id]; 2235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2236 case SND_SOC_DAIFMT_I2S: 2237 etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2238 break; 2239 case SND_SOC_DAIFMT_LEFT_J: 2240 etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2241 break; 2242 case SND_SOC_DAIFMT_RIGHT_J: 2243 etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2244 break; 2245 case SND_SOC_DAIFMT_DSP_A: 2246 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2247 break; 2248 case SND_SOC_DAIFMT_DSP_B: 2249 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2250 break; 2251 default: 2252 return -EINVAL; 2253 } 2254 2255 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2256 case SND_SOC_DAIFMT_NB_NF: 2257 etdm_data->bck_inv = false; 2258 etdm_data->lrck_inv = false; 2259 break; 2260 case SND_SOC_DAIFMT_NB_IF: 2261 etdm_data->bck_inv = false; 2262 etdm_data->lrck_inv = true; 2263 break; 2264 case SND_SOC_DAIFMT_IB_NF: 2265 etdm_data->bck_inv = true; 2266 etdm_data->lrck_inv = false; 2267 break; 2268 case SND_SOC_DAIFMT_IB_IF: 2269 etdm_data->bck_inv = true; 2270 etdm_data->lrck_inv = true; 2271 break; 2272 default: 2273 return -EINVAL; 2274 } 2275 2276 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2277 case SND_SOC_DAIFMT_BC_FC: 2278 etdm_data->slave_mode = true; 2279 break; 2280 case SND_SOC_DAIFMT_BP_FP: 2281 etdm_data->slave_mode = false; 2282 break; 2283 default: 2284 return -EINVAL; 2285 } 2286 2287 return 0; 2288 } 2289 2290 static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2291 struct snd_soc_dai *dai) 2292 { 2293 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2294 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2295 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2296 2297 if (cg_id >= 0) 2298 mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2299 2300 mtk_dai_etdm_enable_mclk(afe, dai->id); 2301 2302 return 0; 2303 } 2304 2305 static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2306 struct snd_soc_dai *dai) 2307 { 2308 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2309 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2310 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2311 2312 mtk_dai_etdm_disable_mclk(afe, dai->id); 2313 2314 if (cg_id >= 0) 2315 mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2316 } 2317 2318 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2319 { 2320 switch (channel) { 2321 case 1 ... 2: 2322 return AFE_DPTX_CON_CH_EN_2CH; 2323 case 3 ... 4: 2324 return AFE_DPTX_CON_CH_EN_4CH; 2325 case 5 ... 6: 2326 return AFE_DPTX_CON_CH_EN_6CH; 2327 case 7 ... 8: 2328 return AFE_DPTX_CON_CH_EN_8CH; 2329 default: 2330 return AFE_DPTX_CON_CH_EN_2CH; 2331 } 2332 } 2333 2334 static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2335 { 2336 return (ch > 2) ? 2337 AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2338 } 2339 2340 static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2341 { 2342 return snd_pcm_format_physical_width(format) <= 16 ? 2343 AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2344 } 2345 2346 static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2347 struct snd_pcm_hw_params *params, 2348 struct snd_soc_dai *dai) 2349 { 2350 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2351 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2352 struct mtk_dai_etdm_priv *etdm_data; 2353 unsigned int rate = params_rate(params); 2354 unsigned int channels = params_channels(params); 2355 snd_pcm_format_t format = params_format(params); 2356 int width = snd_pcm_format_physical_width(format); 2357 int ret = 0; 2358 2359 if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id)) 2360 return -EINVAL; 2361 2362 etdm_data = afe_priv->dai_priv[dai->id]; 2363 2364 /* dptx configure */ 2365 if (dai->id == MT8195_AFE_IO_DPTX) { 2366 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2367 AFE_DPTX_CON_CH_EN_MASK, 2368 mtk_dai_get_dptx_ch_en(channels)); 2369 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2370 AFE_DPTX_CON_CH_NUM_MASK, 2371 mtk_dai_get_dptx_ch(channels)); 2372 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2373 AFE_DPTX_CON_16BIT_MASK, 2374 mtk_dai_get_dptx_wlen(format)); 2375 2376 if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2377 etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2378 channels = 8; 2379 } else { 2380 channels = 2; 2381 } 2382 } else { 2383 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2384 } 2385 2386 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2387 if (ret) 2388 return ret; 2389 2390 ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2391 2392 return ret; 2393 } 2394 2395 static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream, 2396 int cmd, 2397 struct snd_soc_dai *dai) 2398 { 2399 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2400 int ret = 0; 2401 2402 dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 2403 2404 switch (cmd) { 2405 case SNDRV_PCM_TRIGGER_START: 2406 case SNDRV_PCM_TRIGGER_RESUME: 2407 /* enable dptx interface */ 2408 if (dai->id == MT8195_AFE_IO_DPTX) 2409 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2410 AFE_DPTX_CON_ON_MASK, 2411 AFE_DPTX_CON_ON); 2412 2413 /* enable etdm_out3 */ 2414 ret = mt8195_afe_enable_etdm(afe, dai->id); 2415 break; 2416 case SNDRV_PCM_TRIGGER_STOP: 2417 case SNDRV_PCM_TRIGGER_SUSPEND: 2418 /* disable etdm_out3 */ 2419 ret = mt8195_afe_disable_etdm(afe, dai->id); 2420 2421 /* disable dptx interface */ 2422 if (dai->id == MT8195_AFE_IO_DPTX) 2423 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2424 AFE_DPTX_CON_ON_MASK, 0); 2425 break; 2426 default: 2427 return -EINVAL; 2428 } 2429 2430 return ret; 2431 } 2432 2433 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2434 int clk_id, 2435 unsigned int freq, 2436 int dir) 2437 { 2438 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2439 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2440 struct mtk_dai_etdm_priv *etdm_data; 2441 2442 if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id)) 2443 return -EINVAL; 2444 2445 etdm_data = afe_priv->dai_priv[dai->id]; 2446 2447 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2448 __func__, dai->id, freq, dir); 2449 2450 etdm_data->mclk_dir = dir; 2451 return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2452 } 2453 2454 /* dai driver */ 2455 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000) 2456 2457 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2458 SNDRV_PCM_FMTBIT_S24_LE |\ 2459 SNDRV_PCM_FMTBIT_S32_LE) 2460 2461 static int mtk_dai_etdm_probe(struct snd_soc_dai *dai) 2462 { 2463 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2464 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2465 struct mtk_dai_etdm_priv *etdm_data; 2466 2467 dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id); 2468 2469 if (!mt8195_afe_etdm_is_valid(dai->id)) 2470 return -EINVAL; 2471 2472 etdm_data = afe_priv->dai_priv[dai->id]; 2473 if (etdm_data->mclk_freq) { 2474 dev_dbg(afe->dev, "MCLK always on, rate %d\n", 2475 etdm_data->mclk_freq); 2476 pm_runtime_get_sync(afe->dev); 2477 mtk_dai_etdm_mclk_configure(afe, dai->id); 2478 mtk_dai_etdm_enable_mclk(afe, dai->id); 2479 pm_runtime_put_sync(afe->dev); 2480 } 2481 return 0; 2482 } 2483 2484 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2485 .startup = mtk_dai_hdmitx_dptx_startup, 2486 .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2487 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2488 .trigger = mtk_dai_hdmitx_dptx_trigger, 2489 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2490 .set_fmt = mtk_dai_etdm_set_fmt, 2491 }; 2492 2493 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops2 = { 2494 .probe = mtk_dai_etdm_probe, 2495 .startup = mtk_dai_hdmitx_dptx_startup, 2496 .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2497 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2498 .trigger = mtk_dai_hdmitx_dptx_trigger, 2499 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2500 .set_fmt = mtk_dai_etdm_set_fmt, 2501 }; 2502 2503 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2504 .probe = mtk_dai_etdm_probe, 2505 .startup = mtk_dai_etdm_startup, 2506 .shutdown = mtk_dai_etdm_shutdown, 2507 .hw_params = mtk_dai_etdm_hw_params, 2508 .trigger = mtk_dai_etdm_trigger, 2509 .set_sysclk = mtk_dai_etdm_set_sysclk, 2510 .set_fmt = mtk_dai_etdm_set_fmt, 2511 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2512 }; 2513 2514 static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2515 { 2516 .name = "DPTX", 2517 .id = MT8195_AFE_IO_DPTX, 2518 .playback = { 2519 .stream_name = "DPTX Playback", 2520 .channels_min = 1, 2521 .channels_max = 8, 2522 .rates = MTK_ETDM_RATES, 2523 .formats = MTK_ETDM_FORMATS, 2524 }, 2525 .ops = &mtk_dai_hdmitx_dptx_ops, 2526 }, 2527 { 2528 .name = "ETDM1_IN", 2529 .id = MT8195_AFE_IO_ETDM1_IN, 2530 .capture = { 2531 .stream_name = "ETDM1 Capture", 2532 .channels_min = 1, 2533 .channels_max = 24, 2534 .rates = MTK_ETDM_RATES, 2535 .formats = MTK_ETDM_FORMATS, 2536 }, 2537 .ops = &mtk_dai_etdm_ops, 2538 }, 2539 { 2540 .name = "ETDM2_IN", 2541 .id = MT8195_AFE_IO_ETDM2_IN, 2542 .capture = { 2543 .stream_name = "ETDM2 Capture", 2544 .channels_min = 1, 2545 .channels_max = 16, 2546 .rates = MTK_ETDM_RATES, 2547 .formats = MTK_ETDM_FORMATS, 2548 }, 2549 .ops = &mtk_dai_etdm_ops, 2550 }, 2551 { 2552 .name = "ETDM1_OUT", 2553 .id = MT8195_AFE_IO_ETDM1_OUT, 2554 .playback = { 2555 .stream_name = "ETDM1 Playback", 2556 .channels_min = 1, 2557 .channels_max = 24, 2558 .rates = MTK_ETDM_RATES, 2559 .formats = MTK_ETDM_FORMATS, 2560 }, 2561 .ops = &mtk_dai_etdm_ops, 2562 }, 2563 { 2564 .name = "ETDM2_OUT", 2565 .id = MT8195_AFE_IO_ETDM2_OUT, 2566 .playback = { 2567 .stream_name = "ETDM2 Playback", 2568 .channels_min = 1, 2569 .channels_max = 24, 2570 .rates = MTK_ETDM_RATES, 2571 .formats = MTK_ETDM_FORMATS, 2572 }, 2573 .ops = &mtk_dai_etdm_ops, 2574 }, 2575 { 2576 .name = "ETDM3_OUT", 2577 .id = MT8195_AFE_IO_ETDM3_OUT, 2578 .playback = { 2579 .stream_name = "ETDM3 Playback", 2580 .channels_min = 1, 2581 .channels_max = 8, 2582 .rates = MTK_ETDM_RATES, 2583 .formats = MTK_ETDM_FORMATS, 2584 }, 2585 .ops = &mtk_dai_hdmitx_dptx_ops2, 2586 }, 2587 }; 2588 2589 static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe) 2590 { 2591 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2592 struct mtk_dai_etdm_priv *etdm_data; 2593 struct mtk_dai_etdm_priv *mst_data; 2594 int i; 2595 int mst_dai_id; 2596 2597 for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 2598 etdm_data = afe_priv->dai_priv[i]; 2599 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2600 mst_dai_id = etdm_data->cowork_source_id; 2601 if (!mt8195_afe_etdm_is_valid(mst_dai_id)) { 2602 dev_err(afe->dev, "%s invalid dai id %d\n", 2603 __func__, mst_dai_id); 2604 return; 2605 } 2606 mst_data = afe_priv->dai_priv[mst_dai_id]; 2607 if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2608 dev_info(afe->dev, "%s [%d] wrong sync source\n" 2609 , __func__, i); 2610 mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2611 mst_data->cowork_slv_count++; 2612 } 2613 } 2614 } 2615 2616 static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe) 2617 { 2618 const struct device_node *of_node = afe->dev->of_node; 2619 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2620 struct mtk_dai_etdm_priv *etdm_data; 2621 int i, j; 2622 char prop[48]; 2623 u8 disable_chn[MT8195_ETDM_MAX_CHANNELS]; 2624 int max_chn = MT8195_ETDM_MAX_CHANNELS; 2625 u32 sel; 2626 int ret; 2627 int dai_id; 2628 unsigned int sync_id; 2629 struct { 2630 const char *name; 2631 const unsigned int sync_id; 2632 } of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = { 2633 {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2634 {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2635 {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2636 {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2637 {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2638 }; 2639 2640 for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) { 2641 dai_id = ETDM_TO_DAI_ID(i); 2642 if (!mt8195_afe_etdm_is_valid(dai_id)) { 2643 dev_err(afe->dev, "%s invalid dai id %d\n", 2644 __func__, dai_id); 2645 return; 2646 } 2647 2648 etdm_data = afe_priv->dai_priv[dai_id]; 2649 2650 scnprintf(prop, sizeof(prop), 2651 "mediatek,%s-mclk-always-on-rate", 2652 of_afe_etdms[i].name); 2653 ret = of_property_read_u32(of_node, prop, &sel); 2654 if (ret == 0) { 2655 etdm_data->mclk_dir = SND_SOC_CLOCK_OUT; 2656 if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id)) 2657 dev_info(afe->dev, "%s unsupported mclk %uHz\n", 2658 __func__, sel); 2659 } 2660 2661 scnprintf(prop, sizeof(prop), 2662 "mediatek,%s-multi-pin-mode", 2663 of_afe_etdms[i].name); 2664 etdm_data->data_mode = of_property_read_bool(of_node, prop); 2665 2666 scnprintf(prop, sizeof(prop), 2667 "mediatek,%s-cowork-source", 2668 of_afe_etdms[i].name); 2669 ret = of_property_read_u32(of_node, prop, &sel); 2670 if (ret == 0) { 2671 if (sel >= MT8195_AFE_IO_ETDM_NUM) { 2672 dev_info(afe->dev, "%s invalid id=%d\n", 2673 __func__, sel); 2674 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2675 } else { 2676 sync_id = of_afe_etdms[sel].sync_id; 2677 etdm_data->cowork_source_id = 2678 sync_to_dai_id(sync_id); 2679 } 2680 } else { 2681 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2682 } 2683 } 2684 2685 /* etdm in only */ 2686 for (i = 0; i < 2; i++) { 2687 dai_id = ETDM_TO_DAI_ID(i); 2688 etdm_data = afe_priv->dai_priv[dai_id]; 2689 2690 scnprintf(prop, sizeof(prop), 2691 "mediatek,%s-chn-disabled", 2692 of_afe_etdms[i].name); 2693 ret = of_property_read_variable_u8_array(of_node, prop, 2694 disable_chn, 2695 1, max_chn); 2696 if (ret < 0) 2697 continue; 2698 2699 for (j = 0; j < ret; j++) { 2700 if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS) 2701 dev_info(afe->dev, "%s [%d] invalid chn %u\n", 2702 __func__, j, disable_chn[j]); 2703 else 2704 etdm_data->in_disable_ch[disable_chn[j]] = true; 2705 } 2706 } 2707 mt8195_etdm_update_sync_info(afe); 2708 } 2709 2710 static int init_etdm_priv_data(struct mtk_base_afe *afe) 2711 { 2712 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2713 struct mtk_dai_etdm_priv *etdm_priv; 2714 int i; 2715 2716 for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 2717 etdm_priv = devm_kzalloc(afe->dev, 2718 sizeof(struct mtk_dai_etdm_priv), 2719 GFP_KERNEL); 2720 if (!etdm_priv) 2721 return -ENOMEM; 2722 2723 afe_priv->dai_priv[i] = etdm_priv; 2724 } 2725 2726 afe_priv->dai_priv[MT8195_AFE_IO_DPTX] = 2727 afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT]; 2728 2729 mt8195_dai_etdm_parse_of(afe); 2730 return 0; 2731 } 2732 2733 int mt8195_dai_etdm_register(struct mtk_base_afe *afe) 2734 { 2735 struct mtk_base_afe_dai *dai; 2736 2737 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2738 if (!dai) 2739 return -ENOMEM; 2740 2741 list_add(&dai->list, &afe->sub_dais); 2742 2743 dai->dai_drivers = mtk_dai_etdm_driver; 2744 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2745 2746 dai->dapm_widgets = mtk_dai_etdm_widgets; 2747 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2748 dai->dapm_routes = mtk_dai_etdm_routes; 2749 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2750 dai->controls = mtk_dai_etdm_controls; 2751 dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2752 2753 return init_etdm_priv_data(afe); 2754 } 2755