1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2025 Mobileye Vision Technologies Ltd. 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H 7 #define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H 8 9 /* ACC0 and ACC1 OLBs PLL and dividers */ 10 #define EQ7HC_ACC_PLL_VMP 0 11 #define EQ7HC_ACC_PLL_MPC 1 12 #define EQ7HC_ACC_PLL_PMA 2 13 #define EQ7HC_ACC_PLL_NOC 3 14 #define EQ7HC_ACC_DIV_PMA 4 15 #define EQ7HC_ACC_DIV_NCORE 5 16 #define EQ7HC_ACC_DIV_CFG 6 17 18 /* DDR0 and DDR1 OLBs PLL and dividers */ 19 #define EQ7HC_DDR_PLL 0 20 #define EQ7HC_DDR_DIV_APB 1 21 #define EQ7HC_DDR_DIV_PLLREF 2 22 #define EQ7HC_DDR_DIV_DFI 3 23 24 /* east OLB PLL and dividers */ 25 #define EQ7HC_EAST_PLL_106P6 0 26 #define EQ7HC_EAST_DIV_REF_106P6 1 27 #define EQ7HC_EAST_PLL_NOC 2 28 #define EQ7HC_EAST_PLL_ISP 3 29 #define EQ7HC_EAST_PLL_VEU 4 30 #define EQ7HC_EAST_DIV_REF_DDR_PHY 5 31 #define EQ7HC_EAST_DIV_CORE 6 32 #define EQ7HC_EAST_DIV_CORE_MBIST 7 33 #define EQ7HC_EAST_DIV_ISRAM_MBIST 8 34 #define EQ7HC_EAST_DIV_CFG 9 35 #define EQ7HC_EAST_DIV_VEU_CORE 10 36 #define EQ7HC_EAST_DIV_VEU_MBIST 11 37 #define EQ7HC_EAST_DIV_VEU_OCP 12 38 #define EQ7HC_EAST_DIV_LBITS 13 39 #define EQ7HC_EAST_DIV_ISP0_CORE 14 40 41 /* MIPS0, MIPS1 and MIPS2 OLBs PLL and dividers */ 42 #define EQ7HC_MIPS_PLL_CPU 0 43 #define EQ7HC_MIPS_DIV_CM 1 44 45 /* periph east OLB PLL and dividers */ 46 #define EQ7HC_PERIPH_EAST_PLL_PER 0 47 #define EQ7HC_PERIPH_EAST_DIV_PER 1 48 49 /* periph west OLB PLL and dividers */ 50 #define EQ7HC_PERIPH_WEST_PLL_PER 0 51 #define EQ7HC_PERIPH_WEST_PLL_I2S 1 52 #define EQ7HC_PERIPH_WEST_DIV_PER 2 53 #define EQ7HC_PERIPH_WEST_DIV_I2S 3 54 55 /* south OLB PLL and dividers */ 56 #define EQ7HC_SOUTH_PLL_100P0 0 57 #define EQ7HC_SOUTH_DIV_REF_100P0 1 58 #define EQ7HC_SOUTH_PLL_XSPI 2 59 #define EQ7HC_SOUTH_PLL_VDIO 3 60 #define EQ7HC_SOUTH_PLL_PER 4 61 #define EQ7HC_SOUTH_DIV_VDO_DSI_SYS 5 62 #define EQ7HC_SOUTH_DIV_PMA_CMN_REF 6 63 #define EQ7HC_SOUTH_DIV_REF_UFS 7 64 #define EQ7HC_SOUTH_DIV_XSPI_SYS 8 65 #define EQ7HC_SOUTH_DIV_XSPI_MBIST 9 66 #define EQ7HC_SOUTH_DIV_NOC_S 10 67 #define EQ7HC_SOUTH_DIV_PCIE_SYS 11 68 #define EQ7HC_SOUTH_DIV_PCIE_SYS_MBIST 12 69 #define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY 13 70 #define EQ7HC_SOUTH_DIV_UFS_CORE 14 71 #define EQ7HC_SOUTH_DIV_UFS_SMS 15 72 #define EQ7HC_SOUTH_DIV_UFS_ROM_SMS 16 73 #define EQ7HC_SOUTH_DIV_ETH_SYS 17 74 #define EQ7HC_SOUTH_DIV_ETH_MBIST 18 75 #define EQ7HC_SOUTH_DIV_CFG_S 19 76 #define EQ7HC_SOUTH_DIV_TSU 20 77 #define EQ7HC_SOUTH_DIV_VDIO 21 78 #define EQ7HC_SOUTH_DIV_VDIO_CORE 22 79 #define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIST 23 80 #define EQ7HC_SOUTH_DIV_VDO_CORE_MBIST 24 81 #define EQ7HC_SOUTH_DIV_VDO_P 25 82 #define EQ7HC_SOUTH_DIV_VDIO_CFG 26 83 #define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC 27 84 85 /* west OLB PLL and dividers */ 86 #define EQ7HC_WEST_PLL_106P6 0 87 #define EQ7HC_WEST_DIV_REF_106P6 1 88 #define EQ7HC_WEST_PLL_NOC 2 89 #define EQ7HC_WEST_PLL_GPU 3 90 #define EQ7HC_WEST_PLL_SSI 4 91 #define EQ7HC_WEST_DIV_GPU 5 92 #define EQ7HC_WEST_DIV_GPU_MBIST 6 93 #define EQ7HC_WEST_DIV_LBITS 7 94 #define EQ7HC_WEST_DIV_MIPS_TIMER 8 95 #define EQ7HC_WEST_DIV_SSI_CORE 9 96 #define EQ7HC_WEST_DIV_SSI_CORE_MBIST 10 97 #define EQ7HC_WEST_DIV_SSI_ROM 11 98 #define EQ7HC_WEST_DIV_SSI_ROM_MBIST 12 99 #define EQ7HC_WEST_DIV_REF_DDR_PHY 13 100 #define EQ7HC_WEST_DIV_CORE 14 101 #define EQ7HC_WEST_DIV_CORE_MBIST 15 102 #define EQ7HC_WEST_DIV_CFG 16 103 #define EQ7HC_WEST_DIV_CAU 17 104 #define EQ7HC_WEST_DIV_CAU_MBIST 18 105 106 /* XNN0 and XNN1 OLBs PLL and dividers */ 107 #define EQ7HC_XNN_PLL_XNN0 0 108 #define EQ7HC_XNN_PLL_XNN1 1 109 #define EQ7HC_XNN_PLL_XNN2 2 110 #define EQ7HC_XNN_PLL_CLSTR 3 111 #define EQ7HC_XNN_DIV_XNN0 4 112 #define EQ7HC_XNN_DIV_XNN1 5 113 #define EQ7HC_XNN_DIV_XNN2 6 114 #define EQ7HC_XNN_DIV_CLSTR 7 115 #define EQ7HC_XNN_DIV_I2 8 116 #define EQ7HC_XNN_DIV_I2_SMS 9 117 #define EQ7HC_XNN_DIV_CFG 10 118 119 #endif 120