1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/bitops.h>
5
6 #define ENETC_MM_VERIFY_SLEEP_US USEC_PER_MSEC
7 #define ENETC_MM_VERIFY_RETRIES 3
8
9 #define ENETC_NUM_TC 8
10
11 /* ENETC device IDs */
12 #define ENETC_DEV_ID_PF 0xe100
13 #define ENETC_DEV_ID_VF 0xef00
14 #define ENETC_DEV_ID_PTP 0xee02
15
16 /* ENETC register block BAR */
17 #define ENETC_BAR_REGS 0
18
19 /** SI regs, offset: 0h */
20 #define ENETC_SIMR 0
21 #define ENETC_SIMR_EN BIT(31)
22 #define ENETC_SIMR_RSSE BIT(0)
23 #define ENETC_SICTR0 0x18
24 #define ENETC_SICTR1 0x1c
25 #define ENETC_SIPCAPR0 0x20
26 #define ENETC_SIPCAPR0_RSS BIT(8)
27 #define ENETC_SIPCAPR0_RFS BIT(2)
28 #define ENETC_SIPCAPR0_LSO BIT(1)
29 #define ENETC_SIPCAPR1 0x24
30 #define ENETC_SITGTGR 0x30
31 #define ENETC_SIRBGCR 0x38
32 /* cache attribute registers for transactions initiated by ENETC */
33 #define ENETC_SICAR0 0x40
34 #define ENETC_SICAR1 0x44
35 #define ENETC_SICAR2 0x48
36 /* rd snoop, no alloc
37 * wr snoop, no alloc, partial cache line update for BDs and full cache line
38 * update for data
39 */
40 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
41 #define ENETC_SICAR_WR_COHERENT 0x00006727
42 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
43
44 #define ENETC_SIPMAR0 0x80
45 #define ENETC_SIPMAR1 0x84
46 #define ENETC_SICVLANR1 0x90
47 #define ENETC_SICVLANR2 0x94
48 #define SICVLANR_ETYPE GENMASK(15, 0)
49
50 /* VF-PF Message passing */
51 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
52 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
enetc_vsi_set_msize(u32 size)53 static inline u32 enetc_vsi_set_msize(u32 size)
54 {
55 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
56 }
57
58 #define ENETC_PSIMSGRR 0x204
59 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
60 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
61
62 /* Message received mask, n is the active number of VSIs.
63 * It is available for ENETC_PSIMSGRR, ENETC_PSIIER, and
64 * ENETC_PSIIDR registers.
65 */
66 #define ENETC_PSIMR_MASK(n) \
67 ({ typeof(n) _n = (n); (_n) ? GENMASK((_n), 1) : 0; })
68
69 /* Message received bit, n is VSI index. It is available for
70 * ENETC_PSIMSGRR, ENETC_PSIIER, and ENETC_PSIIDR registers.
71 */
72 #define ENETC_PSIMR_BIT(n) BIT((n) + 1)
73
74 #define ENETC_VSIMSGSR 0x204 /* RO */
75 #define ENETC_VSIMSGSR_MB BIT(0)
76 #define ENETC_VSIMSGSR_MS BIT(1)
77 #define ENETC_VSIMSGSNDAR0 0x210
78 #define ENETC_VSIMSGSNDAR1 0x214
79
80 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
81 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
82
83 /* SI statistics */
84 #define ENETC_SIROCT 0x300
85 #define ENETC_SIRFRM 0x308
86 #define ENETC_SIRUCA 0x310
87 #define ENETC_SIRMCA 0x318
88 #define ENETC_SITOCT 0x320
89 #define ENETC_SITFRM 0x328
90 #define ENETC_SITUCA 0x330
91 #define ENETC_SITMCA 0x338
92 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
93
94 /* Control BDR regs */
95 #define ENETC_SICBDRMR 0x800
96 #define ENETC_SICBDRSR 0x804 /* RO */
97 #define ENETC_SICBDRBAR0 0x810
98 #define ENETC_SICBDRBAR1 0x814
99 #define ENETC_SICBDRPIR 0x818
100 #define ENETC_SICBDRCIR 0x81c
101 #define ENETC_SICBDRLENR 0x820
102
103 #define ENETC_SICAPR0 0x900
104 #define ENETC_SICAPR1 0x904
105
106 #define ENETC_PSIIER 0xa00
107 #define ENETC_PSIIDR 0xa08
108 #define ENETC_SITXIDR 0xa18
109 #define ENETC_SIRXIDR 0xa28
110 #define ENETC_SIMSIVR 0xa30
111
112 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
113 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
114
115 #define ENETC_SIUEFDCR 0xe28
116
117 #define ENETC_SIRFSCAPR 0x1200
118 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
119 #define ENETC_SIRSSCAPR 0x1600
120 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
121
122 /** SI BDR sub-blocks, n = 0..7 */
123 enum enetc_bdr_type {TX, RX};
124 #define ENETC_BDR_OFF(i) ((i) * 0x200)
125 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
126 /* RX BDR reg offsets */
127 #define ENETC_RBMR 0
128 #define ENETC_RBMR_BDS BIT(2)
129 #define ENETC_RBMR_CM BIT(4)
130 #define ENETC_RBMR_VTE BIT(5)
131 #define ENETC_RBMR_EN BIT(31)
132 #define ENETC_RBSR 0x4
133 #define ENETC_RBBSR 0x8
134 #define ENETC_RBCIR 0xc
135 #define ENETC_RBBAR0 0x10
136 #define ENETC_RBBAR1 0x14
137 #define ENETC_RBPIR 0x18
138 #define ENETC_RBLENR 0x20
139 #define ENETC_RBIER 0xa0
140 #define ENETC_RBIER_RXTIE BIT(0)
141 #define ENETC_RBIDR 0xa4
142 #define ENETC_RBICR0 0xa8
143 #define ENETC_RBICR0_ICEN BIT(31)
144 #define ENETC_RBICR0_ICPT_MASK 0x1ff
145 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK)
146 #define ENETC_RBICR1 0xac
147
148 /* TX BDR reg offsets */
149 #define ENETC_TBMR 0
150 #define ENETC_TBSR_BUSY BIT(0)
151 #define ENETC_TBMR_VIH BIT(9)
152 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
153 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
154 #define ENETC_TBMR_EN BIT(31)
155 #define ENETC_TBSR 0x4
156 #define ENETC_TBBAR0 0x10
157 #define ENETC_TBBAR1 0x14
158 #define ENETC_TBPIR 0x18
159 #define ENETC_TBCIR 0x1c
160 #define ENETC_TBCIR_IDX_MASK 0xffff
161 #define ENETC_TBLENR 0x20
162 #define ENETC_TBIER 0xa0
163 #define ENETC_TBIER_TXTIE BIT(0)
164 #define ENETC_TBIDR 0xa4
165 #define ENETC_TBICR0 0xa8
166 #define ENETC_TBICR0_ICEN BIT(31)
167 #define ENETC_TBICR0_ICPT_MASK 0xf
168 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK)
169 #define ENETC_TBICR1 0xac
170
171 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
172
173 /* Port regs, offset: 1_0000h */
174 #define ENETC_PORT_BASE 0x10000
175 #define ENETC_PMR 0x0000
176 #define ENETC_PMR_EN GENMASK(18, 16)
177 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
178 #define ENETC_PMR_PSPEED_10M 0
179 #define ENETC_PMR_PSPEED_100M BIT(8)
180 #define ENETC_PMR_PSPEED_1000M BIT(9)
181 #define ENETC_PMR_PSPEED_2500M BIT(10)
182 #define ENETC_PSR 0x0004 /* RO */
183 #define ENETC_PSIPMR 0x0018
184 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
185 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
186 #define ENETC_PSIPVMR 0x001c
187 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
188 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
189 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
190 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
191 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
192 #define ENETC_PVCLCTR 0x0208
193 #define ENETC_PCVLANR1 0x0210
194 #define ENETC_PCVLANR2 0x0214
195 #define ENETC_VLAN_TYPE_C BIT(0)
196 #define ENETC_VLAN_TYPE_S BIT(1)
197 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
198 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
199 #define ENETC_PSIVLAN_EN BIT(31)
200 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12)
201 #define ENETC_PPAUONTR 0x0410
202 #define ENETC_PPAUOFFTR 0x0414
203 #define ENETC_PTXMBAR 0x0608
204 #define ENETC_PCAPR0 0x0900
205 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
206 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
207 #define ENETC_PCAPR0_PSFP BIT(9)
208 #define ENETC_PCAPR0_QBV BIT(4)
209 #define ENETC_PCAPR0_QBU BIT(3)
210 #define ENETC_PCAPR1 0x0904
211 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
212 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
213 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
214 #define ENETC_PSICFGR0_VTE BIT(12)
215 #define ENETC_PSICFGR0_SIVIE BIT(14)
216 #define ENETC_PSICFGR0_ASE BIT(15)
217 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
218
219 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
220 #define ENETC_CBSE BIT(31)
221 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
222 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
223 #define ENETC_RSSHASH_KEY_SIZE 40
224 #define ENETC_PRSSCAPR 0x1404
225 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
226 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
227 #define ENETC_PSIVLANFMR 0x1700
228 #define ENETC_PSIVLANFMR_VS BIT(0)
229 #define ENETC_PRFSMR 0x1800
230 #define ENETC_PRFSMR_RFSE BIT(31)
231 #define ENETC_PRFSCAPR 0x1804
232 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
233 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
234 #define ENETC_PFPMR 0x1900
235 #define ENETC_PFPMR_PMACE BIT(1)
236 #define ENETC_EMDIO_BASE 0x1c00
237 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
238 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
239 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
240 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
241 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
242 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
243 #define ENETC_MMCSR 0x1f00
244 #define ENETC_MMCSR_LINK_FAIL BIT(31)
245 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */
246 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK)
247 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23)
248 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */
249 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21)
250 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */
251 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18)
252 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */
253 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */
254 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */
255 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK)
256 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8)
257 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */
258 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3)
259 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */
260 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */
261 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */
262 #define ENETC_MMFAECR 0x1f08
263 #define ENETC_MMFSECR 0x1f0c
264 #define ENETC_MMFAOCR 0x1f10
265 #define ENETC_MMFCRXR 0x1f14
266 #define ENETC_MMFCTXR 0x1f18
267 #define ENETC_MMHCR 0x1f1c
268 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
269
270 #define ENETC_PMAC_OFFSET 0x1000
271
272 #define ENETC_PM0_CMD_CFG 0x8008
273 #define ENETC_PM0_TX_EN BIT(0)
274 #define ENETC_PM0_RX_EN BIT(1)
275 #define ENETC_PM0_PROMISC BIT(4)
276 #define ENETC_PM0_PAUSE_IGN BIT(8)
277 #define ENETC_PM0_CMD_XGLP BIT(10)
278 #define ENETC_PM0_CMD_TXP BIT(11)
279 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
280 #define ENETC_PM0_CMD_SFD BIT(21)
281 #define ENETC_PM0_MAXFRM 0x8014
282 #define ENETC_SET_TX_MTU(val) ((val) << 16)
283 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
284 #define ENETC_PM0_RX_FIFO 0x801c
285 #define ENETC_PM0_RX_FIFO_VAL 1
286
287 #define ENETC_PM_IMDIO_BASE 0x8030
288
289 #define ENETC_PM0_PAUSE_QUANTA 0x8054
290 #define ENETC_PM0_PAUSE_THRESH 0x8064
291
292 #define ENETC_PM0_SINGLE_STEP 0x80c0
293 #define ENETC_PM0_SINGLE_STEP_CH BIT(7)
294 #define ENETC_PM0_SINGLE_STEP_EN BIT(31)
295 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
296
297 #define ENETC_PM0_IF_MODE 0x8300
298 #define ENETC_PM0_IFM_RG BIT(2)
299 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
300 #define ENETC_PM0_IFM_EN_AUTO BIT(15)
301 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13)
302 #define ENETC_PM0_IFM_SSP_1000 (2 << 13)
303 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
304 #define ENETC_PM0_IFM_SSP_10 (1 << 13)
305 #define ENETC_PM0_IFM_FULL_DPX BIT(12)
306 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
307 #define ENETC_PM0_IFM_IFMODE_XGMII 0
308 #define ENETC_PM0_IFM_IFMODE_GMII 2
309 #define ENETC_PSIDCAPR 0x1b08
310 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
311 #define ENETC_PSFCAPR 0x1b18
312 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
313 #define ENETC_PSGCAPR 0x1b28
314 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16)
315 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
316 #define ENETC_PFMCAPR 0x1b38
317 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
318
319 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and
320 * Port MAC 1 to the pMAC.
321 */
322 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac))
323 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac))
324 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac))
325 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac))
326 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac))
327 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac))
328 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac))
329 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac))
330 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac))
331 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac))
332 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac))
333 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac))
334 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac))
335 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac))
336 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac))
337 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac))
338 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac))
339 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac))
340 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac))
341 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac))
342 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac))
343 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac))
344 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac))
345 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac))
346 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac))
347 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac))
348 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac))
349 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac))
350 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac))
351 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac))
352 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac))
353 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac))
354 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac))
355 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac))
356 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac))
357 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac))
358 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac))
359 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac))
360 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac))
361 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac))
362 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac))
363 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac))
364 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac))
365 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac))
366 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac))
367 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac))
368 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac))
369 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac))
370 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac))
371 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac))
372 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac))
373
374 /* Port counters */
375 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
376 #define ENETC_PBFDSIR 0x0810
377 #define ENETC_PFDMSAPR 0x0814
378 #define ENETC_UFDMF 0x1680
379 #define ENETC_MFDMF 0x1684
380 #define ENETC_PUFDVFR 0x1780
381 #define ENETC_PMFDVFR 0x1784
382 #define ENETC_PBFDVFR 0x1788
383
384 /** Global regs, offset: 2_0000h */
385 #define ENETC_GLOBAL_BASE 0x20000
386 #define ENETC_G_EIPBRR0 0x0bf8
387 #define EIPBRR0_REVISION GENMASK(15, 0)
388 #define ENETC_REV_1_0 0x0100
389 #define ENETC_REV_4_1 0X0401
390 #define ENETC_REV_4_3 0x0403
391
392 #define ENETC_G_EIPBRR1 0x0bfc
393 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
394 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
395
396 /* PCI device info */
397 struct enetc_hw {
398 /* SI registers, used by all PCI functions */
399 void __iomem *reg;
400 /* Port registers, PF only */
401 void __iomem *port;
402 /* IP global registers, PF only */
403 void __iomem *global;
404 };
405
406 /* ENETC register accessors */
407
408 /* MDIO issue workaround (on LS1028A) -
409 * Due to a hardware issue, an access to MDIO registers
410 * that is concurrent with other ENETC register accesses
411 * may lead to the MDIO access being dropped or corrupted.
412 * To protect the MDIO accesses a readers-writers locking
413 * scheme is used, where the MDIO register accesses are
414 * protected by write locks to insure exclusivity, while
415 * the remaining ENETC registers are accessed under read
416 * locks since they only compete with MDIO accesses.
417 */
418 extern rwlock_t enetc_mdio_lock;
419
420 DECLARE_STATIC_KEY_FALSE(enetc_has_err050089);
421
422 /* use this locking primitive only on the fast datapath to
423 * group together multiple non-MDIO register accesses to
424 * minimize the overhead of the lock
425 */
enetc_lock_mdio(void)426 static inline void enetc_lock_mdio(void)
427 {
428 if (static_branch_unlikely(&enetc_has_err050089))
429 read_lock(&enetc_mdio_lock);
430 }
431
enetc_unlock_mdio(void)432 static inline void enetc_unlock_mdio(void)
433 {
434 if (static_branch_unlikely(&enetc_has_err050089))
435 read_unlock(&enetc_mdio_lock);
436 }
437
438 /* use these accessors only on the fast datapath under
439 * the enetc_lock_mdio() locking primitive to minimize
440 * the overhead of the lock
441 */
enetc_rd_reg_hot(void __iomem * reg)442 static inline u32 enetc_rd_reg_hot(void __iomem *reg)
443 {
444 if (static_branch_unlikely(&enetc_has_err050089))
445 lockdep_assert_held(&enetc_mdio_lock);
446
447 return ioread32(reg);
448 }
449
enetc_wr_reg_hot(void __iomem * reg,u32 val)450 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val)
451 {
452 if (static_branch_unlikely(&enetc_has_err050089))
453 lockdep_assert_held(&enetc_mdio_lock);
454
455 iowrite32(val, reg);
456 }
457
458 /* internal helpers for the MDIO w/a */
_enetc_rd_reg_wa(void __iomem * reg)459 static inline u32 _enetc_rd_reg_wa(void __iomem *reg)
460 {
461 u32 val;
462
463 enetc_lock_mdio();
464 val = ioread32(reg);
465 enetc_unlock_mdio();
466
467 return val;
468 }
469
_enetc_wr_reg_wa(void __iomem * reg,u32 val)470 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val)
471 {
472 enetc_lock_mdio();
473 iowrite32(val, reg);
474 enetc_unlock_mdio();
475 }
476
_enetc_rd_mdio_reg_wa(void __iomem * reg)477 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg)
478 {
479 unsigned long flags;
480 u32 val;
481
482 if (static_branch_unlikely(&enetc_has_err050089)) {
483 write_lock_irqsave(&enetc_mdio_lock, flags);
484 val = ioread32(reg);
485 write_unlock_irqrestore(&enetc_mdio_lock, flags);
486 } else {
487 val = ioread32(reg);
488 }
489
490 return val;
491 }
492
_enetc_wr_mdio_reg_wa(void __iomem * reg,u32 val)493 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val)
494 {
495 unsigned long flags;
496
497 if (static_branch_unlikely(&enetc_has_err050089)) {
498 write_lock_irqsave(&enetc_mdio_lock, flags);
499 iowrite32(val, reg);
500 write_unlock_irqrestore(&enetc_mdio_lock, flags);
501 } else {
502 iowrite32(val, reg);
503 }
504 }
505
506 #ifdef ioread64
_enetc_rd_reg64(void __iomem * reg)507 static inline u64 _enetc_rd_reg64(void __iomem *reg)
508 {
509 return ioread64(reg);
510 }
511 #else
512 /* using this to read out stats on 32b systems */
_enetc_rd_reg64(void __iomem * reg)513 static inline u64 _enetc_rd_reg64(void __iomem *reg)
514 {
515 u32 low, high, tmp;
516
517 do {
518 high = ioread32(reg + 4);
519 low = ioread32(reg);
520 tmp = ioread32(reg + 4);
521 } while (high != tmp);
522
523 return (u64)high << 32 | low;
524 }
525 #endif
526
_enetc_rd_reg64_wa(void __iomem * reg)527 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg)
528 {
529 u64 val;
530
531 enetc_lock_mdio();
532 val = _enetc_rd_reg64(reg);
533 enetc_unlock_mdio();
534
535 return val;
536 }
537
538 /* general register accessors */
539 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg))
540 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val))
541 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off))
542 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val)
543 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off))
544 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val)
545 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off))
546 /* port register accessors - PF only */
547 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off))
548 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val)
549 #define enetc_port_rd64(hw, off) _enetc_rd_reg64_wa((hw)->port + (off))
550 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off))
551 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\
552 (hw)->port + (off), val)
553 /* global register accessors - PF only */
554 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off))
555 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val)
556 /* BDR register accessors, see ENETC_BDR() */
557 #define enetc_bdr_rd(hw, t, n, off) \
558 enetc_rd(hw, ENETC_BDR(t, n, off))
559 #define enetc_bdr_wr(hw, t, n, off, val) \
560 enetc_wr(hw, ENETC_BDR(t, n, off), val)
561 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
562 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
563 #define enetc_txbdr_wr(hw, n, off, val) \
564 enetc_bdr_wr(hw, TX, n, off, val)
565 #define enetc_rxbdr_wr(hw, n, off, val) \
566 enetc_bdr_wr(hw, RX, n, off, val)
567
568 /* Buffer Descriptors (BD) */
569 union enetc_tx_bd {
570 struct {
571 __le64 addr;
572 union {
573 __le16 buf_len;
574 __le16 hdr_len; /* For LSO, ENETC 4.1 and later */
575 };
576 __le16 frm_len;
577 union {
578 struct {
579 u8 l3_aux0;
580 #define ENETC_TX_BD_L3_START GENMASK(6, 0)
581 #define ENETC_TX_BD_IPCS BIT(7)
582 u8 l3_aux1;
583 #define ENETC_TX_BD_L3_HDR_LEN GENMASK(6, 0)
584 #define ENETC_TX_BD_L3T BIT(7)
585 u8 l4_aux;
586 #define ENETC_TX_BD_L4T GENMASK(7, 5)
587 #define ENETC_TXBD_L4T_UDP 1
588 #define ENETC_TXBD_L4T_TCP 2
589 u8 flags;
590 }; /* default layout */
591 __le32 txstart;
592 __le32 lstatus;
593 };
594 };
595 struct {
596 __le32 tstamp;
597 __le16 tpid;
598 __le16 vid;
599 __le16 lso_sg_size; /* For ENETC 4.1 and later */
600 __le16 frm_len_ext; /* For ENETC 4.1 and later */
601 u8 reserved[2];
602 u8 e_flags;
603 u8 flags;
604 } ext; /* Tx BD extension */
605 struct {
606 __le32 tstamp;
607 u8 reserved[8];
608 __le16 lso_err_count; /* For ENETC 4.1 and later */
609 u8 status;
610 u8 flags;
611 } wb; /* writeback descriptor */
612 };
613
614 enum enetc_txbd_flags {
615 ENETC_TXBD_FLAGS_L4CS = BIT(0), /* For ENETC 4.1 and later */
616 ENETC_TXBD_FLAGS_TSE = BIT(1),
617 ENETC_TXBD_FLAGS_LSO = BIT(1), /* For ENETC 4.1 and later */
618 ENETC_TXBD_FLAGS_W = BIT(2),
619 ENETC_TXBD_FLAGS_CSUM_LSO = BIT(3), /* For ENETC 4.1 and later */
620 ENETC_TXBD_FLAGS_TXSTART = BIT(4),
621 ENETC_TXBD_FLAGS_EX = BIT(6),
622 ENETC_TXBD_FLAGS_F = BIT(7)
623 };
624 #define ENETC_TXBD_STATS_WIN BIT(7)
625 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
626 #define ENETC_TXBD_FLAGS_OFFSET 24
627 #define ENETC_TXBD_TSTAMP GENMASK(29, 0)
628
enetc_txbd_set_tx_start(u64 tx_start,u8 flags)629 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags)
630 {
631 u32 temp;
632
633 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) |
634 (flags << ENETC_TXBD_FLAGS_OFFSET);
635
636 return cpu_to_le32(temp);
637 }
638
enetc_clear_tx_bd(union enetc_tx_bd * txbd)639 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
640 {
641 memset(txbd, 0, sizeof(*txbd));
642 }
643
644 /* Extension flags */
645 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
646 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1)
647 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
648
649 union enetc_rx_bd {
650 struct {
651 __le64 addr;
652 u8 reserved[8];
653 } w;
654 struct {
655 __le16 inet_csum;
656 __le16 parse_summary;
657 __le32 rss_hash;
658 __le16 buf_len;
659 __le16 vlan_opt;
660 union {
661 struct {
662 __le16 flags;
663 __le16 error;
664 };
665 __le32 lstatus;
666 };
667 } r;
668 struct {
669 __le32 tstamp;
670 u8 reserved[12];
671 } ext;
672 };
673
674 #define ENETC_RXBD_LSTATUS_R BIT(30)
675 #define ENETC_RXBD_LSTATUS_F BIT(31)
676 #define ENETC_RXBD_ERR_MASK 0xff
677 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
678 #define ENETC_RXBD_FLAG_VLAN BIT(9)
679 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
680 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
681
682 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
683 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
684 #define ENETC_MAX_NUM_VFS 2
685
686 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
687 #define ENETC_CBD_STATUS_MASK 0xf
688
689 #define ENETC_TPID_8021Q 0
690
691 struct enetc_cmd_rfse {
692 u8 smac_h[6];
693 u8 smac_m[6];
694 u8 dmac_h[6];
695 u8 dmac_m[6];
696 __be32 sip_h[4];
697 __be32 sip_m[4];
698 __be32 dip_h[4];
699 __be32 dip_m[4];
700 u16 ethtype_h;
701 u16 ethtype_m;
702 u16 ethtype4_h;
703 u16 ethtype4_m;
704 u16 sport_h;
705 u16 sport_m;
706 u16 dport_h;
707 u16 dport_m;
708 u16 vlan_h;
709 u16 vlan_m;
710 u8 proto_h;
711 u8 proto_m;
712 u16 flags;
713 u16 result;
714 u16 mode;
715 };
716
717 #define ENETC_RFSE_EN BIT(15)
718 #define ENETC_RFSE_MODE_BD 2
719
enetc_get_primary_mac_addr(struct enetc_hw * hw,u8 * addr)720 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr)
721 {
722 u32 upper;
723 u16 lower;
724
725 upper = __raw_readl(hw->reg + ENETC_SIPMAR0);
726 lower = __raw_readl(hw->reg + ENETC_SIPMAR1);
727
728 put_unaligned_le32(upper, addr);
729 put_unaligned_le16(lower, addr + 4);
730 }
731
enetc_load_primary_mac_addr(struct enetc_hw * hw,struct net_device * ndev)732 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw,
733 struct net_device *ndev)
734 {
735 u8 addr[ETH_ALEN];
736
737 enetc_get_primary_mac_addr(hw, addr);
738 eth_hw_addr_set(ndev, addr);
739 }
740
741 #define ENETC_SI_INT_IDX 0
742 /* base index for Rx/Tx interrupts */
743 #define ENETC_BDR_INT_BASE_IDX 1
744
745 /* Messaging */
746
747 /* Command completion status */
748 enum enetc_msg_cmd_status {
749 ENETC_MSG_CMD_STATUS_OK,
750 ENETC_MSG_CMD_STATUS_FAIL
751 };
752
753 /* VSI-PSI command message types */
754 enum enetc_msg_cmd_type {
755 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
756 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
757 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
758 };
759
760 /* VSI-PSI command action types */
761 enum enetc_msg_cmd_action_type {
762 ENETC_MSG_CMD_MNG_ADD = 1,
763 ENETC_MSG_CMD_MNG_REMOVE
764 };
765
766 /* PSI-VSI command header format */
767 struct enetc_msg_cmd_header {
768 u16 type; /* command class type */
769 u16 id; /* denotes the specific required action */
770 };
771
772 /* Common H/W utility functions */
773
enetc_bdr_enable_rxvlan(struct enetc_hw * hw,int idx,bool en)774 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx,
775 bool en)
776 {
777 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
778
779 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
780 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val);
781 }
782
enetc_bdr_enable_txvlan(struct enetc_hw * hw,int idx,bool en)783 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx,
784 bool en)
785 {
786 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR);
787
788 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
789 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val);
790 }
791
enetc_set_bdr_prio(struct enetc_hw * hw,int bdr_idx,int prio)792 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
793 int prio)
794 {
795 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
796
797 val &= ~ENETC_TBMR_PRIO_MASK;
798 val |= ENETC_TBMR_SET_PRIO(prio);
799 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
800 }
801
802 enum bdcr_cmd_class {
803 BDCR_CMD_UNSPEC = 0,
804 BDCR_CMD_MAC_FILTER,
805 BDCR_CMD_VLAN_FILTER,
806 BDCR_CMD_RSS,
807 BDCR_CMD_RFS,
808 BDCR_CMD_PORT_GCL,
809 BDCR_CMD_RECV_CLASSIFIER,
810 BDCR_CMD_STREAM_IDENTIFY,
811 BDCR_CMD_STREAM_FILTER,
812 BDCR_CMD_STREAM_GCL,
813 BDCR_CMD_FLOW_METER,
814 __BDCR_CMD_MAX_LEN,
815 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
816 };
817
818 /* class 5, command 0 */
819 struct tgs_gcl_conf {
820 u8 atc; /* init gate value */
821 u8 res[7];
822 struct {
823 u8 res1[4];
824 __le16 acl_len;
825 u8 res2[2];
826 };
827 };
828
829 /* gate control list entry */
830 struct gce {
831 __le32 period;
832 u8 gate;
833 u8 res[3];
834 };
835
836 /* tgs_gcl_conf address point to this data space */
837 struct tgs_gcl_data {
838 __le32 btl;
839 __le32 bth;
840 __le32 ct;
841 __le32 cte;
842 struct gce entry[];
843 };
844
845 /* class 7, command 0, Stream Identity Entry Configuration */
846 struct streamid_conf {
847 __le32 stream_handle; /* init gate value */
848 __le32 iports;
849 u8 id_type;
850 u8 oui[3];
851 u8 res[3];
852 u8 en;
853 };
854
855 #define ENETC_CBDR_SID_VID_MASK 0xfff
856 #define ENETC_CBDR_SID_VIDM BIT(12)
857 #define ENETC_CBDR_SID_TG_MASK 0xc000
858 /* streamid_conf address point to this data space */
859 struct streamid_data {
860 union {
861 u8 dmac[6];
862 u8 smac[6];
863 };
864 u16 vid_vidm_tg;
865 };
866
867 #define ENETC_CBDR_SFI_PRI_MASK 0x7
868 #define ENETC_CBDR_SFI_PRIM BIT(3)
869 #define ENETC_CBDR_SFI_BLOV BIT(4)
870 #define ENETC_CBDR_SFI_BLEN BIT(5)
871 #define ENETC_CBDR_SFI_MSDUEN BIT(6)
872 #define ENETC_CBDR_SFI_FMITEN BIT(7)
873 #define ENETC_CBDR_SFI_ENABLE BIT(7)
874 /* class 8, command 0, Stream Filter Instance, Short Format */
875 struct sfi_conf {
876 __le32 stream_handle;
877 u8 multi;
878 u8 res[2];
879 u8 sthm;
880 /* Max Service Data Unit or Flow Meter Instance Table index.
881 * Depending on the value of FLT this represents either Max
882 * Service Data Unit (max frame size) allowed by the filter
883 * entry or is an index into the Flow Meter Instance table
884 * index identifying the policer which will be used to police
885 * it.
886 */
887 __le16 fm_inst_table_index;
888 __le16 msdu;
889 __le16 sg_inst_table_index;
890 u8 res1[2];
891 __le32 input_ports;
892 u8 res2[3];
893 u8 en;
894 };
895
896 /* class 8, command 2 stream Filter Instance status query short format
897 * command no need structure define
898 * Stream Filter Instance Query Statistics Response data
899 */
900 struct sfi_counter_data {
901 u32 matchl;
902 u32 matchh;
903 u32 msdu_dropl;
904 u32 msdu_droph;
905 u32 stream_gate_dropl;
906 u32 stream_gate_droph;
907 u32 flow_meter_dropl;
908 u32 flow_meter_droph;
909 };
910
911 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
912 #define ENETC_CBDR_SGI_OIPV_EN BIT(3)
913 #define ENETC_CBDR_SGI_CGTST BIT(6)
914 #define ENETC_CBDR_SGI_OGTST BIT(7)
915 #define ENETC_CBDR_SGI_CFG_CHG BIT(1)
916 #define ENETC_CBDR_SGI_CFG_PND BIT(2)
917 #define ENETC_CBDR_SGI_OEX BIT(4)
918 #define ENETC_CBDR_SGI_OEXEN BIT(5)
919 #define ENETC_CBDR_SGI_IRX BIT(6)
920 #define ENETC_CBDR_SGI_IRXEN BIT(7)
921 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
922 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
923 #define ENETC_CBDR_SGI_EN BIT(7)
924 /* class 9, command 0, Stream Gate Instance Table, Short Format
925 * class 9, command 2, Stream Gate Instance Table entry query write back
926 * Short Format
927 */
928 struct sgi_table {
929 u8 res[8];
930 u8 oipv;
931 u8 res0[2];
932 u8 ocgtst;
933 u8 res1[7];
934 u8 gset;
935 u8 oacl_len;
936 u8 res2[2];
937 u8 en;
938 };
939
940 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
941 #define ENETC_CBDR_SGI_AIPV_EN BIT(3)
942 #define ENETC_CBDR_SGI_AGTST BIT(7)
943
944 /* class 9, command 1, Stream Gate Control List, Long Format */
945 struct sgcl_conf {
946 u8 aipv;
947 u8 res[2];
948 u8 agtst;
949 u8 res1[4];
950 union {
951 struct {
952 u8 res2[4];
953 u8 acl_len;
954 u8 res3[3];
955 };
956 u8 cct[8]; /* Config change time */
957 };
958 };
959
960 #define ENETC_CBDR_SGL_IOMEN BIT(0)
961 #define ENETC_CBDR_SGL_IPVEN BIT(3)
962 #define ENETC_CBDR_SGL_GTST BIT(4)
963 #define ENETC_CBDR_SGL_IPV_MASK 0xe
964 /* Stream Gate Control List Entry */
965 struct sgce {
966 u32 interval;
967 u8 msdu[3];
968 u8 multi;
969 };
970
971 /* stream control list class 9 , cmd 1 data buffer */
972 struct sgcl_data {
973 u32 btl;
974 u32 bth;
975 u32 ct;
976 u32 cte;
977 struct sgce sgcl[];
978 };
979
980 #define ENETC_CBDR_FMI_MR BIT(0)
981 #define ENETC_CBDR_FMI_MREN BIT(1)
982 #define ENETC_CBDR_FMI_DOY BIT(2)
983 #define ENETC_CBDR_FMI_CM BIT(3)
984 #define ENETC_CBDR_FMI_CF BIT(4)
985 #define ENETC_CBDR_FMI_NDOR BIT(5)
986 #define ENETC_CBDR_FMI_OALEN BIT(6)
987 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
988
989 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
990 struct fmi_conf {
991 __le32 cir;
992 __le32 cbs;
993 __le32 eir;
994 __le32 ebs;
995 u8 conf;
996 u8 res1;
997 u8 ir_fpp;
998 u8 res2[4];
999 u8 en;
1000 };
1001
1002 struct enetc_cbd {
1003 union{
1004 struct sfi_conf sfi_conf;
1005 struct sgi_table sgi_table;
1006 struct fmi_conf fmi_conf;
1007 struct {
1008 __le32 addr[2];
1009 union {
1010 __le32 opt[4];
1011 struct tgs_gcl_conf gcl_conf;
1012 struct streamid_conf sid_set;
1013 struct sgcl_conf sgcl_conf;
1014 };
1015 }; /* Long format */
1016 __le32 data[6];
1017 };
1018 __le16 index;
1019 __le16 length;
1020 u8 cmd;
1021 u8 cls;
1022 u8 _res;
1023 u8 status_flags;
1024 };
1025
1026 #define ENETC_CLK_400M 400000000ULL
1027 #define ENETC_CLK_333M 333000000ULL
1028
enetc_cycles_to_usecs(u32 cycles,u64 clk_freq)1029 static inline u32 enetc_cycles_to_usecs(u32 cycles, u64 clk_freq)
1030 {
1031 return (u32)div_u64(cycles * 1000000ULL, clk_freq);
1032 }
1033
enetc_usecs_to_cycles(u32 usecs,u64 clk_freq)1034 static inline u32 enetc_usecs_to_cycles(u32 usecs, u64 clk_freq)
1035 {
1036 return (u32)div_u64(usecs * clk_freq, 1000000ULL);
1037 }
1038
1039 /* Port traffic class frame preemption register */
1040 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */
1041 #define ENETC_PTCFPR_FPE BIT(31)
1042
1043 /* port time gating control register */
1044 #define ENETC_PTGCR 0x11a00
1045 #define ENETC_PTGCR_TGE BIT(31)
1046 #define ENETC_PTGCR_TGPE BIT(30)
1047
1048 /* Port time gating capability register */
1049 #define ENETC_PTGCAPR 0x11a08
1050 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
1051
1052 /* Port time specific departure */
1053 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
1054 #define ENETC_TSDE BIT(31)
1055
1056 /* PSFP setting */
1057 #define ENETC_PPSFPMR 0x11b00
1058 #define ENETC_PPSFPMR_PSFPEN BIT(0)
1059 #define ENETC_PPSFPMR_VS BIT(1)
1060 #define ENETC_PPSFPMR_PVC BIT(2)
1061 #define ENETC_PPSFPMR_PVZC BIT(3)
1062