1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2024 Loongson Technology Corporation Limited 4 */ 5 6 #ifndef __ASM_KVM_EIOINTC_H 7 #define __ASM_KVM_EIOINTC_H 8 9 #include <kvm/iodev.h> 10 11 #define EIOINTC_IRQS 256 12 #define EIOINTC_ROUTE_MAX_VCPUS 256 13 #define EIOINTC_IRQS_U64_NUMS (EIOINTC_IRQS / 64) 14 /* map to ipnum per 32 irqs */ 15 #define EIOINTC_IRQS_NODETYPE_COUNT 16 16 17 #define EIOINTC_BASE 0x1400 18 #define EIOINTC_SIZE 0x900 19 20 #define EIOINTC_NODETYPE_START 0xa0 21 #define EIOINTC_NODETYPE_END 0xbf 22 #define EIOINTC_IPMAP_START 0xc0 23 #define EIOINTC_IPMAP_END 0xc7 24 #define EIOINTC_ENABLE_START 0x200 25 #define EIOINTC_ENABLE_END 0x21f 26 #define EIOINTC_BOUNCE_START 0x280 27 #define EIOINTC_BOUNCE_END 0x29f 28 #define EIOINTC_ISR_START 0x300 29 #define EIOINTC_ISR_END 0x31f 30 #define EIOINTC_COREISR_START 0x400 31 #define EIOINTC_COREISR_END 0x41f 32 #define EIOINTC_COREMAP_START 0x800 33 #define EIOINTC_COREMAP_END 0x8ff 34 35 #define EIOINTC_VIRT_BASE (0x40000000) 36 #define EIOINTC_VIRT_SIZE (0x1000) 37 38 #define EIOINTC_VIRT_FEATURES (0x0) 39 #define EIOINTC_HAS_VIRT_EXTENSION (0) 40 #define EIOINTC_HAS_ENABLE_OPTION (1) 41 #define EIOINTC_HAS_INT_ENCODE (2) 42 #define EIOINTC_HAS_CPU_ENCODE (3) 43 #define EIOINTC_VIRT_HAS_FEATURES ((1U << EIOINTC_HAS_VIRT_EXTENSION) \ 44 | (1U << EIOINTC_HAS_ENABLE_OPTION) \ 45 | (1U << EIOINTC_HAS_INT_ENCODE) \ 46 | (1U << EIOINTC_HAS_CPU_ENCODE)) 47 #define EIOINTC_VIRT_CONFIG (0x4) 48 #define EIOINTC_ENABLE (1) 49 #define EIOINTC_ENABLE_INT_ENCODE (2) 50 #define EIOINTC_ENABLE_CPU_ENCODE (3) 51 52 #define LOONGSON_IP_NUM 8 53 54 struct loongarch_eiointc { 55 spinlock_t lock; 56 struct kvm *kvm; 57 struct kvm_io_device device; 58 struct kvm_io_device device_vext; 59 uint32_t num_cpu; 60 uint32_t features; 61 uint32_t status; 62 63 /* hardware state */ 64 u64 nodetype[EIOINTC_IRQS_NODETYPE_COUNT / 4]; 65 66 /* one bit shows the state of one irq */ 67 u64 bounce[EIOINTC_IRQS_U64_NUMS]; 68 u64 isr[EIOINTC_IRQS_U64_NUMS]; 69 u64 coreisr[EIOINTC_ROUTE_MAX_VCPUS][EIOINTC_IRQS_U64_NUMS]; 70 u64 enable[EIOINTC_IRQS_U64_NUMS]; 71 72 /* use one byte to config ipmap for 32 irqs at once */ 73 u64 ipmap; 74 /* use one byte to config coremap for one irq */ 75 u64 coremap[EIOINTC_IRQS / 8]; 76 77 DECLARE_BITMAP(sw_coreisr[EIOINTC_ROUTE_MAX_VCPUS][LOONGSON_IP_NUM], EIOINTC_IRQS); 78 uint8_t sw_coremap[EIOINTC_IRQS]; 79 }; 80 81 int kvm_loongarch_register_eiointc_device(void); 82 void eiointc_set_irq(struct loongarch_eiointc *s, int irq, int level); 83 84 #endif /* __ASM_KVM_EIOINTC_H */ 85