xref: /linux/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h (revision 762f99f4f3cb41a775b5157dd761217beba65873)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2020, Intel Corporation
3  * DWMAC Intel header file
4  */
5 
6 #ifndef __DWMAC_INTEL_H__
7 #define __DWMAC_INTEL_H__
8 
9 #define POLL_DELAY_US 8
10 
11 /* SERDES Register */
12 #define SERDES_GCR	0x0	/* Global Conguration */
13 #define SERDES_GSR0	0x5	/* Global Status Reg0 */
14 #define SERDES_GCR0	0xb	/* Global Configuration Reg0 */
15 
16 /* SERDES defines */
17 #define SERDES_PLL_CLK		BIT(0)		/* PLL clk valid signal */
18 #define SERDES_PHY_RX_CLK	BIT(1)		/* PSE SGMII PHY rx clk */
19 #define SERDES_RST		BIT(2)		/* Serdes Reset */
20 #define SERDES_PWR_ST_MASK	GENMASK(6, 4)	/* Serdes Power state*/
21 #define SERDES_RATE_MASK	GENMASK(9, 8)
22 #define SERDES_PCLK_MASK	GENMASK(14, 12)	/* PCLK rate to PHY */
23 #define SERDES_LINK_MODE_MASK	GENMASK(2, 1)
24 #define SERDES_LINK_MODE_SHIFT	1
25 #define SERDES_PWR_ST_SHIFT	4
26 #define SERDES_PWR_ST_P0	0x0
27 #define SERDES_PWR_ST_P3	0x3
28 #define SERDES_LINK_MODE_2G5	0x3
29 #define SERSED_LINK_MODE_1G	0x2
30 #define SERDES_PCLK_37p5MHZ	0x0
31 #define SERDES_PCLK_70MHZ	0x1
32 #define SERDES_RATE_PCIE_GEN1	0x0
33 #define SERDES_RATE_PCIE_GEN2	0x1
34 #define SERDES_RATE_PCIE_SHIFT	8
35 #define SERDES_PCLK_SHIFT	12
36 
37 #define INTEL_MGBE_ADHOC_ADDR	0x15
38 #define INTEL_MGBE_XPCS_ADDR	0x16
39 
40 /* Cross-timestamping defines */
41 #define ART_CPUID_LEAF		0x15
42 #define EHL_PSE_ART_MHZ		19200000
43 
44 /* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
45 #define PSE_PTP_CLK_FREQ_MASK		(GMAC_GPO0 | GMAC_GPO3)
46 #define PSE_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)
47 #define PSE_PTP_CLK_FREQ_200MHZ		(GMAC_GPO0 | GMAC_GPO3)
48 #define PSE_PTP_CLK_FREQ_256MHZ		(0)
49 #define PCH_PTP_CLK_FREQ_MASK		(GMAC_GPO0)
50 #define PCH_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)
51 #define PCH_PTP_CLK_FREQ_200MHZ		(0)
52 
53 #endif /* __DWMAC_INTEL_H__ */
54