xref: /linux/drivers/net/ethernet/qlogic/qed/qed_mfw_hsi.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3  * Copyright (c) 2019-2021 Marvell International Ltd.
4  */
5 
6 #ifndef _QED_MFW_HSI_H
7 #define _QED_MFW_HSI_H
8 
9 #define MFW_TRACE_SIGNATURE     0x25071946
10 
11 /* The trace in the buffer */
12 #define MFW_TRACE_EVENTID_MASK          0x00ffff
13 #define MFW_TRACE_PRM_SIZE_MASK         0x0f0000
14 #define MFW_TRACE_PRM_SIZE_OFFSET	16
15 #define MFW_TRACE_ENTRY_SIZE            3
16 
17 struct mcp_trace {
18 	u32 signature;		/* Help to identify that the trace is valid */
19 	u32 size;		/* the size of the trace buffer in bytes */
20 	u32 curr_level;		/* 2 - all will be written to the buffer
21 				 * 1 - debug trace will not be written
22 				 * 0 - just errors will be written to the buffer
23 				 */
24 	u32 modules_mask[2];	/* a bit per module, 1 means write it, 0 means
25 				 * mask it.
26 				 */
27 
28 	/* Warning: the following pointers are assumed to be 32bits as they are
29 	 * used only in the MFW.
30 	 */
31 	u32 trace_prod; /* The next trace will be written to this offset */
32 	u32 trace_oldest; /* The oldest valid trace starts at this offset
33 			   * (usually very close after the current producer).
34 			   */
35 };
36 
37 #define VF_MAX_STATIC 192
38 #define VF_BITMAP_SIZE_IN_DWORDS (VF_MAX_STATIC / 32)
39 #define VF_BITMAP_SIZE_IN_BYTES (VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32))
40 
41 #define EXT_VF_MAX_STATIC 240
42 #define EXT_VF_BITMAP_SIZE_IN_DWORDS (((EXT_VF_MAX_STATIC - 1) / 32) + 1)
43 #define EXT_VF_BITMAP_SIZE_IN_BYTES (EXT_VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32))
44 #define ADDED_VF_BITMAP_SIZE 2
45 
46 #define MCP_GLOB_PATH_MAX	2
47 #define MCP_PORT_MAX		2
48 #define MCP_GLOB_PORT_MAX	4
49 #define MCP_GLOB_FUNC_MAX	16
50 
51 typedef u32 offsize_t;		/* In DWORDS !!! */
52 /* Offset from the beginning of the MCP scratchpad */
53 #define OFFSIZE_OFFSET_SHIFT	0
54 #define OFFSIZE_OFFSET_MASK	0x0000ffff
55 /* Size of specific element (not the whole array if any) */
56 #define OFFSIZE_SIZE_SHIFT	16
57 #define OFFSIZE_SIZE_MASK	0xffff0000
58 
59 #define SECTION_OFFSET(_offsize) (((((_offsize) &			\
60 				     OFFSIZE_OFFSET_MASK) >>	\
61 				    OFFSIZE_OFFSET_SHIFT) << 2))
62 
63 #define QED_SECTION_SIZE(_offsize) ((((_offsize) &		\
64 				      OFFSIZE_SIZE_MASK) >>	\
65 				     OFFSIZE_SIZE_SHIFT) << 2)
66 
67 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH +			\
68 				     SECTION_OFFSET((_offsize)) +	\
69 				     (QED_SECTION_SIZE((_offsize)) * (idx)))
70 
71 #define SECTION_OFFSIZE_ADDR(_pub_base, _section)	\
72 	((_pub_base) + offsetof(struct mcp_public_data, sections[_section]))
73 
74 /* PHY configuration */
75 struct eth_phy_cfg {
76 	u32					speed;
77 #define ETH_SPEED_AUTONEG			0x0
78 #define ETH_SPEED_SMARTLINQ			0x8
79 
80 	u32					pause;
81 #define ETH_PAUSE_NONE				0x0
82 #define ETH_PAUSE_AUTONEG			0x1
83 #define ETH_PAUSE_RX				0x2
84 #define ETH_PAUSE_TX				0x4
85 
86 	u32					adv_speed;
87 
88 	u32					loopback_mode;
89 #define ETH_LOOPBACK_NONE			0x0
90 #define ETH_LOOPBACK_INT_PHY			0x1
91 #define ETH_LOOPBACK_EXT_PHY			0x2
92 #define ETH_LOOPBACK_EXT			0x3
93 #define ETH_LOOPBACK_MAC			0x4
94 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123		0x5
95 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301		0x6
96 #define ETH_LOOPBACK_PCS_AH_ONLY		0x7
97 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY	0x8
98 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY	0x9
99 
100 	u32					eee_cfg;
101 #define EEE_CFG_EEE_ENABLED			BIT(0)
102 #define EEE_CFG_TX_LPI				BIT(1)
103 #define EEE_CFG_ADV_SPEED_1G			BIT(2)
104 #define EEE_CFG_ADV_SPEED_10G			BIT(3)
105 #define EEE_TX_TIMER_USEC_MASK			0xfffffff0
106 #define EEE_TX_TIMER_USEC_OFFSET		4
107 #define EEE_TX_TIMER_USEC_BALANCED_TIME		0xa00
108 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	0x100
109 #define EEE_TX_TIMER_USEC_LATENCY_TIME		0x6000
110 
111 	u32					link_modes;
112 
113 	u32					fec_mode;
114 #define FEC_FORCE_MODE_MASK			0x000000ff
115 #define FEC_FORCE_MODE_OFFSET			0
116 #define FEC_FORCE_MODE_NONE			0x00
117 #define FEC_FORCE_MODE_FIRECODE			0x01
118 #define FEC_FORCE_MODE_RS			0x02
119 #define FEC_FORCE_MODE_AUTO			0x07
120 #define FEC_EXTENDED_MODE_MASK			0xffffff00
121 #define FEC_EXTENDED_MODE_OFFSET		8
122 #define ETH_EXT_FEC_NONE			0x00000000
123 #define ETH_EXT_FEC_10G_NONE			0x00000100
124 #define ETH_EXT_FEC_10G_BASE_R			0x00000200
125 #define ETH_EXT_FEC_25G_NONE			0x00000400
126 #define ETH_EXT_FEC_25G_BASE_R			0x00000800
127 #define ETH_EXT_FEC_25G_RS528			0x00001000
128 #define ETH_EXT_FEC_40G_NONE			0x00002000
129 #define ETH_EXT_FEC_40G_BASE_R			0x00004000
130 #define ETH_EXT_FEC_50G_NONE			0x00008000
131 #define ETH_EXT_FEC_50G_BASE_R			0x00010000
132 #define ETH_EXT_FEC_50G_RS528			0x00020000
133 #define ETH_EXT_FEC_50G_RS544			0x00040000
134 #define ETH_EXT_FEC_100G_NONE			0x00080000
135 #define ETH_EXT_FEC_100G_BASE_R			0x00100000
136 #define ETH_EXT_FEC_100G_RS528			0x00200000
137 #define ETH_EXT_FEC_100G_RS544			0x00400000
138 
139 	u32					extended_speed;
140 #define ETH_EXT_SPEED_MASK			0x0000ffff
141 #define ETH_EXT_SPEED_OFFSET			0
142 #define ETH_EXT_SPEED_NONE			0x00000001
143 #define ETH_EXT_SPEED_1G			0x00000002
144 #define ETH_EXT_SPEED_10G			0x00000004
145 #define ETH_EXT_SPEED_25G			0x00000008
146 #define ETH_EXT_SPEED_40G			0x00000010
147 #define ETH_EXT_SPEED_50G_BASE_R		0x00000020
148 #define ETH_EXT_SPEED_50G_BASE_R2		0x00000040
149 #define ETH_EXT_SPEED_100G_BASE_R2		0x00000080
150 #define ETH_EXT_SPEED_100G_BASE_R4		0x00000100
151 #define ETH_EXT_SPEED_100G_BASE_P4		0x00000200
152 #define ETH_EXT_ADV_SPEED_MASK			0xFFFF0000
153 #define ETH_EXT_ADV_SPEED_OFFSET		16
154 #define ETH_EXT_ADV_SPEED_1G			0x00010000
155 #define ETH_EXT_ADV_SPEED_10G			0x00020000
156 #define ETH_EXT_ADV_SPEED_25G			0x00040000
157 #define ETH_EXT_ADV_SPEED_40G			0x00080000
158 #define ETH_EXT_ADV_SPEED_50G_BASE_R		0x00100000
159 #define ETH_EXT_ADV_SPEED_50G_BASE_R2		0x00200000
160 #define ETH_EXT_ADV_SPEED_100G_BASE_R2		0x00400000
161 #define ETH_EXT_ADV_SPEED_100G_BASE_R4		0x00800000
162 #define ETH_EXT_ADV_SPEED_100G_BASE_P4		0x01000000
163 };
164 
165 struct port_mf_cfg {
166 	u32 dynamic_cfg;
167 #define PORT_MF_CFG_OV_TAG_MASK		0x0000ffff
168 #define PORT_MF_CFG_OV_TAG_SHIFT	0
169 #define PORT_MF_CFG_OV_TAG_DEFAULT	PORT_MF_CFG_OV_TAG_MASK
170 
171 	u32 reserved[1];
172 };
173 
174 struct eth_stats {
175 	u64 r64;
176 	u64 r127;
177 	u64 r255;
178 	u64 r511;
179 	u64 r1023;
180 	u64 r1518;
181 
182 	union {
183 		struct {
184 			u64 r1522;
185 			u64 r2047;
186 			u64 r4095;
187 			u64 r9216;
188 			u64 r16383;
189 		} bb0;
190 		struct {
191 			u64 unused1;
192 			u64 r1519_to_max;
193 			u64 unused2;
194 			u64 unused3;
195 			u64 unused4;
196 		} ah0;
197 	} u0;
198 
199 	u64 rfcs;
200 	u64 rxcf;
201 	u64 rxpf;
202 	u64 rxpp;
203 	u64 raln;
204 	u64 rfcr;
205 	u64 rovr;
206 	u64 rjbr;
207 	u64 rund;
208 	u64 rfrg;
209 	u64 t64;
210 	u64 t127;
211 	u64 t255;
212 	u64 t511;
213 	u64 t1023;
214 	u64 t1518;
215 
216 	union {
217 		struct {
218 			u64 t2047;
219 			u64 t4095;
220 			u64 t9216;
221 			u64 t16383;
222 		} bb1;
223 		struct {
224 			u64 t1519_to_max;
225 			u64 unused6;
226 			u64 unused7;
227 			u64 unused8;
228 		} ah1;
229 	} u1;
230 
231 	u64 txpf;
232 	u64 txpp;
233 
234 	union {
235 		struct {
236 			u64 tlpiec;
237 			u64 tncl;
238 		} bb2;
239 		struct {
240 			u64 unused9;
241 			u64 unused10;
242 		} ah2;
243 	} u2;
244 
245 	u64 rbyte;
246 	u64 rxuca;
247 	u64 rxmca;
248 	u64 rxbca;
249 	u64 rxpok;
250 	u64 tbyte;
251 	u64 txuca;
252 	u64 txmca;
253 	u64 txbca;
254 	u64 txcf;
255 };
256 
257 struct pkt_type_cnt {
258 	u64 tc_tx_pkt_cnt[8];
259 	u64 tc_tx_oct_cnt[8];
260 	u64 priority_rx_pkt_cnt[8];
261 	u64 priority_rx_oct_cnt[8];
262 };
263 
264 struct brb_stats {
265 	u64 brb_truncate[8];
266 	u64 brb_discard[8];
267 };
268 
269 struct port_stats {
270 	struct brb_stats brb;
271 	struct eth_stats eth;
272 };
273 
274 struct couple_mode_teaming {
275 	u8 port_cmt[MCP_GLOB_PORT_MAX];
276 #define PORT_CMT_IN_TEAM	BIT(0)
277 
278 #define PORT_CMT_PORT_ROLE	BIT(1)
279 #define PORT_CMT_PORT_INACTIVE	(0 << 1)
280 #define PORT_CMT_PORT_ACTIVE	BIT(1)
281 
282 #define PORT_CMT_TEAM_MASK	BIT(2)
283 #define PORT_CMT_TEAM0		(0 << 2)
284 #define PORT_CMT_TEAM1		BIT(2)
285 };
286 
287 #define LLDP_CHASSIS_ID_STAT_LEN	4
288 #define LLDP_PORT_ID_STAT_LEN		4
289 #define DCBX_MAX_APP_PROTOCOL		32
290 #define MAX_SYSTEM_LLDP_TLV_DATA	32
291 #define MAX_TLV_BUFFER			128
292 
293 enum _lldp_agent {
294 	LLDP_NEAREST_BRIDGE = 0,
295 	LLDP_NEAREST_NON_TPMR_BRIDGE,
296 	LLDP_NEAREST_CUSTOMER_BRIDGE,
297 	LLDP_MAX_LLDP_AGENTS
298 };
299 
300 struct lldp_config_params_s {
301 	u32 config;
302 #define LLDP_CONFIG_TX_INTERVAL_MASK	0x000000ff
303 #define LLDP_CONFIG_TX_INTERVAL_SHIFT	0
304 #define LLDP_CONFIG_HOLD_MASK		0x00000f00
305 #define LLDP_CONFIG_HOLD_SHIFT		8
306 #define LLDP_CONFIG_MAX_CREDIT_MASK	0x0000f000
307 #define LLDP_CONFIG_MAX_CREDIT_SHIFT	12
308 #define LLDP_CONFIG_ENABLE_RX_MASK	0x40000000
309 #define LLDP_CONFIG_ENABLE_RX_SHIFT	30
310 #define LLDP_CONFIG_ENABLE_TX_MASK	0x80000000
311 #define LLDP_CONFIG_ENABLE_TX_SHIFT	31
312 	u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
313 	u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
314 };
315 
316 struct lldp_status_params_s {
317 	u32 prefix_seq_num;
318 	u32 status;
319 	u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
320 	u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
321 	u32 suffix_seq_num;
322 };
323 
324 struct dcbx_ets_feature {
325 	u32 flags;
326 #define DCBX_ETS_ENABLED_MASK	0x00000001
327 #define DCBX_ETS_ENABLED_SHIFT	0
328 #define DCBX_ETS_WILLING_MASK	0x00000002
329 #define DCBX_ETS_WILLING_SHIFT	1
330 #define DCBX_ETS_ERROR_MASK	0x00000004
331 #define DCBX_ETS_ERROR_SHIFT	2
332 #define DCBX_ETS_CBS_MASK	0x00000008
333 #define DCBX_ETS_CBS_SHIFT	3
334 #define DCBX_ETS_MAX_TCS_MASK	0x000000f0
335 #define DCBX_ETS_MAX_TCS_SHIFT	4
336 #define DCBX_OOO_TC_MASK	0x00000f00
337 #define DCBX_OOO_TC_SHIFT	8
338 	u32 pri_tc_tbl[1];
339 #define DCBX_TCP_OOO_TC		(4)
340 #define DCBX_TCP_OOO_K2_4PORT_TC (3)
341 
342 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET	(DCBX_TCP_OOO_TC + 1)
343 #define DCBX_CEE_STRICT_PRIORITY	0xf
344 	u32 tc_bw_tbl[2];
345 	u32 tc_tsa_tbl[2];
346 #define DCBX_ETS_TSA_STRICT	0
347 #define DCBX_ETS_TSA_CBS	1
348 #define DCBX_ETS_TSA_ETS	2
349 };
350 
351 #define DCBX_TCP_OOO_TC			(4)
352 #define DCBX_TCP_OOO_K2_4PORT_TC	(3)
353 
354 struct dcbx_app_priority_entry {
355 	u32 entry;
356 #define DCBX_APP_PRI_MAP_MASK		0x000000ff
357 #define DCBX_APP_PRI_MAP_SHIFT		0
358 #define DCBX_APP_PRI_0			0x01
359 #define DCBX_APP_PRI_1			0x02
360 #define DCBX_APP_PRI_2			0x04
361 #define DCBX_APP_PRI_3			0x08
362 #define DCBX_APP_PRI_4			0x10
363 #define DCBX_APP_PRI_5			0x20
364 #define DCBX_APP_PRI_6			0x40
365 #define DCBX_APP_PRI_7			0x80
366 #define DCBX_APP_SF_MASK		0x00000300
367 #define DCBX_APP_SF_SHIFT		8
368 #define DCBX_APP_SF_ETHTYPE		0
369 #define DCBX_APP_SF_PORT		1
370 #define DCBX_APP_SF_IEEE_MASK		0x0000f000
371 #define DCBX_APP_SF_IEEE_SHIFT		12
372 #define DCBX_APP_SF_IEEE_RESERVED	0
373 #define DCBX_APP_SF_IEEE_ETHTYPE	1
374 #define DCBX_APP_SF_IEEE_TCP_PORT	2
375 #define DCBX_APP_SF_IEEE_UDP_PORT	3
376 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT	4
377 
378 #define DCBX_APP_PROTOCOL_ID_MASK	0xffff0000
379 #define DCBX_APP_PROTOCOL_ID_SHIFT	16
380 };
381 
382 struct dcbx_app_priority_feature {
383 	u32 flags;
384 #define DCBX_APP_ENABLED_MASK		0x00000001
385 #define DCBX_APP_ENABLED_SHIFT		0
386 #define DCBX_APP_WILLING_MASK		0x00000002
387 #define DCBX_APP_WILLING_SHIFT		1
388 #define DCBX_APP_ERROR_MASK		0x00000004
389 #define DCBX_APP_ERROR_SHIFT		2
390 #define DCBX_APP_MAX_TCS_MASK		0x0000f000
391 #define DCBX_APP_MAX_TCS_SHIFT		12
392 #define DCBX_APP_NUM_ENTRIES_MASK	0x00ff0000
393 #define DCBX_APP_NUM_ENTRIES_SHIFT	16
394 	struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
395 };
396 
397 struct dcbx_features {
398 	struct dcbx_ets_feature ets;
399 	u32 pfc;
400 #define DCBX_PFC_PRI_EN_BITMAP_MASK	0x000000ff
401 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT	0
402 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0	0x01
403 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1	0x02
404 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2	0x04
405 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3	0x08
406 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4	0x10
407 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5	0x20
408 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6	0x40
409 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7	0x80
410 
411 #define DCBX_PFC_FLAGS_MASK		0x0000ff00
412 #define DCBX_PFC_FLAGS_SHIFT		8
413 #define DCBX_PFC_CAPS_MASK		0x00000f00
414 #define DCBX_PFC_CAPS_SHIFT		8
415 #define DCBX_PFC_MBC_MASK		0x00004000
416 #define DCBX_PFC_MBC_SHIFT		14
417 #define DCBX_PFC_WILLING_MASK		0x00008000
418 #define DCBX_PFC_WILLING_SHIFT		15
419 #define DCBX_PFC_ENABLED_MASK		0x00010000
420 #define DCBX_PFC_ENABLED_SHIFT		16
421 #define DCBX_PFC_ERROR_MASK		0x00020000
422 #define DCBX_PFC_ERROR_SHIFT		17
423 
424 	struct dcbx_app_priority_feature app;
425 };
426 
427 struct dcbx_local_params {
428 	u32 config;
429 #define DCBX_CONFIG_VERSION_MASK	0x00000007
430 #define DCBX_CONFIG_VERSION_SHIFT	0
431 #define DCBX_CONFIG_VERSION_DISABLED	0
432 #define DCBX_CONFIG_VERSION_IEEE	1
433 #define DCBX_CONFIG_VERSION_CEE		2
434 #define DCBX_CONFIG_VERSION_STATIC	4
435 
436 	u32 flags;
437 	struct dcbx_features features;
438 };
439 
440 struct dcbx_mib {
441 	u32 prefix_seq_num;
442 	u32 flags;
443 	struct dcbx_features features;
444 	u32 suffix_seq_num;
445 };
446 
447 struct lldp_system_tlvs_buffer_s {
448 	u32 flags;
449 #define LLDP_SYSTEM_TLV_VALID_MASK 0x1
450 #define LLDP_SYSTEM_TLV_VALID_OFFSET 0
451 #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2
452 #define LLDP_SYSTEM_TLV_MANDATORY_SHIFT 1
453 #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000
454 #define LLDP_SYSTEM_TLV_LENGTH_SHIFT 16
455 	u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
456 };
457 
458 struct lldp_received_tlvs_s {
459 	u32 prefix_seq_num;
460 	u32 length;
461 	u32 tlvs_buffer[MAX_TLV_BUFFER];
462 	u32 suffix_seq_num;
463 };
464 
465 struct dcb_dscp_map {
466 	u32 flags;
467 #define DCB_DSCP_ENABLE_MASK	0x1
468 #define DCB_DSCP_ENABLE_SHIFT	0
469 #define DCB_DSCP_ENABLE	1
470 	u32 dscp_pri_map[8];
471 };
472 
473 struct mcp_val64 {
474 	u32 lo;
475 	u32 hi;
476 };
477 
478 struct generic_idc_msg_s {
479 	u32 source_pf;
480 	struct mcp_val64 msg;
481 };
482 
483 struct pcie_stats_stc {
484 	u32 sr_cnt_wr_byte_msb;
485 	u32 sr_cnt_wr_byte_lsb;
486 	u32 sr_cnt_wr_cnt;
487 	u32 sr_cnt_rd_byte_msb;
488 	u32 sr_cnt_rd_byte_lsb;
489 	u32 sr_cnt_rd_cnt;
490 };
491 
492 enum _attribute_commands_e {
493 	ATTRIBUTE_CMD_READ = 0,
494 	ATTRIBUTE_CMD_WRITE,
495 	ATTRIBUTE_CMD_READ_CLEAR,
496 	ATTRIBUTE_CMD_CLEAR,
497 	ATTRIBUTE_NUM_OF_COMMANDS
498 };
499 
500 struct public_global {
501 	u32 max_path;
502 	u32 max_ports;
503 #define MODE_1P 1
504 #define MODE_2P 2
505 #define MODE_3P 3
506 #define MODE_4P 4
507 	u32 debug_mb_offset;
508 	u32 phymod_dbg_mb_offset;
509 	struct couple_mode_teaming cmt;
510 	s32 internal_temperature;
511 	u32 mfw_ver;
512 	u32 running_bundle_id;
513 	s32 external_temperature;
514 	u32 mdump_reason;
515 	u32 ext_phy_upgrade_fw;
516 	u8 runtime_port_swap_map[MODE_4P];
517 	u32 data_ptr;
518 	u32 data_size;
519 	u32 bmb_error_status_cnt;
520 	u32 bmb_jumbo_frame_cnt;
521 	u32 sent_to_bmc_cnt;
522 	u32 handled_by_mfw;
523 	u32 sent_to_nw_cnt;
524 	u32 to_bmc_kb_per_second;
525 	u32 bcast_dropped_to_bmc_cnt;
526 	u32 mcast_dropped_to_bmc_cnt;
527 	u32 ucast_dropped_to_bmc_cnt;
528 	u32 ncsi_response_failure_cnt;
529 	u32 device_attr;
530 	u32 vpd_warning;
531 };
532 
533 struct fw_flr_mb {
534 	u32 aggint;
535 	u32 opgen_addr;
536 	u32 accum_ack;
537 };
538 
539 struct public_path {
540 	struct fw_flr_mb flr_mb;
541 	u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
542 
543 	u32 process_kill;
544 #define PROCESS_KILL_COUNTER_MASK	0x0000ffff
545 #define PROCESS_KILL_COUNTER_SHIFT	0
546 #define PROCESS_KILL_GLOB_AEU_BIT_MASK	0xffff0000
547 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT	16
548 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) ((aeu_reg_id) * 32 + (aeu_bit))
549 };
550 
551 #define FC_NPIV_WWPN_SIZE	8
552 #define FC_NPIV_WWNN_SIZE	8
553 struct dci_npiv_settings {
554 	u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
555 	u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
556 };
557 
558 struct dci_fc_npiv_cfg {
559 	/* hdr used internally by the MFW */
560 	u32 hdr;
561 	u32 num_of_npiv;
562 };
563 
564 #define MAX_NUMBER_NPIV    64
565 struct dci_fc_npiv_tbl {
566 	struct dci_fc_npiv_cfg fc_npiv_cfg;
567 	struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
568 };
569 
570 struct pause_flood_monitor {
571 	u8 period_cnt;
572 	u8 any_brb_prs_packet_hist;
573 	u8 any_brb_block_is_full_hist;
574 	u8 flags;
575 	u32 num_of_state_changes;
576 };
577 
578 struct public_port {
579 	u32						validity_map;
580 
581 	u32						link_status;
582 #define LINK_STATUS_LINK_UP				0x00000001
583 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001e
584 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		BIT(1)
585 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(2 << 1)
586 #define LINK_STATUS_SPEED_AND_DUPLEX_10G		(3 << 1)
587 #define LINK_STATUS_SPEED_AND_DUPLEX_20G		(4 << 1)
588 #define LINK_STATUS_SPEED_AND_DUPLEX_40G		(5 << 1)
589 #define LINK_STATUS_SPEED_AND_DUPLEX_50G		(6 << 1)
590 #define LINK_STATUS_SPEED_AND_DUPLEX_100G		(7 << 1)
591 #define LINK_STATUS_SPEED_AND_DUPLEX_25G		(8 << 1)
592 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
593 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
594 #define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
595 #define LINK_STATUS_PFC_ENABLED				0x00000100
596 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
597 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
598 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE		0x00000800
599 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE		0x00001000
600 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE		0x00002000
601 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE		0x00004000
602 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE		0x00008000
603 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE		0x00010000
604 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000c0000
605 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0 << 18)
606 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	BIT(18)
607 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2 << 18)
608 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3 << 18)
609 #define LINK_STATUS_SFP_TX_FAULT			0x00100000
610 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00200000
611 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00400000
612 #define LINK_STATUS_RX_SIGNAL_PRESENT			0x00800000
613 #define LINK_STATUS_MAC_LOCAL_FAULT			0x01000000
614 #define LINK_STATUS_MAC_REMOTE_FAULT			0x02000000
615 #define LINK_STATUS_UNSUPPORTED_SPD_REQ			0x04000000
616 
617 #define LINK_STATUS_FEC_MODE_MASK			0x38000000
618 #define LINK_STATUS_FEC_MODE_NONE			(0 << 27)
619 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74		BIT(27)
620 #define LINK_STATUS_FEC_MODE_RS_CL91			(2 << 27)
621 #define LINK_STATUS_EXT_PHY_LINK_UP			BIT(30)
622 
623 	u32 link_status1;
624 	u32 ext_phy_fw_version;
625 	u32 drv_phy_cfg_addr;
626 
627 	u32 port_stx;
628 
629 	u32 stat_nig_timer;
630 
631 	struct port_mf_cfg port_mf_config;
632 	struct port_stats stats;
633 
634 	u32 media_type;
635 #define MEDIA_UNSPECIFIED	0x0
636 #define MEDIA_SFPP_10G_FIBER	0x1
637 #define MEDIA_XFP_FIBER		0x2
638 #define MEDIA_DA_TWINAX		0x3
639 #define MEDIA_BASE_T		0x4
640 #define MEDIA_SFP_1G_FIBER	0x5
641 #define MEDIA_MODULE_FIBER	0x6
642 #define MEDIA_KR		0xf0
643 #define MEDIA_NOT_PRESENT	0xff
644 
645 	u32 lfa_status;
646 	u32 link_change_count;
647 
648 	struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
649 	struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
650 	struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
651 
652 	/* DCBX related MIB */
653 	struct dcbx_local_params local_admin_dcbx_mib;
654 	struct dcbx_mib remote_dcbx_mib;
655 	struct dcbx_mib operational_dcbx_mib;
656 
657 	u32 fc_npiv_nvram_tbl_addr;
658 	u32 fc_npiv_nvram_tbl_size;
659 
660 	u32						transceiver_data;
661 #define ETH_TRANSCEIVER_STATE_MASK			0x000000ff
662 #define ETH_TRANSCEIVER_STATE_SHIFT			0x00000000
663 #define ETH_TRANSCEIVER_STATE_OFFSET			0x00000000
664 #define ETH_TRANSCEIVER_STATE_UNPLUGGED			0x00000000
665 #define ETH_TRANSCEIVER_STATE_PRESENT			0x00000001
666 #define ETH_TRANSCEIVER_STATE_VALID			0x00000003
667 #define ETH_TRANSCEIVER_STATE_UPDATING			0x00000008
668 #define ETH_TRANSCEIVER_STATE_IN_SETUP			0x10
669 #define ETH_TRANSCEIVER_TYPE_MASK			0x0000ff00
670 #define ETH_TRANSCEIVER_TYPE_OFFSET			0x8
671 #define ETH_TRANSCEIVER_TYPE_NONE			0x00
672 #define ETH_TRANSCEIVER_TYPE_UNKNOWN			0xff
673 #define ETH_TRANSCEIVER_TYPE_1G_PCC			0x01
674 #define ETH_TRANSCEIVER_TYPE_1G_ACC			0x02
675 #define ETH_TRANSCEIVER_TYPE_1G_LX			0x03
676 #define ETH_TRANSCEIVER_TYPE_1G_SX			0x04
677 #define ETH_TRANSCEIVER_TYPE_10G_SR			0x05
678 #define ETH_TRANSCEIVER_TYPE_10G_LR			0x06
679 #define ETH_TRANSCEIVER_TYPE_10G_LRM			0x07
680 #define ETH_TRANSCEIVER_TYPE_10G_ER			0x08
681 #define ETH_TRANSCEIVER_TYPE_10G_PCC			0x09
682 #define ETH_TRANSCEIVER_TYPE_10G_ACC			0x0a
683 #define ETH_TRANSCEIVER_TYPE_XLPPI			0x0b
684 #define ETH_TRANSCEIVER_TYPE_40G_LR4			0x0c
685 #define ETH_TRANSCEIVER_TYPE_40G_SR4			0x0d
686 #define ETH_TRANSCEIVER_TYPE_40G_CR4			0x0e
687 #define ETH_TRANSCEIVER_TYPE_100G_AOC			0x0f
688 #define ETH_TRANSCEIVER_TYPE_100G_SR4			0x10
689 #define ETH_TRANSCEIVER_TYPE_100G_LR4			0x11
690 #define ETH_TRANSCEIVER_TYPE_100G_ER4			0x12
691 #define ETH_TRANSCEIVER_TYPE_100G_ACC			0x13
692 #define ETH_TRANSCEIVER_TYPE_100G_CR4			0x14
693 #define ETH_TRANSCEIVER_TYPE_4x10G_SR			0x15
694 #define ETH_TRANSCEIVER_TYPE_25G_CA_N			0x16
695 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S			0x17
696 #define ETH_TRANSCEIVER_TYPE_25G_CA_S			0x18
697 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M			0x19
698 #define ETH_TRANSCEIVER_TYPE_25G_CA_L			0x1a
699 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L			0x1b
700 #define ETH_TRANSCEIVER_TYPE_25G_SR			0x1c
701 #define ETH_TRANSCEIVER_TYPE_25G_LR			0x1d
702 #define ETH_TRANSCEIVER_TYPE_25G_AOC			0x1e
703 #define ETH_TRANSCEIVER_TYPE_4x10G			0x1f
704 #define ETH_TRANSCEIVER_TYPE_4x25G_CR			0x20
705 #define ETH_TRANSCEIVER_TYPE_1000BASET			0x21
706 #define ETH_TRANSCEIVER_TYPE_10G_BASET			0x22
707 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR	0x30
708 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR	0x31
709 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR	0x32
710 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR	0x33
711 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR	0x34
712 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR	0x35
713 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC	0x36
714 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR	0x37
715 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR	0x38
716 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR	0x39
717 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR	0x3a
718 
719 	u32 wol_info;
720 	u32 wol_pkt_len;
721 	u32 wol_pkt_details;
722 	struct dcb_dscp_map dcb_dscp_map;
723 
724 	u32 eee_status;
725 #define EEE_ACTIVE_BIT			BIT(0)
726 #define EEE_LD_ADV_STATUS_MASK		0x000000f0
727 #define EEE_LD_ADV_STATUS_OFFSET	4
728 #define EEE_1G_ADV			BIT(1)
729 #define EEE_10G_ADV			BIT(2)
730 #define EEE_LP_ADV_STATUS_MASK		0x00000f00
731 #define EEE_LP_ADV_STATUS_OFFSET	8
732 #define EEE_SUPPORTED_SPEED_MASK	0x0000f000
733 #define EEE_SUPPORTED_SPEED_OFFSET	12
734 #define EEE_1G_SUPPORTED		BIT(1)
735 #define EEE_10G_SUPPORTED		BIT(2)
736 
737 	u32 eee_remote;
738 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
739 #define EEE_REMOTE_TW_TX_OFFSET 0
740 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
741 #define EEE_REMOTE_TW_RX_OFFSET 16
742 
743 	u32 module_info;
744 
745 	u32 oem_cfg_port;
746 #define OEM_CFG_CHANNEL_TYPE_MASK                       0x00000003
747 #define OEM_CFG_CHANNEL_TYPE_OFFSET                     0
748 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION             0x1
749 #define OEM_CFG_CHANNEL_TYPE_STAGGED                    0x2
750 #define OEM_CFG_SCHED_TYPE_MASK                         0x0000000C
751 #define OEM_CFG_SCHED_TYPE_OFFSET                       2
752 #define OEM_CFG_SCHED_TYPE_ETS                          0x1
753 #define OEM_CFG_SCHED_TYPE_VNIC_BW                      0x2
754 
755 	struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS];
756 	u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA];
757 	u32 phy_module_temperature;
758 	u32 nig_reg_stat_rx_bmb_packet;
759 	u32 nig_reg_rx_llh_ncsi_mcp_mask;
760 	u32 nig_reg_rx_llh_ncsi_mcp_mask_2;
761 	struct pause_flood_monitor pause_flood_monitor;
762 	u32 nig_drain_cnt;
763 	struct pkt_type_cnt pkt_tc_priority_cnt;
764 };
765 
766 #define MCP_DRV_VER_STR_SIZE 16
767 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
768 #define MCP_DRV_NVM_BUF_LEN 32
769 struct drv_version_stc {
770 	u32 version;
771 	u8 name[MCP_DRV_VER_STR_SIZE - 4];
772 };
773 
774 struct public_func {
775 	u32 iscsi_boot_signature;
776 	u32 iscsi_boot_block_offset;
777 
778 	u32 mtu_size;
779 
780 	u32 c2s_pcp_map_lower;
781 	u32 c2s_pcp_map_upper;
782 	u32 c2s_pcp_map_default;
783 
784 	struct generic_idc_msg_s generic_idc_msg;
785 
786 	u32 num_of_msix;
787 
788 	u32 config;
789 #define FUNC_MF_CFG_FUNC_HIDE			0x00000001
790 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING		0x00000002
791 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT	0x00000001
792 
793 #define FUNC_MF_CFG_PROTOCOL_MASK	0x000000f0
794 #define FUNC_MF_CFG_PROTOCOL_SHIFT	4
795 #define FUNC_MF_CFG_PROTOCOL_ETHERNET	0x00000000
796 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
797 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
798 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
799 #define FUNC_MF_CFG_PROTOCOL_MAX	0x00000030
800 
801 #define FUNC_MF_CFG_MIN_BW_MASK		0x0000ff00
802 #define FUNC_MF_CFG_MIN_BW_SHIFT	8
803 #define FUNC_MF_CFG_MIN_BW_DEFAULT	0x00000000
804 #define FUNC_MF_CFG_MAX_BW_MASK		0x00ff0000
805 #define FUNC_MF_CFG_MAX_BW_SHIFT	16
806 #define FUNC_MF_CFG_MAX_BW_DEFAULT	0x00640000
807 
808 	u32 status;
809 #define FUNC_STATUS_VIRTUAL_LINK_UP	0x00000001
810 
811 	u32 mac_upper;
812 #define FUNC_MF_CFG_UPPERMAC_MASK	0x0000ffff
813 #define FUNC_MF_CFG_UPPERMAC_SHIFT	0
814 #define FUNC_MF_CFG_UPPERMAC_DEFAULT	FUNC_MF_CFG_UPPERMAC_MASK
815 	u32 mac_lower;
816 #define FUNC_MF_CFG_LOWERMAC_DEFAULT	0xffffffff
817 
818 	u32 fcoe_wwn_port_name_upper;
819 	u32 fcoe_wwn_port_name_lower;
820 
821 	u32 fcoe_wwn_node_name_upper;
822 	u32 fcoe_wwn_node_name_lower;
823 
824 	u32 ovlan_stag;
825 #define FUNC_MF_CFG_OV_STAG_MASK	0x0000ffff
826 #define FUNC_MF_CFG_OV_STAG_SHIFT	0
827 #define FUNC_MF_CFG_OV_STAG_DEFAULT	FUNC_MF_CFG_OV_STAG_MASK
828 
829 	u32 pf_allocation;
830 
831 	u32 preserve_data;
832 
833 	u32 driver_last_activity_ts;
834 
835 	u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
836 
837 	u32 drv_id;
838 #define DRV_ID_PDA_COMP_VER_MASK	0x0000ffff
839 #define DRV_ID_PDA_COMP_VER_SHIFT	0
840 
841 #define LOAD_REQ_HSI_VERSION		2
842 #define DRV_ID_MCP_HSI_VER_MASK		0x00ff0000
843 #define DRV_ID_MCP_HSI_VER_SHIFT	16
844 #define DRV_ID_MCP_HSI_VER_CURRENT	(LOAD_REQ_HSI_VERSION << \
845 					 DRV_ID_MCP_HSI_VER_SHIFT)
846 
847 #define DRV_ID_DRV_TYPE_MASK		0x7f000000
848 #define DRV_ID_DRV_TYPE_SHIFT		24
849 #define DRV_ID_DRV_TYPE_UNKNOWN		(0 << DRV_ID_DRV_TYPE_SHIFT)
850 #define DRV_ID_DRV_TYPE_LINUX		BIT(DRV_ID_DRV_TYPE_SHIFT)
851 
852 #define DRV_ID_DRV_INIT_HW_MASK		0x80000000
853 #define DRV_ID_DRV_INIT_HW_SHIFT	31
854 #define DRV_ID_DRV_INIT_HW_FLAG		BIT(DRV_ID_DRV_INIT_HW_SHIFT)
855 
856 	u32 oem_cfg_func;
857 #define OEM_CFG_FUNC_TC_MASK                    0x0000000F
858 #define OEM_CFG_FUNC_TC_OFFSET                  0
859 #define OEM_CFG_FUNC_TC_0                       0x0
860 #define OEM_CFG_FUNC_TC_1                       0x1
861 #define OEM_CFG_FUNC_TC_2                       0x2
862 #define OEM_CFG_FUNC_TC_3                       0x3
863 #define OEM_CFG_FUNC_TC_4                       0x4
864 #define OEM_CFG_FUNC_TC_5                       0x5
865 #define OEM_CFG_FUNC_TC_6                       0x6
866 #define OEM_CFG_FUNC_TC_7                       0x7
867 
868 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK         0x00000030
869 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET       4
870 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC         0x1
871 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS           0x2
872 
873 	struct drv_version_stc drv_ver;
874 };
875 
876 struct mcp_mac {
877 	u32 mac_upper;
878 	u32 mac_lower;
879 };
880 
881 struct mcp_file_att {
882 	u32 nvm_start_addr;
883 	u32 len;
884 };
885 
886 struct bist_nvm_image_att {
887 	u32 return_code;
888 	u32 image_type;
889 	u32 nvm_start_addr;
890 	u32 len;
891 };
892 
893 struct lan_stats_stc {
894 	u64 ucast_rx_pkts;
895 	u64 ucast_tx_pkts;
896 	u32 fcs_err;
897 	u32 rserved;
898 };
899 
900 struct fcoe_stats_stc {
901 	u64 rx_pkts;
902 	u64 tx_pkts;
903 	u32 fcs_err;
904 	u32 login_failure;
905 };
906 
907 struct iscsi_stats_stc {
908 	u64 rx_pdus;
909 	u64 tx_pdus;
910 	u64 rx_bytes;
911 	u64 tx_bytes;
912 };
913 
914 struct rdma_stats_stc {
915 	u64 rx_pkts;
916 	u64 tx_pkts;
917 	u64 rx_bytes;
918 	u64 tx_bytes;
919 };
920 
921 struct ocbb_data_stc {
922 	u32 ocbb_host_addr;
923 	u32 ocsd_host_addr;
924 	u32 ocsd_req_update_interval;
925 };
926 
927 struct fcoe_cap_stc {
928 	u32 max_ios;
929 	u32 max_log;
930 	u32 max_exch;
931 	u32 max_npiv;
932 	u32 max_tgt;
933 	u32 max_outstnd;
934 };
935 
936 #define MAX_NUM_OF_SENSORS 7
937 struct temperature_status_stc {
938 	u32 num_of_sensors;
939 	u32 sensor[MAX_NUM_OF_SENSORS];
940 };
941 
942 /* crash dump configuration header */
943 struct mdump_config_stc {
944 	u32 version;
945 	u32 config;
946 	u32 epoc;
947 	u32 num_of_logs;
948 	u32 valid_logs;
949 };
950 
951 enum resource_id_enum {
952 	RESOURCE_NUM_SB_E = 0,
953 	RESOURCE_NUM_L2_QUEUE_E = 1,
954 	RESOURCE_NUM_VPORT_E = 2,
955 	RESOURCE_NUM_VMQ_E = 3,
956 	RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
957 	RESOURCE_FACTOR_RSS_PER_VF_E = 5,
958 	RESOURCE_NUM_RL_E = 6,
959 	RESOURCE_NUM_PQ_E = 7,
960 	RESOURCE_NUM_VF_E = 8,
961 	RESOURCE_VFC_FILTER_E = 9,
962 	RESOURCE_ILT_E = 10,
963 	RESOURCE_CQS_E = 11,
964 	RESOURCE_GFT_PROFILES_E = 12,
965 	RESOURCE_NUM_TC_E = 13,
966 	RESOURCE_NUM_RSS_ENGINES_E = 14,
967 	RESOURCE_LL2_QUEUE_E = 15,
968 	RESOURCE_RDMA_STATS_QUEUE_E = 16,
969 	RESOURCE_BDQ_E = 17,
970 	RESOURCE_QCN_E = 18,
971 	RESOURCE_LLH_FILTER_E = 19,
972 	RESOURCE_VF_MAC_ADDR = 20,
973 	RESOURCE_LL2_CQS_E = 21,
974 	RESOURCE_VF_CNQS = 22,
975 	RESOURCE_MAX_NUM,
976 	RESOURCE_NUM_INVALID = 0xFFFFFFFF
977 };
978 
979 /* Resource ID is to be filled by the driver in the MB request
980  * Size, offset & flags to be filled by the MFW in the MB response
981  */
982 struct resource_info {
983 	enum resource_id_enum res_id;
984 	u32 size;		/* number of allocated resources */
985 	u32 offset;		/* Offset of the 1st resource */
986 	u32 vf_size;
987 	u32 vf_offset;
988 	u32 flags;
989 #define RESOURCE_ELEMENT_STRICT BIT(0)
990 };
991 
992 struct mcp_wwn {
993 	u32 wwn_upper;
994 	u32 wwn_lower;
995 };
996 
997 #define DRV_ROLE_NONE           0
998 #define DRV_ROLE_PREBOOT        1
999 #define DRV_ROLE_OS             2
1000 #define DRV_ROLE_KDUMP          3
1001 
1002 struct load_req_stc {
1003 	u32 drv_ver_0;
1004 	u32 drv_ver_1;
1005 	u32 fw_ver;
1006 	u32 misc0;
1007 #define LOAD_REQ_ROLE_MASK              0x000000FF
1008 #define LOAD_REQ_ROLE_SHIFT             0
1009 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
1010 #define LOAD_REQ_LOCK_TO_SHIFT          8
1011 #define LOAD_REQ_LOCK_TO_DEFAULT        0
1012 #define LOAD_REQ_LOCK_TO_NONE           255
1013 #define LOAD_REQ_FORCE_MASK             0x000F0000
1014 #define LOAD_REQ_FORCE_SHIFT            16
1015 #define LOAD_REQ_FORCE_NONE             0
1016 #define LOAD_REQ_FORCE_PF               1
1017 #define LOAD_REQ_FORCE_ALL              2
1018 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
1019 #define LOAD_REQ_FLAGS0_SHIFT           20
1020 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
1021 };
1022 
1023 struct load_rsp_stc {
1024 	u32 drv_ver_0;
1025 	u32 drv_ver_1;
1026 	u32 fw_ver;
1027 	u32 misc0;
1028 #define LOAD_RSP_ROLE_MASK              0x000000FF
1029 #define LOAD_RSP_ROLE_SHIFT             0
1030 #define LOAD_RSP_HSI_MASK               0x0000FF00
1031 #define LOAD_RSP_HSI_SHIFT              8
1032 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
1033 #define LOAD_RSP_FLAGS0_SHIFT           16
1034 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
1035 };
1036 
1037 struct mdump_retain_data_stc {
1038 	u32 valid;
1039 	u32 epoch;
1040 	u32 pf;
1041 	u32 status;
1042 };
1043 
1044 struct attribute_cmd_write_stc {
1045 	u32 val;
1046 	u32 mask;
1047 	u32 offset;
1048 };
1049 
1050 struct lldp_stats_stc {
1051 	u32 tx_frames_total;
1052 	u32 rx_frames_total;
1053 	u32 rx_frames_discarded;
1054 	u32 rx_age_outs;
1055 };
1056 
1057 struct get_att_ctrl_stc {
1058 	u32 disabled_attns;
1059 	u32 controllable_attns;
1060 };
1061 
1062 struct trace_filter_stc {
1063 	u32 level;
1064 	u32 modules;
1065 };
1066 
1067 union drv_union_data {
1068 	struct mcp_mac wol_mac;
1069 
1070 	struct eth_phy_cfg drv_phy_cfg;
1071 
1072 	struct mcp_val64 val64;
1073 
1074 	u8 raw_data[MCP_DRV_NVM_BUF_LEN];
1075 
1076 	struct mcp_file_att file_att;
1077 
1078 	u32 ack_vf_disabled[EXT_VF_BITMAP_SIZE_IN_DWORDS];
1079 
1080 	struct drv_version_stc drv_version;
1081 
1082 	struct lan_stats_stc lan_stats;
1083 	struct fcoe_stats_stc fcoe_stats;
1084 	struct iscsi_stats_stc iscsi_stats;
1085 	struct rdma_stats_stc rdma_stats;
1086 	struct ocbb_data_stc ocbb_info;
1087 	struct temperature_status_stc temp_info;
1088 	struct resource_info resource;
1089 	struct bist_nvm_image_att nvm_image_att;
1090 	struct mdump_config_stc mdump_config;
1091 	struct mcp_mac lldp_mac;
1092 	struct mcp_wwn fcoe_fabric_name;
1093 	u32 dword;
1094 
1095 	struct load_req_stc load_req;
1096 	struct load_rsp_stc load_rsp;
1097 	struct mdump_retain_data_stc mdump_retain;
1098 	struct attribute_cmd_write_stc attribute_cmd_write;
1099 	struct lldp_stats_stc lldp_stats;
1100 	struct pcie_stats_stc pcie_stats;
1101 
1102 	struct get_att_ctrl_stc get_att_ctrl;
1103 	struct fcoe_cap_stc fcoe_cap;
1104 	struct trace_filter_stc trace_filter;
1105 };
1106 
1107 struct public_drv_mb {
1108 	u32 drv_mb_header;
1109 #define DRV_MSG_SEQ_NUMBER_MASK			0x0000ffff
1110 #define DRV_MSG_SEQ_NUMBER_OFFSET		0
1111 #define DRV_MSG_CODE_MASK			0xffff0000
1112 #define DRV_MSG_CODE_OFFSET			16
1113 
1114 	u32 drv_mb_param;
1115 
1116 	u32 fw_mb_header;
1117 #define FW_MSG_SEQ_NUMBER_MASK			0x0000ffff
1118 #define FW_MSG_SEQ_NUMBER_OFFSET		0
1119 #define FW_MSG_CODE_MASK			0xffff0000
1120 #define FW_MSG_CODE_OFFSET			16
1121 
1122 	u32 fw_mb_param;
1123 
1124 	u32 drv_pulse_mb;
1125 #define DRV_PULSE_SEQ_MASK			0x00007fff
1126 #define DRV_PULSE_SYSTEM_TIME_MASK		0xffff0000
1127 #define DRV_PULSE_ALWAYS_ALIVE			0x00008000
1128 
1129 	u32 mcp_pulse_mb;
1130 #define MCP_PULSE_SEQ_MASK			0x00007fff
1131 #define MCP_PULSE_ALWAYS_ALIVE			0x00008000
1132 #define MCP_EVENT_MASK				0xffff0000
1133 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ	0x00010000
1134 
1135 	union drv_union_data union_data;
1136 };
1137 
1138 #define DRV_MSG_CODE(_code_)    ((_code_) << DRV_MSG_CODE_OFFSET)
1139 enum drv_msg_code_enum {
1140 	DRV_MSG_CODE_NVM_PUT_FILE_BEGIN = DRV_MSG_CODE(0x0001),
1141 	DRV_MSG_CODE_NVM_PUT_FILE_DATA = DRV_MSG_CODE(0x0002),
1142 	DRV_MSG_CODE_NVM_GET_FILE_ATT = DRV_MSG_CODE(0x0003),
1143 	DRV_MSG_CODE_NVM_READ_NVRAM = DRV_MSG_CODE(0x0005),
1144 	DRV_MSG_CODE_NVM_WRITE_NVRAM = DRV_MSG_CODE(0x0006),
1145 	DRV_MSG_CODE_MCP_RESET = DRV_MSG_CODE(0x0009),
1146 	DRV_MSG_CODE_SET_VERSION = DRV_MSG_CODE(0x000f),
1147 	DRV_MSG_CODE_MCP_HALT = DRV_MSG_CODE(0x0010),
1148 	DRV_MSG_CODE_SET_VMAC = DRV_MSG_CODE(0x0011),
1149 	DRV_MSG_CODE_GET_VMAC = DRV_MSG_CODE(0x0012),
1150 	DRV_MSG_CODE_GET_STATS = DRV_MSG_CODE(0x0013),
1151 	DRV_MSG_CODE_TRANSCEIVER_READ = DRV_MSG_CODE(0x0016),
1152 	DRV_MSG_CODE_MASK_PARITIES = DRV_MSG_CODE(0x001a),
1153 	DRV_MSG_CODE_BIST_TEST = DRV_MSG_CODE(0x001e),
1154 	DRV_MSG_CODE_SET_LED_MODE = DRV_MSG_CODE(0x0020),
1155 	DRV_MSG_CODE_RESOURCE_CMD = DRV_MSG_CODE(0x0023),
1156 	DRV_MSG_CODE_MDUMP_CMD = DRV_MSG_CODE(0x0025),
1157 	DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL = DRV_MSG_CODE(0x002b),
1158 	DRV_MSG_CODE_OS_WOL = DRV_MSG_CODE(0x002e),
1159 	DRV_MSG_CODE_GET_TLV_DONE = DRV_MSG_CODE(0x002f),
1160 	DRV_MSG_CODE_FEATURE_SUPPORT = DRV_MSG_CODE(0x0030),
1161 	DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT = DRV_MSG_CODE(0x0031),
1162 	DRV_MSG_CODE_GET_ENGINE_CONFIG = DRV_MSG_CODE(0x0037),
1163 	DRV_MSG_CODE_GET_NVM_CFG_OPTION = DRV_MSG_CODE(0x003e),
1164 	DRV_MSG_CODE_SET_NVM_CFG_OPTION = DRV_MSG_CODE(0x003f),
1165 	DRV_MSG_CODE_INITIATE_PF_FLR = DRV_MSG_CODE(0x0201),
1166 	DRV_MSG_CODE_LOAD_REQ = DRV_MSG_CODE(0x1000),
1167 	DRV_MSG_CODE_LOAD_DONE = DRV_MSG_CODE(0x1100),
1168 	DRV_MSG_CODE_INIT_HW = DRV_MSG_CODE(0x1200),
1169 	DRV_MSG_CODE_CANCEL_LOAD_REQ = DRV_MSG_CODE(0x1300),
1170 	DRV_MSG_CODE_UNLOAD_REQ = DRV_MSG_CODE(0x2000),
1171 	DRV_MSG_CODE_UNLOAD_DONE = DRV_MSG_CODE(0x2100),
1172 	DRV_MSG_CODE_INIT_PHY = DRV_MSG_CODE(0x2200),
1173 	DRV_MSG_CODE_LINK_RESET = DRV_MSG_CODE(0x2300),
1174 	DRV_MSG_CODE_SET_DCBX = DRV_MSG_CODE(0x2500),
1175 	DRV_MSG_CODE_OV_UPDATE_CURR_CFG = DRV_MSG_CODE(0x2600),
1176 	DRV_MSG_CODE_OV_UPDATE_BUS_NUM = DRV_MSG_CODE(0x2700),
1177 	DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS = DRV_MSG_CODE(0x2800),
1178 	DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER = DRV_MSG_CODE(0x2900),
1179 	DRV_MSG_CODE_NIG_DRAIN = DRV_MSG_CODE(0x3000),
1180 	DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE = DRV_MSG_CODE(0x3100),
1181 	DRV_MSG_CODE_BW_UPDATE_ACK = DRV_MSG_CODE(0x3200),
1182 	DRV_MSG_CODE_OV_UPDATE_MTU = DRV_MSG_CODE(0x3300),
1183 	DRV_MSG_GET_RESOURCE_ALLOC_MSG = DRV_MSG_CODE(0x3400),
1184 	DRV_MSG_SET_RESOURCE_VALUE_MSG = DRV_MSG_CODE(0x3500),
1185 	DRV_MSG_CODE_OV_UPDATE_WOL = DRV_MSG_CODE(0x3800),
1186 	DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE = DRV_MSG_CODE(0x3900),
1187 	DRV_MSG_CODE_S_TAG_UPDATE_ACK = DRV_MSG_CODE(0x3b00),
1188 	DRV_MSG_CODE_GET_OEM_UPDATES = DRV_MSG_CODE(0x4100),
1189 	DRV_MSG_CODE_GET_PPFID_BITMAP = DRV_MSG_CODE(0x4300),
1190 	DRV_MSG_CODE_VF_DISABLED_DONE = DRV_MSG_CODE(0xc000),
1191 	DRV_MSG_CODE_CFG_VF_MSIX = DRV_MSG_CODE(0xc001),
1192 	DRV_MSG_CODE_CFG_PF_VFS_MSIX = DRV_MSG_CODE(0xc002),
1193 	DRV_MSG_CODE_DEBUG_DATA_SEND = DRV_MSG_CODE(0xc004),
1194 	DRV_MSG_CODE_GET_MANAGEMENT_STATUS = DRV_MSG_CODE(0xc007),
1195 };
1196 
1197 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT            4
1198 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
1199 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
1200 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
1201 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
1202 
1203 /* DRV_MSG_CODE_RETAIN_VMAC parameters */
1204 #define DRV_MSG_CODE_RETAIN_VMAC_FUNC_SHIFT 0
1205 #define DRV_MSG_CODE_RETAIN_VMAC_FUNC_MASK 0xf
1206 
1207 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_SHIFT 4
1208 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_MASK 0x70
1209 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_L2 0
1210 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_ISCSI 1
1211 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_FCOE 2
1212 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_WWNN 3
1213 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_WWPN 4
1214 
1215 #define DRV_MSG_CODE_MCP_RESET_FORCE 0xf04ce
1216 
1217 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
1218 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
1219 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
1220 #define DRV_MSG_CODE_STATS_TYPE_RDMA            4
1221 
1222 #define BW_MAX_MASK 0x000000ff
1223 #define BW_MAX_OFFSET 0
1224 #define BW_MIN_MASK 0x0000ff00
1225 #define BW_MIN_OFFSET 8
1226 
1227 #define DRV_MSG_FAN_FAILURE_TYPE BIT(0)
1228 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE BIT(1)
1229 
1230 #define RESOURCE_CMD_REQ_RESC_MASK		0x0000001F
1231 #define RESOURCE_CMD_REQ_RESC_SHIFT		0
1232 #define RESOURCE_CMD_REQ_OPCODE_MASK		0x000000E0
1233 #define RESOURCE_CMD_REQ_OPCODE_SHIFT		5
1234 #define RESOURCE_OPCODE_REQ			1
1235 #define RESOURCE_OPCODE_REQ_WO_AGING		2
1236 #define RESOURCE_OPCODE_REQ_W_AGING		3
1237 #define RESOURCE_OPCODE_RELEASE			4
1238 #define RESOURCE_OPCODE_FORCE_RELEASE		5
1239 #define RESOURCE_CMD_REQ_AGE_MASK		0x0000FF00
1240 #define RESOURCE_CMD_REQ_AGE_SHIFT		8
1241 
1242 #define RESOURCE_CMD_RSP_OWNER_MASK		0x000000FF
1243 #define RESOURCE_CMD_RSP_OWNER_SHIFT		0
1244 #define RESOURCE_CMD_RSP_OPCODE_MASK		0x00000700
1245 #define RESOURCE_CMD_RSP_OPCODE_SHIFT		8
1246 #define RESOURCE_OPCODE_GNT			1
1247 #define RESOURCE_OPCODE_BUSY			2
1248 #define RESOURCE_OPCODE_RELEASED		3
1249 #define RESOURCE_OPCODE_RELEASED_PREVIOUS	4
1250 #define RESOURCE_OPCODE_WRONG_OWNER		5
1251 #define RESOURCE_OPCODE_UNKNOWN_CMD		255
1252 
1253 #define RESOURCE_DUMP				0
1254 
1255 /* DRV_MSG_CODE_MDUMP_CMD parameters */
1256 #define MDUMP_DRV_PARAM_OPCODE_MASK             0x000000ff
1257 #define DRV_MSG_CODE_MDUMP_ACK                  0x01
1258 #define DRV_MSG_CODE_MDUMP_SET_VALUES           0x02
1259 #define DRV_MSG_CODE_MDUMP_TRIGGER              0x03
1260 #define DRV_MSG_CODE_MDUMP_GET_CONFIG           0x04
1261 #define DRV_MSG_CODE_MDUMP_SET_ENABLE           0x05
1262 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS           0x06
1263 #define DRV_MSG_CODE_MDUMP_GET_RETAIN           0x07
1264 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN           0x08
1265 
1266 #define DRV_MSG_CODE_HW_DUMP_TRIGGER            0x0a
1267 
1268 #define DRV_MSG_CODE_MDUMP_FREE_DRIVER_BUF 0x0b
1269 #define DRV_MSG_CODE_MDUMP_GEN_LINK_DUMP 0x0c
1270 #define DRV_MSG_CODE_MDUMP_GEN_IDLE_CHK 0x0d
1271 
1272 /* DRV_MSG_CODE_MDUMP_CMD options */
1273 #define MDUMP_DRV_PARAM_OPTION_MASK 0x00000f00
1274 #define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_OFFSET 8
1275 #define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_MASK 0x100
1276 
1277 /* DRV_MSG_CODE_EXT_PHY_READ/DRV_MSG_CODE_EXT_PHY_WRITE parameters */
1278 #define DRV_MB_PARAM_ADDR_SHIFT 0
1279 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF
1280 #define DRV_MB_PARAM_DEVAD_SHIFT 16
1281 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000
1282 #define DRV_MB_PARAM_PORT_SHIFT 21
1283 #define DRV_MB_PARAM_PORT_MASK 0x00600000
1284 
1285 /* DRV_MSG_CODE_PMBUS_READ/DRV_MSG_CODE_PMBUS_WRITE parameters */
1286 #define DRV_MB_PARAM_PMBUS_CMD_SHIFT 0
1287 #define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF
1288 #define DRV_MB_PARAM_PMBUS_LEN_SHIFT 8
1289 #define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300
1290 #define DRV_MB_PARAM_PMBUS_DATA_SHIFT 16
1291 #define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000
1292 
1293 /* UNLOAD_REQ params */
1294 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
1295 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
1296 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
1297 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
1298 
1299 /* UNLOAD_DONE_params */
1300 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
1301 
1302 /* INIT_PHY params */
1303 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
1304 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
1305 
1306 /* LLDP / DCBX params*/
1307 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
1308 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
1309 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
1310 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
1311 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001
1312 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_SHIFT 0
1313 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0
1314 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_SHIFT 4
1315 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
1316 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
1317 #define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_MASK 0x00000010
1318 #define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_SHIFT 4
1319 
1320 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
1321 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
1322 
1323 #define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_MASK 0x000000ff
1324 #define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_SHIFT 0
1325 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
1326 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
1327 
1328 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI     0x3
1329 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET          0
1330 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
1331 #define DRV_MB_PARAM_NVM_LEN_OFFSET		24
1332 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
1333 
1334 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT	0
1335 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK	0x000000FF
1336 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT	8
1337 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK	0x0000FF00
1338 
1339 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT		0
1340 #define DRV_MB_PARAM_OV_CURR_CFG_MASK		0x0000000F
1341 #define DRV_MB_PARAM_OV_CURR_CFG_NONE		0
1342 #define DRV_MB_PARAM_OV_CURR_CFG_OS		1
1343 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC	2
1344 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER		3
1345 
1346 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT	0
1347 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK	0xFFFFFFFF
1348 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK	0xFF000000
1349 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK	0x00FF0000
1350 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK	0x0000FF00
1351 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK	0x000000FF
1352 
1353 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT	0
1354 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK	0xF
1355 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN	0x1
1356 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED	0x2
1357 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING	0x3
1358 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED	0x4
1359 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE	0x5
1360 
1361 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT	0
1362 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK	0xFFFFFFFF
1363 
1364 #define DRV_MB_PARAM_WOL_MASK	(DRV_MB_PARAM_WOL_DEFAULT | \
1365 				 DRV_MB_PARAM_WOL_DISABLED | \
1366 				 DRV_MB_PARAM_WOL_ENABLED)
1367 #define DRV_MB_PARAM_WOL_DEFAULT	DRV_MB_PARAM_UNLOAD_WOL_MCP
1368 #define DRV_MB_PARAM_WOL_DISABLED	DRV_MB_PARAM_UNLOAD_WOL_DISABLED
1369 #define DRV_MB_PARAM_WOL_ENABLED	DRV_MB_PARAM_UNLOAD_WOL_ENABLED
1370 
1371 #define DRV_MB_PARAM_ESWITCH_MODE_MASK	(DRV_MB_PARAM_ESWITCH_MODE_NONE | \
1372 					 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
1373 					 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
1374 #define DRV_MB_PARAM_ESWITCH_MODE_NONE	0x0
1375 #define DRV_MB_PARAM_ESWITCH_MODE_VEB	0x1
1376 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA	0x2
1377 
1378 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK	0x1
1379 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET	0
1380 
1381 #define DRV_MB_PARAM_SET_LED_MODE_OPER		0x0
1382 #define DRV_MB_PARAM_SET_LED_MODE_ON		0x1
1383 #define DRV_MB_PARAM_SET_LED_MODE_OFF		0x2
1384 
1385 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET			0
1386 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK			0x00000003
1387 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET			2
1388 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK			0x000000fc
1389 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET		8
1390 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK		0x0000ff00
1391 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET			16
1392 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK			0xffff0000
1393 
1394 	/* Resource Allocation params - Driver version support */
1395 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK		0xffff0000
1396 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT		16
1397 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK		0x0000ffff
1398 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
1399 
1400 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST				0
1401 #define DRV_MB_PARAM_BIST_REGISTER_TEST				1
1402 #define DRV_MB_PARAM_BIST_CLOCK_TEST				2
1403 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES			3
1404 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX		4
1405 
1406 #define DRV_MB_PARAM_BIST_RC_UNKNOWN				0
1407 #define DRV_MB_PARAM_BIST_RC_PASSED				1
1408 #define DRV_MB_PARAM_BIST_RC_FAILED				2
1409 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER			3
1410 
1411 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT			0
1412 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK			0x000000ff
1413 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT		8
1414 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK			0x0000ff00
1415 
1416 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK			0x0000ffff
1417 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET		0
1418 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ		0x00000001
1419 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE			0x00000002
1420 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL		0x00000004
1421 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL	0x00000008
1422 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK			0x00010000
1423 
1424 /* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */
1425 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET		0
1426 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK			0xff
1427 
1428 /* Driver attributes params */
1429 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET			0
1430 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK				0x00ffffff
1431 #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET			24
1432 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK				0xff000000
1433 
1434 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET			0
1435 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK			0x0000ffff
1436 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_IGNORE			0x0000ffff
1437 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT			0
1438 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT			16
1439 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK			0x00010000
1440 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT			17
1441 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK			0x00020000
1442 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT		18
1443 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK			0x00040000
1444 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT			19
1445 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK			0x00080000
1446 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT		20
1447 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK		0x00100000
1448 #define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_SHIFT	21
1449 #define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_MASK 0x00200000
1450 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT		24
1451 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK		0x0f000000
1452 
1453 /*DRV_MSG_CODE_GET_PERM_MAC parametres*/
1454 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_SHIFT		0
1455 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MASK		0xF
1456 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_PF		0
1457 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_BMC		1
1458 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_VF		2
1459 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_LLDP		3
1460 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MAX		4
1461 #define DRV_MSG_CODE_GET_PERM_MAC_INDEX_SHIFT		8
1462 #define DRV_MSG_CODE_GET_PERM_MAC_INDEX_MASK		0xFFFF00
1463 
1464 #define FW_MSG_CODE(_code_)    ((_code_) << FW_MSG_CODE_OFFSET)
1465 enum fw_msg_code_enum {
1466 	FW_MSG_CODE_UNSUPPORTED = FW_MSG_CODE(0x0000),
1467 	FW_MSG_CODE_NVM_OK = FW_MSG_CODE(0x0001),
1468 	FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK = FW_MSG_CODE(0x0040),
1469 	FW_MSG_CODE_PHY_OK = FW_MSG_CODE(0x0011),
1470 	FW_MSG_CODE_OK = FW_MSG_CODE(0x0016),
1471 	FW_MSG_CODE_ERROR = FW_MSG_CODE(0x0017),
1472 	FW_MSG_CODE_TRANSCEIVER_DIAG_OK = FW_MSG_CODE(0x0016),
1473 	FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT = FW_MSG_CODE(0x0002),
1474 	FW_MSG_CODE_MDUMP_INVALID_CMD = FW_MSG_CODE(0x0003),
1475 	FW_MSG_CODE_OS_WOL_SUPPORTED = FW_MSG_CODE(0x0080),
1476 	FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE = FW_MSG_CODE(0x0087),
1477 	FW_MSG_CODE_DRV_LOAD_ENGINE = FW_MSG_CODE(0x1010),
1478 	FW_MSG_CODE_DRV_LOAD_PORT = FW_MSG_CODE(0x1011),
1479 	FW_MSG_CODE_DRV_LOAD_FUNCTION = FW_MSG_CODE(0x1012),
1480 	FW_MSG_CODE_DRV_LOAD_REFUSED_PDA = FW_MSG_CODE(0x1020),
1481 	FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 = FW_MSG_CODE(0x1021),
1482 	FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG = FW_MSG_CODE(0x1022),
1483 	FW_MSG_CODE_DRV_LOAD_REFUSED_HSI = FW_MSG_CODE(0x1023),
1484 	FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE = FW_MSG_CODE(0x1030),
1485 	FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT = FW_MSG_CODE(0x1031),
1486 	FW_MSG_CODE_DRV_LOAD_DONE = FW_MSG_CODE(0x1110),
1487 	FW_MSG_CODE_DRV_UNLOAD_ENGINE = FW_MSG_CODE(0x2011),
1488 	FW_MSG_CODE_DRV_UNLOAD_PORT = FW_MSG_CODE(0x2012),
1489 	FW_MSG_CODE_DRV_UNLOAD_FUNCTION = FW_MSG_CODE(0x2013),
1490 	FW_MSG_CODE_DRV_UNLOAD_DONE = FW_MSG_CODE(0x2110),
1491 	FW_MSG_CODE_RESOURCE_ALLOC_OK = FW_MSG_CODE(0x3400),
1492 	FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN = FW_MSG_CODE(0x3500),
1493 	FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE = FW_MSG_CODE(0x3b00),
1494 	FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE = FW_MSG_CODE(0xb001),
1495 	FW_MSG_CODE_DEBUG_NOT_ENABLED = FW_MSG_CODE(0xb00a),
1496 	FW_MSG_CODE_DEBUG_DATA_SEND_OK = FW_MSG_CODE(0xb00b),
1497 };
1498 
1499 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK		0xffff0000
1500 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT		16
1501 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK		0x0000ffff
1502 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
1503 
1504 /* Get PF RDMA protocol command response */
1505 #define FW_MB_PARAM_GET_PF_RDMA_NONE				0x0
1506 #define FW_MB_PARAM_GET_PF_RDMA_ROCE				0x1
1507 #define FW_MB_PARAM_GET_PF_RDMA_IWARP				0x2
1508 #define FW_MB_PARAM_GET_PF_RDMA_BOTH				0x3
1509 
1510 /* Get MFW feature support response */
1511 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ			BIT(0)
1512 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE				BIT(1)
1513 #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO			BIT(2)
1514 #define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET			BIT(3)
1515 #define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD			BIT(4)
1516 #define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL			BIT(5)
1517 #define FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL	BIT(6)
1518 #define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP			BIT(7)
1519 #define FW_MB_PARAM_FEATURE_SUPPORT_VF_DPM			BIT(8)
1520 #define FW_MB_PARAM_FEATURE_SUPPORT_IDLE_CHK			BIT(9)
1521 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK			BIT(16)
1522 #define FW_MB_PARAM_FEATURE_SUPPORT_DISABLE_LLDP		BIT(17)
1523 #define FW_MB_PARAM_FEATURE_SUPPORT_ENHANCED_SYS_LCK		BIT(18)
1524 #define FW_MB_PARAM_FEATURE_SUPPORT_RESTORE_DEFAULT_CFG		BIT(19)
1525 
1526 #define FW_MB_PARAM_MANAGEMENT_STATUS_LOCKDOWN_ENABLED		0x00000001
1527 
1528 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR			BIT(0)
1529 
1530 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK		0x00000001
1531 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT		0
1532 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK		0x00000002
1533 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT		1
1534 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK			0x00000004
1535 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT		2
1536 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK			0x00000008
1537 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT		3
1538 
1539 #define FW_MB_PARAM_PPFID_BITMAP_MASK				0xff
1540 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT				0
1541 
1542 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK		0x00ffffff
1543 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT		0
1544 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK			0xff000000
1545 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT			24
1546 
1547 enum MFW_DRV_MSG_TYPE {
1548 	MFW_DRV_MSG_LINK_CHANGE,
1549 	MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1550 	MFW_DRV_MSG_VF_DISABLED,
1551 	MFW_DRV_MSG_LLDP_DATA_UPDATED,
1552 	MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1553 	MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1554 	MFW_DRV_MSG_ERROR_RECOVERY,
1555 	MFW_DRV_MSG_BW_UPDATE,
1556 	MFW_DRV_MSG_S_TAG_UPDATE,
1557 	MFW_DRV_MSG_GET_LAN_STATS,
1558 	MFW_DRV_MSG_GET_FCOE_STATS,
1559 	MFW_DRV_MSG_GET_ISCSI_STATS,
1560 	MFW_DRV_MSG_GET_RDMA_STATS,
1561 	MFW_DRV_MSG_FAILURE_DETECTED,
1562 	MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1563 	MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
1564 	MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE,
1565 	MFW_DRV_MSG_GET_TLV_REQ,
1566 	MFW_DRV_MSG_OEM_CFG_UPDATE,
1567 	MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED,
1568 	MFW_DRV_MSG_GENERIC_IDC,
1569 	MFW_DRV_MSG_XCVR_TX_FAULT,
1570 	MFW_DRV_MSG_XCVR_RX_LOS,
1571 	MFW_DRV_MSG_GET_FCOE_CAP,
1572 	MFW_DRV_MSG_GEN_LINK_DUMP,
1573 	MFW_DRV_MSG_GEN_IDLE_CHK,
1574 	MFW_DRV_MSG_DCBX_ADMIN_CFG_APPLIED,
1575 	MFW_DRV_MSG_MAX
1576 };
1577 
1578 #define MFW_DRV_MSG_MAX_DWORDS(msgs)	((((msgs) - 1) >> 2) + 1)
1579 #define MFW_DRV_MSG_DWORD(msg_id)	((msg_id) >> 2)
1580 #define MFW_DRV_MSG_OFFSET(msg_id)	(((msg_id) & 0x3) << 3)
1581 #define MFW_DRV_MSG_MASK(msg_id)	(0xff << MFW_DRV_MSG_OFFSET(msg_id))
1582 
1583 struct public_mfw_mb {
1584 	u32 sup_msgs;
1585 	u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1586 	u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
1587 };
1588 
1589 enum public_sections {
1590 	PUBLIC_DRV_MB,
1591 	PUBLIC_MFW_MB,
1592 	PUBLIC_GLOBAL,
1593 	PUBLIC_PATH,
1594 	PUBLIC_PORT,
1595 	PUBLIC_FUNC,
1596 	PUBLIC_MAX_SECTIONS
1597 };
1598 
1599 struct drv_ver_info_stc {
1600 	u32 ver;
1601 	u8 name[32];
1602 };
1603 
1604 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1605  * Please make sure data does not exceed this size.
1606  */
1607 #define NUM_RUNTIME_DWORDS    16
1608 struct drv_init_hw_stc {
1609 	u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1610 	u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1611 };
1612 
1613 struct mcp_public_data {
1614 	u32 num_sections;
1615 	u32 sections[PUBLIC_MAX_SECTIONS];
1616 	struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1617 	struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1618 	struct public_global global;
1619 	struct public_path path[MCP_GLOB_PATH_MAX];
1620 	struct public_port port[MCP_GLOB_PORT_MAX];
1621 	struct public_func func[MCP_GLOB_FUNC_MAX];
1622 };
1623 
1624 #define I2C_TRANSCEIVER_ADDR		0xa0
1625 #define MAX_I2C_TRANSACTION_SIZE	16
1626 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE	256
1627 
1628 /* OCBB definitions */
1629 enum tlvs {
1630 	/* Category 1: Device Properties */
1631 	DRV_TLV_CLP_STR,
1632 	DRV_TLV_CLP_STR_CTD,
1633 	/* Category 6: Device Configuration */
1634 	DRV_TLV_SCSI_TO,
1635 	DRV_TLV_R_T_TOV,
1636 	DRV_TLV_R_A_TOV,
1637 	DRV_TLV_E_D_TOV,
1638 	DRV_TLV_CR_TOV,
1639 	DRV_TLV_BOOT_TYPE,
1640 	/* Category 8: Port Configuration */
1641 	DRV_TLV_NPIV_ENABLED,
1642 	/* Category 10: Function Configuration */
1643 	DRV_TLV_FEATURE_FLAGS,
1644 	DRV_TLV_LOCAL_ADMIN_ADDR,
1645 	DRV_TLV_ADDITIONAL_MAC_ADDR_1,
1646 	DRV_TLV_ADDITIONAL_MAC_ADDR_2,
1647 	DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
1648 	DRV_TLV_LSO_MIN_SEGMENT_COUNT,
1649 	DRV_TLV_PROMISCUOUS_MODE,
1650 	DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
1651 	DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
1652 	DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
1653 	DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
1654 	DRV_TLV_OS_DRIVER_STATES,
1655 	DRV_TLV_PXE_BOOT_PROGRESS,
1656 	/* Category 12: FC/FCoE Configuration */
1657 	DRV_TLV_NPIV_STATE,
1658 	DRV_TLV_NUM_OF_NPIV_IDS,
1659 	DRV_TLV_SWITCH_NAME,
1660 	DRV_TLV_SWITCH_PORT_NUM,
1661 	DRV_TLV_SWITCH_PORT_ID,
1662 	DRV_TLV_VENDOR_NAME,
1663 	DRV_TLV_SWITCH_MODEL,
1664 	DRV_TLV_SWITCH_FW_VER,
1665 	DRV_TLV_QOS_PRIORITY_PER_802_1P,
1666 	DRV_TLV_PORT_ALIAS,
1667 	DRV_TLV_PORT_STATE,
1668 	DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
1669 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
1670 	DRV_TLV_LINK_FAILURE_COUNT,
1671 	DRV_TLV_FCOE_BOOT_PROGRESS,
1672 	/* Category 13: iSCSI Configuration */
1673 	DRV_TLV_TARGET_LLMNR_ENABLED,
1674 	DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
1675 	DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
1676 	DRV_TLV_AUTHENTICATION_METHOD,
1677 	DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
1678 	DRV_TLV_MAX_FRAME_SIZE,
1679 	DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
1680 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
1681 	DRV_TLV_ISCSI_BOOT_PROGRESS,
1682 	/* Category 20: Device Data */
1683 	DRV_TLV_PCIE_BUS_RX_UTILIZATION,
1684 	DRV_TLV_PCIE_BUS_TX_UTILIZATION,
1685 	DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
1686 	DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
1687 	DRV_TLV_NCSI_RX_BYTES_RECEIVED,
1688 	DRV_TLV_NCSI_TX_BYTES_SENT,
1689 	/* Category 22: Base Port Data */
1690 	DRV_TLV_RX_DISCARDS,
1691 	DRV_TLV_RX_ERRORS,
1692 	DRV_TLV_TX_ERRORS,
1693 	DRV_TLV_TX_DISCARDS,
1694 	DRV_TLV_RX_FRAMES_RECEIVED,
1695 	DRV_TLV_TX_FRAMES_SENT,
1696 	/* Category 23: FC/FCoE Port Data */
1697 	DRV_TLV_RX_BROADCAST_PACKETS,
1698 	DRV_TLV_TX_BROADCAST_PACKETS,
1699 	/* Category 28: Base Function Data */
1700 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
1701 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
1702 	DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1703 	DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1704 	DRV_TLV_PF_RX_FRAMES_RECEIVED,
1705 	DRV_TLV_RX_BYTES_RECEIVED,
1706 	DRV_TLV_PF_TX_FRAMES_SENT,
1707 	DRV_TLV_TX_BYTES_SENT,
1708 	DRV_TLV_IOV_OFFLOAD,
1709 	DRV_TLV_PCI_ERRORS_CAP_ID,
1710 	DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
1711 	DRV_TLV_UNCORRECTABLE_ERROR_MASK,
1712 	DRV_TLV_CORRECTABLE_ERROR_STATUS,
1713 	DRV_TLV_CORRECTABLE_ERROR_MASK,
1714 	DRV_TLV_PCI_ERRORS_AECC_REGISTER,
1715 	DRV_TLV_TX_QUEUES_EMPTY,
1716 	DRV_TLV_RX_QUEUES_EMPTY,
1717 	DRV_TLV_TX_QUEUES_FULL,
1718 	DRV_TLV_RX_QUEUES_FULL,
1719 	/* Category 29: FC/FCoE Function Data */
1720 	DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1721 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1722 	DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
1723 	DRV_TLV_FCOE_RX_BYTES_RECEIVED,
1724 	DRV_TLV_FCOE_TX_FRAMES_SENT,
1725 	DRV_TLV_FCOE_TX_BYTES_SENT,
1726 	DRV_TLV_CRC_ERROR_COUNT,
1727 	DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
1728 	DRV_TLV_CRC_ERROR_1_TIMESTAMP,
1729 	DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
1730 	DRV_TLV_CRC_ERROR_2_TIMESTAMP,
1731 	DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
1732 	DRV_TLV_CRC_ERROR_3_TIMESTAMP,
1733 	DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
1734 	DRV_TLV_CRC_ERROR_4_TIMESTAMP,
1735 	DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
1736 	DRV_TLV_CRC_ERROR_5_TIMESTAMP,
1737 	DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
1738 	DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
1739 	DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
1740 	DRV_TLV_DISPARITY_ERROR_COUNT,
1741 	DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
1742 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
1743 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
1744 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
1745 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
1746 	DRV_TLV_LAST_FLOGI_TIMESTAMP,
1747 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
1748 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
1749 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
1750 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
1751 	DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
1752 	DRV_TLV_LAST_FLOGI_RJT,
1753 	DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
1754 	DRV_TLV_FDISCS_SENT_COUNT,
1755 	DRV_TLV_FDISC_ACCS_RECEIVED,
1756 	DRV_TLV_FDISC_RJTS_RECEIVED,
1757 	DRV_TLV_PLOGI_SENT_COUNT,
1758 	DRV_TLV_PLOGI_ACCS_RECEIVED,
1759 	DRV_TLV_PLOGI_RJTS_RECEIVED,
1760 	DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
1761 	DRV_TLV_PLOGI_1_TIMESTAMP,
1762 	DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
1763 	DRV_TLV_PLOGI_2_TIMESTAMP,
1764 	DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
1765 	DRV_TLV_PLOGI_3_TIMESTAMP,
1766 	DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
1767 	DRV_TLV_PLOGI_4_TIMESTAMP,
1768 	DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
1769 	DRV_TLV_PLOGI_5_TIMESTAMP,
1770 	DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
1771 	DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
1772 	DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
1773 	DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
1774 	DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
1775 	DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
1776 	DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
1777 	DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
1778 	DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
1779 	DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
1780 	DRV_TLV_LOGOS_ISSUED,
1781 	DRV_TLV_LOGO_ACCS_RECEIVED,
1782 	DRV_TLV_LOGO_RJTS_RECEIVED,
1783 	DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
1784 	DRV_TLV_LOGO_1_TIMESTAMP,
1785 	DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
1786 	DRV_TLV_LOGO_2_TIMESTAMP,
1787 	DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
1788 	DRV_TLV_LOGO_3_TIMESTAMP,
1789 	DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
1790 	DRV_TLV_LOGO_4_TIMESTAMP,
1791 	DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
1792 	DRV_TLV_LOGO_5_TIMESTAMP,
1793 	DRV_TLV_LOGOS_RECEIVED,
1794 	DRV_TLV_ACCS_ISSUED,
1795 	DRV_TLV_PRLIS_ISSUED,
1796 	DRV_TLV_ACCS_RECEIVED,
1797 	DRV_TLV_ABTS_SENT_COUNT,
1798 	DRV_TLV_ABTS_ACCS_RECEIVED,
1799 	DRV_TLV_ABTS_RJTS_RECEIVED,
1800 	DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
1801 	DRV_TLV_ABTS_1_TIMESTAMP,
1802 	DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
1803 	DRV_TLV_ABTS_2_TIMESTAMP,
1804 	DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
1805 	DRV_TLV_ABTS_3_TIMESTAMP,
1806 	DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
1807 	DRV_TLV_ABTS_4_TIMESTAMP,
1808 	DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
1809 	DRV_TLV_ABTS_5_TIMESTAMP,
1810 	DRV_TLV_RSCNS_RECEIVED,
1811 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
1812 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
1813 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
1814 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
1815 	DRV_TLV_LUN_RESETS_ISSUED,
1816 	DRV_TLV_ABORT_TASK_SETS_ISSUED,
1817 	DRV_TLV_TPRLOS_SENT,
1818 	DRV_TLV_NOS_SENT_COUNT,
1819 	DRV_TLV_NOS_RECEIVED_COUNT,
1820 	DRV_TLV_OLS_COUNT,
1821 	DRV_TLV_LR_COUNT,
1822 	DRV_TLV_LRR_COUNT,
1823 	DRV_TLV_LIP_SENT_COUNT,
1824 	DRV_TLV_LIP_RECEIVED_COUNT,
1825 	DRV_TLV_EOFA_COUNT,
1826 	DRV_TLV_EOFNI_COUNT,
1827 	DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
1828 	DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
1829 	DRV_TLV_SCSI_STATUS_BUSY_COUNT,
1830 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
1831 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
1832 	DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
1833 	DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
1834 	DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
1835 	DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
1836 	DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
1837 	DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
1838 	DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
1839 	DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
1840 	DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
1841 	DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
1842 	DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
1843 	DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
1844 	DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
1845 	DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
1846 	/* Category 30: iSCSI Function Data */
1847 	DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1848 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1849 	DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
1850 	DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
1851 	DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
1852 	DRV_TLV_ISCSI_PDU_TX_BYTES_SENT,
1853 	DRV_TLV_RDMA_DRV_VERSION
1854 };
1855 
1856 #define I2C_DEV_ADDR_A2				0xa2
1857 #define SFP_EEPROM_A2_TEMPERATURE_ADDR		0x60
1858 #define SFP_EEPROM_A2_TEMPERATURE_SIZE		2
1859 #define SFP_EEPROM_A2_VCC_ADDR			0x62
1860 #define SFP_EEPROM_A2_VCC_SIZE			2
1861 #define SFP_EEPROM_A2_TX_BIAS_ADDR		0x64
1862 #define SFP_EEPROM_A2_TX_BIAS_SIZE		2
1863 #define SFP_EEPROM_A2_TX_POWER_ADDR		0x66
1864 #define SFP_EEPROM_A2_TX_POWER_SIZE		2
1865 #define SFP_EEPROM_A2_RX_POWER_ADDR		0x68
1866 #define SFP_EEPROM_A2_RX_POWER_SIZE		2
1867 
1868 #define I2C_DEV_ADDR_A0				0xa0
1869 #define QSFP_EEPROM_A0_TEMPERATURE_ADDR		0x16
1870 #define QSFP_EEPROM_A0_TEMPERATURE_SIZE		2
1871 #define QSFP_EEPROM_A0_VCC_ADDR			0x1a
1872 #define QSFP_EEPROM_A0_VCC_SIZE			2
1873 #define QSFP_EEPROM_A0_TX1_BIAS_ADDR		0x2a
1874 #define QSFP_EEPROM_A0_TX1_BIAS_SIZE		2
1875 #define QSFP_EEPROM_A0_TX1_POWER_ADDR		0x32
1876 #define QSFP_EEPROM_A0_TX1_POWER_SIZE		2
1877 #define QSFP_EEPROM_A0_RX1_POWER_ADDR		0x22
1878 #define QSFP_EEPROM_A0_RX1_POWER_SIZE		2
1879 
1880 struct nvm_cfg_mac_address {
1881 	u32 mac_addr_hi;
1882 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff
1883 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
1884 
1885 	u32 mac_addr_lo;
1886 };
1887 
1888 struct nvm_cfg1_glob {
1889 	u32 generic_cont0;
1890 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0
1891 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
1892 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
1893 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
1894 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
1895 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
1896 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
1897 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
1898 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
1899 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
1900 
1901 	u32 engineering_change[3];
1902 	u32 manufacturing_id;
1903 	u32 serial_number[4];
1904 	u32 pcie_cfg;
1905 	u32 mgmt_traffic;
1906 
1907 	u32 core_cfg;
1908 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff
1909 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
1910 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
1911 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
1912 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
1913 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
1914 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
1915 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
1916 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb
1917 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc
1918 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd
1919 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe
1920 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf
1921 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1 0x11
1922 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1 0x12
1923 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2 0x13
1924 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2 0x14
1925 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4 0x15
1926 
1927 	u32 e_lane_cfg1;
1928 	u32 e_lane_cfg2;
1929 	u32 f_lane_cfg1;
1930 	u32 f_lane_cfg2;
1931 	u32 mps10_preemphasis;
1932 	u32 mps10_driver_current;
1933 	u32 mps25_preemphasis;
1934 	u32 mps25_driver_current;
1935 	u32 pci_id;
1936 	u32 pci_subsys_id;
1937 	u32 bar;
1938 	u32 mps10_txfir_main;
1939 	u32 mps10_txfir_post;
1940 	u32 mps25_txfir_main;
1941 	u32 mps25_txfir_post;
1942 	u32 manufacture_ver;
1943 	u32 manufacture_time;
1944 	u32 led_global_settings;
1945 	u32 generic_cont1;
1946 
1947 	u32 mbi_version;
1948 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff
1949 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
1950 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00
1951 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
1952 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000
1953 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
1954 
1955 	u32 mbi_date;
1956 	u32 misc_sig;
1957 
1958 	u32 device_capabilities;
1959 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
1960 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
1961 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
1962 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
1963 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
1964 
1965 	u32 power_dissipated;
1966 	u32 power_consumed;
1967 	u32 efi_version;
1968 	u32 multi_network_modes_capability;
1969 	u32 nvm_cfg_version;
1970 	u32 nvm_cfg_new_option_seq;
1971 	u32 nvm_cfg_removed_option_seq;
1972 	u32 nvm_cfg_updated_value_seq;
1973 	u32 extended_serial_number[8];
1974 	u32 option_kit_pn[8];
1975 	u32 spare_pn[8];
1976 	u32 mps25_active_txfir_pre;
1977 	u32 mps25_active_txfir_main;
1978 	u32 mps25_active_txfir_post;
1979 	u32 features;
1980 	u32 tx_rx_eq_25g_hlpc;
1981 	u32 tx_rx_eq_25g_llpc;
1982 	u32 tx_rx_eq_25g_ac;
1983 	u32 tx_rx_eq_10g_pc;
1984 	u32 tx_rx_eq_10g_ac;
1985 	u32 tx_rx_eq_1g;
1986 	u32 tx_rx_eq_25g_bt;
1987 	u32 tx_rx_eq_10g_bt;
1988 	u32 generic_cont4;
1989 	u32 preboot_debug_mode_std;
1990 	u32 preboot_debug_mode_ext;
1991 	u32 ext_phy_cfg1;
1992 	u32 clocks;
1993 	u32 pre2_generic_cont_1;
1994 	u32 pre2_generic_cont_2;
1995 	u32 pre2_generic_cont_3;
1996 	u32 tx_rx_eq_50g_hlpc;
1997 	u32 tx_rx_eq_50g_mlpc;
1998 	u32 tx_rx_eq_50g_llpc;
1999 	u32 tx_rx_eq_50g_ac;
2000 	u32 trace_modules;
2001 	u32 pcie_class_code_fcoe;
2002 	u32 pcie_class_code_iscsi;
2003 	u32 no_provisioned_mac;
2004 	u32 lowest_mbi_version;
2005 	u32 generic_cont5;
2006 	u32 pre2_generic_cont_4;
2007 	u32 reserved[40];
2008 };
2009 
2010 struct nvm_cfg1_path {
2011 	u32 reserved[1];
2012 };
2013 
2014 struct nvm_cfg1_port {
2015 	u32 rel_to_opt123;
2016 	u32 rel_to_opt124;
2017 
2018 	u32 generic_cont0;
2019 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000
2020 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
2021 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
2022 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
2023 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
2024 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
2025 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000
2026 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
2027 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
2028 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
2029 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
2030 
2031 	u32 pcie_cfg;
2032 	u32 features;
2033 
2034 	u32 speed_cap_mask;
2035 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff
2036 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
2037 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
2038 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
2039 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
2040 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
2041 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
2042 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
2043 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
2044 
2045 	u32 link_settings;
2046 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f
2047 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
2048 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
2049 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
2050 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
2051 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
2052 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
2053 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
2054 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
2055 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
2056 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
2057 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
2058 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
2059 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
2060 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
2061 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
2062 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000e0000
2063 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
2064 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
2065 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
2066 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
2067 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
2068 
2069 	u32 phy_cfg;
2070 	u32 mgmt_traffic;
2071 
2072 	u32 ext_phy;
2073 	/* EEE power saving mode */
2074 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000
2075 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
2076 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
2077 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
2078 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
2079 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
2080 
2081 	u32 mba_cfg1;
2082 	u32 mba_cfg2;
2083 	u32							vf_cfg;
2084 	struct nvm_cfg_mac_address lldp_mac_address;
2085 	u32 led_port_settings;
2086 	u32 transceiver_00;
2087 	u32 device_ids;
2088 
2089 	u32 board_cfg;
2090 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff
2091 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
2092 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
2093 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
2094 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
2095 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
2096 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
2097 
2098 	u32 mnm_10g_cap;
2099 	u32 mnm_10g_ctrl;
2100 	u32 mnm_10g_misc;
2101 	u32 mnm_25g_cap;
2102 	u32 mnm_25g_ctrl;
2103 	u32 mnm_25g_misc;
2104 	u32 mnm_40g_cap;
2105 	u32 mnm_40g_ctrl;
2106 	u32 mnm_40g_misc;
2107 	u32 mnm_50g_cap;
2108 	u32 mnm_50g_ctrl;
2109 	u32 mnm_50g_misc;
2110 	u32 mnm_100g_cap;
2111 	u32 mnm_100g_ctrl;
2112 	u32 mnm_100g_misc;
2113 
2114 	u32 temperature;
2115 	u32 ext_phy_cfg1;
2116 
2117 	u32 extended_speed;
2118 #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000ffff
2119 #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
2120 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN 0x1
2121 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
2122 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
2123 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G 0x8
2124 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x10
2125 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x20
2126 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x40
2127 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x80
2128 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x100
2129 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x200
2130 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x400
2131 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xffff0000
2132 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16
2133 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED 0x1
2134 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
2135 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
2136 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G 0x8
2137 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x10
2138 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x20
2139 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x40
2140 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x80
2141 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x100
2142 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x200
2143 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x400
2144 
2145 	u32 extended_fec_mode;
2146 	u32 port_generic_cont_01;
2147 	u32 port_generic_cont_02;
2148 	u32 phy_temp_monitor;
2149 	u32 reserved[109];
2150 };
2151 
2152 struct nvm_cfg1_func {
2153 	struct nvm_cfg_mac_address mac_address;
2154 	u32 rsrv1;
2155 	u32 rsrv2;
2156 	u32 device_id;
2157 	u32 cmn_cfg;
2158 	u32 pci_cfg;
2159 	struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
2160 	struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
2161 	u32 preboot_generic_cfg;
2162 	u32 features;
2163 	u32 mf_mode_feature;
2164 	u32 reserved[6];
2165 };
2166 
2167 struct nvm_cfg1 {
2168 	struct nvm_cfg1_glob glob;
2169 	struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
2170 	struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
2171 	struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
2172 };
2173 
2174 struct board_info {
2175 	u16 vendor_id;
2176 	u16 eth_did_suffix;
2177 	u16 sub_vendor_id;
2178 	u16 sub_device_id;
2179 	char *board_name;
2180 	char *friendly_name;
2181 };
2182 
2183 struct trace_module_info {
2184 	char *module_name;
2185 };
2186 
2187 #define NUM_TRACE_MODULES    25
2188 
2189 enum nvm_cfg_sections {
2190 	NVM_CFG_SECTION_NVM_CFG1,
2191 	NVM_CFG_SECTION_MAX
2192 };
2193 
2194 struct nvm_cfg {
2195 	u32 num_sections;
2196 	u32 sections_offset[NVM_CFG_SECTION_MAX];
2197 	struct nvm_cfg1 cfg1;
2198 };
2199 
2200 #define PORT_0		0
2201 #define PORT_1		1
2202 #define PORT_2		2
2203 #define PORT_3		3
2204 
2205 extern struct spad_layout g_spad;
2206 struct spad_layout {
2207 	struct nvm_cfg nvm_cfg;
2208 	struct mcp_public_data public_data;
2209 };
2210 
2211 #define MCP_SPAD_SIZE    0x00028000	/* 160 KB */
2212 
2213 #define SPAD_OFFSET(addr)    (((u32)(addr) - (u32)CPU_SPAD_BASE))
2214 
2215 #define TO_OFFSIZE(_offset, _size)                               \
2216 		((u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_OFFSET) | \
2217 		 (((u32)(_size) >> 2) << OFFSIZE_SIZE_OFFSET)))
2218 
2219 enum spad_sections {
2220 	SPAD_SECTION_TRACE,
2221 	SPAD_SECTION_NVM_CFG,
2222 	SPAD_SECTION_PUBLIC,
2223 	SPAD_SECTION_PRIVATE,
2224 	SPAD_SECTION_MAX
2225 };
2226 
2227 #define STRUCT_OFFSET(f)    (STATIC_INIT_BASE + \
2228 			     __builtin_offsetof(struct static_init, f))
2229 
2230 /* This section is located at a fixed location in the beginning of the
2231  * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
2232  * All the rest of data has a floating location which differs from version to
2233  * version, and is pointed by the mcp_meta_data below.
2234  * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
2235  * with it from nvram in order to clear this portion.
2236  */
2237 struct static_init {
2238 	u32 num_sections;
2239 	offsize_t sections[SPAD_SECTION_MAX];
2240 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
2241 
2242 	u32 tim_hash[8];
2243 #define PRESERVED_TIM_HASH	((u8 *)(STRUCT_OFFSET(tim_hash)))
2244 	u32 tpu_hash[8];
2245 #define PRESERVED_TPU_HASH	((u8 *)(STRUCT_OFFSET(tpu_hash)))
2246 	u32 secure_pcie_fw_ver;
2247 #define SECURE_PCIE_FW_VER	(*((u32 *)(STRUCT_OFFSET(secure_pcie_fw_ver))))
2248 	u32 secure_running_mfw;
2249 #define SECURE_RUNNING_MFW	(*((u32 *)(STRUCT_OFFSET(secure_running_mfw))))
2250 	struct mcp_trace trace;
2251 };
2252 
2253 #define CRC_MAGIC_VALUE		0xDEBB20E3
2254 #define CRC32_POLYNOMIAL	0xEDB88320
2255 #define _KB(x)			((x) * 1024)
2256 #define _MB(x)			(_KB(x) * 1024)
2257 #define NVM_CRC_SIZE		(sizeof(u32))
2258 enum nvm_sw_arbitrator {
2259 	NVM_SW_ARB_HOST,
2260 	NVM_SW_ARB_MCP,
2261 	NVM_SW_ARB_UART,
2262 	NVM_SW_ARB_RESERVED
2263 };
2264 
2265 struct legacy_bootstrap_region {
2266 	u32 magic_value;
2267 #define NVM_MAGIC_VALUE    0x669955aa
2268 	u32 sram_start_addr;
2269 	u32 code_len;
2270 	u32 code_start_addr;
2271 	u32 crc;
2272 };
2273 
2274 struct nvm_code_entry {
2275 	u32 image_type;
2276 	u32 nvm_start_addr;
2277 	u32 len;
2278 	u32 sram_start_addr;
2279 	u32 sram_run_addr;
2280 };
2281 
2282 enum nvm_image_type {
2283 	NVM_TYPE_TIM1 = 0x01,
2284 	NVM_TYPE_TIM2 = 0x02,
2285 	NVM_TYPE_MIM1 = 0x03,
2286 	NVM_TYPE_MIM2 = 0x04,
2287 	NVM_TYPE_MBA = 0x05,
2288 	NVM_TYPE_MODULES_PN = 0x06,
2289 	NVM_TYPE_VPD = 0x07,
2290 	NVM_TYPE_MFW_TRACE1 = 0x08,
2291 	NVM_TYPE_MFW_TRACE2 = 0x09,
2292 	NVM_TYPE_NVM_CFG1 = 0x0a,
2293 	NVM_TYPE_L2B = 0x0b,
2294 	NVM_TYPE_DIR1 = 0x0c,
2295 	NVM_TYPE_EAGLE_FW1 = 0x0d,
2296 	NVM_TYPE_FALCON_FW1 = 0x0e,
2297 	NVM_TYPE_PCIE_FW1 = 0x0f,
2298 	NVM_TYPE_HW_SET = 0x10,
2299 	NVM_TYPE_LIM = 0x11,
2300 	NVM_TYPE_AVS_FW1 = 0x12,
2301 	NVM_TYPE_DIR2 = 0x13,
2302 	NVM_TYPE_CCM = 0x14,
2303 	NVM_TYPE_EAGLE_FW2 = 0x15,
2304 	NVM_TYPE_FALCON_FW2 = 0x16,
2305 	NVM_TYPE_PCIE_FW2 = 0x17,
2306 	NVM_TYPE_AVS_FW2 = 0x18,
2307 	NVM_TYPE_INIT_HW = 0x19,
2308 	NVM_TYPE_DEFAULT_CFG = 0x1a,
2309 	NVM_TYPE_MDUMP = 0x1b,
2310 	NVM_TYPE_NVM_META = 0x1c,
2311 	NVM_TYPE_ISCSI_CFG = 0x1d,
2312 	NVM_TYPE_FCOE_CFG = 0x1f,
2313 	NVM_TYPE_ETH_PHY_FW1 = 0x20,
2314 	NVM_TYPE_ETH_PHY_FW2 = 0x21,
2315 	NVM_TYPE_BDN = 0x22,
2316 	NVM_TYPE_8485X_PHY_FW = 0x23,
2317 	NVM_TYPE_PUB_KEY = 0x24,
2318 	NVM_TYPE_RECOVERY = 0x25,
2319 	NVM_TYPE_PLDM = 0x26,
2320 	NVM_TYPE_UPK1 = 0x27,
2321 	NVM_TYPE_UPK2 = 0x28,
2322 	NVM_TYPE_MASTER_KC = 0x29,
2323 	NVM_TYPE_BACKUP_KC = 0x2a,
2324 	NVM_TYPE_HW_DUMP = 0x2b,
2325 	NVM_TYPE_HW_DUMP_OUT = 0x2c,
2326 	NVM_TYPE_BIN_NVM_META = 0x30,
2327 	NVM_TYPE_ROM_TEST = 0xf0,
2328 	NVM_TYPE_88X33X0_PHY_FW = 0x31,
2329 	NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
2330 	NVM_TYPE_IDLE_CHK = 0x33,
2331 	NVM_TYPE_MAX,
2332 };
2333 
2334 #define MAX_NVM_DIR_ENTRIES 100
2335 
2336 struct nvm_dir_meta {
2337 	u32 dir_id;
2338 	u32 nvm_dir_addr;
2339 	u32 num_images;
2340 	u32 next_mfw_to_run;
2341 };
2342 
2343 struct nvm_dir {
2344 	s32 seq;
2345 #define NVM_DIR_NEXT_MFW_MASK 0x00000001
2346 #define NVM_DIR_SEQ_MASK 0xfffffffe
2347 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
2348 #define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw)\
2349 	({ \
2350 		_seq =  (((_seq + 2) & \
2351 			 NVM_DIR_SEQ_MASK) | \
2352 			 (NVM_DIR_NEXT_MFW(_seq ^ (swap_mfw))));\
2353 	})
2354 
2355 #define IS_DIR_SEQ_VALID(seq) (((seq) & NVM_DIR_SEQ_MASK) != \
2356 			       NVM_DIR_SEQ_MASK)
2357 
2358 	u32 num_images;
2359 	u32 rsrv;
2360 	struct nvm_code_entry code[1];	/* Up to MAX_NVM_DIR_ENTRIES */
2361 };
2362 
2363 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \
2364 				   ((_num_images) - 1) *\
2365 				   sizeof(struct nvm_code_entry) +\
2366 				   NVM_CRC_SIZE)
2367 
2368 struct nvm_vpd_image {
2369 	u32 format_revision;
2370 #define VPD_IMAGE_VERSION 1
2371 
2372 	u8 vpd_data[1];
2373 };
2374 
2375 #define DIR_ID_1    (0)
2376 #define DIR_ID_2    (1)
2377 #define MAX_DIR_IDS (2)
2378 
2379 #define MFW_BUNDLE_1 (0)
2380 #define MFW_BUNDLE_2 (1)
2381 #define MAX_MFW_BUNDLES (2)
2382 
2383 #define FLASH_PAGE_SIZE 0x1000
2384 #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE)
2385 #define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200))
2386 
2387 #define FPGA_MIM_MAX_SIZE (0x40000)
2388 
2389 #define LIM_MAX_SIZE ((2 * FLASH_PAGE_SIZE) - \
2390 		      sizeof(struct legacy_bootstrap_region) \
2391 		      - NVM_RSV_SIZE)
2392 #define LIM_OFFSET (NVM_OFFSET(lim_image))
2393 #define NVM_RSV_SIZE (44)
2394 #define GET_MIM_MAX_SIZE(is_asic, is_e4) (LEGACY_ASIC_MIM_MAX_SIZE)
2395 #define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES])\
2396 					     + (((idx) == NVM_TYPE_MIM2) ? \
2397 					     GET_MIM_MAX_SIZE(is_asic, is_e4)\
2398 					     : 0))
2399 #define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4)	(sizeof(struct nvm_image) + \
2400 						 GET_MIM_MAX_SIZE(is_asic,\
2401 						is_e4) * 2)
2402 
2403 union nvm_dir_union {
2404 	struct nvm_dir dir;
2405 	u8 page[FLASH_PAGE_SIZE];
2406 };
2407 
2408 struct nvm_image {
2409 	struct legacy_bootstrap_region bootstrap;
2410 	u8 rsrv[NVM_RSV_SIZE];
2411 	u8 lim_image[LIM_MAX_SIZE];
2412 	union nvm_dir_union dir[MAX_MFW_BUNDLES];
2413 };
2414 
2415 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->(f)))))
2416 
2417 struct hw_set_info {
2418 	u32 reg_type;
2419 #define GRC_REG_TYPE 1
2420 #define PHY_REG_TYPE 2
2421 #define PCI_REG_TYPE 4
2422 
2423 	u32 bank_num;
2424 	u32 pf_num;
2425 	u32 operation;
2426 #define READ_OP 1
2427 #define WRITE_OP 2
2428 #define RMW_SET_OP 3
2429 #define RMW_CLR_OP 4
2430 
2431 	u32 reg_addr;
2432 	u32 reg_data;
2433 
2434 	u32 reset_type;
2435 #define POR_RESET_TYPE BIT(0)
2436 #define HARD_RESET_TYPE BIT(1)
2437 #define CORE_RESET_TYPE BIT(2)
2438 #define MCP_RESET_TYPE BIT(3)
2439 #define PERSET_ASSERT BIT(4)
2440 #define PERSET_DEASSERT BIT(5)
2441 };
2442 
2443 struct hw_set_image {
2444 	u32 format_version;
2445 #define HW_SET_IMAGE_VERSION 1
2446 	u32 no_hw_sets;
2447 	struct hw_set_info hw_sets[1];
2448 };
2449 
2450 #define MAX_SUPPORTED_NVM_OPTIONS 1000
2451 
2452 #define NVM_META_BIN_OPTION_OFFSET_MASK 0x0000ffff
2453 #define NVM_META_BIN_OPTION_OFFSET_SHIFT 0
2454 #define NVM_META_BIN_OPTION_LEN_MASK 0x00ff0000
2455 #define NVM_META_BIN_OPTION_LEN_OFFSET 16
2456 #define NVM_META_BIN_OPTION_ENTITY_MASK 0x03000000
2457 #define NVM_META_BIN_OPTION_ENTITY_SHIFT 24
2458 #define NVM_META_BIN_OPTION_ENTITY_GLOB 0
2459 #define NVM_META_BIN_OPTION_ENTITY_PORT 1
2460 #define NVM_META_BIN_OPTION_ENTITY_FUNC 2
2461 #define NVM_META_BIN_OPTION_CONFIG_TYPE_MASK 0x0c000000
2462 #define NVM_META_BIN_OPTION_CONFIG_TYPE_SHIFT 26
2463 #define NVM_META_BIN_OPTION_CONFIG_TYPE_USER 0
2464 #define NVM_META_BIN_OPTION_CONFIG_TYPE_FIXED 1
2465 #define NVM_META_BIN_OPTION_CONFIG_TYPE_FORCED 2
2466 
2467 struct nvm_meta_bin_t {
2468 	u32 magic;
2469 #define NVM_META_BIN_MAGIC 0x669955bb
2470 	u32 version;
2471 #define NVM_META_BIN_VERSION 1
2472 	u32 num_options;
2473 	u32 options[];
2474 };
2475 #endif
2476