1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <linux/workqueue.h>
40 #include <net/addrconf.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_cache.h>
43 #include <rdma/ib_umem.h>
44 #include <rdma/uverbs_ioctl.h>
45
46 #include "hclge_main.h"
47 #include "hns_roce_common.h"
48 #include "hns_roce_device.h"
49 #include "hns_roce_cmd.h"
50 #include "hns_roce_hem.h"
51 #include "hns_roce_hw_v2.h"
52 #include "hns_roce_bond.h"
53
54 #define CREATE_TRACE_POINTS
55 #include "hns_roce_trace.h"
56
57 enum {
58 CMD_RST_PRC_OTHERS,
59 CMD_RST_PRC_SUCCESS,
60 CMD_RST_PRC_EBUSY,
61 };
62
63 enum ecc_resource_type {
64 ECC_RESOURCE_QPC,
65 ECC_RESOURCE_CQC,
66 ECC_RESOURCE_MPT,
67 ECC_RESOURCE_SRQC,
68 ECC_RESOURCE_GMV,
69 ECC_RESOURCE_QPC_TIMER,
70 ECC_RESOURCE_CQC_TIMER,
71 ECC_RESOURCE_SCCC,
72 ECC_RESOURCE_COUNT,
73 };
74
75 static const struct {
76 const char *name;
77 u8 read_bt0_op;
78 u8 write_bt0_op;
79 } fmea_ram_res[] = {
80 { "ECC_RESOURCE_QPC",
81 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
82 { "ECC_RESOURCE_CQC",
83 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
84 { "ECC_RESOURCE_MPT",
85 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
86 { "ECC_RESOURCE_SRQC",
87 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
88 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
89 { "ECC_RESOURCE_GMV",
90 0, 0 },
91 { "ECC_RESOURCE_QPC_TIMER",
92 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
93 { "ECC_RESOURCE_CQC_TIMER",
94 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
95 { "ECC_RESOURCE_SCCC",
96 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
97 };
98
set_data_seg_v2(struct hns_roce_v2_wqe_data_seg * dseg,struct ib_sge * sg)99 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
100 struct ib_sge *sg)
101 {
102 dseg->lkey = cpu_to_le32(sg->lkey);
103 dseg->addr = cpu_to_le64(sg->addr);
104 dseg->len = cpu_to_le32(sg->length);
105 }
106
107 /*
108 * mapped-value = 1 + real-value
109 * The hns wr opcode real value is start from 0, In order to distinguish between
110 * initialized and uninitialized map values, we plus 1 to the actual value when
111 * defining the mapping, so that the validity can be identified by checking the
112 * mapped value is greater than 0.
113 */
114 #define HR_OPC_MAP(ib_key, hr_key) \
115 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
116
117 static const u32 hns_roce_op_code[] = {
118 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
119 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
120 HR_OPC_MAP(SEND, SEND),
121 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
122 HR_OPC_MAP(RDMA_READ, RDMA_READ),
123 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
124 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
125 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
126 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
127 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
128 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
129 };
130
to_hr_opcode(u32 ib_opcode)131 static u32 to_hr_opcode(u32 ib_opcode)
132 {
133 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
134 return HNS_ROCE_V2_WQE_OP_MASK;
135
136 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
137 HNS_ROCE_V2_WQE_OP_MASK;
138 }
139
set_frmr_seg(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_reg_wr * wr)140 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
141 const struct ib_reg_wr *wr)
142 {
143 struct hns_roce_wqe_frmr_seg *fseg =
144 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
145 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
146 u64 pbl_ba;
147
148 /* use ib_access_flags */
149 hr_reg_write_bool(fseg, FRMR_BIND_EN, 0);
150 hr_reg_write_bool(fseg, FRMR_ATOMIC,
151 wr->access & IB_ACCESS_REMOTE_ATOMIC);
152 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
153 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
154 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
155
156 /* Data structure reuse may lead to confusion */
157 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
158 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
159 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
160
161 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
162 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
163 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
164 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
165
166 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
167 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
168 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
169 hr_reg_clear(fseg, FRMR_BLK_MODE);
170 hr_reg_clear(fseg, FRMR_BLOCK_SIZE);
171 hr_reg_clear(fseg, FRMR_ZBVA);
172 }
173
set_atomic_seg(const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int valid_num_sge)174 static void set_atomic_seg(const struct ib_send_wr *wr,
175 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
176 unsigned int valid_num_sge)
177 {
178 struct hns_roce_v2_wqe_data_seg *dseg =
179 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
180 struct hns_roce_wqe_atomic_seg *aseg =
181 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
182
183 set_data_seg_v2(dseg, wr->sg_list);
184
185 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
186 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
187 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
188 } else {
189 aseg->fetchadd_swap_data =
190 cpu_to_le64(atomic_wr(wr)->compare_add);
191 aseg->cmp_data = 0;
192 }
193
194 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
195 }
196
fill_ext_sge_inl_data(struct hns_roce_qp * qp,const struct ib_send_wr * wr,unsigned int * sge_idx,u32 msg_len)197 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
198 const struct ib_send_wr *wr,
199 unsigned int *sge_idx, u32 msg_len)
200 {
201 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
202 unsigned int left_len_in_pg;
203 unsigned int idx = *sge_idx;
204 unsigned int i = 0;
205 unsigned int len;
206 void *addr;
207 void *dseg;
208
209 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
210 ibdev_err(ibdev,
211 "no enough extended sge space for inline data.\n");
212 return -EINVAL;
213 }
214
215 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
216 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
217 len = wr->sg_list[0].length;
218 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
219
220 /* When copying data to extended sge space, the left length in page may
221 * not long enough for current user's sge. So the data should be
222 * splited into several parts, one in the first page, and the others in
223 * the subsequent pages.
224 */
225 while (1) {
226 if (len <= left_len_in_pg) {
227 memcpy(dseg, addr, len);
228
229 idx += len / HNS_ROCE_SGE_SIZE;
230
231 i++;
232 if (i >= wr->num_sge)
233 break;
234
235 left_len_in_pg -= len;
236 len = wr->sg_list[i].length;
237 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
238 dseg += len;
239 } else {
240 memcpy(dseg, addr, left_len_in_pg);
241
242 len -= left_len_in_pg;
243 addr += left_len_in_pg;
244 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
245 dseg = hns_roce_get_extend_sge(qp,
246 idx & (qp->sge.sge_cnt - 1));
247 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
248 }
249 }
250
251 *sge_idx = idx;
252
253 return 0;
254 }
255
set_extend_sge(struct hns_roce_qp * qp,struct ib_sge * sge,unsigned int * sge_ind,unsigned int cnt)256 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
257 unsigned int *sge_ind, unsigned int cnt)
258 {
259 struct hns_roce_v2_wqe_data_seg *dseg;
260 unsigned int idx = *sge_ind;
261
262 while (cnt > 0) {
263 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
264 if (likely(sge->length)) {
265 set_data_seg_v2(dseg, sge);
266 idx++;
267 cnt--;
268 }
269 sge++;
270 }
271
272 *sge_ind = idx;
273 }
274
check_inl_data_len(struct hns_roce_qp * qp,unsigned int len)275 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
276 {
277 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
278 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
279
280 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
281 ibdev_err(&hr_dev->ib_dev,
282 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
283 len, qp->max_inline_data, mtu);
284 return false;
285 }
286
287 return true;
288 }
289
set_rc_inl(struct hns_roce_qp * qp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_idx)290 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
291 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
292 unsigned int *sge_idx)
293 {
294 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
295 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
296 struct ib_device *ibdev = &hr_dev->ib_dev;
297 unsigned int curr_idx = *sge_idx;
298 void *dseg = rc_sq_wqe;
299 unsigned int i;
300 int ret;
301
302 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
303 ibdev_err(ibdev, "invalid inline parameters!\n");
304 return -EINVAL;
305 }
306
307 if (!check_inl_data_len(qp, msg_len))
308 return -EINVAL;
309
310 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
311
312 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
313 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
314
315 for (i = 0; i < wr->num_sge; i++) {
316 memcpy(dseg, ((void *)wr->sg_list[i].addr),
317 wr->sg_list[i].length);
318 dseg += wr->sg_list[i].length;
319 }
320 } else {
321 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
322
323 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
324 if (ret)
325 return ret;
326
327 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
328 }
329
330 *sge_idx = curr_idx;
331
332 return 0;
333 }
334
set_rwqe_data_seg(struct ib_qp * ibqp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_ind,unsigned int valid_num_sge)335 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
336 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
337 unsigned int *sge_ind,
338 unsigned int valid_num_sge)
339 {
340 struct hns_roce_v2_wqe_data_seg *dseg =
341 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
342 struct hns_roce_qp *qp = to_hr_qp(ibqp);
343 int j = 0;
344 int i;
345
346 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
347 !!(wr->send_flags & IB_SEND_INLINE));
348 if (wr->send_flags & IB_SEND_INLINE)
349 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
350
351 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
352 for (i = 0; i < wr->num_sge; i++) {
353 if (likely(wr->sg_list[i].length)) {
354 set_data_seg_v2(dseg, wr->sg_list + i);
355 dseg++;
356 }
357 }
358 } else {
359 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
360 if (likely(wr->sg_list[i].length)) {
361 set_data_seg_v2(dseg, wr->sg_list + i);
362 dseg++;
363 j++;
364 }
365 }
366
367 set_extend_sge(qp, wr->sg_list + i, sge_ind,
368 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
369 }
370
371 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
372
373 return 0;
374 }
375
check_send_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)376 static int check_send_valid(struct hns_roce_dev *hr_dev,
377 struct hns_roce_qp *hr_qp)
378 {
379 if (unlikely(hr_qp->state == IB_QPS_RESET ||
380 hr_qp->state == IB_QPS_INIT ||
381 hr_qp->state == IB_QPS_RTR))
382 return -EINVAL;
383 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
384 return -EIO;
385
386 return 0;
387 }
388
calc_wr_sge_num(const struct ib_send_wr * wr,unsigned int * sge_len)389 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
390 unsigned int *sge_len)
391 {
392 unsigned int valid_num = 0;
393 unsigned int len = 0;
394 int i;
395
396 for (i = 0; i < wr->num_sge; i++) {
397 if (likely(wr->sg_list[i].length)) {
398 len += wr->sg_list[i].length;
399 valid_num++;
400 }
401 }
402
403 *sge_len = len;
404 return valid_num;
405 }
406
get_immtdata(const struct ib_send_wr * wr)407 static __le32 get_immtdata(const struct ib_send_wr *wr)
408 {
409 switch (wr->opcode) {
410 case IB_WR_SEND_WITH_IMM:
411 case IB_WR_RDMA_WRITE_WITH_IMM:
412 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
413 default:
414 return 0;
415 }
416 }
417
set_ud_opcode(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,const struct ib_send_wr * wr)418 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
419 const struct ib_send_wr *wr)
420 {
421 u32 ib_op = wr->opcode;
422
423 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
424 return -EINVAL;
425
426 ud_sq_wqe->immtdata = get_immtdata(wr);
427
428 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
429
430 return 0;
431 }
432
fill_ud_av(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,struct hns_roce_ah * ah)433 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
434 struct hns_roce_ah *ah)
435 {
436 struct ib_device *ib_dev = ah->ibah.device;
437 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
438
439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
441 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
444
445 ud_sq_wqe->sgid_index = ah->av.gid_index;
446
447 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
448 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
449
450 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
451 return 0;
452
453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
454 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
455
456 return 0;
457 }
458
set_ud_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)459 static inline int set_ud_wqe(struct hns_roce_qp *qp,
460 const struct ib_send_wr *wr,
461 void *wqe, unsigned int *sge_idx,
462 unsigned int owner_bit)
463 {
464 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
465 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
466 unsigned int curr_idx = *sge_idx;
467 unsigned int valid_num_sge;
468 u32 msg_len = 0;
469 int ret;
470
471 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
472
473 ret = set_ud_opcode(ud_sq_wqe, wr);
474 if (WARN_ON_ONCE(ret))
475 return ret;
476
477 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
478
479 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
480 !!(wr->send_flags & IB_SEND_SIGNALED));
481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
482 !!(wr->send_flags & IB_SEND_SOLICITED));
483
484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
487 curr_idx & (qp->sge.sge_cnt - 1));
488
489 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
490 qp->qkey : ud_wr(wr)->remote_qkey);
491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
492
493 ret = fill_ud_av(ud_sq_wqe, ah);
494 if (ret)
495 return ret;
496
497 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
498
499 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
500
501 /*
502 * The pipeline can sequentially post all valid WQEs into WQ buffer,
503 * including new WQEs waiting for the doorbell to update the PI again.
504 * Therefore, the owner bit of WQE MUST be updated after all fields
505 * and extSGEs have been written into DDR instead of cache.
506 */
507 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
508 dma_wmb();
509
510 *sge_idx = curr_idx;
511 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
512
513 return 0;
514 }
515
set_rc_opcode(struct hns_roce_dev * hr_dev,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_send_wr * wr)516 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
517 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
518 const struct ib_send_wr *wr)
519 {
520 u32 ib_op = wr->opcode;
521 int ret = 0;
522
523 rc_sq_wqe->immtdata = get_immtdata(wr);
524
525 switch (ib_op) {
526 case IB_WR_RDMA_READ:
527 case IB_WR_RDMA_WRITE:
528 case IB_WR_RDMA_WRITE_WITH_IMM:
529 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
530 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
531 break;
532 case IB_WR_SEND:
533 case IB_WR_SEND_WITH_IMM:
534 break;
535 case IB_WR_ATOMIC_CMP_AND_SWP:
536 case IB_WR_ATOMIC_FETCH_AND_ADD:
537 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
538 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
539 break;
540 case IB_WR_REG_MR:
541 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
542 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
543 else
544 ret = -EOPNOTSUPP;
545 break;
546 case IB_WR_SEND_WITH_INV:
547 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
548 break;
549 default:
550 ret = -EINVAL;
551 }
552
553 if (unlikely(ret))
554 return ret;
555
556 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
557
558 return ret;
559 }
560
set_rc_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)561 static inline int set_rc_wqe(struct hns_roce_qp *qp,
562 const struct ib_send_wr *wr,
563 void *wqe, unsigned int *sge_idx,
564 unsigned int owner_bit)
565 {
566 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
567 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
568 unsigned int curr_idx = *sge_idx;
569 unsigned int valid_num_sge;
570 u32 msg_len = 0;
571 int ret;
572
573 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
574
575 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
576
577 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
578 if (WARN_ON_ONCE(ret))
579 return ret;
580
581 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO,
582 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
583
584 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
585 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
586
587 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
588 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
589
590 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
591 curr_idx & (qp->sge.sge_cnt - 1));
592
593 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
594 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
595 if (msg_len != ATOMIC_WR_LEN)
596 return -EINVAL;
597 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
598 } else if (wr->opcode != IB_WR_REG_MR) {
599 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
600 &curr_idx, valid_num_sge);
601 if (ret)
602 return ret;
603 }
604
605 /*
606 * The pipeline can sequentially post all valid WQEs into WQ buffer,
607 * including new WQEs waiting for the doorbell to update the PI again.
608 * Therefore, the owner bit of WQE MUST be updated after all fields
609 * and extSGEs have been written into DDR instead of cache.
610 */
611 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
612 dma_wmb();
613
614 *sge_idx = curr_idx;
615 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
616
617 return ret;
618 }
619
update_sq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)620 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
621 struct hns_roce_qp *qp)
622 {
623 if (unlikely(qp->state == IB_QPS_ERR)) {
624 flush_cqe(hr_dev, qp);
625 } else {
626 struct hns_roce_v2_db sq_db = {};
627
628 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
629 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
630 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
631 hr_reg_write(&sq_db, DB_SL, qp->sl);
632
633 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
634 }
635 }
636
update_rq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)637 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
638 struct hns_roce_qp *qp)
639 {
640 if (unlikely(qp->state == IB_QPS_ERR)) {
641 flush_cqe(hr_dev, qp);
642 } else {
643 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
644 *qp->rdb.db_record =
645 qp->rq.head & V2_DB_PRODUCER_IDX_M;
646 } else {
647 struct hns_roce_v2_db rq_db = {};
648
649 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
650 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
651 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
652
653 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
654 qp->rq.db_reg);
655 }
656 }
657 }
658
hns_roce_write512(struct hns_roce_dev * hr_dev,u64 * val,u64 __iomem * dest)659 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
660 u64 __iomem *dest)
661 {
662 #define HNS_ROCE_WRITE_TIMES 8
663 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
664 struct hnae3_handle *handle = priv->handle;
665 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
666 int i;
667
668 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
669 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
670 writeq_relaxed(*(val + i), dest + i);
671 }
672
write_dwqe(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,void * wqe)673 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
674 void *wqe)
675 {
676 #define HNS_ROCE_SL_SHIFT 2
677 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
678
679 if (unlikely(qp->state == IB_QPS_ERR)) {
680 flush_cqe(hr_dev, qp);
681 return;
682 }
683 /* All kinds of DirectWQE have the same header field layout */
684 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
685 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
686 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
687 qp->sl >> HNS_ROCE_SL_SHIFT);
688 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
689
690 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
691 }
692
hns_roce_v2_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)693 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
694 const struct ib_send_wr *wr,
695 const struct ib_send_wr **bad_wr)
696 {
697 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
698 struct ib_device *ibdev = &hr_dev->ib_dev;
699 struct hns_roce_qp *qp = to_hr_qp(ibqp);
700 unsigned long flags = 0;
701 unsigned int owner_bit;
702 unsigned int sge_idx;
703 unsigned int wqe_idx;
704 void *wqe = NULL;
705 u32 nreq;
706 int ret;
707
708 spin_lock_irqsave(&qp->sq.lock, flags);
709
710 ret = check_send_valid(hr_dev, qp);
711 if (unlikely(ret)) {
712 *bad_wr = wr;
713 nreq = 0;
714 goto out;
715 }
716
717 sge_idx = qp->next_sge;
718
719 for (nreq = 0; wr; ++nreq, wr = wr->next) {
720 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
721 ret = -ENOMEM;
722 *bad_wr = wr;
723 goto out;
724 }
725
726 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
727
728 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
729 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
730 wr->num_sge, qp->sq.max_gs);
731 ret = -EINVAL;
732 *bad_wr = wr;
733 goto out;
734 }
735
736 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
737 qp->sq.wrid[wqe_idx] = wr->wr_id;
738 owner_bit =
739 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
740
741 /* RC and UD share the same DirectWQE field layout */
742 ((struct hns_roce_v2_rc_send_wqe *)wqe)->byte_4 = 0;
743
744 /* Corresponding to the QP type, wqe process separately */
745 if (ibqp->qp_type == IB_QPT_RC)
746 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
747 else
748 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
749
750 trace_hns_sq_wqe(qp->qpn, wqe_idx, wqe, 1 << qp->sq.wqe_shift,
751 wr->wr_id, TRACE_SQ);
752 if (unlikely(ret)) {
753 *bad_wr = wr;
754 goto out;
755 }
756 }
757
758 out:
759 if (likely(nreq)) {
760 qp->sq.head += nreq;
761 qp->next_sge = sge_idx;
762
763 if (nreq == 1 && !ret &&
764 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
765 write_dwqe(hr_dev, qp, wqe);
766 else
767 update_sq_db(hr_dev, qp);
768 }
769
770 spin_unlock_irqrestore(&qp->sq.lock, flags);
771
772 return ret;
773 }
774
check_recv_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)775 static int check_recv_valid(struct hns_roce_dev *hr_dev,
776 struct hns_roce_qp *hr_qp)
777 {
778 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
779 return -EIO;
780
781 if (hr_qp->state == IB_QPS_RESET)
782 return -EINVAL;
783
784 return 0;
785 }
786
fill_recv_sge_to_wqe(const struct ib_recv_wr * wr,void * wqe,u32 max_sge,bool rsv)787 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
788 u32 max_sge, bool rsv)
789 {
790 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
791 u32 i, cnt;
792
793 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
794 /* Skip zero-length sge */
795 if (!wr->sg_list[i].length)
796 continue;
797 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
798 cnt++;
799 }
800
801 /* Fill a reserved sge to make hw stop reading remaining segments */
802 if (rsv) {
803 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
804 dseg[cnt].addr = 0;
805 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
806 } else {
807 /* Clear remaining segments to make ROCEE ignore sges */
808 if (cnt < max_sge)
809 memset(dseg + cnt, 0,
810 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
811 }
812 }
813
fill_rq_wqe(struct hns_roce_qp * hr_qp,const struct ib_recv_wr * wr,u32 wqe_idx,u32 max_sge)814 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
815 u32 wqe_idx, u32 max_sge)
816 {
817 void *wqe = NULL;
818
819 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
820 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
821
822 trace_hns_rq_wqe(hr_qp->qpn, wqe_idx, wqe, 1 << hr_qp->rq.wqe_shift,
823 wr->wr_id, TRACE_RQ);
824 }
825
hns_roce_v2_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)826 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
827 const struct ib_recv_wr *wr,
828 const struct ib_recv_wr **bad_wr)
829 {
830 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
831 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
832 struct ib_device *ibdev = &hr_dev->ib_dev;
833 u32 wqe_idx, nreq, max_sge;
834 unsigned long flags;
835 int ret;
836
837 spin_lock_irqsave(&hr_qp->rq.lock, flags);
838
839 ret = check_recv_valid(hr_dev, hr_qp);
840 if (unlikely(ret)) {
841 *bad_wr = wr;
842 nreq = 0;
843 goto out;
844 }
845
846 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
847 for (nreq = 0; wr; ++nreq, wr = wr->next) {
848 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
849 hr_qp->ibqp.recv_cq))) {
850 ret = -ENOMEM;
851 *bad_wr = wr;
852 goto out;
853 }
854
855 if (unlikely(wr->num_sge > max_sge)) {
856 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
857 wr->num_sge, max_sge);
858 ret = -EINVAL;
859 *bad_wr = wr;
860 goto out;
861 }
862
863 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
864 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
865 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
866 }
867
868 out:
869 if (likely(nreq)) {
870 hr_qp->rq.head += nreq;
871
872 update_rq_db(hr_dev, hr_qp);
873 }
874 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
875
876 return ret;
877 }
878
get_srq_wqe_buf(struct hns_roce_srq * srq,u32 n)879 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
880 {
881 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
882 }
883
get_idx_buf(struct hns_roce_idx_que * idx_que,u32 n)884 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
885 {
886 return hns_roce_buf_offset(idx_que->mtr.kmem,
887 n << idx_que->entry_shift);
888 }
889
hns_roce_free_srq_wqe(struct hns_roce_srq * srq,u32 wqe_index)890 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
891 {
892 /* always called with interrupts disabled. */
893 spin_lock(&srq->lock);
894
895 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
896 srq->idx_que.tail++;
897
898 spin_unlock(&srq->lock);
899 }
900
hns_roce_srqwq_overflow(struct hns_roce_srq * srq)901 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
902 {
903 struct hns_roce_idx_que *idx_que = &srq->idx_que;
904
905 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
906 }
907
check_post_srq_valid(struct hns_roce_srq * srq,u32 max_sge,const struct ib_recv_wr * wr)908 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
909 const struct ib_recv_wr *wr)
910 {
911 struct ib_device *ib_dev = srq->ibsrq.device;
912
913 if (unlikely(wr->num_sge > max_sge)) {
914 ibdev_err(ib_dev,
915 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
916 wr->num_sge, max_sge);
917 return -EINVAL;
918 }
919
920 if (unlikely(hns_roce_srqwq_overflow(srq))) {
921 ibdev_err(ib_dev,
922 "failed to check srqwq status, srqwq is full.\n");
923 return -ENOMEM;
924 }
925
926 return 0;
927 }
928
get_srq_wqe_idx(struct hns_roce_srq * srq,u32 * wqe_idx)929 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
930 {
931 struct hns_roce_idx_que *idx_que = &srq->idx_que;
932 u32 pos;
933
934 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
935 if (unlikely(pos == srq->wqe_cnt))
936 return -ENOSPC;
937
938 bitmap_set(idx_que->bitmap, pos, 1);
939 *wqe_idx = pos;
940 return 0;
941 }
942
fill_wqe_idx(struct hns_roce_srq * srq,unsigned int wqe_idx)943 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
944 {
945 struct hns_roce_idx_que *idx_que = &srq->idx_que;
946 unsigned int head;
947 __le32 *buf;
948
949 head = idx_que->head & (srq->wqe_cnt - 1);
950
951 buf = get_idx_buf(idx_que, head);
952 *buf = cpu_to_le32(wqe_idx);
953
954 idx_que->head++;
955 }
956
update_srq_db(struct hns_roce_srq * srq)957 static void update_srq_db(struct hns_roce_srq *srq)
958 {
959 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device);
960 struct hns_roce_v2_db db = {};
961
962 hr_reg_write(&db, DB_TAG, srq->srqn);
963 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
964 hr_reg_write(&db, DB_PI, srq->idx_que.head);
965
966 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg);
967 }
968
hns_roce_v2_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)969 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
970 const struct ib_recv_wr *wr,
971 const struct ib_recv_wr **bad_wr)
972 {
973 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
974 unsigned long flags;
975 int ret = 0;
976 u32 max_sge;
977 u32 wqe_idx;
978 void *wqe;
979 u32 nreq;
980
981 spin_lock_irqsave(&srq->lock, flags);
982
983 max_sge = srq->max_gs - srq->rsv_sge;
984 for (nreq = 0; wr; ++nreq, wr = wr->next) {
985 ret = check_post_srq_valid(srq, max_sge, wr);
986 if (ret) {
987 *bad_wr = wr;
988 break;
989 }
990
991 ret = get_srq_wqe_idx(srq, &wqe_idx);
992 if (unlikely(ret)) {
993 *bad_wr = wr;
994 break;
995 }
996
997 wqe = get_srq_wqe_buf(srq, wqe_idx);
998 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
999 fill_wqe_idx(srq, wqe_idx);
1000 srq->wrid[wqe_idx] = wr->wr_id;
1001
1002 trace_hns_srq_wqe(srq->srqn, wqe_idx, wqe, 1 << srq->wqe_shift,
1003 wr->wr_id, TRACE_SRQ);
1004 }
1005
1006 if (likely(nreq)) {
1007 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB)
1008 *srq->rdb.db_record = srq->idx_que.head &
1009 V2_DB_PRODUCER_IDX_M;
1010 else
1011 update_srq_db(srq);
1012 }
1013
1014 spin_unlock_irqrestore(&srq->lock, flags);
1015
1016 return ret;
1017 }
1018
hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1019 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1020 unsigned long instance_stage,
1021 unsigned long reset_stage)
1022 {
1023 /* When hardware reset has been completed once or more, we should stop
1024 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1025 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1026 * stage of soft reset process, we should exit with error, and then
1027 * HNAE3_INIT_CLIENT related process can rollback the operation like
1028 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1029 * process will exit with error to notify NIC driver to reschedule soft
1030 * reset process once again.
1031 */
1032 hr_dev->is_reset = true;
1033 hr_dev->dis_db = true;
1034
1035 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1036 instance_stage == HNS_ROCE_STATE_INIT)
1037 return CMD_RST_PRC_EBUSY;
1038
1039 return CMD_RST_PRC_SUCCESS;
1040 }
1041
hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1042 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1043 unsigned long instance_stage,
1044 unsigned long reset_stage)
1045 {
1046 #define HW_RESET_TIMEOUT_US 1000000
1047 #define HW_RESET_SLEEP_US 1000
1048
1049 struct hns_roce_v2_priv *priv = hr_dev->priv;
1050 struct hnae3_handle *handle = priv->handle;
1051 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1052 unsigned long val;
1053 int ret;
1054
1055 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1056 * doorbell to hardware. If now in .init_instance() function, we should
1057 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1058 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1059 * related process can rollback the operation like notifing hardware to
1060 * free resources, HNAE3_INIT_CLIENT related process will exit with
1061 * error to notify NIC driver to reschedule soft reset process once
1062 * again.
1063 */
1064 hr_dev->dis_db = true;
1065
1066 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1067 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1068 HW_RESET_TIMEOUT_US, false, handle);
1069 if (!ret)
1070 hr_dev->is_reset = true;
1071
1072 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1073 instance_stage == HNS_ROCE_STATE_INIT)
1074 return CMD_RST_PRC_EBUSY;
1075
1076 return CMD_RST_PRC_SUCCESS;
1077 }
1078
hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev * hr_dev)1079 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1080 {
1081 struct hns_roce_v2_priv *priv = hr_dev->priv;
1082 struct hnae3_handle *handle = priv->handle;
1083 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1084
1085 /* When software reset is detected at .init_instance() function, we
1086 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1087 * with error.
1088 */
1089 hr_dev->dis_db = true;
1090 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1091 hr_dev->is_reset = true;
1092
1093 return CMD_RST_PRC_EBUSY;
1094 }
1095
check_aedev_reset_status(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1096 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1097 struct hnae3_handle *handle)
1098 {
1099 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1100 unsigned long instance_stage; /* the current instance stage */
1101 unsigned long reset_stage; /* the current reset stage */
1102 unsigned long reset_cnt;
1103 bool sw_resetting;
1104 bool hw_resetting;
1105
1106 /* Get information about reset from NIC driver or RoCE driver itself,
1107 * the meaning of the following variables from NIC driver are described
1108 * as below:
1109 * reset_cnt -- The count value of completed hardware reset.
1110 * hw_resetting -- Whether hardware device is resetting now.
1111 * sw_resetting -- Whether NIC's software reset process is running now.
1112 */
1113 instance_stage = handle->rinfo.instance_state;
1114 reset_stage = handle->rinfo.reset_state;
1115 reset_cnt = ops->ae_dev_reset_cnt(handle);
1116 if (reset_cnt != hr_dev->reset_cnt)
1117 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1118 reset_stage);
1119
1120 hw_resetting = ops->get_cmdq_stat(handle);
1121 if (hw_resetting)
1122 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1123 reset_stage);
1124
1125 sw_resetting = ops->ae_dev_resetting(handle);
1126 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1127 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1128
1129 return CMD_RST_PRC_OTHERS;
1130 }
1131
check_device_is_in_reset(struct hns_roce_dev * hr_dev)1132 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1133 {
1134 struct hns_roce_v2_priv *priv = hr_dev->priv;
1135 struct hnae3_handle *handle = priv->handle;
1136 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1137
1138 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1139 return true;
1140
1141 if (ops->get_hw_reset_stat(handle))
1142 return true;
1143
1144 if (ops->ae_dev_resetting(handle))
1145 return true;
1146
1147 return false;
1148 }
1149
v2_chk_mbox_is_avail(struct hns_roce_dev * hr_dev,bool * busy)1150 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1151 {
1152 struct hns_roce_v2_priv *priv = hr_dev->priv;
1153 u32 status;
1154
1155 if (hr_dev->is_reset)
1156 status = CMD_RST_PRC_SUCCESS;
1157 else
1158 status = check_aedev_reset_status(hr_dev, priv->handle);
1159
1160 *busy = (status == CMD_RST_PRC_EBUSY);
1161
1162 return status == CMD_RST_PRC_OTHERS;
1163 }
1164
hns_roce_alloc_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1165 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1166 struct hns_roce_v2_cmq_ring *ring)
1167 {
1168 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1169
1170 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1171 &ring->desc_dma_addr, GFP_KERNEL);
1172 if (!ring->desc)
1173 return -ENOMEM;
1174
1175 return 0;
1176 }
1177
hns_roce_free_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1178 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1179 struct hns_roce_v2_cmq_ring *ring)
1180 {
1181 dma_free_coherent(hr_dev->dev,
1182 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1183 ring->desc, ring->desc_dma_addr);
1184
1185 ring->desc_dma_addr = 0;
1186 }
1187
init_csq(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * csq)1188 static int init_csq(struct hns_roce_dev *hr_dev,
1189 struct hns_roce_v2_cmq_ring *csq)
1190 {
1191 dma_addr_t dma;
1192 int ret;
1193
1194 csq->desc_num = CMD_CSQ_DESC_NUM;
1195 spin_lock_init(&csq->lock);
1196 csq->flag = TYPE_CSQ;
1197 csq->head = 0;
1198
1199 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1200 if (ret)
1201 return ret;
1202
1203 dma = csq->desc_dma_addr;
1204 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1205 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1206 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1207 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1208
1209 /* Make sure to write CI first and then PI */
1210 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1211 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1212
1213 return 0;
1214 }
1215
hns_roce_v2_cmq_init(struct hns_roce_dev * hr_dev)1216 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1217 {
1218 struct hns_roce_v2_priv *priv = hr_dev->priv;
1219 int ret;
1220
1221 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1222
1223 ret = init_csq(hr_dev, &priv->cmq.csq);
1224 if (ret)
1225 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1226
1227 return ret;
1228 }
1229
hns_roce_v2_cmq_exit(struct hns_roce_dev * hr_dev)1230 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1231 {
1232 struct hns_roce_v2_priv *priv = hr_dev->priv;
1233
1234 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1235 }
1236
hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc * desc,enum hns_roce_opcode_type opcode,bool is_read)1237 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1238 enum hns_roce_opcode_type opcode,
1239 bool is_read)
1240 {
1241 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1242 desc->opcode = cpu_to_le16(opcode);
1243 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1244 if (is_read)
1245 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1246 else
1247 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1248 }
1249
hns_roce_cmq_csq_done(struct hns_roce_dev * hr_dev)1250 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1251 {
1252 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1253 struct hns_roce_v2_priv *priv = hr_dev->priv;
1254
1255 return tail == priv->cmq.csq.head;
1256 }
1257
update_cmdq_status(struct hns_roce_dev * hr_dev)1258 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1259 {
1260 struct hns_roce_v2_priv *priv = hr_dev->priv;
1261 struct hnae3_handle *handle = priv->handle;
1262
1263 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1264 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1265 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1266 }
1267
hns_roce_cmd_err_convert_errno(u16 desc_ret)1268 static int hns_roce_cmd_err_convert_errno(u16 desc_ret)
1269 {
1270 struct hns_roce_cmd_errcode errcode_table[] = {
1271 {CMD_EXEC_SUCCESS, 0},
1272 {CMD_NO_AUTH, -EPERM},
1273 {CMD_NOT_EXIST, -EOPNOTSUPP},
1274 {CMD_CRQ_FULL, -EXFULL},
1275 {CMD_NEXT_ERR, -ENOSR},
1276 {CMD_NOT_EXEC, -ENOTBLK},
1277 {CMD_PARA_ERR, -EINVAL},
1278 {CMD_RESULT_ERR, -ERANGE},
1279 {CMD_TIMEOUT, -ETIME},
1280 {CMD_HILINK_ERR, -ENOLINK},
1281 {CMD_INFO_ILLEGAL, -ENXIO},
1282 {CMD_INVALID, -EBADR},
1283 };
1284 u16 i;
1285
1286 for (i = 0; i < ARRAY_SIZE(errcode_table); i++)
1287 if (desc_ret == errcode_table[i].return_status)
1288 return errcode_table[i].errno;
1289 return -EIO;
1290 }
1291
hns_roce_cmdq_tx_timeout(u16 opcode,u32 tx_timeout)1292 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
1293 {
1294 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = {
1295 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT},
1296 };
1297 int i;
1298
1299 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++)
1300 if (cmdq_tx_timeout[i].opcode == opcode)
1301 return cmdq_tx_timeout[i].tx_timeout;
1302
1303 return tx_timeout;
1304 }
1305
hns_roce_wait_csq_done(struct hns_roce_dev * hr_dev,u32 tx_timeout)1306 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout)
1307 {
1308 u32 timeout = 0;
1309
1310 do {
1311 if (hns_roce_cmq_csq_done(hr_dev))
1312 break;
1313 udelay(1);
1314 } while (++timeout < tx_timeout);
1315 }
1316
__hns_roce_cmq_send_one(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num,u32 tx_timeout)1317 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev,
1318 struct hns_roce_cmq_desc *desc,
1319 int num, u32 tx_timeout)
1320 {
1321 struct hns_roce_v2_priv *priv = hr_dev->priv;
1322 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1323 u16 desc_ret;
1324 u32 tail;
1325 int ret;
1326 int i;
1327
1328 tail = csq->head;
1329
1330 for (i = 0; i < num; i++) {
1331 trace_hns_cmdq_req(hr_dev, &desc[i]);
1332
1333 csq->desc[csq->head++] = desc[i];
1334 if (csq->head == csq->desc_num)
1335 csq->head = 0;
1336 }
1337
1338 /* Write to hardware */
1339 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1340
1341 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);
1342
1343 hns_roce_wait_csq_done(hr_dev, tx_timeout);
1344 if (hns_roce_cmq_csq_done(hr_dev)) {
1345 ret = 0;
1346 for (i = 0; i < num; i++) {
1347 trace_hns_cmdq_resp(hr_dev, &csq->desc[tail]);
1348
1349 /* check the result of hardware write back */
1350 desc_ret = le16_to_cpu(csq->desc[tail++].retval);
1351 if (tail == csq->desc_num)
1352 tail = 0;
1353 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1354 continue;
1355
1356 ret = hns_roce_cmd_err_convert_errno(desc_ret);
1357 }
1358 } else {
1359 /* FW/HW reset or incorrect number of desc */
1360 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1361 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1362 csq->head, tail);
1363 csq->head = tail;
1364
1365 update_cmdq_status(hr_dev);
1366
1367 ret = -EAGAIN;
1368 }
1369
1370 if (ret)
1371 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]);
1372
1373 return ret;
1374 }
1375
__hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1376 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1377 struct hns_roce_cmq_desc *desc, int num)
1378 {
1379 struct hns_roce_v2_priv *priv = hr_dev->priv;
1380 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1381 u16 opcode = le16_to_cpu(desc->opcode);
1382 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout);
1383 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT;
1384 u32 rsv_tail;
1385 int ret;
1386 int i;
1387
1388 while (try_cnt) {
1389 try_cnt--;
1390
1391 spin_lock_bh(&csq->lock);
1392 rsv_tail = csq->head;
1393 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout);
1394 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME &&
1395 try_cnt) {
1396 spin_unlock_bh(&csq->lock);
1397 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC);
1398 continue;
1399 }
1400
1401 for (i = 0; i < num; i++) {
1402 desc[i] = csq->desc[rsv_tail++];
1403 if (rsv_tail == csq->desc_num)
1404 rsv_tail = 0;
1405 }
1406 spin_unlock_bh(&csq->lock);
1407 break;
1408 }
1409
1410 if (ret)
1411 dev_err_ratelimited(hr_dev->dev,
1412 "Cmdq IO error, opcode = 0x%x, return = %d.\n",
1413 opcode, ret);
1414
1415 return ret;
1416 }
1417
hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1418 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1419 struct hns_roce_cmq_desc *desc, int num)
1420 {
1421 bool busy;
1422 int ret;
1423
1424 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1425 return -EIO;
1426
1427 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1428 return busy ? -EBUSY : 0;
1429
1430 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1431 if (ret) {
1432 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1433 return busy ? -EBUSY : 0;
1434 }
1435
1436 return ret;
1437 }
1438
1439 static enum hns_roce_opcode_type
get_bond_opcode(enum hns_roce_bond_cmd_type bond_type)1440 get_bond_opcode(enum hns_roce_bond_cmd_type bond_type)
1441 {
1442 switch (bond_type) {
1443 case HNS_ROCE_SET_BOND:
1444 return HNS_ROCE_OPC_SET_BOND_INFO;
1445 case HNS_ROCE_CHANGE_BOND:
1446 return HNS_ROCE_OPC_CHANGE_ACTIVE_PORT;
1447 case HNS_ROCE_CLEAR_BOND:
1448 return HNS_ROCE_OPC_CLEAR_BOND_INFO;
1449 default:
1450 WARN(true, "Invalid bond type %d!\n", bond_type);
1451 return HNS_ROCE_OPC_SET_BOND_INFO;
1452 }
1453 }
1454
1455 static enum hns_roce_bond_hashtype
get_bond_hashtype(enum netdev_lag_hash netdev_hashtype)1456 get_bond_hashtype(enum netdev_lag_hash netdev_hashtype)
1457 {
1458 switch (netdev_hashtype) {
1459 case NETDEV_LAG_HASH_L2:
1460 return BOND_HASH_L2;
1461 case NETDEV_LAG_HASH_L34:
1462 return BOND_HASH_L34;
1463 case NETDEV_LAG_HASH_L23:
1464 return BOND_HASH_L23;
1465 default:
1466 WARN(true, "Invalid hash type %d!\n", netdev_hashtype);
1467 return BOND_HASH_L2;
1468 }
1469 }
1470
hns_roce_cmd_bond(struct hns_roce_bond_group * bond_grp,enum hns_roce_bond_cmd_type bond_type)1471 int hns_roce_cmd_bond(struct hns_roce_bond_group *bond_grp,
1472 enum hns_roce_bond_cmd_type bond_type)
1473 {
1474 enum hns_roce_opcode_type opcode = get_bond_opcode(bond_type);
1475 struct hns_roce_bond_info *slave_info;
1476 struct hns_roce_cmq_desc desc = {};
1477 int ret;
1478
1479 slave_info = (struct hns_roce_bond_info *)desc.data;
1480 hns_roce_cmq_setup_basic_desc(&desc, opcode, false);
1481
1482 slave_info->bond_id = cpu_to_le32(bond_grp->bond_id);
1483 if (bond_type == HNS_ROCE_CLEAR_BOND)
1484 goto out;
1485
1486 if (bond_grp->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) {
1487 slave_info->bond_mode = cpu_to_le32(BOND_MODE_1);
1488 if (bond_grp->active_slave_num != 1)
1489 ibdev_warn(&bond_grp->main_hr_dev->ib_dev,
1490 "active slave cnt(%u) in Mode 1 is invalid.\n",
1491 bond_grp->active_slave_num);
1492 } else {
1493 slave_info->bond_mode = cpu_to_le32(BOND_MODE_2_4);
1494 slave_info->hash_policy =
1495 cpu_to_le32(get_bond_hashtype(bond_grp->hash_type));
1496 }
1497
1498 slave_info->active_slave_cnt = cpu_to_le32(bond_grp->active_slave_num);
1499 slave_info->active_slave_mask = cpu_to_le32(bond_grp->active_slave_map);
1500 slave_info->slave_mask = cpu_to_le32(bond_grp->slave_map);
1501
1502 out:
1503 ret = hns_roce_cmq_send(bond_grp->main_hr_dev, &desc, 1);
1504 if (ret)
1505 ibdev_err(&bond_grp->main_hr_dev->ib_dev,
1506 "cmq bond type(%d) failed, ret = %d.\n",
1507 bond_type, ret);
1508
1509 return ret;
1510 }
1511
config_hem_ba_to_hw(struct hns_roce_dev * hr_dev,dma_addr_t base_addr,u8 cmd,unsigned long tag)1512 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1513 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1514 {
1515 struct hns_roce_cmd_mailbox *mbox;
1516 int ret;
1517
1518 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1519 if (IS_ERR(mbox))
1520 return PTR_ERR(mbox);
1521
1522 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1523 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1524 return ret;
1525 }
1526
hns_roce_cmq_query_hw_info(struct hns_roce_dev * hr_dev)1527 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1528 {
1529 struct hns_roce_query_version *resp;
1530 struct hns_roce_cmq_desc desc;
1531 int ret;
1532
1533 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1534 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1535 if (ret)
1536 return ret;
1537
1538 resp = (struct hns_roce_query_version *)desc.data;
1539 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1540 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1541
1542 return 0;
1543 }
1544
func_clr_hw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1545 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1546 struct hnae3_handle *handle)
1547 {
1548 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1549 unsigned long end;
1550
1551 hr_dev->dis_db = true;
1552
1553 dev_warn(hr_dev->dev,
1554 "func clear is pending, device in resetting state.\n");
1555 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1556 while (end) {
1557 if (!ops->get_hw_reset_stat(handle)) {
1558 hr_dev->is_reset = true;
1559 dev_info(hr_dev->dev,
1560 "func clear success after reset.\n");
1561 return;
1562 }
1563 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1564 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1565 }
1566
1567 dev_warn(hr_dev->dev, "func clear failed.\n");
1568 }
1569
func_clr_sw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1570 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1571 struct hnae3_handle *handle)
1572 {
1573 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1574 unsigned long end;
1575
1576 hr_dev->dis_db = true;
1577
1578 dev_warn(hr_dev->dev,
1579 "func clear is pending, device in resetting state.\n");
1580 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1581 while (end) {
1582 if (ops->ae_dev_reset_cnt(handle) !=
1583 hr_dev->reset_cnt) {
1584 hr_dev->is_reset = true;
1585 dev_info(hr_dev->dev,
1586 "func clear success after sw reset\n");
1587 return;
1588 }
1589 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1590 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1591 }
1592
1593 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1594 }
1595
hns_roce_func_clr_rst_proc(struct hns_roce_dev * hr_dev,int retval,int flag)1596 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1597 int flag)
1598 {
1599 struct hns_roce_v2_priv *priv = hr_dev->priv;
1600 struct hnae3_handle *handle = priv->handle;
1601 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1602
1603 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1604 hr_dev->dis_db = true;
1605 hr_dev->is_reset = true;
1606 dev_info(hr_dev->dev, "func clear success after reset.\n");
1607 return;
1608 }
1609
1610 if (ops->get_hw_reset_stat(handle)) {
1611 func_clr_hw_resetting_state(hr_dev, handle);
1612 return;
1613 }
1614
1615 if (ops->ae_dev_resetting(handle) &&
1616 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1617 func_clr_sw_resetting_state(hr_dev, handle);
1618 return;
1619 }
1620
1621 if (retval && !flag)
1622 dev_warn(hr_dev->dev,
1623 "func clear read failed, ret = %d.\n", retval);
1624
1625 dev_warn(hr_dev->dev, "func clear failed.\n");
1626 }
1627
__hns_roce_function_clear(struct hns_roce_dev * hr_dev,int vf_id)1628 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1629 {
1630 bool fclr_write_fail_flag = false;
1631 struct hns_roce_func_clear *resp;
1632 struct hns_roce_cmq_desc desc;
1633 unsigned long end;
1634 int ret = 0;
1635
1636 if (check_device_is_in_reset(hr_dev))
1637 goto out;
1638
1639 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1640 resp = (struct hns_roce_func_clear *)desc.data;
1641 resp->rst_funcid_en = cpu_to_le32(vf_id);
1642
1643 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1644 if (ret) {
1645 fclr_write_fail_flag = true;
1646 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1647 ret);
1648 goto out;
1649 }
1650
1651 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1652 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1653 while (end) {
1654 if (check_device_is_in_reset(hr_dev))
1655 goto out;
1656 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1657 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1658
1659 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1660 true);
1661
1662 resp->rst_funcid_en = cpu_to_le32(vf_id);
1663 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1664 if (ret)
1665 continue;
1666
1667 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1668 if (vf_id == 0)
1669 hr_dev->is_reset = true;
1670 return;
1671 }
1672 }
1673
1674 out:
1675 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1676 }
1677
hns_roce_free_vf_resource(struct hns_roce_dev * hr_dev,int vf_id)1678 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1679 {
1680 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1681 struct hns_roce_cmq_desc desc[2];
1682 struct hns_roce_cmq_req *req_a;
1683
1684 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1685 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1686 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1687 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1688 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1689
1690 return hns_roce_cmq_send(hr_dev, desc, 2);
1691 }
1692
hns_roce_function_clear(struct hns_roce_dev * hr_dev)1693 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1694 {
1695 int ret;
1696 int i;
1697
1698 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1699 return;
1700
1701 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1702 __hns_roce_function_clear(hr_dev, i);
1703
1704 if (i == 0)
1705 continue;
1706
1707 ret = hns_roce_free_vf_resource(hr_dev, i);
1708 if (ret)
1709 ibdev_err(&hr_dev->ib_dev,
1710 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1711 i, ret);
1712 }
1713 }
1714
hns_roce_clear_extdb_list_info(struct hns_roce_dev * hr_dev)1715 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1716 {
1717 struct hns_roce_cmq_desc desc;
1718 int ret;
1719
1720 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1721 false);
1722 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1723 if (ret)
1724 ibdev_err(&hr_dev->ib_dev,
1725 "failed to clear extended doorbell info, ret = %d.\n",
1726 ret);
1727
1728 return ret;
1729 }
1730
hns_roce_query_fw_ver(struct hns_roce_dev * hr_dev)1731 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1732 {
1733 struct hns_roce_query_fw_info *resp;
1734 struct hns_roce_cmq_desc desc;
1735 int ret;
1736
1737 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1738 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1739 if (ret)
1740 return ret;
1741
1742 resp = (struct hns_roce_query_fw_info *)desc.data;
1743 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1744
1745 return 0;
1746 }
1747
hns_roce_query_func_info(struct hns_roce_dev * hr_dev)1748 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1749 {
1750 struct hns_roce_cmq_desc desc;
1751 int ret;
1752
1753 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1754 hr_dev->func_num = 1;
1755 return 0;
1756 }
1757
1758 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1759 true);
1760 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1761 if (ret) {
1762 hr_dev->func_num = 1;
1763 return ret;
1764 }
1765
1766 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1767 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1768
1769 return 0;
1770 }
1771
hns_roce_hw_v2_query_counter(struct hns_roce_dev * hr_dev,u64 * stats,u32 port,int * num_counters)1772 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev,
1773 u64 *stats, u32 port, int *num_counters)
1774 {
1775 #define CNT_PER_DESC 3
1776 struct hns_roce_cmq_desc *desc;
1777 int bd_idx, cnt_idx;
1778 __le64 *cnt_data;
1779 int desc_num;
1780 int ret;
1781 int i;
1782
1783 if (port > hr_dev->caps.num_ports)
1784 return -EINVAL;
1785
1786 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC);
1787 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL);
1788 if (!desc)
1789 return -ENOMEM;
1790
1791 for (i = 0; i < desc_num; i++) {
1792 hns_roce_cmq_setup_basic_desc(&desc[i],
1793 HNS_ROCE_OPC_QUERY_COUNTER, true);
1794 if (i != desc_num - 1)
1795 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1796 }
1797
1798 ret = hns_roce_cmq_send(hr_dev, desc, desc_num);
1799 if (ret) {
1800 ibdev_err(&hr_dev->ib_dev,
1801 "failed to get counter, ret = %d.\n", ret);
1802 goto err_out;
1803 }
1804
1805 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) {
1806 bd_idx = i / CNT_PER_DESC;
1807 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC &&
1808 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT)))
1809 break;
1810
1811 cnt_data = (__le64 *)&desc[bd_idx].data[0];
1812 cnt_idx = i % CNT_PER_DESC;
1813 stats[i] = le64_to_cpu(cnt_data[cnt_idx]);
1814 }
1815 *num_counters = i;
1816
1817 err_out:
1818 kfree(desc);
1819 return ret;
1820 }
1821
hns_roce_config_global_param(struct hns_roce_dev * hr_dev)1822 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1823 {
1824 struct hns_roce_cmq_desc desc;
1825 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1826 u32 clock_cycles_of_1us;
1827
1828 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1829 false);
1830
1831 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1832 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1833 else
1834 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1835
1836 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1837 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1838
1839 return hns_roce_cmq_send(hr_dev, &desc, 1);
1840 }
1841
load_func_res_caps(struct hns_roce_dev * hr_dev,bool is_vf)1842 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1843 {
1844 struct hns_roce_cmq_desc desc[2];
1845 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1846 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1847 struct hns_roce_caps *caps = &hr_dev->caps;
1848 enum hns_roce_opcode_type opcode;
1849 u32 func_num;
1850 int ret;
1851
1852 if (is_vf) {
1853 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1854 func_num = 1;
1855 } else {
1856 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1857 func_num = hr_dev->func_num;
1858 }
1859
1860 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1861 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1862 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1863
1864 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1865 if (ret)
1866 return ret;
1867
1868 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1869 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1870 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1871 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1872 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1873 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1874 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1875 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1876
1877 if (is_vf) {
1878 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1879 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1880 func_num;
1881 } else {
1882 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1883 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1884 func_num;
1885 }
1886
1887 return 0;
1888 }
1889
load_pf_timer_res_caps(struct hns_roce_dev * hr_dev)1890 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1891 {
1892 struct hns_roce_cmq_desc desc;
1893 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1894 struct hns_roce_caps *caps = &hr_dev->caps;
1895 int ret;
1896
1897 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1898 true);
1899
1900 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1901 if (ret)
1902 return ret;
1903
1904 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1905 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1906
1907 return 0;
1908 }
1909
hns_roce_query_pf_resource(struct hns_roce_dev * hr_dev)1910 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1911 {
1912 struct device *dev = hr_dev->dev;
1913 int ret;
1914
1915 ret = load_func_res_caps(hr_dev, false);
1916 if (ret) {
1917 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);
1918 return ret;
1919 }
1920
1921 ret = load_pf_timer_res_caps(hr_dev);
1922 if (ret)
1923 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1924 ret);
1925
1926 return ret;
1927 }
1928
hns_roce_query_vf_resource(struct hns_roce_dev * hr_dev)1929 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1930 {
1931 struct device *dev = hr_dev->dev;
1932 int ret;
1933
1934 ret = load_func_res_caps(hr_dev, true);
1935 if (ret)
1936 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);
1937
1938 return ret;
1939 }
1940
__hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev,u32 vf_id)1941 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1942 u32 vf_id)
1943 {
1944 struct hns_roce_vf_switch *swt;
1945 struct hns_roce_cmq_desc desc;
1946 int ret;
1947
1948 swt = (struct hns_roce_vf_switch *)desc.data;
1949 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1950 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1951 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1952 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1953 if (ret)
1954 return ret;
1955
1956 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1957 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1958 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1959 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1960 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1961
1962 return hns_roce_cmq_send(hr_dev, &desc, 1);
1963 }
1964
hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev)1965 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1966 {
1967 u32 vf_id;
1968 int ret;
1969
1970 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1971 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1972 if (ret)
1973 return ret;
1974 }
1975 return 0;
1976 }
1977
config_vf_hem_resource(struct hns_roce_dev * hr_dev,int vf_id)1978 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1979 {
1980 struct hns_roce_cmq_desc desc[2];
1981 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1982 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1983 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1984 struct hns_roce_caps *caps = &hr_dev->caps;
1985
1986 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1987 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1988 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1989
1990 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1991
1992 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1993 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1994 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1995 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1996 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1997 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1998 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1999 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
2000 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
2001 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
2002 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
2003 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
2004 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
2005 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
2006
2007 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2008 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
2009 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
2010 vf_id * caps->gmv_bt_num);
2011 } else {
2012 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
2013 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
2014 vf_id * caps->sgid_bt_num);
2015 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
2016 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
2017 vf_id * caps->smac_bt_num);
2018 }
2019
2020 return hns_roce_cmq_send(hr_dev, desc, 2);
2021 }
2022
hns_roce_alloc_vf_resource(struct hns_roce_dev * hr_dev)2023 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
2024 {
2025 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2026 u32 vf_id;
2027 int ret;
2028
2029 for (vf_id = 0; vf_id < func_num; vf_id++) {
2030 ret = config_vf_hem_resource(hr_dev, vf_id);
2031 if (ret) {
2032 dev_err(hr_dev->dev,
2033 "failed to config vf-%u hem res, ret = %d.\n",
2034 vf_id, ret);
2035 return ret;
2036 }
2037 }
2038
2039 return 0;
2040 }
2041
hns_roce_v2_set_bt(struct hns_roce_dev * hr_dev)2042 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
2043 {
2044 struct hns_roce_cmq_desc desc;
2045 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2046 struct hns_roce_caps *caps = &hr_dev->caps;
2047
2048 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
2049
2050 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
2051 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
2052 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
2053 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
2054 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
2055 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
2056
2057 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
2058 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
2059 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
2060 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
2061 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
2062 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
2063
2064 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
2065 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
2066 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
2067 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
2068 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
2069 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
2070
2071 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
2072 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
2073 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
2074 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
2075 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
2076 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
2077
2078 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
2079 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
2080 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
2081 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
2082 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
2083 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
2084
2085 return hns_roce_cmq_send(hr_dev, &desc, 1);
2086 }
2087
calc_pg_sz(u32 obj_num,u32 obj_size,u32 hop_num,u32 ctx_bt_num,u32 * buf_page_size,u32 * bt_page_size,u32 hem_type)2088 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
2089 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
2090 {
2091 u64 obj_per_chunk;
2092 u64 bt_chunk_size = PAGE_SIZE;
2093 u64 buf_chunk_size = PAGE_SIZE;
2094 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
2095
2096 *buf_page_size = 0;
2097 *bt_page_size = 0;
2098
2099 switch (hop_num) {
2100 case 3:
2101 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2102 (bt_chunk_size / BA_BYTE_LEN) *
2103 (bt_chunk_size / BA_BYTE_LEN) *
2104 obj_per_chunk_default;
2105 break;
2106 case 2:
2107 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2108 (bt_chunk_size / BA_BYTE_LEN) *
2109 obj_per_chunk_default;
2110 break;
2111 case 1:
2112 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2113 obj_per_chunk_default;
2114 break;
2115 case HNS_ROCE_HOP_NUM_0:
2116 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
2117 break;
2118 default:
2119 pr_err("table %u not support hop_num = %u!\n", hem_type,
2120 hop_num);
2121 return;
2122 }
2123
2124 if (hem_type >= HEM_TYPE_MTT)
2125 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2126 else
2127 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2128 }
2129
set_hem_page_size(struct hns_roce_dev * hr_dev)2130 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
2131 {
2132 struct hns_roce_caps *caps = &hr_dev->caps;
2133
2134 /* EQ */
2135 caps->eqe_ba_pg_sz = 0;
2136 caps->eqe_buf_pg_sz = 0;
2137
2138 /* Link Table */
2139 caps->llm_buf_pg_sz = 0;
2140
2141 /* MR */
2142 caps->mpt_ba_pg_sz = 0;
2143 caps->mpt_buf_pg_sz = 0;
2144 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2145 caps->pbl_buf_pg_sz = 0;
2146 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2147 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2148 HEM_TYPE_MTPT);
2149
2150 /* QP */
2151 caps->qpc_ba_pg_sz = 0;
2152 caps->qpc_buf_pg_sz = 0;
2153 caps->qpc_timer_ba_pg_sz = 0;
2154 caps->qpc_timer_buf_pg_sz = 0;
2155 caps->sccc_ba_pg_sz = 0;
2156 caps->sccc_buf_pg_sz = 0;
2157 caps->mtt_ba_pg_sz = 0;
2158 caps->mtt_buf_pg_sz = 0;
2159 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2160 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2161 HEM_TYPE_QPC);
2162
2163 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2164 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2165 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2166 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2167
2168 /* CQ */
2169 caps->cqc_ba_pg_sz = 0;
2170 caps->cqc_buf_pg_sz = 0;
2171 caps->cqc_timer_ba_pg_sz = 0;
2172 caps->cqc_timer_buf_pg_sz = 0;
2173 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2174 caps->cqe_buf_pg_sz = 0;
2175 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2176 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2177 HEM_TYPE_CQC);
2178 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2179 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2180
2181 /* SRQ */
2182 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2183 caps->srqc_ba_pg_sz = 0;
2184 caps->srqc_buf_pg_sz = 0;
2185 caps->srqwqe_ba_pg_sz = 0;
2186 caps->srqwqe_buf_pg_sz = 0;
2187 caps->idx_ba_pg_sz = 0;
2188 caps->idx_buf_pg_sz = 0;
2189 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2190 caps->srqc_hop_num, caps->srqc_bt_num,
2191 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2192 HEM_TYPE_SRQC);
2193 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2194 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2195 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2196 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2197 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2198 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2199 }
2200
2201 /* GMV */
2202 caps->gmv_ba_pg_sz = 0;
2203 caps->gmv_buf_pg_sz = 0;
2204 }
2205
2206 /* Apply all loaded caps before setting to hardware */
apply_func_caps(struct hns_roce_dev * hr_dev)2207 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2208 {
2209 #define MAX_GID_TBL_LEN 256
2210 struct hns_roce_caps *caps = &hr_dev->caps;
2211 struct hns_roce_v2_priv *priv = hr_dev->priv;
2212
2213 /* The following configurations don't need to be got from firmware. */
2214 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2215 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2216 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2217
2218 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2219 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2220 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2221
2222 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2223 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2224
2225 if (!caps->num_comp_vectors)
2226 caps->num_comp_vectors =
2227 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2228 (u32)priv->handle->rinfo.num_vectors -
2229 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2230
2231 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2232 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2233 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2234 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2235
2236 /* The following configurations will be overwritten */
2237 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2238 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2239 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2240
2241 /* The following configurations are not got from firmware */
2242 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2243
2244 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2245
2246 /* It's meaningless to support excessively large gid_table_len,
2247 * as the type of sgid_index in kernel struct ib_global_route
2248 * and userspace struct ibv_global_route are u8/uint8_t (0-255).
2249 */
2250 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN,
2251 caps->gmv_bt_num *
2252 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz));
2253
2254 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE /
2255 caps->gmv_entry_sz);
2256 } else {
2257 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2258
2259 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2260 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2261 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2262 caps->gid_table_len[0] /= func_num;
2263 }
2264
2265 if (hr_dev->is_vf) {
2266 caps->default_aeq_arm_st = 0x3;
2267 caps->default_ceq_arm_st = 0x3;
2268 caps->default_ceq_max_cnt = 0x1;
2269 caps->default_ceq_period = 0x10;
2270 caps->default_aeq_max_cnt = 0x1;
2271 caps->default_aeq_period = 0x10;
2272 }
2273
2274 set_hem_page_size(hr_dev);
2275 }
2276
hns_roce_query_caps(struct hns_roce_dev * hr_dev)2277 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)
2278 {
2279 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM] = {};
2280 struct hns_roce_caps *caps = &hr_dev->caps;
2281 struct hns_roce_query_pf_caps_a *resp_a;
2282 struct hns_roce_query_pf_caps_b *resp_b;
2283 struct hns_roce_query_pf_caps_c *resp_c;
2284 struct hns_roce_query_pf_caps_d *resp_d;
2285 struct hns_roce_query_pf_caps_e *resp_e;
2286 struct hns_roce_query_pf_caps_f *resp_f;
2287 enum hns_roce_opcode_type cmd;
2288 int ctx_hop_num;
2289 int pbl_hop_num;
2290 int cmd_num;
2291 int ret;
2292 int i;
2293
2294 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :
2295 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;
2296 cmd_num = hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
2297 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM_HIP08 :
2298 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM;
2299
2300 for (i = 0; i < cmd_num - 1; i++) {
2301 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);
2302 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2303 }
2304
2305 hns_roce_cmq_setup_basic_desc(&desc[cmd_num - 1], cmd, true);
2306 desc[cmd_num - 1].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2307
2308 ret = hns_roce_cmq_send(hr_dev, desc, cmd_num);
2309 if (ret)
2310 return ret;
2311
2312 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2313 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2314 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2315 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2316 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2317 resp_f = (struct hns_roce_query_pf_caps_f *)desc[5].data;
2318
2319 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2320 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2321 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2322 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2323 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2324 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2325 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2326 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2327 caps->num_other_vectors = resp_a->num_other_vectors;
2328 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2329 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2330
2331 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2332 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2333 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2334 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2335 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2336 caps->idx_entry_sz = resp_b->idx_entry_sz;
2337 caps->sccc_sz = resp_b->sccc_sz;
2338 caps->max_mtu = resp_b->max_mtu;
2339 caps->min_cqes = resp_b->min_cqes;
2340 caps->min_wqes = resp_b->min_wqes;
2341 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2342 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2343 caps->phy_num_uars = resp_b->phy_num_uars;
2344 ctx_hop_num = resp_b->ctx_hop_num;
2345 pbl_hop_num = resp_b->pbl_hop_num;
2346
2347 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2348
2349 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2350 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2351 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2352
2353 if (hr_dev->is_vf)
2354 caps->flags &= ~HNS_ROCE_CAP_FLAG_BOND;
2355
2356 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2357 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2358 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2359 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
2360 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2361 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2362 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2363 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2364 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2365
2366 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2367 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP);
2368 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2369 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2370 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2371 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2372 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG);
2373 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2374 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2375 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2376 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2377
2378 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2379 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2380 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2381 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
2382 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2383 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2384
2385 caps->max_ack_req_msg_len = le32_to_cpu(resp_f->max_ack_req_msg_len);
2386
2387 caps->qpc_hop_num = ctx_hop_num;
2388 caps->sccc_hop_num = ctx_hop_num;
2389 caps->srqc_hop_num = ctx_hop_num;
2390 caps->cqc_hop_num = ctx_hop_num;
2391 caps->mpt_hop_num = ctx_hop_num;
2392 caps->mtt_hop_num = pbl_hop_num;
2393 caps->cqe_hop_num = pbl_hop_num;
2394 caps->srqwqe_hop_num = pbl_hop_num;
2395 caps->idx_hop_num = pbl_hop_num;
2396 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2397 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2398 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2399
2400 if (!(caps->page_size_cap & PAGE_SIZE))
2401 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2402
2403 if (!hr_dev->is_vf) {
2404 caps->cqe_sz = resp_a->cqe_sz;
2405 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2406 caps->default_aeq_arm_st =
2407 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2408 caps->default_ceq_arm_st =
2409 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2410 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2411 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2412 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2413 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2414 }
2415
2416 return 0;
2417 }
2418
config_hem_entry_size(struct hns_roce_dev * hr_dev,u32 type,u32 val)2419 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2420 {
2421 struct hns_roce_cmq_desc desc;
2422 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2423
2424 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2425 false);
2426
2427 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2428 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2429
2430 return hns_roce_cmq_send(hr_dev, &desc, 1);
2431 }
2432
hns_roce_config_entry_size(struct hns_roce_dev * hr_dev)2433 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2434 {
2435 struct hns_roce_caps *caps = &hr_dev->caps;
2436 int ret;
2437
2438 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2439 return 0;
2440
2441 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2442 caps->qpc_sz);
2443 if (ret) {
2444 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2445 return ret;
2446 }
2447
2448 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2449 caps->sccc_sz);
2450 if (ret)
2451 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2452
2453 return ret;
2454 }
2455
hns_roce_v2_vf_profile(struct hns_roce_dev * hr_dev)2456 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2457 {
2458 struct device *dev = hr_dev->dev;
2459 int ret;
2460
2461 hr_dev->func_num = 1;
2462
2463 ret = hns_roce_query_caps(hr_dev);
2464 if (ret) {
2465 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);
2466 return ret;
2467 }
2468
2469 ret = hns_roce_query_vf_resource(hr_dev);
2470 if (ret) {
2471 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2472 return ret;
2473 }
2474
2475 apply_func_caps(hr_dev);
2476
2477 ret = hns_roce_v2_set_bt(hr_dev);
2478 if (ret)
2479 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2480
2481 return ret;
2482 }
2483
hns_roce_v2_pf_profile(struct hns_roce_dev * hr_dev)2484 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2485 {
2486 struct device *dev = hr_dev->dev;
2487 int ret;
2488
2489 ret = hns_roce_query_func_info(hr_dev);
2490 if (ret) {
2491 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2492 return ret;
2493 }
2494
2495 ret = hns_roce_config_global_param(hr_dev);
2496 if (ret) {
2497 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2498 return ret;
2499 }
2500
2501 ret = hns_roce_set_vf_switch_param(hr_dev);
2502 if (ret) {
2503 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2504 return ret;
2505 }
2506
2507 ret = hns_roce_query_caps(hr_dev);
2508 if (ret) {
2509 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);
2510 return ret;
2511 }
2512
2513 ret = hns_roce_query_pf_resource(hr_dev);
2514 if (ret) {
2515 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2516 return ret;
2517 }
2518
2519 apply_func_caps(hr_dev);
2520
2521 ret = hns_roce_alloc_vf_resource(hr_dev);
2522 if (ret) {
2523 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2524 return ret;
2525 }
2526
2527 ret = hns_roce_v2_set_bt(hr_dev);
2528 if (ret) {
2529 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2530 return ret;
2531 }
2532
2533 /* Configure the size of QPC, SCCC, etc. */
2534 return hns_roce_config_entry_size(hr_dev);
2535 }
2536
hns_roce_v2_profile(struct hns_roce_dev * hr_dev)2537 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2538 {
2539 struct device *dev = hr_dev->dev;
2540 int ret;
2541
2542 ret = hns_roce_cmq_query_hw_info(hr_dev);
2543 if (ret) {
2544 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2545 return ret;
2546 }
2547
2548 ret = hns_roce_query_fw_ver(hr_dev);
2549 if (ret) {
2550 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2551 return ret;
2552 }
2553
2554 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2555 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2556
2557 if (hr_dev->is_vf)
2558 return hns_roce_v2_vf_profile(hr_dev);
2559 else
2560 return hns_roce_v2_pf_profile(hr_dev);
2561 }
2562
config_llm_table(struct hns_roce_buf * data_buf,void * cfg_buf)2563 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2564 {
2565 u32 i, next_ptr, page_num;
2566 __le64 *entry = cfg_buf;
2567 dma_addr_t addr;
2568 u64 val;
2569
2570 page_num = data_buf->npages;
2571 for (i = 0; i < page_num; i++) {
2572 addr = hns_roce_buf_page(data_buf, i);
2573 if (i == (page_num - 1))
2574 next_ptr = 0;
2575 else
2576 next_ptr = i + 1;
2577
2578 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2579 entry[i] = cpu_to_le64(val);
2580 }
2581 }
2582
set_llm_cfg_to_hw(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * table)2583 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2584 struct hns_roce_link_table *table)
2585 {
2586 struct hns_roce_cmq_desc desc[2];
2587 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2588 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2589 struct hns_roce_buf *buf = table->buf;
2590 enum hns_roce_opcode_type opcode;
2591 dma_addr_t addr;
2592
2593 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2594 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2595 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2596 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2597
2598 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2599 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2600 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2601 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2602 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2603
2604 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2605 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2606 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2607 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2608 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2609
2610 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2611 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2612 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2613 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2614
2615 return hns_roce_cmq_send(hr_dev, desc, 2);
2616 }
2617
2618 static struct hns_roce_link_table *
alloc_link_table_buf(struct hns_roce_dev * hr_dev)2619 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2620 {
2621 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;
2622 struct hns_roce_v2_priv *priv = hr_dev->priv;
2623 struct hns_roce_link_table *link_tbl;
2624 u32 pg_shift, size, min_size;
2625
2626 link_tbl = &priv->ext_llm;
2627 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2628 size = hr_dev->caps.num_qps * hr_dev->func_num *
2629 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2630 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;
2631
2632 /* Alloc data table */
2633 size = max(size, min_size);
2634 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2635 if (IS_ERR(link_tbl->buf))
2636 return ERR_PTR(-ENOMEM);
2637
2638 /* Alloc config table */
2639 size = link_tbl->buf->npages * sizeof(u64);
2640 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2641 &link_tbl->table.map,
2642 GFP_KERNEL);
2643 if (!link_tbl->table.buf) {
2644 hns_roce_buf_free(hr_dev, link_tbl->buf);
2645 return ERR_PTR(-ENOMEM);
2646 }
2647
2648 return link_tbl;
2649 }
2650
free_link_table_buf(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * tbl)2651 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2652 struct hns_roce_link_table *tbl)
2653 {
2654 if (tbl->buf) {
2655 u32 size = tbl->buf->npages * sizeof(u64);
2656
2657 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2658 tbl->table.map);
2659 }
2660
2661 hns_roce_buf_free(hr_dev, tbl->buf);
2662 }
2663
hns_roce_init_link_table(struct hns_roce_dev * hr_dev)2664 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2665 {
2666 struct hns_roce_link_table *link_tbl;
2667 int ret;
2668
2669 link_tbl = alloc_link_table_buf(hr_dev);
2670 if (IS_ERR(link_tbl))
2671 return -ENOMEM;
2672
2673 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2674 ret = -EINVAL;
2675 goto err_alloc;
2676 }
2677
2678 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2679 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2680 if (ret)
2681 goto err_alloc;
2682
2683 return 0;
2684
2685 err_alloc:
2686 free_link_table_buf(hr_dev, link_tbl);
2687 return ret;
2688 }
2689
hns_roce_free_link_table(struct hns_roce_dev * hr_dev)2690 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2691 {
2692 struct hns_roce_v2_priv *priv = hr_dev->priv;
2693
2694 free_link_table_buf(hr_dev, &priv->ext_llm);
2695 }
2696
free_dip_entry(struct hns_roce_dev * hr_dev)2697 static void free_dip_entry(struct hns_roce_dev *hr_dev)
2698 {
2699 struct hns_roce_dip *hr_dip;
2700 unsigned long idx;
2701
2702 xa_lock(&hr_dev->qp_table.dip_xa);
2703
2704 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) {
2705 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx);
2706 kfree(hr_dip);
2707 }
2708
2709 xa_unlock(&hr_dev->qp_table.dip_xa);
2710 }
2711
free_mr_init_pd(struct hns_roce_dev * hr_dev)2712 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2713 {
2714 struct hns_roce_v2_priv *priv = hr_dev->priv;
2715 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2716 struct ib_device *ibdev = &hr_dev->ib_dev;
2717 struct hns_roce_pd *hr_pd;
2718 struct ib_pd *pd;
2719
2720 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2721 if (!hr_pd)
2722 return NULL;
2723 pd = &hr_pd->ibpd;
2724 pd->device = ibdev;
2725
2726 if (hns_roce_alloc_pd(pd, NULL)) {
2727 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2728 kfree(hr_pd);
2729 return NULL;
2730 }
2731 free_mr->rsv_pd = to_hr_pd(pd);
2732 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2733 free_mr->rsv_pd->ibpd.uobject = NULL;
2734 free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2735 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2736
2737 return pd;
2738 }
2739
free_mr_init_cq(struct hns_roce_dev * hr_dev)2740 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2741 {
2742 struct hns_roce_v2_priv *priv = hr_dev->priv;
2743 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2744 struct ib_device *ibdev = &hr_dev->ib_dev;
2745 struct ib_cq_init_attr cq_init_attr = {};
2746 struct hns_roce_cq *hr_cq;
2747 struct ib_cq *cq;
2748
2749 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2750
2751 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2752 if (!hr_cq)
2753 return NULL;
2754
2755 cq = &hr_cq->ib_cq;
2756 cq->device = ibdev;
2757
2758 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2759 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2760 kfree(hr_cq);
2761 return NULL;
2762 }
2763 free_mr->rsv_cq = to_hr_cq(cq);
2764 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2765 free_mr->rsv_cq->ib_cq.uobject = NULL;
2766 free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2767 free_mr->rsv_cq->ib_cq.event_handler = NULL;
2768 free_mr->rsv_cq->ib_cq.cq_context = NULL;
2769 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2770
2771 return cq;
2772 }
2773
free_mr_init_qp(struct hns_roce_dev * hr_dev,struct ib_cq * cq,struct ib_qp_init_attr * init_attr,int i)2774 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2775 struct ib_qp_init_attr *init_attr, int i)
2776 {
2777 struct hns_roce_v2_priv *priv = hr_dev->priv;
2778 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2779 struct ib_device *ibdev = &hr_dev->ib_dev;
2780 struct hns_roce_qp *hr_qp;
2781 struct ib_qp *qp;
2782 int ret;
2783
2784 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2785 if (!hr_qp)
2786 return -ENOMEM;
2787
2788 qp = &hr_qp->ibqp;
2789 qp->device = ibdev;
2790
2791 ret = hns_roce_create_qp(qp, init_attr, NULL);
2792 if (ret) {
2793 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2794 kfree(hr_qp);
2795 return ret;
2796 }
2797
2798 free_mr->rsv_qp[i] = hr_qp;
2799 free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2800 free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2801
2802 return 0;
2803 }
2804
free_mr_exit(struct hns_roce_dev * hr_dev)2805 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2806 {
2807 struct hns_roce_v2_priv *priv = hr_dev->priv;
2808 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2809 struct ib_qp *qp;
2810 int i;
2811
2812 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2813 if (free_mr->rsv_qp[i]) {
2814 qp = &free_mr->rsv_qp[i]->ibqp;
2815 hns_roce_v2_destroy_qp(qp, NULL);
2816 kfree(free_mr->rsv_qp[i]);
2817 free_mr->rsv_qp[i] = NULL;
2818 }
2819 }
2820
2821 if (free_mr->rsv_cq) {
2822 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2823 kfree(free_mr->rsv_cq);
2824 free_mr->rsv_cq = NULL;
2825 }
2826
2827 if (free_mr->rsv_pd) {
2828 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2829 kfree(free_mr->rsv_pd);
2830 free_mr->rsv_pd = NULL;
2831 }
2832
2833 mutex_destroy(&free_mr->mutex);
2834 }
2835
free_mr_alloc_res(struct hns_roce_dev * hr_dev)2836 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2837 {
2838 struct hns_roce_v2_priv *priv = hr_dev->priv;
2839 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2840 struct ib_qp_init_attr qp_init_attr = {};
2841 struct ib_pd *pd;
2842 struct ib_cq *cq;
2843 int ret;
2844 int i;
2845
2846 pd = free_mr_init_pd(hr_dev);
2847 if (!pd)
2848 return -ENOMEM;
2849
2850 cq = free_mr_init_cq(hr_dev);
2851 if (!cq) {
2852 ret = -ENOMEM;
2853 goto create_failed_cq;
2854 }
2855
2856 qp_init_attr.qp_type = IB_QPT_RC;
2857 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2858 qp_init_attr.send_cq = cq;
2859 qp_init_attr.recv_cq = cq;
2860 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2861 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2862 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2863 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2864 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2865
2866 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2867 if (ret)
2868 goto create_failed_qp;
2869 }
2870
2871 return 0;
2872
2873 create_failed_qp:
2874 for (i--; i >= 0; i--) {
2875 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL);
2876 kfree(free_mr->rsv_qp[i]);
2877 }
2878 hns_roce_destroy_cq(cq, NULL);
2879 kfree(cq);
2880
2881 create_failed_cq:
2882 hns_roce_dealloc_pd(pd, NULL);
2883 kfree(pd);
2884
2885 return ret;
2886 }
2887
free_mr_modify_rsv_qp(struct hns_roce_dev * hr_dev,struct ib_qp_attr * attr,int sl_num)2888 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2889 struct ib_qp_attr *attr, int sl_num)
2890 {
2891 struct hns_roce_v2_priv *priv = hr_dev->priv;
2892 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2893 struct ib_device *ibdev = &hr_dev->ib_dev;
2894 struct hns_roce_qp *hr_qp;
2895 int loopback;
2896 int mask;
2897 int ret;
2898
2899 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2900 hr_qp->free_mr_en = 1;
2901 hr_qp->ibqp.device = ibdev;
2902 hr_qp->ibqp.qp_type = IB_QPT_RC;
2903
2904 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2905 attr->qp_state = IB_QPS_INIT;
2906 attr->port_num = 1;
2907 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2908 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2909 IB_QPS_INIT, NULL);
2910 if (ret) {
2911 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n",
2912 ret);
2913 return ret;
2914 }
2915
2916 loopback = hr_dev->loop_idc;
2917 /* Set qpc lbi = 1 incidate loopback IO */
2918 hr_dev->loop_idc = 1;
2919
2920 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2921 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2922 attr->qp_state = IB_QPS_RTR;
2923 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2924 attr->path_mtu = IB_MTU_256;
2925 attr->dest_qp_num = hr_qp->qpn;
2926 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2927
2928 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2929
2930 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2931 IB_QPS_RTR, NULL);
2932 hr_dev->loop_idc = loopback;
2933 if (ret) {
2934 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2935 ret);
2936 return ret;
2937 }
2938
2939 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2940 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2941 attr->qp_state = IB_QPS_RTS;
2942 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2943 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2944 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2945 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2946 IB_QPS_RTS, NULL);
2947 if (ret)
2948 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2949 ret);
2950
2951 return ret;
2952 }
2953
free_mr_modify_qp(struct hns_roce_dev * hr_dev)2954 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2955 {
2956 struct hns_roce_v2_priv *priv = hr_dev->priv;
2957 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2958 struct ib_qp_attr attr = {};
2959 int ret;
2960 int i;
2961
2962 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2963 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2964 rdma_ah_set_port_num(&attr.ah_attr, 1);
2965
2966 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2967 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2968 if (ret)
2969 return ret;
2970 }
2971
2972 return 0;
2973 }
2974
free_mr_init(struct hns_roce_dev * hr_dev)2975 static int free_mr_init(struct hns_roce_dev *hr_dev)
2976 {
2977 struct hns_roce_v2_priv *priv = hr_dev->priv;
2978 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2979 int ret;
2980
2981 mutex_init(&free_mr->mutex);
2982
2983 ret = free_mr_alloc_res(hr_dev);
2984 if (ret) {
2985 mutex_destroy(&free_mr->mutex);
2986 return ret;
2987 }
2988
2989 ret = free_mr_modify_qp(hr_dev);
2990 if (ret)
2991 goto err_modify_qp;
2992
2993 return 0;
2994
2995 err_modify_qp:
2996 free_mr_exit(hr_dev);
2997
2998 return ret;
2999 }
3000
get_hem_table(struct hns_roce_dev * hr_dev)3001 static int get_hem_table(struct hns_roce_dev *hr_dev)
3002 {
3003 unsigned int qpc_count;
3004 unsigned int cqc_count;
3005 unsigned int gmv_count;
3006 int ret;
3007 int i;
3008
3009 /* Alloc memory for source address table buffer space chunk */
3010 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
3011 gmv_count++) {
3012 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
3013 if (ret)
3014 goto err_gmv_failed;
3015 }
3016
3017 if (hr_dev->is_vf)
3018 return 0;
3019
3020 /* Alloc memory for QPC Timer buffer space chunk */
3021 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
3022 qpc_count++) {
3023 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
3024 qpc_count);
3025 if (ret) {
3026 dev_err(hr_dev->dev, "QPC Timer get failed\n");
3027 goto err_qpc_timer_failed;
3028 }
3029 }
3030
3031 /* Alloc memory for CQC Timer buffer space chunk */
3032 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
3033 cqc_count++) {
3034 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
3035 cqc_count);
3036 if (ret) {
3037 dev_err(hr_dev->dev, "CQC Timer get failed\n");
3038 goto err_cqc_timer_failed;
3039 }
3040 }
3041
3042 return 0;
3043
3044 err_cqc_timer_failed:
3045 for (i = 0; i < cqc_count; i++)
3046 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
3047
3048 err_qpc_timer_failed:
3049 for (i = 0; i < qpc_count; i++)
3050 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
3051
3052 err_gmv_failed:
3053 for (i = 0; i < gmv_count; i++)
3054 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
3055
3056 return ret;
3057 }
3058
put_hem_table(struct hns_roce_dev * hr_dev)3059 static void put_hem_table(struct hns_roce_dev *hr_dev)
3060 {
3061 int i;
3062
3063 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
3064 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
3065
3066 if (hr_dev->is_vf)
3067 return;
3068
3069 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
3070 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
3071
3072 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
3073 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
3074 }
3075
hns_roce_v2_init(struct hns_roce_dev * hr_dev)3076 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
3077 {
3078 int ret;
3079
3080 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
3081 ret = free_mr_init(hr_dev);
3082 if (ret) {
3083 dev_err(hr_dev->dev, "failed to init free mr!\n");
3084 return ret;
3085 }
3086 }
3087
3088 /* The hns ROCEE requires the extdb info to be cleared before using */
3089 ret = hns_roce_clear_extdb_list_info(hr_dev);
3090 if (ret)
3091 goto err_clear_extdb_failed;
3092
3093 ret = get_hem_table(hr_dev);
3094 if (ret)
3095 goto err_get_hem_table_failed;
3096
3097 if (hr_dev->is_vf)
3098 return 0;
3099
3100 ret = hns_roce_init_link_table(hr_dev);
3101 if (ret) {
3102 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
3103 goto err_llm_init_failed;
3104 }
3105
3106 return 0;
3107
3108 err_llm_init_failed:
3109 put_hem_table(hr_dev);
3110 err_get_hem_table_failed:
3111 hns_roce_function_clear(hr_dev);
3112 err_clear_extdb_failed:
3113 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3114 free_mr_exit(hr_dev);
3115
3116 return ret;
3117 }
3118
hns_roce_v2_exit(struct hns_roce_dev * hr_dev)3119 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
3120 {
3121 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3122 free_mr_exit(hr_dev);
3123
3124 hns_roce_function_clear(hr_dev);
3125
3126 if (!hr_dev->is_vf)
3127 hns_roce_free_link_table(hr_dev);
3128
3129 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3130 free_dip_entry(hr_dev);
3131 }
3132
hns_roce_mbox_post(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3133 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
3134 struct hns_roce_mbox_msg *mbox_msg)
3135 {
3136 struct hns_roce_cmq_desc desc;
3137 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
3138
3139 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
3140
3141 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
3142 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
3143 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
3144 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
3145 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
3146 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
3147 mbox_msg->token);
3148
3149 return hns_roce_cmq_send(hr_dev, &desc, 1);
3150 }
3151
v2_wait_mbox_complete(struct hns_roce_dev * hr_dev,u32 timeout,u8 * complete_status)3152 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
3153 u8 *complete_status)
3154 {
3155 struct hns_roce_mbox_status *mb_st;
3156 struct hns_roce_cmq_desc desc;
3157 unsigned long end;
3158 int ret = -EBUSY;
3159 u32 status;
3160 bool busy;
3161
3162 mb_st = (struct hns_roce_mbox_status *)desc.data;
3163 end = msecs_to_jiffies(timeout) + jiffies;
3164 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
3165 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
3166 return -EIO;
3167
3168 status = 0;
3169 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
3170 true);
3171 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
3172 if (!ret) {
3173 status = le32_to_cpu(mb_st->mb_status_hw_run);
3174 /* No pending message exists in ROCEE mbox. */
3175 if (!(status & MB_ST_HW_RUN_M))
3176 break;
3177 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3178 break;
3179 }
3180
3181 if (time_after(jiffies, end)) {
3182 dev_err_ratelimited(hr_dev->dev,
3183 "failed to wait mbox status 0x%x\n",
3184 status);
3185 return -ETIMEDOUT;
3186 }
3187
3188 cond_resched();
3189 ret = -EBUSY;
3190 }
3191
3192 if (!ret) {
3193 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3194 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3195 /* Ignore all errors if the mbox is unavailable. */
3196 ret = 0;
3197 *complete_status = MB_ST_COMPLETE_M;
3198 }
3199
3200 return ret;
3201 }
3202
v2_post_mbox(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3203 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3204 struct hns_roce_mbox_msg *mbox_msg)
3205 {
3206 u8 status = 0;
3207 int ret;
3208
3209 /* Waiting for the mbox to be idle */
3210 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3211 &status);
3212 if (unlikely(ret)) {
3213 dev_err_ratelimited(hr_dev->dev,
3214 "failed to check post mbox status = 0x%x, ret = %d.\n",
3215 status, ret);
3216 return ret;
3217 }
3218
3219 /* Post new message to mbox */
3220 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3221 if (ret)
3222 dev_err_ratelimited(hr_dev->dev,
3223 "failed to post mailbox, ret = %d.\n", ret);
3224
3225 return ret;
3226 }
3227
v2_poll_mbox_done(struct hns_roce_dev * hr_dev)3228 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3229 {
3230 u8 status = 0;
3231 int ret;
3232
3233 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3234 &status);
3235 if (!ret) {
3236 if (status != MB_ST_COMPLETE_SUCC)
3237 return -EBUSY;
3238 } else {
3239 dev_err_ratelimited(hr_dev->dev,
3240 "failed to check mbox status = 0x%x, ret = %d.\n",
3241 status, ret);
3242 }
3243
3244 return ret;
3245 }
3246
copy_gid(void * dest,const union ib_gid * gid)3247 static void copy_gid(void *dest, const union ib_gid *gid)
3248 {
3249 #define GID_SIZE 4
3250 const union ib_gid *src = gid;
3251 __le32 (*p)[GID_SIZE] = dest;
3252 int i;
3253
3254 if (!gid)
3255 src = &zgid;
3256
3257 for (i = 0; i < GID_SIZE; i++)
3258 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3259 }
3260
config_sgid_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type)3261 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3262 int gid_index, const union ib_gid *gid,
3263 enum hns_roce_sgid_type sgid_type)
3264 {
3265 struct hns_roce_cmq_desc desc;
3266 struct hns_roce_cfg_sgid_tb *sgid_tb =
3267 (struct hns_roce_cfg_sgid_tb *)desc.data;
3268
3269 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3270
3271 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3272 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3273
3274 copy_gid(&sgid_tb->vf_sgid_l, gid);
3275
3276 return hns_roce_cmq_send(hr_dev, &desc, 1);
3277 }
3278
config_gmv_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type,const struct ib_gid_attr * attr)3279 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3280 int gid_index, const union ib_gid *gid,
3281 enum hns_roce_sgid_type sgid_type,
3282 const struct ib_gid_attr *attr)
3283 {
3284 struct hns_roce_cmq_desc desc[2];
3285 struct hns_roce_cfg_gmv_tb_a *tb_a =
3286 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3287 struct hns_roce_cfg_gmv_tb_b *tb_b =
3288 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3289
3290 u16 vlan_id = VLAN_CFI_MASK;
3291 u8 mac[ETH_ALEN] = {};
3292 int ret;
3293
3294 if (gid) {
3295 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3296 if (ret)
3297 return ret;
3298 }
3299
3300 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3301 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3302
3303 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3304
3305 copy_gid(&tb_a->vf_sgid_l, gid);
3306
3307 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3308 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3309 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3310
3311 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3312
3313 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3314 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3315
3316 return hns_roce_cmq_send(hr_dev, desc, 2);
3317 }
3318
hns_roce_v2_set_gid(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)3319 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3320 const union ib_gid *gid,
3321 const struct ib_gid_attr *attr)
3322 {
3323 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3324 int ret;
3325
3326 if (gid) {
3327 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3328 if (ipv6_addr_v4mapped((void *)gid))
3329 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3330 else
3331 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3332 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3333 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3334 }
3335 }
3336
3337 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3338 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3339 else
3340 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3341
3342 if (ret)
3343 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3344 ret);
3345
3346 return ret;
3347 }
3348
hns_roce_v2_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,const u8 * addr)3349 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3350 const u8 *addr)
3351 {
3352 struct hns_roce_cmq_desc desc;
3353 struct hns_roce_cfg_smac_tb *smac_tb =
3354 (struct hns_roce_cfg_smac_tb *)desc.data;
3355 u16 reg_smac_h;
3356 u32 reg_smac_l;
3357
3358 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3359
3360 reg_smac_l = *(u32 *)(&addr[0]);
3361 reg_smac_h = *(u16 *)(&addr[4]);
3362
3363 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3364 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3365 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3366
3367 return hns_roce_cmq_send(hr_dev, &desc, 1);
3368 }
3369
set_mtpt_pbl(struct hns_roce_dev * hr_dev,struct hns_roce_v2_mpt_entry * mpt_entry,struct hns_roce_mr * mr)3370 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3371 struct hns_roce_v2_mpt_entry *mpt_entry,
3372 struct hns_roce_mr *mr)
3373 {
3374 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3375 struct ib_device *ibdev = &hr_dev->ib_dev;
3376 dma_addr_t pbl_ba;
3377 int ret;
3378 int i;
3379
3380 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3381 min_t(int, ARRAY_SIZE(pages), mr->npages));
3382 if (ret) {
3383 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret);
3384 return ret;
3385 }
3386
3387 /* Aligned to the hardware address access unit */
3388 for (i = 0; i < ARRAY_SIZE(pages); i++)
3389 pages[i] >>= MPT_PBL_BUF_ADDR_S;
3390
3391 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3392
3393 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3394 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S);
3395 hr_reg_write(mpt_entry, MPT_PBL_BA_H,
3396 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S));
3397
3398 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3399 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3400
3401 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3402 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3403 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3404 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3405
3406 return 0;
3407 }
3408
hns_roce_v2_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)3409 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3410 void *mb_buf, struct hns_roce_mr *mr)
3411 {
3412 struct hns_roce_v2_mpt_entry *mpt_entry;
3413
3414 mpt_entry = mb_buf;
3415 memset(mpt_entry, 0, sizeof(*mpt_entry));
3416
3417 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3418 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3419
3420 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3421 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3422 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3423 mr->access & IB_ACCESS_REMOTE_READ);
3424 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3425 mr->access & IB_ACCESS_REMOTE_WRITE);
3426 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3427 mr->access & IB_ACCESS_LOCAL_WRITE);
3428
3429 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3430 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3431 mpt_entry->lkey = cpu_to_le32(mr->key);
3432 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3433 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3434
3435 if (mr->type != MR_TYPE_MR)
3436 hr_reg_enable(mpt_entry, MPT_PA);
3437
3438 if (mr->type == MR_TYPE_DMA)
3439 return 0;
3440
3441 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3442 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3443
3444 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3445 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3446 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3447
3448 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3449 }
3450
hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,int flags,void * mb_buf)3451 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3452 struct hns_roce_mr *mr, int flags,
3453 void *mb_buf)
3454 {
3455 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3456 u32 mr_access_flags = mr->access;
3457 int ret = 0;
3458
3459 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3460 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3461
3462 if (flags & IB_MR_REREG_ACCESS) {
3463 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3464 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3465 hr_reg_write(mpt_entry, MPT_RR_EN,
3466 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3467 hr_reg_write(mpt_entry, MPT_RW_EN,
3468 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3469 hr_reg_write(mpt_entry, MPT_LW_EN,
3470 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3471 }
3472
3473 if (flags & IB_MR_REREG_TRANS) {
3474 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3475 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3476 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3477 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3478
3479 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3480 }
3481
3482 return ret;
3483 }
3484
hns_roce_v2_frmr_write_mtpt(void * mb_buf,struct hns_roce_mr * mr)3485 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
3486 {
3487 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3488 struct hns_roce_v2_mpt_entry *mpt_entry;
3489
3490 mpt_entry = mb_buf;
3491 memset(mpt_entry, 0, sizeof(*mpt_entry));
3492
3493 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3494 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3495
3496 hr_reg_enable(mpt_entry, MPT_RA_EN);
3497 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3498
3499 hr_reg_enable(mpt_entry, MPT_FRE);
3500 hr_reg_enable(mpt_entry, MPT_BPD);
3501 hr_reg_clear(mpt_entry, MPT_PA);
3502
3503 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3504 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3505 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3506 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3507 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3508
3509 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3510
3511 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >>
3512 MPT_PBL_BA_ADDR_S));
3513 hr_reg_write(mpt_entry, MPT_PBL_BA_H,
3514 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S));
3515
3516 return 0;
3517 }
3518
free_mr_post_send_lp_wqe(struct hns_roce_qp * hr_qp)3519 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3520 {
3521 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3522 struct ib_device *ibdev = &hr_dev->ib_dev;
3523 const struct ib_send_wr *bad_wr;
3524 struct ib_rdma_wr rdma_wr = {};
3525 struct ib_send_wr *send_wr;
3526 int ret;
3527
3528 send_wr = &rdma_wr.wr;
3529 send_wr->opcode = IB_WR_RDMA_WRITE;
3530
3531 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3532 if (ret) {
3533 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3534 ret);
3535 return ret;
3536 }
3537
3538 return 0;
3539 }
3540
3541 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3542 struct ib_wc *wc);
3543
free_mr_send_cmd_to_hw(struct hns_roce_dev * hr_dev)3544 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3545 {
3546 struct hns_roce_v2_priv *priv = hr_dev->priv;
3547 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3548 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3549 struct ib_device *ibdev = &hr_dev->ib_dev;
3550 struct hns_roce_qp *hr_qp;
3551 unsigned long end;
3552 int cqe_cnt = 0;
3553 int npolled;
3554 int ret;
3555 int i;
3556
3557 /*
3558 * If the device initialization is not complete or in the uninstall
3559 * process, then there is no need to execute free mr.
3560 */
3561 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3562 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3563 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3564 return;
3565
3566 mutex_lock(&free_mr->mutex);
3567
3568 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3569 hr_qp = free_mr->rsv_qp[i];
3570
3571 ret = free_mr_post_send_lp_wqe(hr_qp);
3572 if (ret) {
3573 ibdev_err_ratelimited(ibdev,
3574 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3575 hr_qp->qpn, ret);
3576 break;
3577 }
3578
3579 cqe_cnt++;
3580 }
3581
3582 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3583 while (cqe_cnt) {
3584 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3585 if (npolled < 0) {
3586 ibdev_err_ratelimited(ibdev,
3587 "failed to poll cqe for free mr, remain %d cqe.\n",
3588 cqe_cnt);
3589 goto out;
3590 }
3591
3592 if (time_after(jiffies, end)) {
3593 ibdev_err_ratelimited(ibdev,
3594 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3595 cqe_cnt);
3596 goto out;
3597 }
3598 cqe_cnt -= npolled;
3599 }
3600
3601 out:
3602 mutex_unlock(&free_mr->mutex);
3603 }
3604
hns_roce_v2_dereg_mr(struct hns_roce_dev * hr_dev)3605 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3606 {
3607 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3608 free_mr_send_cmd_to_hw(hr_dev);
3609 }
3610
get_cqe_v2(struct hns_roce_cq * hr_cq,int n)3611 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3612 {
3613 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3614 }
3615
get_sw_cqe_v2(struct hns_roce_cq * hr_cq,unsigned int n)3616 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3617 {
3618 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3619
3620 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3621 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3622 NULL;
3623 }
3624
update_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)3625 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3626 struct hns_roce_cq *hr_cq)
3627 {
3628 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3629 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3630 } else {
3631 struct hns_roce_v2_db cq_db = {};
3632
3633 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3634 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3635 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3636 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3637
3638 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3639 }
3640 }
3641
__hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3642 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3643 struct hns_roce_srq *srq)
3644 {
3645 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3646 struct hns_roce_v2_cqe *cqe, *dest;
3647 u32 prod_index;
3648 int nfreed = 0;
3649 int wqe_index;
3650 u8 owner_bit;
3651
3652 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3653 ++prod_index) {
3654 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3655 break;
3656 }
3657
3658 /*
3659 * Now backwards through the CQ, removing CQ entries
3660 * that match our QP by overwriting them with next entries.
3661 */
3662 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3663 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3664 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3665 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3666 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3667 hns_roce_free_srq_wqe(srq, wqe_index);
3668 }
3669 ++nfreed;
3670 } else if (nfreed) {
3671 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3672 hr_cq->ib_cq.cqe);
3673 owner_bit = hr_reg_read(dest, CQE_OWNER);
3674 memcpy(dest, cqe, hr_cq->cqe_size);
3675 hr_reg_write(dest, CQE_OWNER, owner_bit);
3676 }
3677 }
3678
3679 if (nfreed) {
3680 hr_cq->cons_index += nfreed;
3681 update_cq_db(hr_dev, hr_cq);
3682 }
3683 }
3684
hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3685 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3686 struct hns_roce_srq *srq)
3687 {
3688 spin_lock_irq(&hr_cq->lock);
3689 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3690 spin_unlock_irq(&hr_cq->lock);
3691 }
3692
hns_roce_v2_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)3693 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3694 struct hns_roce_cq *hr_cq, void *mb_buf,
3695 u64 *mtts, dma_addr_t dma_handle)
3696 {
3697 struct hns_roce_v2_cq_context *cq_context;
3698
3699 cq_context = mb_buf;
3700 memset(cq_context, 0, sizeof(*cq_context));
3701
3702 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3703 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3704 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3705 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3706 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3707
3708 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3709 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3710
3711 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3712 hr_reg_enable(cq_context, CQC_STASH);
3713
3714 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3715 to_hr_hw_page_addr(mtts[0]));
3716 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3717 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3718 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3719 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3720 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3721 to_hr_hw_page_addr(mtts[1]));
3722 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3723 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3724 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3725 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3726 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3727 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3728 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S);
3729 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S);
3730 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3731 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3732 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3733 ((u32)hr_cq->db.dma) >> 1);
3734 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3735 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S);
3736 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3737 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3738 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3739 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3740 }
3741
hns_roce_v2_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)3742 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3743 enum ib_cq_notify_flags flags)
3744 {
3745 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3746 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3747 struct hns_roce_v2_db cq_db = {};
3748 u32 notify_flag;
3749
3750 /*
3751 * flags = 0, then notify_flag : next
3752 * flags = 1, then notify flag : solocited
3753 */
3754 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3755 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3756
3757 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3758 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3759 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3760 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3761 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3762
3763 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3764
3765 return 0;
3766 }
3767
sw_comp(struct hns_roce_qp * hr_qp,struct hns_roce_wq * wq,int num_entries,struct ib_wc * wc)3768 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3769 int num_entries, struct ib_wc *wc)
3770 {
3771 unsigned int left;
3772 int npolled = 0;
3773
3774 left = wq->head - wq->tail;
3775 if (left == 0)
3776 return 0;
3777
3778 left = min_t(unsigned int, (unsigned int)num_entries, left);
3779 while (npolled < left) {
3780 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3781 wc->status = IB_WC_WR_FLUSH_ERR;
3782 wc->vendor_err = 0;
3783 wc->qp = &hr_qp->ibqp;
3784
3785 wq->tail++;
3786 wc++;
3787 npolled++;
3788 }
3789
3790 return npolled;
3791 }
3792
hns_roce_v2_sw_poll_cq(struct hns_roce_cq * hr_cq,int num_entries,struct ib_wc * wc)3793 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3794 struct ib_wc *wc)
3795 {
3796 struct hns_roce_qp *hr_qp;
3797 int npolled = 0;
3798
3799 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3800 npolled += sw_comp(hr_qp, &hr_qp->sq,
3801 num_entries - npolled, wc + npolled);
3802 if (npolled >= num_entries)
3803 goto out;
3804 }
3805
3806 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3807 npolled += sw_comp(hr_qp, &hr_qp->rq,
3808 num_entries - npolled, wc + npolled);
3809 if (npolled >= num_entries)
3810 goto out;
3811 }
3812
3813 out:
3814 return npolled;
3815 }
3816
get_cqe_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,struct hns_roce_cq * cq,struct hns_roce_v2_cqe * cqe,struct ib_wc * wc)3817 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3818 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3819 struct ib_wc *wc)
3820 {
3821 static const struct {
3822 u32 cqe_status;
3823 enum ib_wc_status wc_status;
3824 } map[] = {
3825 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3826 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3827 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3828 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3829 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3830 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3831 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3832 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3833 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3834 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3835 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3836 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3837 IB_WC_RETRY_EXC_ERR },
3838 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3839 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3840 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3841 };
3842
3843 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3844 int i;
3845
3846 wc->status = IB_WC_GENERAL_ERR;
3847 for (i = 0; i < ARRAY_SIZE(map); i++)
3848 if (cqe_status == map[i].cqe_status) {
3849 wc->status = map[i].wc_status;
3850 break;
3851 }
3852
3853 if (likely(wc->status == IB_WC_SUCCESS ||
3854 wc->status == IB_WC_WR_FLUSH_ERR))
3855 return;
3856
3857 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n",
3858 cqe_status);
3859 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3860 cq->cqe_size, false);
3861 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3862
3863 /*
3864 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3865 * the standard protocol, the driver must ignore it and needn't to set
3866 * the QP to an error state.
3867 */
3868 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3869 return;
3870
3871 flush_cqe(hr_dev, qp);
3872 }
3873
get_cur_qp(struct hns_roce_cq * hr_cq,struct hns_roce_v2_cqe * cqe,struct hns_roce_qp ** cur_qp)3874 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3875 struct hns_roce_qp **cur_qp)
3876 {
3877 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3878 struct hns_roce_qp *hr_qp = *cur_qp;
3879 u32 qpn;
3880
3881 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3882
3883 if (!hr_qp || qpn != hr_qp->qpn) {
3884 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3885 if (unlikely(!hr_qp)) {
3886 ibdev_err(&hr_dev->ib_dev,
3887 "CQ %06lx with entry for unknown QPN %06x\n",
3888 hr_cq->cqn, qpn);
3889 return -EINVAL;
3890 }
3891 *cur_qp = hr_qp;
3892 }
3893
3894 return 0;
3895 }
3896
3897 /*
3898 * mapped-value = 1 + real-value
3899 * The ib wc opcode's real value is start from 0, In order to distinguish
3900 * between initialized and uninitialized map values, we plus 1 to the actual
3901 * value when defining the mapping, so that the validity can be identified by
3902 * checking whether the mapped value is greater than 0.
3903 */
3904 #define HR_WC_OP_MAP(hr_key, ib_key) \
3905 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3906
3907 static const u32 wc_send_op_map[] = {
3908 HR_WC_OP_MAP(SEND, SEND),
3909 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3910 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3911 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3912 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3913 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3914 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3915 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3916 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3917 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3918 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3919 };
3920
to_ib_wc_send_op(u32 hr_opcode)3921 static int to_ib_wc_send_op(u32 hr_opcode)
3922 {
3923 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3924 return -EINVAL;
3925
3926 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3927 -EINVAL;
3928 }
3929
3930 static const u32 wc_recv_op_map[] = {
3931 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3932 HR_WC_OP_MAP(SEND, RECV),
3933 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3934 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3935 };
3936
to_ib_wc_recv_op(u32 hr_opcode)3937 static int to_ib_wc_recv_op(u32 hr_opcode)
3938 {
3939 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3940 return -EINVAL;
3941
3942 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3943 -EINVAL;
3944 }
3945
fill_send_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3946 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3947 {
3948 u32 hr_opcode;
3949 int ib_opcode;
3950
3951 wc->wc_flags = 0;
3952
3953 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3954 switch (hr_opcode) {
3955 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3956 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3957 break;
3958 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3959 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3960 wc->wc_flags |= IB_WC_WITH_IMM;
3961 break;
3962 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3963 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3964 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3965 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3966 wc->byte_len = 8;
3967 break;
3968 default:
3969 break;
3970 }
3971
3972 ib_opcode = to_ib_wc_send_op(hr_opcode);
3973 if (ib_opcode < 0)
3974 wc->status = IB_WC_GENERAL_ERR;
3975 else
3976 wc->opcode = ib_opcode;
3977 }
3978
fill_recv_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3979 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3980 {
3981 u32 hr_opcode;
3982 int ib_opcode;
3983
3984 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3985
3986 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3987 switch (hr_opcode) {
3988 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3989 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3990 wc->wc_flags = IB_WC_WITH_IMM;
3991 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3992 break;
3993 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3994 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3995 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3996 break;
3997 default:
3998 wc->wc_flags = 0;
3999 }
4000
4001 ib_opcode = to_ib_wc_recv_op(hr_opcode);
4002 if (ib_opcode < 0)
4003 wc->status = IB_WC_GENERAL_ERR;
4004 else
4005 wc->opcode = ib_opcode;
4006
4007 wc->sl = hr_reg_read(cqe, CQE_SL);
4008 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
4009 wc->slid = 0;
4010 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
4011 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
4012 wc->pkey_index = 0;
4013
4014 if (hr_reg_read(cqe, CQE_VID_VLD)) {
4015 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
4016 wc->wc_flags |= IB_WC_WITH_VLAN;
4017 } else {
4018 wc->vlan_id = 0xffff;
4019 }
4020
4021 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
4022
4023 return 0;
4024 }
4025
hns_roce_v2_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)4026 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
4027 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
4028 {
4029 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
4030 struct hns_roce_qp *qp = *cur_qp;
4031 struct hns_roce_srq *srq = NULL;
4032 struct hns_roce_v2_cqe *cqe;
4033 struct hns_roce_wq *wq;
4034 int is_send;
4035 u16 wqe_idx;
4036 int ret;
4037
4038 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
4039 if (!cqe)
4040 return -EAGAIN;
4041
4042 ++hr_cq->cons_index;
4043 /* Memory barrier */
4044 rmb();
4045
4046 ret = get_cur_qp(hr_cq, cqe, &qp);
4047 if (ret)
4048 return ret;
4049
4050 wc->qp = &qp->ibqp;
4051 wc->vendor_err = 0;
4052
4053 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
4054
4055 is_send = !hr_reg_read(cqe, CQE_S_R);
4056 if (is_send) {
4057 wq = &qp->sq;
4058
4059 /* If sg_signal_bit is set, tail pointer will be updated to
4060 * the WQE corresponding to the current CQE.
4061 */
4062 if (qp->sq_signal_bits)
4063 wq->tail += (wqe_idx - (u16)wq->tail) &
4064 (wq->wqe_cnt - 1);
4065
4066 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
4067 ++wq->tail;
4068
4069 fill_send_wc(wc, cqe);
4070 } else {
4071 if (qp->ibqp.srq) {
4072 srq = to_hr_srq(qp->ibqp.srq);
4073 wc->wr_id = srq->wrid[wqe_idx];
4074 hns_roce_free_srq_wqe(srq, wqe_idx);
4075 } else {
4076 wq = &qp->rq;
4077 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
4078 ++wq->tail;
4079 }
4080
4081 ret = fill_recv_wc(wc, cqe);
4082 }
4083
4084 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
4085 if (unlikely(wc->status != IB_WC_SUCCESS))
4086 return 0;
4087
4088 return ret;
4089 }
4090
hns_roce_v2_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)4091 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
4092 struct ib_wc *wc)
4093 {
4094 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4095 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4096 struct hns_roce_qp *cur_qp = NULL;
4097 unsigned long flags;
4098 int npolled;
4099
4100 spin_lock_irqsave(&hr_cq->lock, flags);
4101
4102 /*
4103 * When the device starts to reset, the state is RST_DOWN. At this time,
4104 * there may still be some valid CQEs in the hardware that are not
4105 * polled. Therefore, it is not allowed to switch to the software mode
4106 * immediately. When the state changes to UNINIT, CQE no longer exists
4107 * in the hardware, and then switch to software mode.
4108 */
4109 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
4110 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
4111 goto out;
4112 }
4113
4114 for (npolled = 0; npolled < num_entries; ++npolled) {
4115 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
4116 break;
4117 }
4118
4119 if (npolled)
4120 update_cq_db(hr_dev, hr_cq);
4121
4122 out:
4123 spin_unlock_irqrestore(&hr_cq->lock, flags);
4124
4125 return npolled;
4126 }
4127
get_op_for_set_hem(struct hns_roce_dev * hr_dev,u32 type,u32 step_idx,u8 * mbox_cmd)4128 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
4129 u32 step_idx, u8 *mbox_cmd)
4130 {
4131 u8 cmd;
4132
4133 switch (type) {
4134 case HEM_TYPE_QPC:
4135 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
4136 break;
4137 case HEM_TYPE_MTPT:
4138 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
4139 break;
4140 case HEM_TYPE_CQC:
4141 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
4142 break;
4143 case HEM_TYPE_SRQC:
4144 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4145 break;
4146 case HEM_TYPE_SCCC:
4147 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4148 break;
4149 case HEM_TYPE_QPC_TIMER:
4150 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4151 break;
4152 case HEM_TYPE_CQC_TIMER:
4153 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4154 break;
4155 default:
4156 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4157 return -EINVAL;
4158 }
4159
4160 *mbox_cmd = cmd + step_idx;
4161
4162 return 0;
4163 }
4164
config_gmv_ba_to_hw(struct hns_roce_dev * hr_dev,unsigned long obj,dma_addr_t base_addr)4165 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4166 dma_addr_t base_addr)
4167 {
4168 struct hns_roce_cmq_desc desc;
4169 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4170 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4171 u64 addr = to_hr_hw_page_addr(base_addr);
4172
4173 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4174
4175 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4176 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4177 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4178
4179 return hns_roce_cmq_send(hr_dev, &desc, 1);
4180 }
4181
set_hem_to_hw(struct hns_roce_dev * hr_dev,int obj,dma_addr_t base_addr,u32 hem_type,u32 step_idx)4182 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4183 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4184 {
4185 int ret;
4186 u8 cmd;
4187
4188 if (unlikely(hem_type == HEM_TYPE_GMV))
4189 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4190
4191 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4192 return 0;
4193
4194 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4195 if (ret < 0)
4196 return ret;
4197
4198 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4199 }
4200
hns_roce_v2_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,u32 step_idx)4201 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4202 struct hns_roce_hem_table *table, int obj,
4203 u32 step_idx)
4204 {
4205 struct hns_roce_hem_mhop mhop;
4206 struct hns_roce_hem *hem;
4207 unsigned long mhop_obj = obj;
4208 int i, j, k;
4209 int ret = 0;
4210 u64 hem_idx = 0;
4211 u64 l1_idx = 0;
4212 u64 bt_ba = 0;
4213 u32 chunk_ba_num;
4214 u32 hop_num;
4215
4216 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4217 return 0;
4218
4219 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4220 i = mhop.l0_idx;
4221 j = mhop.l1_idx;
4222 k = mhop.l2_idx;
4223 hop_num = mhop.hop_num;
4224 chunk_ba_num = mhop.bt_chunk_size / 8;
4225
4226 if (hop_num == 2) {
4227 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4228 k;
4229 l1_idx = i * chunk_ba_num + j;
4230 } else if (hop_num == 1) {
4231 hem_idx = i * chunk_ba_num + j;
4232 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4233 hem_idx = i;
4234 }
4235
4236 if (table->type == HEM_TYPE_SCCC)
4237 obj = mhop.l0_idx;
4238
4239 if (check_whether_last_step(hop_num, step_idx)) {
4240 hem = table->hem[hem_idx];
4241
4242 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx);
4243 } else {
4244 if (step_idx == 0)
4245 bt_ba = table->bt_l0_dma_addr[i];
4246 else if (step_idx == 1 && hop_num == 2)
4247 bt_ba = table->bt_l1_dma_addr[l1_idx];
4248
4249 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4250 }
4251
4252 return ret;
4253 }
4254
hns_roce_v2_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int tag,u32 step_idx)4255 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4256 struct hns_roce_hem_table *table,
4257 int tag, u32 step_idx)
4258 {
4259 struct hns_roce_cmd_mailbox *mailbox;
4260 struct device *dev = hr_dev->dev;
4261 u8 cmd = 0xff;
4262 int ret;
4263
4264 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4265 return 0;
4266
4267 switch (table->type) {
4268 case HEM_TYPE_QPC:
4269 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4270 break;
4271 case HEM_TYPE_MTPT:
4272 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4273 break;
4274 case HEM_TYPE_CQC:
4275 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4276 break;
4277 case HEM_TYPE_SRQC:
4278 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4279 break;
4280 case HEM_TYPE_SCCC:
4281 case HEM_TYPE_QPC_TIMER:
4282 case HEM_TYPE_CQC_TIMER:
4283 case HEM_TYPE_GMV:
4284 return 0;
4285 default:
4286 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4287 table->type);
4288 return 0;
4289 }
4290
4291 cmd += step_idx;
4292
4293 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4294 if (IS_ERR(mailbox))
4295 return PTR_ERR(mailbox);
4296
4297 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4298
4299 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4300 return ret;
4301 }
4302
hns_roce_v2_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct hns_roce_qp * hr_qp)4303 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4304 struct hns_roce_v2_qp_context *context,
4305 struct hns_roce_v2_qp_context *qpc_mask,
4306 struct hns_roce_qp *hr_qp)
4307 {
4308 struct hns_roce_cmd_mailbox *mailbox;
4309 int qpc_size;
4310 int ret;
4311
4312 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4313 if (IS_ERR(mailbox))
4314 return PTR_ERR(mailbox);
4315
4316 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4317 qpc_size = hr_dev->caps.qpc_sz;
4318 memcpy(mailbox->buf, context, qpc_size);
4319 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4320
4321 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4322 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4323
4324 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4325
4326 return ret;
4327 }
4328
set_access_flags(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,const struct ib_qp_attr * attr,int attr_mask)4329 static void set_access_flags(struct hns_roce_qp *hr_qp,
4330 struct hns_roce_v2_qp_context *context,
4331 struct hns_roce_v2_qp_context *qpc_mask,
4332 const struct ib_qp_attr *attr, int attr_mask)
4333 {
4334 u8 dest_rd_atomic;
4335 u32 access_flags;
4336
4337 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4338 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4339
4340 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4341 attr->qp_access_flags : hr_qp->atomic_rd_en;
4342
4343 if (!dest_rd_atomic)
4344 access_flags &= IB_ACCESS_REMOTE_WRITE;
4345
4346 hr_reg_write_bool(context, QPC_RRE,
4347 access_flags & IB_ACCESS_REMOTE_READ);
4348 hr_reg_clear(qpc_mask, QPC_RRE);
4349
4350 hr_reg_write_bool(context, QPC_RWE,
4351 access_flags & IB_ACCESS_REMOTE_WRITE);
4352 hr_reg_clear(qpc_mask, QPC_RWE);
4353
4354 hr_reg_write_bool(context, QPC_ATE,
4355 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4356 hr_reg_clear(qpc_mask, QPC_ATE);
4357 hr_reg_write_bool(context, QPC_EXT_ATE,
4358 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4359 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4360 }
4361
set_qpc_wqe_cnt(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context)4362 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4363 struct hns_roce_v2_qp_context *context)
4364 {
4365 hr_reg_write(context, QPC_SGE_SHIFT,
4366 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4367 hr_qp->sge.sge_shift));
4368
4369 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4370
4371 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4372 }
4373
get_cqn(struct ib_cq * ib_cq)4374 static inline int get_cqn(struct ib_cq *ib_cq)
4375 {
4376 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4377 }
4378
get_pdn(struct ib_pd * ib_pd)4379 static inline int get_pdn(struct ib_pd *ib_pd)
4380 {
4381 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4382 }
4383
modify_qp_reset_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context)4384 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4385 struct hns_roce_v2_qp_context *context)
4386 {
4387 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4388 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4389
4390 /*
4391 * In v2 engine, software pass context and context mask to hardware
4392 * when modifying qp. If software need modify some fields in context,
4393 * we should set all bits of the relevant fields in context mask to
4394 * 0 at the same time, else set them to 0x1.
4395 */
4396 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4397
4398 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4399
4400 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4401
4402 set_qpc_wqe_cnt(hr_qp, context);
4403
4404 /* No VLAN need to set 0xFFF */
4405 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4406
4407 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4408 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4409
4410 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4411 }
4412
4413 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4414 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4415
4416 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4417 hr_reg_enable(context, QPC_OWNER_MODE);
4418
4419 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4420 lower_32_bits(hr_qp->rdb.dma) >> 1);
4421 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4422 upper_32_bits(hr_qp->rdb.dma));
4423
4424 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4425
4426 if (ibqp->srq) {
4427 hr_reg_enable(context, QPC_SRQ_EN);
4428 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4429 }
4430
4431 hr_reg_enable(context, QPC_FRE);
4432
4433 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4434
4435 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4436 return;
4437
4438 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4439 hr_reg_enable(&context->ext, QPCEX_STASH);
4440 }
4441
modify_qp_init_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4442 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4443 struct hns_roce_v2_qp_context *context,
4444 struct hns_roce_v2_qp_context *qpc_mask)
4445 {
4446 /*
4447 * In v2 engine, software pass context and context mask to hardware
4448 * when modifying qp. If software need modify some fields in context,
4449 * we should set all bits of the relevant fields in context mask to
4450 * 0 at the same time, else set them to 0x1.
4451 */
4452 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4453 hr_reg_clear(qpc_mask, QPC_TST);
4454
4455 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4456 hr_reg_clear(qpc_mask, QPC_PD);
4457
4458 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4459 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4460
4461 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4462 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4463
4464 if (ibqp->srq) {
4465 hr_reg_enable(context, QPC_SRQ_EN);
4466 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4467 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4468 hr_reg_clear(qpc_mask, QPC_SRQN);
4469 }
4470 }
4471
config_qp_rq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4472 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4473 struct hns_roce_qp *hr_qp,
4474 struct hns_roce_v2_qp_context *context,
4475 struct hns_roce_v2_qp_context *qpc_mask)
4476 {
4477 u64 mtts[MTT_MIN_COUNT] = { 0 };
4478 u64 wqe_sge_ba;
4479 int ret;
4480
4481 /* Search qp buf's mtts */
4482 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4483 MTT_MIN_COUNT);
4484 if (hr_qp->rq.wqe_cnt && ret) {
4485 ibdev_err(&hr_dev->ib_dev,
4486 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n",
4487 hr_qp->qpn, ret);
4488 return ret;
4489 }
4490
4491 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr);
4492
4493 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4494 qpc_mask->wqe_sge_ba = 0;
4495
4496 /*
4497 * In v2 engine, software pass context and context mask to hardware
4498 * when modifying qp. If software need modify some fields in context,
4499 * we should set all bits of the relevant fields in context mask to
4500 * 0 at the same time, else set them to 0x1.
4501 */
4502 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4503 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4504
4505 hr_reg_write(context, QPC_SQ_HOP_NUM,
4506 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4507 hr_qp->sq.wqe_cnt));
4508 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4509
4510 hr_reg_write(context, QPC_SGE_HOP_NUM,
4511 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4512 hr_qp->sge.sge_cnt));
4513 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4514
4515 hr_reg_write(context, QPC_RQ_HOP_NUM,
4516 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4517 hr_qp->rq.wqe_cnt));
4518
4519 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4520
4521 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4522 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4523 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4524
4525 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4526 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4527 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4528
4529 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4530 qpc_mask->rq_cur_blk_addr = 0;
4531
4532 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4533 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4534 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4535
4536 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4537 context->rq_nxt_blk_addr =
4538 cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4539 qpc_mask->rq_nxt_blk_addr = 0;
4540 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4541 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4542 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4543 }
4544
4545 return 0;
4546 }
4547
config_qp_sq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4548 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4549 struct hns_roce_qp *hr_qp,
4550 struct hns_roce_v2_qp_context *context,
4551 struct hns_roce_v2_qp_context *qpc_mask)
4552 {
4553 struct ib_device *ibdev = &hr_dev->ib_dev;
4554 u64 sge_cur_blk = 0;
4555 u64 sq_cur_blk = 0;
4556 int ret;
4557
4558 /* search qp buf's mtts */
4559 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset,
4560 &sq_cur_blk, 1);
4561 if (ret) {
4562 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n",
4563 hr_qp->qpn, ret);
4564 return ret;
4565 }
4566 if (hr_qp->sge.sge_cnt > 0) {
4567 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4568 hr_qp->sge.offset, &sge_cur_blk, 1);
4569 if (ret) {
4570 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n",
4571 hr_qp->qpn, ret);
4572 return ret;
4573 }
4574 }
4575
4576 /*
4577 * In v2 engine, software pass context and context mask to hardware
4578 * when modifying qp. If software need modify some fields in context,
4579 * we should set all bits of the relevant fields in context mask to
4580 * 0 at the same time, else set them to 0x1.
4581 */
4582 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4583 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4584 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4585 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4586 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4587 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4588
4589 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4590 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4591 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4592 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4593 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4594 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4595
4596 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4597 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4598 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4599 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4600 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4601 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4602
4603 return 0;
4604 }
4605
get_mtu(struct ib_qp * ibqp,const struct ib_qp_attr * attr)4606 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4607 const struct ib_qp_attr *attr)
4608 {
4609 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4610 return IB_MTU_4096;
4611
4612 return attr->path_mtu;
4613 }
4614
modify_qp_init_to_rtr(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4615 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4616 const struct ib_qp_attr *attr, int attr_mask,
4617 struct hns_roce_v2_qp_context *context,
4618 struct hns_roce_v2_qp_context *qpc_mask,
4619 struct ib_udata *udata)
4620 {
4621 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
4622 struct hns_roce_ucontext, ibucontext);
4623 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4624 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4625 struct ib_device *ibdev = &hr_dev->ib_dev;
4626 dma_addr_t trrl_ba;
4627 dma_addr_t irrl_ba;
4628 enum ib_mtu ib_mtu;
4629 u8 ack_req_freq;
4630 const u8 *smac;
4631 int lp_msg_len;
4632 u8 lp_pktn_ini;
4633 u64 *mtts;
4634 u8 *dmac;
4635 u32 port;
4636 int mtu;
4637 int ret;
4638
4639 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4640 if (ret) {
4641 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4642 return ret;
4643 }
4644
4645 /* Search IRRL's mtts */
4646 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4647 hr_qp->qpn, &irrl_ba);
4648 if (!mtts) {
4649 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4650 return -EINVAL;
4651 }
4652
4653 /* Search TRRL's mtts */
4654 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4655 hr_qp->qpn, &trrl_ba);
4656 if (!mtts) {
4657 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4658 return -EINVAL;
4659 }
4660
4661 if (attr_mask & IB_QP_ALT_PATH) {
4662 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4663 attr_mask);
4664 return -EINVAL;
4665 }
4666
4667 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S);
4668 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4669 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S);
4670 qpc_mask->trrl_ba = 0;
4671 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S);
4672 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4673
4674 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S);
4675 qpc_mask->irrl_ba = 0;
4676 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S);
4677 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4678
4679 hr_reg_enable(context, QPC_RMT_E2E);
4680 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4681
4682 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4683 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4684
4685 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4686
4687 smac = (const u8 *)hr_dev->dev_addr[port];
4688 dmac = (u8 *)attr->ah_attr.roce.dmac;
4689 /* when dmac equals smac or loop_idc is 1, it should loopback */
4690 if (ether_addr_equal_unaligned(dmac, smac) ||
4691 hr_dev->loop_idc == 0x1) {
4692 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4693 hr_reg_clear(qpc_mask, QPC_LBI);
4694 }
4695
4696 if (attr_mask & IB_QP_DEST_QPN) {
4697 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4698 hr_reg_clear(qpc_mask, QPC_DQPN);
4699 }
4700
4701 memcpy(&context->dmac, dmac, sizeof(u32));
4702 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4703 qpc_mask->dmac = 0;
4704 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4705
4706 ib_mtu = get_mtu(ibqp, attr);
4707 hr_qp->path_mtu = ib_mtu;
4708
4709 mtu = ib_mtu_enum_to_int(ib_mtu);
4710 if (WARN_ON(mtu <= 0))
4711 return -EINVAL;
4712 #define MIN_LP_MSG_LEN 1024
4713 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */
4714 lp_msg_len = max(mtu, MIN_LP_MSG_LEN);
4715 lp_pktn_ini = ilog2(lp_msg_len / mtu);
4716
4717 if (attr_mask & IB_QP_PATH_MTU) {
4718 hr_reg_write(context, QPC_MTU, ib_mtu);
4719 hr_reg_clear(qpc_mask, QPC_MTU);
4720 }
4721
4722 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4723 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4724
4725 /*
4726 * There are several constraints for ACK_REQ_FREQ:
4727 * 1. mtu * (2 ^ ACK_REQ_FREQ) should not be too large, otherwise
4728 * it may cause some unexpected retries when sending large
4729 * payload.
4730 * 2. ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI.
4731 * 3. ACK_REQ_FREQ must be equal to LP_PKTN_INI when using LDCP
4732 * or HC3 congestion control algorithm.
4733 */
4734 if (hr_qp->cong_type == CONG_TYPE_LDCP ||
4735 hr_qp->cong_type == CONG_TYPE_HC3 ||
4736 hr_dev->caps.max_ack_req_msg_len < lp_msg_len)
4737 ack_req_freq = lp_pktn_ini;
4738 else
4739 ack_req_freq = ilog2(hr_dev->caps.max_ack_req_msg_len / mtu);
4740 hr_reg_write(context, QPC_ACK_REQ_FREQ, ack_req_freq);
4741 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4742
4743 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4744 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4745 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4746
4747 context->rq_rnr_timer = 0;
4748 qpc_mask->rq_rnr_timer = 0;
4749
4750 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4751 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4752
4753 #define MAX_LP_SGEN 3
4754 /* rocee send 2^lp_sgen_ini segs every time */
4755 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN);
4756 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4757
4758 if (udata && ibqp->qp_type == IB_QPT_RC &&
4759 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) {
4760 hr_reg_write_bool(context, QPC_RQIE,
4761 hr_dev->caps.flags &
4762 HNS_ROCE_CAP_FLAG_RQ_INLINE);
4763 hr_reg_clear(qpc_mask, QPC_RQIE);
4764 }
4765
4766 if (udata &&
4767 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) &&
4768 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) {
4769 hr_reg_write_bool(context, QPC_CQEIE,
4770 hr_dev->caps.flags &
4771 HNS_ROCE_CAP_FLAG_CQE_INLINE);
4772 hr_reg_clear(qpc_mask, QPC_CQEIE);
4773
4774 hr_reg_write(context, QPC_CQEIS, 0);
4775 hr_reg_clear(qpc_mask, QPC_CQEIS);
4776 }
4777
4778 return 0;
4779 }
4780
modify_qp_rtr_to_rts(struct ib_qp * ibqp,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4781 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask,
4782 struct hns_roce_v2_qp_context *context,
4783 struct hns_roce_v2_qp_context *qpc_mask)
4784 {
4785 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4786 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4787 struct ib_device *ibdev = &hr_dev->ib_dev;
4788 int ret;
4789
4790 /* Not support alternate path and path migration */
4791 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4792 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4793 return -EINVAL;
4794 }
4795
4796 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4797 if (ret) {
4798 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4799 return ret;
4800 }
4801
4802 /*
4803 * Set some fields in context to zero, Because the default values
4804 * of all fields in context are zero, we need not set them to 0 again.
4805 * but we should set the relevant fields of context mask to 0.
4806 */
4807 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4808
4809 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4810
4811 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4812 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4813 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4814
4815 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4816
4817 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4818
4819 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4820
4821 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4822
4823 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4824
4825 return 0;
4826 }
4827
alloc_dip_entry(struct xarray * dip_xa,u32 qpn)4828 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn)
4829 {
4830 struct hns_roce_dip *hr_dip;
4831 int ret;
4832
4833 hr_dip = xa_load(dip_xa, qpn);
4834 if (hr_dip)
4835 return 0;
4836
4837 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL);
4838 if (!hr_dip)
4839 return -ENOMEM;
4840
4841 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL));
4842 if (ret)
4843 kfree(hr_dip);
4844
4845 return ret;
4846 }
4847
get_dip_ctx_idx(struct ib_qp * ibqp,const struct ib_qp_attr * attr,u32 * dip_idx)4848 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4849 u32 *dip_idx)
4850 {
4851 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4852 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4853 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa;
4854 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4855 struct hns_roce_dip *hr_dip;
4856 unsigned long idx;
4857 int ret = 0;
4858
4859 ret = alloc_dip_entry(dip_xa, ibqp->qp_num);
4860 if (ret)
4861 return ret;
4862
4863 xa_lock(dip_xa);
4864
4865 xa_for_each(dip_xa, idx, hr_dip) {
4866 if (hr_dip->qp_cnt &&
4867 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) {
4868 *dip_idx = hr_dip->dip_idx;
4869 hr_dip->qp_cnt++;
4870 hr_qp->dip = hr_dip;
4871 goto out;
4872 }
4873 }
4874
4875 /* If no dgid is found, a new dip and a mapping between dgid and
4876 * dip_idx will be created.
4877 */
4878 xa_for_each(dip_xa, idx, hr_dip) {
4879 if (hr_dip->qp_cnt)
4880 continue;
4881
4882 *dip_idx = idx;
4883 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4884 hr_dip->dip_idx = idx;
4885 hr_dip->qp_cnt++;
4886 hr_qp->dip = hr_dip;
4887 break;
4888 }
4889
4890 /* This should never happen. */
4891 if (WARN_ON_ONCE(!hr_qp->dip))
4892 ret = -ENOSPC;
4893
4894 out:
4895 xa_unlock(dip_xa);
4896 return ret;
4897 }
4898
4899 enum {
4900 CONG_DCQCN,
4901 CONG_WINDOW,
4902 };
4903
4904 enum {
4905 UNSUPPORT_CONG_LEVEL,
4906 SUPPORT_CONG_LEVEL,
4907 };
4908
4909 enum {
4910 CONG_LDCP,
4911 CONG_HC3,
4912 };
4913
4914 enum {
4915 DIP_INVALID,
4916 DIP_VALID,
4917 };
4918
4919 enum {
4920 WND_LIMIT,
4921 WND_UNLIMIT,
4922 };
4923
check_cong_type(struct ib_qp * ibqp,struct hns_roce_congestion_algorithm * cong_alg)4924 static int check_cong_type(struct ib_qp *ibqp,
4925 struct hns_roce_congestion_algorithm *cong_alg)
4926 {
4927 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4928
4929 /* different congestion types match different configurations */
4930 switch (hr_qp->cong_type) {
4931 case CONG_TYPE_DCQCN:
4932 cong_alg->alg_sel = CONG_DCQCN;
4933 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4934 cong_alg->dip_vld = DIP_INVALID;
4935 cong_alg->wnd_mode_sel = WND_LIMIT;
4936 break;
4937 case CONG_TYPE_LDCP:
4938 cong_alg->alg_sel = CONG_WINDOW;
4939 cong_alg->alg_sub_sel = CONG_LDCP;
4940 cong_alg->dip_vld = DIP_INVALID;
4941 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4942 break;
4943 case CONG_TYPE_HC3:
4944 cong_alg->alg_sel = CONG_WINDOW;
4945 cong_alg->alg_sub_sel = CONG_HC3;
4946 cong_alg->dip_vld = DIP_INVALID;
4947 cong_alg->wnd_mode_sel = WND_LIMIT;
4948 break;
4949 case CONG_TYPE_DIP:
4950 cong_alg->alg_sel = CONG_DCQCN;
4951 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4952 cong_alg->dip_vld = DIP_VALID;
4953 cong_alg->wnd_mode_sel = WND_LIMIT;
4954 break;
4955 default:
4956 hr_qp->cong_type = CONG_TYPE_DCQCN;
4957 cong_alg->alg_sel = CONG_DCQCN;
4958 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4959 cong_alg->dip_vld = DIP_INVALID;
4960 cong_alg->wnd_mode_sel = WND_LIMIT;
4961 break;
4962 }
4963
4964 return 0;
4965 }
4966
fill_cong_field(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4967 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4968 struct hns_roce_v2_qp_context *context,
4969 struct hns_roce_v2_qp_context *qpc_mask)
4970 {
4971 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4972 struct hns_roce_congestion_algorithm cong_field;
4973 struct ib_device *ibdev = ibqp->device;
4974 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4975 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4976 u32 dip_idx = 0;
4977 int ret;
4978
4979 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4980 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4981 return 0;
4982
4983 ret = check_cong_type(ibqp, &cong_field);
4984 if (ret)
4985 return ret;
4986
4987 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4988 hr_qp->cong_type * HNS_ROCE_CONG_SIZE);
4989 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4990 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4991 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4992 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4993 cong_field.alg_sub_sel);
4994 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4995 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4996 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4997 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4998 cong_field.wnd_mode_sel);
4999 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
5000
5001 /* if dip is disabled, there is no need to set dip idx */
5002 if (cong_field.dip_vld == 0)
5003 return 0;
5004
5005 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
5006 if (ret) {
5007 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
5008 return ret;
5009 }
5010
5011 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
5012 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
5013
5014 return 0;
5015 }
5016
hns_roce_hw_v2_get_dscp(struct hns_roce_dev * hr_dev,u8 dscp,u8 * tc_mode,u8 * priority)5017 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp,
5018 u8 *tc_mode, u8 *priority)
5019 {
5020 struct hns_roce_v2_priv *priv = hr_dev->priv;
5021 struct hnae3_handle *handle = priv->handle;
5022 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
5023
5024 if (!ops->get_dscp_prio)
5025 return -EOPNOTSUPP;
5026
5027 return ops->get_dscp_prio(handle, dscp, tc_mode, priority);
5028 }
5029
check_sl_valid(struct hns_roce_dev * hr_dev,u8 sl)5030 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl)
5031 {
5032 u32 max_sl;
5033
5034 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1);
5035 if (unlikely(sl > max_sl)) {
5036 ibdev_err_ratelimited(&hr_dev->ib_dev,
5037 "failed to set SL(%u). Shouldn't be larger than %u.\n",
5038 sl, max_sl);
5039 return false;
5040 }
5041
5042 return true;
5043 }
5044
hns_roce_set_sl(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5045 static int hns_roce_set_sl(struct ib_qp *ibqp,
5046 const struct ib_qp_attr *attr,
5047 struct hns_roce_v2_qp_context *context,
5048 struct hns_roce_v2_qp_context *qpc_mask)
5049 {
5050 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
5051 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5052 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5053 struct ib_device *ibdev = &hr_dev->ib_dev;
5054 int ret;
5055
5056 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh),
5057 &hr_qp->tc_mode, &hr_qp->priority);
5058 if (ret && ret != -EOPNOTSUPP &&
5059 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
5060 ibdev_err_ratelimited(ibdev,
5061 "failed to get dscp, ret = %d.\n", ret);
5062 return ret;
5063 }
5064
5065 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP &&
5066 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
5067 hr_qp->sl = hr_qp->priority;
5068 else
5069 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
5070
5071 if (!check_sl_valid(hr_dev, hr_qp->sl))
5072 return -EINVAL;
5073
5074 hr_reg_write(context, QPC_SL, hr_qp->sl);
5075 hr_reg_clear(qpc_mask, QPC_SL);
5076
5077 return 0;
5078 }
5079
hns_roce_v2_set_path(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5080 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
5081 const struct ib_qp_attr *attr,
5082 int attr_mask,
5083 struct hns_roce_v2_qp_context *context,
5084 struct hns_roce_v2_qp_context *qpc_mask)
5085 {
5086 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
5087 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5088 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5089 struct ib_device *ibdev = &hr_dev->ib_dev;
5090 const struct ib_gid_attr *gid_attr = NULL;
5091 u8 sl = rdma_ah_get_sl(&attr->ah_attr);
5092 int is_roce_protocol;
5093 u16 vlan_id = 0xffff;
5094 bool is_udp = false;
5095 u8 ib_port;
5096 u8 hr_port;
5097 int ret;
5098
5099 /*
5100 * If free_mr_en of qp is set, it means that this qp comes from
5101 * free mr. This qp will perform the loopback operation.
5102 * In the loopback scenario, only sl needs to be set.
5103 */
5104 if (hr_qp->free_mr_en) {
5105 if (!check_sl_valid(hr_dev, sl))
5106 return -EINVAL;
5107 hr_reg_write(context, QPC_SL, sl);
5108 hr_reg_clear(qpc_mask, QPC_SL);
5109 hr_qp->sl = sl;
5110 return 0;
5111 }
5112
5113 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
5114 hr_port = ib_port - 1;
5115 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
5116 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
5117
5118 if (is_roce_protocol) {
5119 gid_attr = attr->ah_attr.grh.sgid_attr;
5120 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
5121 if (ret)
5122 return ret;
5123
5124 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
5125 }
5126
5127 /* Only HIP08 needs to set the vlan_en bits in QPC */
5128 if (vlan_id < VLAN_N_VID &&
5129 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5130 hr_reg_enable(context, QPC_RQ_VLAN_EN);
5131 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
5132 hr_reg_enable(context, QPC_SQ_VLAN_EN);
5133 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
5134 }
5135
5136 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
5137 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
5138
5139 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
5140 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
5141 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
5142 return -EINVAL;
5143 }
5144
5145 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
5146 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
5147 return -EINVAL;
5148 }
5149
5150 hr_reg_write(context, QPC_UDPSPN,
5151 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
5152 attr->dest_qp_num) :
5153 0);
5154
5155 hr_reg_clear(qpc_mask, QPC_UDPSPN);
5156
5157 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
5158
5159 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
5160
5161 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
5162 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
5163
5164 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
5165 if (ret)
5166 return ret;
5167
5168 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
5169 hr_reg_clear(qpc_mask, QPC_TC);
5170
5171 hr_reg_write(context, QPC_FL, grh->flow_label);
5172 hr_reg_clear(qpc_mask, QPC_FL);
5173 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
5174 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
5175
5176 return hns_roce_set_sl(ibqp, attr, context, qpc_mask);
5177 }
5178
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)5179 static bool check_qp_state(enum ib_qp_state cur_state,
5180 enum ib_qp_state new_state)
5181 {
5182 static const bool sm[][IB_QPS_ERR + 1] = {
5183 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
5184 [IB_QPS_INIT] = true },
5185 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
5186 [IB_QPS_INIT] = true,
5187 [IB_QPS_RTR] = true,
5188 [IB_QPS_ERR] = true },
5189 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
5190 [IB_QPS_RTS] = true,
5191 [IB_QPS_ERR] = true },
5192 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
5193 [IB_QPS_RTS] = true,
5194 [IB_QPS_ERR] = true },
5195 [IB_QPS_SQD] = {},
5196 [IB_QPS_SQE] = {},
5197 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
5198 [IB_QPS_ERR] = true }
5199 };
5200
5201 return sm[cur_state][new_state];
5202 }
5203
hns_roce_v2_set_abs_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)5204 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
5205 const struct ib_qp_attr *attr,
5206 int attr_mask,
5207 enum ib_qp_state cur_state,
5208 enum ib_qp_state new_state,
5209 struct hns_roce_v2_qp_context *context,
5210 struct hns_roce_v2_qp_context *qpc_mask,
5211 struct ib_udata *udata)
5212 {
5213 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5214 int ret = 0;
5215
5216 if (!check_qp_state(cur_state, new_state))
5217 return -EINVAL;
5218
5219 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
5220 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
5221 modify_qp_reset_to_init(ibqp, context);
5222 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
5223 modify_qp_init_to_init(ibqp, context, qpc_mask);
5224 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5225 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5226 qpc_mask, udata);
5227 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5228 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask);
5229 }
5230
5231 return ret;
5232 }
5233
check_qp_timeout_cfg_range(struct hns_roce_dev * hr_dev,u8 * timeout)5234 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5235 {
5236 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5237 #define QP_ACK_TIMEOUT_MAX 31
5238
5239 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5240 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5241 ibdev_warn(&hr_dev->ib_dev,
5242 "local ACK timeout shall be 0 to 20.\n");
5243 return false;
5244 }
5245 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5246 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5247 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5248 ibdev_warn(&hr_dev->ib_dev,
5249 "local ACK timeout shall be 0 to 31.\n");
5250 return false;
5251 }
5252 }
5253
5254 return true;
5255 }
5256
hns_roce_v2_set_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5257 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5258 const struct ib_qp_attr *attr,
5259 int attr_mask,
5260 struct hns_roce_v2_qp_context *context,
5261 struct hns_roce_v2_qp_context *qpc_mask)
5262 {
5263 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5264 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5265 int ret = 0;
5266 u8 timeout;
5267
5268 if (attr_mask & IB_QP_AV) {
5269 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5270 qpc_mask);
5271 if (ret)
5272 return ret;
5273 }
5274
5275 if (attr_mask & IB_QP_TIMEOUT) {
5276 timeout = attr->timeout;
5277 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5278 hr_reg_write(context, QPC_AT, timeout);
5279 hr_reg_clear(qpc_mask, QPC_AT);
5280 }
5281 }
5282
5283 if (attr_mask & IB_QP_RETRY_CNT) {
5284 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5285 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5286
5287 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5288 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5289 }
5290
5291 if (attr_mask & IB_QP_RNR_RETRY) {
5292 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5293 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5294
5295 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5296 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5297 }
5298
5299 if (attr_mask & IB_QP_SQ_PSN) {
5300 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5301 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5302
5303 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5304 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5305
5306 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5307 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5308
5309 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5310 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5311 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5312
5313 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5314 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5315
5316 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5317 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5318 }
5319
5320 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5321 attr->max_dest_rd_atomic) {
5322 hr_reg_write(context, QPC_RR_MAX,
5323 fls(attr->max_dest_rd_atomic - 1));
5324 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5325 }
5326
5327 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5328 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5329 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5330 }
5331
5332 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5333 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5334
5335 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5336 hr_reg_write(context, QPC_MIN_RNR_TIME,
5337 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5338 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5339 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5340 }
5341
5342 if (attr_mask & IB_QP_RQ_PSN) {
5343 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5344 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5345
5346 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5347 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5348 }
5349
5350 if (attr_mask & IB_QP_QKEY) {
5351 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5352 qpc_mask->qkey_xrcd = 0;
5353 hr_qp->qkey = attr->qkey;
5354 }
5355
5356 return ret;
5357 }
5358
hns_roce_v2_record_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask)5359 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5360 const struct ib_qp_attr *attr,
5361 int attr_mask)
5362 {
5363 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5364 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5365
5366 if (attr_mask & IB_QP_ACCESS_FLAGS)
5367 hr_qp->atomic_rd_en = attr->qp_access_flags;
5368
5369 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5370 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5371 if (attr_mask & IB_QP_PORT) {
5372 hr_qp->port = attr->port_num - 1;
5373 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5374 }
5375 }
5376
clear_qp(struct hns_roce_qp * hr_qp)5377 static void clear_qp(struct hns_roce_qp *hr_qp)
5378 {
5379 struct ib_qp *ibqp = &hr_qp->ibqp;
5380
5381 if (ibqp->send_cq)
5382 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5383 hr_qp->qpn, NULL);
5384
5385 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5386 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5387 hr_qp->qpn, ibqp->srq ?
5388 to_hr_srq(ibqp->srq) : NULL);
5389
5390 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5391 *hr_qp->rdb.db_record = 0;
5392
5393 hr_qp->rq.head = 0;
5394 hr_qp->rq.tail = 0;
5395 hr_qp->sq.head = 0;
5396 hr_qp->sq.tail = 0;
5397 hr_qp->next_sge = 0;
5398 }
5399
v2_set_flushed_fields(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5400 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5401 struct hns_roce_v2_qp_context *context,
5402 struct hns_roce_v2_qp_context *qpc_mask)
5403 {
5404 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5405 unsigned long sq_flag = 0;
5406 unsigned long rq_flag = 0;
5407
5408 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5409 return;
5410
5411 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5412 trace_hns_sq_flush_cqe(hr_qp->qpn, hr_qp->sq.head, TRACE_SQ);
5413 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5414 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5415 hr_qp->state = IB_QPS_ERR;
5416 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5417
5418 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5419 return;
5420
5421 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5422 trace_hns_rq_flush_cqe(hr_qp->qpn, hr_qp->rq.head, TRACE_RQ);
5423 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5424 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5425 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5426 }
5427
hns_roce_v2_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)5428 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5429 const struct ib_qp_attr *attr,
5430 int attr_mask, enum ib_qp_state cur_state,
5431 enum ib_qp_state new_state, struct ib_udata *udata)
5432 {
5433 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5434 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5435 struct hns_roce_v2_qp_context *context;
5436 struct hns_roce_v2_qp_context *qpc_mask;
5437 struct ib_device *ibdev = &hr_dev->ib_dev;
5438 int ret = -ENOMEM;
5439
5440 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5441 return -EOPNOTSUPP;
5442
5443 /*
5444 * In v2 engine, software pass context and context mask to hardware
5445 * when modifying qp. If software need modify some fields in context,
5446 * we should set all bits of the relevant fields in context mask to
5447 * 0 at the same time, else set them to 0x1.
5448 */
5449 context = kvzalloc(sizeof(*context), GFP_KERNEL);
5450 qpc_mask = kvzalloc(sizeof(*qpc_mask), GFP_KERNEL);
5451 if (!context || !qpc_mask)
5452 goto out;
5453
5454 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5455
5456 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5457 new_state, context, qpc_mask, udata);
5458 if (ret)
5459 goto out;
5460
5461 /* When QP state is err, SQ and RQ WQE should be flushed */
5462 if (new_state == IB_QPS_ERR)
5463 v2_set_flushed_fields(ibqp, context, qpc_mask);
5464
5465 /* Configure the optional fields */
5466 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5467 qpc_mask);
5468 if (ret)
5469 goto out;
5470
5471 hr_reg_write_bool(context, QPC_INV_CREDIT,
5472 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5473 ibqp->srq);
5474 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5475
5476 /* Every status migrate must change state */
5477 hr_reg_write(context, QPC_QP_ST, new_state);
5478 hr_reg_clear(qpc_mask, QPC_QP_ST);
5479
5480 /* SW pass context to HW */
5481 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5482 if (ret) {
5483 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret);
5484 goto out;
5485 }
5486
5487 hr_qp->state = new_state;
5488
5489 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5490
5491 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5492 clear_qp(hr_qp);
5493
5494 out:
5495 kvfree(qpc_mask);
5496 kvfree(context);
5497 return ret;
5498 }
5499
to_ib_qp_st(enum hns_roce_v2_qp_state state)5500 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5501 {
5502 static const enum ib_qp_state map[] = {
5503 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5504 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5505 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5506 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5507 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5508 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5509 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5510 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5511 };
5512
5513 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5514 }
5515
hns_roce_v2_query_qpc(struct hns_roce_dev * hr_dev,u32 qpn,void * buffer)5516 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5517 void *buffer)
5518 {
5519 struct hns_roce_cmd_mailbox *mailbox;
5520 int ret;
5521
5522 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5523 if (IS_ERR(mailbox))
5524 return PTR_ERR(mailbox);
5525
5526 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5527 qpn);
5528 if (ret)
5529 goto out;
5530
5531 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5532
5533 out:
5534 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5535 return ret;
5536 }
5537
hns_roce_v2_query_srqc(struct hns_roce_dev * hr_dev,u32 srqn,void * buffer)5538 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn,
5539 void *buffer)
5540 {
5541 struct hns_roce_srq_context *context;
5542 struct hns_roce_cmd_mailbox *mailbox;
5543 int ret;
5544
5545 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5546 if (IS_ERR(mailbox))
5547 return PTR_ERR(mailbox);
5548
5549 context = mailbox->buf;
5550 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC,
5551 srqn);
5552 if (ret)
5553 goto out;
5554
5555 memcpy(buffer, context, sizeof(*context));
5556
5557 out:
5558 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5559 return ret;
5560 }
5561
hns_roce_v2_query_sccc(struct hns_roce_dev * hr_dev,u32 sccn,void * buffer)5562 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 sccn,
5563 void *buffer)
5564 {
5565 struct hns_roce_v2_scc_context *context;
5566 struct hns_roce_cmd_mailbox *mailbox;
5567 int ret;
5568
5569 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5570 if (IS_ERR(mailbox))
5571 return PTR_ERR(mailbox);
5572
5573 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC,
5574 sccn);
5575 if (ret)
5576 goto out;
5577
5578 context = mailbox->buf;
5579 memcpy(buffer, context, sizeof(*context));
5580
5581 out:
5582 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5583 return ret;
5584 }
5585
get_qp_timeout_attr(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context)5586 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,
5587 struct hns_roce_v2_qp_context *context)
5588 {
5589 u8 timeout;
5590
5591 timeout = (u8)hr_reg_read(context, QPC_AT);
5592 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
5593 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5594
5595 return timeout;
5596 }
5597
hns_roce_v2_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)5598 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5599 int qp_attr_mask,
5600 struct ib_qp_init_attr *qp_init_attr)
5601 {
5602 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5603 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5604 struct hns_roce_v2_qp_context context = {};
5605 struct ib_device *ibdev = &hr_dev->ib_dev;
5606 int tmp_qp_state;
5607 int state;
5608 int ret;
5609
5610 memset(qp_attr, 0, sizeof(*qp_attr));
5611 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5612
5613 mutex_lock(&hr_qp->mutex);
5614
5615 if (hr_qp->state == IB_QPS_RESET) {
5616 qp_attr->qp_state = IB_QPS_RESET;
5617 ret = 0;
5618 goto done;
5619 }
5620
5621 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5622 if (ret) {
5623 ibdev_err_ratelimited(ibdev,
5624 "failed to query QPC, ret = %d.\n",
5625 ret);
5626 ret = -EINVAL;
5627 goto out;
5628 }
5629
5630 state = hr_reg_read(&context, QPC_QP_ST);
5631 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5632 if (tmp_qp_state == -1) {
5633 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n");
5634 ret = -EINVAL;
5635 goto out;
5636 }
5637 hr_qp->state = (u8)tmp_qp_state;
5638 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5639 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5640 qp_attr->path_mig_state = IB_MIG_ARMED;
5641 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5642 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5643 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5644
5645 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5646 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5647 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5648 qp_attr->qp_access_flags =
5649 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5650 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5651 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5652
5653 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5654 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5655 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5656 struct ib_global_route *grh =
5657 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5658
5659 rdma_ah_set_sl(&qp_attr->ah_attr,
5660 hr_reg_read(&context, QPC_SL));
5661 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5662 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5663 grh->flow_label = hr_reg_read(&context, QPC_FL);
5664 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5665 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5666 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5667
5668 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5669 }
5670
5671 qp_attr->port_num = hr_qp->port + 1;
5672 qp_attr->sq_draining = 0;
5673 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5674 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5675
5676 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5677 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);
5678 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5679 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5680
5681 done:
5682 qp_attr->cur_qp_state = qp_attr->qp_state;
5683 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5684 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5685 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5686
5687 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5688 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5689
5690 qp_init_attr->qp_context = ibqp->qp_context;
5691 qp_init_attr->qp_type = ibqp->qp_type;
5692 qp_init_attr->recv_cq = ibqp->recv_cq;
5693 qp_init_attr->send_cq = ibqp->send_cq;
5694 qp_init_attr->srq = ibqp->srq;
5695 qp_init_attr->cap = qp_attr->cap;
5696 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5697
5698 out:
5699 mutex_unlock(&hr_qp->mutex);
5700 return ret;
5701 }
5702
modify_qp_is_ok(struct hns_roce_qp * hr_qp)5703 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5704 {
5705 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5706 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5707 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5708 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5709 hr_qp->state != IB_QPS_RESET);
5710 }
5711
hns_roce_v2_destroy_qp_common(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct ib_udata * udata)5712 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5713 struct hns_roce_qp *hr_qp,
5714 struct ib_udata *udata)
5715 {
5716 struct ib_device *ibdev = &hr_dev->ib_dev;
5717 struct hns_roce_cq *send_cq, *recv_cq;
5718 unsigned long flags;
5719 int ret = 0;
5720
5721 if (modify_qp_is_ok(hr_qp)) {
5722 /* Modify qp to reset before destroying qp */
5723 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5724 hr_qp->state, IB_QPS_RESET, udata);
5725 if (ret)
5726 ibdev_err_ratelimited(ibdev,
5727 "failed to modify QP to RST, ret = %d.\n",
5728 ret);
5729 }
5730
5731 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5732 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5733
5734 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5735 hns_roce_lock_cqs(send_cq, recv_cq);
5736
5737 if (!udata) {
5738 if (recv_cq)
5739 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5740 (hr_qp->ibqp.srq ?
5741 to_hr_srq(hr_qp->ibqp.srq) :
5742 NULL));
5743
5744 if (send_cq && send_cq != recv_cq)
5745 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5746 }
5747
5748 hns_roce_qp_remove(hr_dev, hr_qp);
5749
5750 hns_roce_unlock_cqs(send_cq, recv_cq);
5751 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5752
5753 return ret;
5754 }
5755
put_dip_ctx_idx(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5756 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev,
5757 struct hns_roce_qp *hr_qp)
5758 {
5759 struct hns_roce_dip *hr_dip = hr_qp->dip;
5760
5761 if (!hr_dip)
5762 return;
5763
5764 xa_lock(&hr_dev->qp_table.dip_xa);
5765
5766 hr_dip->qp_cnt--;
5767 if (!hr_dip->qp_cnt)
5768 memset(hr_dip->dgid, 0, GID_LEN_V2);
5769
5770 xa_unlock(&hr_dev->qp_table.dip_xa);
5771 }
5772
hns_roce_v2_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)5773 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5774 {
5775 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5776 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5777 unsigned long flags;
5778 int ret;
5779
5780 /* Make sure flush_cqe() is completed */
5781 spin_lock_irqsave(&hr_qp->flush_lock, flags);
5782 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag);
5783 spin_unlock_irqrestore(&hr_qp->flush_lock, flags);
5784 flush_work(&hr_qp->flush_work.work);
5785
5786 if (hr_qp->cong_type == CONG_TYPE_DIP)
5787 put_dip_ctx_idx(hr_dev, hr_qp);
5788
5789 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5790 if (ret)
5791 ibdev_err_ratelimited(&hr_dev->ib_dev,
5792 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5793 hr_qp->qpn, ret);
5794
5795 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5796
5797 return 0;
5798 }
5799
hns_roce_v2_qp_flow_control_init(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5800 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5801 struct hns_roce_qp *hr_qp)
5802 {
5803 struct ib_device *ibdev = &hr_dev->ib_dev;
5804 struct hns_roce_sccc_clr_done *resp;
5805 struct hns_roce_sccc_clr *clr;
5806 struct hns_roce_cmq_desc desc;
5807 int ret, i;
5808
5809 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5810 return 0;
5811
5812 mutex_lock(&hr_dev->qp_table.scc_mutex);
5813
5814 /* set scc ctx clear done flag */
5815 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5816 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5817 if (ret) {
5818 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5819 goto out;
5820 }
5821
5822 /* clear scc context */
5823 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5824 clr = (struct hns_roce_sccc_clr *)desc.data;
5825 clr->qpn = cpu_to_le32(hr_qp->qpn);
5826 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5827 if (ret) {
5828 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5829 goto out;
5830 }
5831
5832 /* query scc context clear is done or not */
5833 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5834 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5835 hns_roce_cmq_setup_basic_desc(&desc,
5836 HNS_ROCE_OPC_QUERY_SCCC, true);
5837 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5838 if (ret) {
5839 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5840 ret);
5841 goto out;
5842 }
5843
5844 if (resp->clr_done)
5845 goto out;
5846
5847 msleep(20);
5848 }
5849
5850 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5851 ret = -ETIMEDOUT;
5852
5853 out:
5854 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5855 return ret;
5856 }
5857
5858 #define DMA_IDX_SHIFT 3
5859 #define DMA_WQE_SHIFT 3
5860
hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq * srq,struct hns_roce_srq_context * ctx)5861 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5862 struct hns_roce_srq_context *ctx)
5863 {
5864 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5865 struct ib_device *ibdev = srq->ibsrq.device;
5866 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5867 u64 mtts_idx[MTT_MIN_COUNT] = {};
5868 dma_addr_t dma_handle_idx;
5869 int ret;
5870
5871 /* Get physical address of idx que buf */
5872 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5873 ARRAY_SIZE(mtts_idx));
5874 if (ret) {
5875 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5876 ret);
5877 return ret;
5878 }
5879
5880 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr);
5881
5882 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5883 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5884
5885 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5886 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5887 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5888
5889 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5890 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5891 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5892 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5893
5894 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5895 to_hr_hw_page_addr(mtts_idx[0]));
5896 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5897 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5898
5899 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5900 to_hr_hw_page_addr(mtts_idx[1]));
5901 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5902 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5903
5904 return 0;
5905 }
5906
hns_roce_v2_write_srqc(struct hns_roce_srq * srq,void * mb_buf)5907 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5908 {
5909 struct ib_device *ibdev = srq->ibsrq.device;
5910 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5911 struct hns_roce_srq_context *ctx = mb_buf;
5912 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5913 dma_addr_t dma_handle_wqe;
5914 int ret;
5915
5916 memset(ctx, 0, sizeof(*ctx));
5917
5918 /* Get the physical address of srq buf */
5919 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5920 ARRAY_SIZE(mtts_wqe));
5921 if (ret) {
5922 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5923 ret);
5924 return ret;
5925 }
5926
5927 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr);
5928
5929 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5930 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5931 srq->ibsrq.srq_type == IB_SRQT_XRC);
5932 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5933 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5934 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5935 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5936 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5937 hr_reg_write(ctx, SRQC_RQWS,
5938 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5939
5940 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5941 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5942 srq->wqe_cnt));
5943
5944 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5945 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5946 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5947
5948 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5949 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5950 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5951 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5952
5953 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) {
5954 hr_reg_enable(ctx, SRQC_DB_RECORD_EN);
5955 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L,
5956 lower_32_bits(srq->rdb.dma) >> 1);
5957 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H,
5958 upper_32_bits(srq->rdb.dma));
5959 }
5960
5961 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5962 }
5963
hns_roce_v2_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)5964 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5965 struct ib_srq_attr *srq_attr,
5966 enum ib_srq_attr_mask srq_attr_mask,
5967 struct ib_udata *udata)
5968 {
5969 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5970 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5971 struct hns_roce_srq_context *srq_context;
5972 struct hns_roce_srq_context *srqc_mask;
5973 struct hns_roce_cmd_mailbox *mailbox;
5974 int ret = 0;
5975
5976 /* Resizing SRQs is not supported yet */
5977 if (srq_attr_mask & IB_SRQ_MAX_WR) {
5978 ret = -EOPNOTSUPP;
5979 goto out;
5980 }
5981
5982 if (srq_attr_mask & IB_SRQ_LIMIT) {
5983 if (srq_attr->srq_limit > srq->wqe_cnt) {
5984 ret = -EINVAL;
5985 goto out;
5986 }
5987
5988 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5989 if (IS_ERR(mailbox)) {
5990 ret = PTR_ERR(mailbox);
5991 goto out;
5992 }
5993
5994 srq_context = mailbox->buf;
5995 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5996
5997 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5998
5999 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
6000 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
6001
6002 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
6003 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
6004 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6005 if (ret)
6006 ibdev_err(&hr_dev->ib_dev,
6007 "failed to handle cmd of modifying SRQ, ret = %d.\n",
6008 ret);
6009 }
6010
6011 out:
6012 if (ret)
6013 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]);
6014
6015 return ret;
6016 }
6017
hns_roce_v2_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)6018 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
6019 {
6020 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
6021 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
6022 struct hns_roce_srq_context *srq_context;
6023 struct hns_roce_cmd_mailbox *mailbox;
6024 int ret;
6025
6026 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6027 if (IS_ERR(mailbox))
6028 return PTR_ERR(mailbox);
6029
6030 srq_context = mailbox->buf;
6031 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
6032 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
6033 if (ret) {
6034 ibdev_err(&hr_dev->ib_dev,
6035 "failed to process cmd of querying SRQ, ret = %d.\n",
6036 ret);
6037 goto out;
6038 }
6039
6040 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
6041 attr->max_wr = srq->wqe_cnt;
6042 attr->max_sge = srq->max_gs - srq->rsv_sge;
6043
6044 out:
6045 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6046 return ret;
6047 }
6048
hns_roce_v2_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)6049 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
6050 {
6051 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
6052 struct hns_roce_v2_cq_context *cq_context;
6053 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
6054 struct hns_roce_v2_cq_context *cqc_mask;
6055 struct hns_roce_cmd_mailbox *mailbox;
6056 int ret;
6057
6058 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6059 ret = PTR_ERR_OR_ZERO(mailbox);
6060 if (ret)
6061 goto err_out;
6062
6063 cq_context = mailbox->buf;
6064 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
6065
6066 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
6067
6068 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
6069 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
6070
6071 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6072 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6073 dev_info(hr_dev->dev,
6074 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
6075 cq_period);
6076 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;
6077 }
6078 cq_period *= HNS_ROCE_CLOCK_ADJUST;
6079 }
6080 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
6081 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
6082
6083 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
6084 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
6085 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6086 if (ret)
6087 ibdev_err_ratelimited(&hr_dev->ib_dev,
6088 "failed to process cmd when modifying CQ, ret = %d.\n",
6089 ret);
6090
6091 err_out:
6092 if (ret)
6093 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]);
6094
6095 return ret;
6096 }
6097
hns_roce_v2_query_cqc(struct hns_roce_dev * hr_dev,u32 cqn,void * buffer)6098 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
6099 void *buffer)
6100 {
6101 struct hns_roce_v2_cq_context *context;
6102 struct hns_roce_cmd_mailbox *mailbox;
6103 int ret;
6104
6105 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6106 if (IS_ERR(mailbox))
6107 return PTR_ERR(mailbox);
6108
6109 context = mailbox->buf;
6110 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
6111 HNS_ROCE_CMD_QUERY_CQC, cqn);
6112 if (ret) {
6113 ibdev_err_ratelimited(&hr_dev->ib_dev,
6114 "failed to process cmd when querying CQ, ret = %d.\n",
6115 ret);
6116 goto err_mailbox;
6117 }
6118
6119 memcpy(buffer, context, sizeof(*context));
6120
6121 err_mailbox:
6122 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6123
6124 return ret;
6125 }
6126
hns_roce_v2_query_mpt(struct hns_roce_dev * hr_dev,u32 key,void * buffer)6127 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
6128 void *buffer)
6129 {
6130 struct hns_roce_v2_mpt_entry *context;
6131 struct hns_roce_cmd_mailbox *mailbox;
6132 int ret;
6133
6134 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6135 if (IS_ERR(mailbox))
6136 return PTR_ERR(mailbox);
6137
6138 context = mailbox->buf;
6139 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
6140 key_to_hw_index(key));
6141 if (ret) {
6142 ibdev_err(&hr_dev->ib_dev,
6143 "failed to process cmd when querying MPT, ret = %d.\n",
6144 ret);
6145 goto err_mailbox;
6146 }
6147
6148 memcpy(buffer, context, sizeof(*context));
6149
6150 err_mailbox:
6151 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6152
6153 return ret;
6154 }
6155
dump_aeqe_log(struct hns_roce_work * irq_work)6156 static void dump_aeqe_log(struct hns_roce_work *irq_work)
6157 {
6158 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
6159 struct ib_device *ibdev = &hr_dev->ib_dev;
6160
6161 switch (irq_work->event_type) {
6162 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
6163 ibdev_info(ibdev, "path migrated succeeded.\n");
6164 break;
6165 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
6166 ibdev_warn(ibdev, "path migration failed.\n");
6167 break;
6168 case HNS_ROCE_EVENT_TYPE_COMM_EST:
6169 break;
6170 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
6171 ibdev_dbg(ibdev, "send queue drained.\n");
6172 break;
6173 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6174 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
6175 irq_work->queue_num, irq_work->sub_type);
6176 break;
6177 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6178 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
6179 irq_work->queue_num);
6180 break;
6181 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6182 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
6183 irq_work->queue_num, irq_work->sub_type);
6184 break;
6185 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
6186 ibdev_dbg(ibdev, "SRQ limit reach.\n");
6187 break;
6188 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
6189 ibdev_dbg(ibdev, "SRQ last wqe reach.\n");
6190 break;
6191 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
6192 ibdev_err(ibdev, "SRQ catas error.\n");
6193 break;
6194 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
6195 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
6196 break;
6197 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
6198 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
6199 break;
6200 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
6201 ibdev_warn(ibdev, "DB overflow.\n");
6202 break;
6203 case HNS_ROCE_EVENT_TYPE_MB:
6204 break;
6205 case HNS_ROCE_EVENT_TYPE_FLR:
6206 ibdev_warn(ibdev, "function level reset.\n");
6207 break;
6208 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6209 ibdev_err(ibdev, "xrc domain violation error.\n");
6210 break;
6211 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6212 ibdev_err(ibdev, "invalid xrceth error.\n");
6213 break;
6214 default:
6215 ibdev_info(ibdev, "Undefined event %d.\n",
6216 irq_work->event_type);
6217 break;
6218 }
6219 }
6220
hns_roce_irq_work_handle(struct work_struct * work)6221 static void hns_roce_irq_work_handle(struct work_struct *work)
6222 {
6223 struct hns_roce_work *irq_work =
6224 container_of(work, struct hns_roce_work, work);
6225 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
6226 int event_type = irq_work->event_type;
6227 u32 queue_num = irq_work->queue_num;
6228
6229 switch (event_type) {
6230 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
6231 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
6232 case HNS_ROCE_EVENT_TYPE_COMM_EST:
6233 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
6234 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6235 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
6236 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6237 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6238 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6239 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6240 hns_roce_qp_event(hr_dev, queue_num, event_type);
6241 break;
6242 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
6243 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
6244 hns_roce_srq_event(hr_dev, queue_num, event_type);
6245 break;
6246 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
6247 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
6248 hns_roce_cq_event(hr_dev, queue_num, event_type);
6249 break;
6250 default:
6251 break;
6252 }
6253
6254 dump_aeqe_log(irq_work);
6255
6256 kfree(irq_work);
6257 }
6258
hns_roce_v2_init_irq_work(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u32 queue_num)6259 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
6260 struct hns_roce_eq *eq, u32 queue_num)
6261 {
6262 struct hns_roce_work *irq_work;
6263
6264 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
6265 if (!irq_work)
6266 return;
6267
6268 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
6269 irq_work->hr_dev = hr_dev;
6270 irq_work->event_type = eq->event_type;
6271 irq_work->sub_type = eq->sub_type;
6272 irq_work->queue_num = queue_num;
6273 queue_work(hr_dev->irq_workq, &irq_work->work);
6274 }
6275
update_eq_db(struct hns_roce_eq * eq)6276 static void update_eq_db(struct hns_roce_eq *eq)
6277 {
6278 struct hns_roce_dev *hr_dev = eq->hr_dev;
6279 struct hns_roce_v2_db eq_db = {};
6280
6281 if (eq->type_flag == HNS_ROCE_AEQ) {
6282 hr_reg_write(&eq_db, EQ_DB_CMD,
6283 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
6284 HNS_ROCE_EQ_DB_CMD_AEQ :
6285 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
6286 } else {
6287 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
6288
6289 hr_reg_write(&eq_db, EQ_DB_CMD,
6290 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
6291 HNS_ROCE_EQ_DB_CMD_CEQ :
6292 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
6293 }
6294
6295 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
6296
6297 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
6298 }
6299
next_aeqe_sw_v2(struct hns_roce_eq * eq)6300 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
6301 {
6302 struct hns_roce_aeqe *aeqe;
6303
6304 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
6305 (eq->cons_index & (eq->entries - 1)) *
6306 eq->eqe_size);
6307
6308 return (hr_reg_read(aeqe, AEQE_OWNER) ^
6309 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
6310 }
6311
hns_roce_v2_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6312 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
6313 struct hns_roce_eq *eq)
6314 {
6315 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
6316 irqreturn_t aeqe_found = IRQ_NONE;
6317 int num_aeqes = 0;
6318 int event_type;
6319 u32 queue_num;
6320 int sub_type;
6321
6322 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) {
6323 /* Make sure we read AEQ entry after we have checked the
6324 * ownership bit
6325 */
6326 dma_rmb();
6327
6328 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
6329 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
6330 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
6331
6332 switch (event_type) {
6333 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6334 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6335 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6336 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6337 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6338 hns_roce_flush_cqe(hr_dev, queue_num);
6339 break;
6340 case HNS_ROCE_EVENT_TYPE_MB:
6341 hns_roce_cmd_event(hr_dev,
6342 le16_to_cpu(aeqe->event.cmd.token),
6343 aeqe->event.cmd.status,
6344 le64_to_cpu(aeqe->event.cmd.out_param));
6345 break;
6346 default:
6347 break;
6348 }
6349
6350 eq->event_type = event_type;
6351 eq->sub_type = sub_type;
6352 ++eq->cons_index;
6353 aeqe_found = IRQ_HANDLED;
6354 trace_hns_ae_info(event_type, aeqe, eq->eqe_size);
6355
6356 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]);
6357
6358 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6359
6360 aeqe = next_aeqe_sw_v2(eq);
6361 ++num_aeqes;
6362 }
6363
6364 update_eq_db(eq);
6365
6366 return IRQ_RETVAL(aeqe_found);
6367 }
6368
next_ceqe_sw_v2(struct hns_roce_eq * eq)6369 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6370 {
6371 struct hns_roce_ceqe *ceqe;
6372
6373 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6374 (eq->cons_index & (eq->entries - 1)) *
6375 eq->eqe_size);
6376
6377 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6378 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6379 }
6380
hns_roce_v2_ceq_int(struct hns_roce_eq * eq)6381 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq)
6382 {
6383 queue_work(system_bh_wq, &eq->work);
6384
6385 return IRQ_HANDLED;
6386 }
6387
hns_roce_v2_msix_interrupt_eq(int irq,void * eq_ptr)6388 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6389 {
6390 struct hns_roce_eq *eq = eq_ptr;
6391 struct hns_roce_dev *hr_dev = eq->hr_dev;
6392 irqreturn_t int_work;
6393
6394 if (eq->type_flag == HNS_ROCE_CEQ)
6395 /* Completion event interrupt */
6396 int_work = hns_roce_v2_ceq_int(eq);
6397 else
6398 /* Asynchronous event interrupt */
6399 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6400
6401 return IRQ_RETVAL(int_work);
6402 }
6403
abnormal_interrupt_basic(struct hns_roce_dev * hr_dev,u32 int_st)6404 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6405 u32 int_st)
6406 {
6407 struct pci_dev *pdev = hr_dev->pci_dev;
6408 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6409 const struct hnae3_ae_ops *ops = ae_dev->ops;
6410 enum hnae3_reset_type reset_type;
6411 irqreturn_t int_work = IRQ_NONE;
6412 u32 int_en;
6413
6414 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6415
6416 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6417 dev_err(hr_dev->dev, "AEQ overflow!\n");
6418
6419 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6420 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6421
6422 reset_type = hr_dev->is_vf ?
6423 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET;
6424
6425 /* Set reset level for reset_event() */
6426 if (ops->set_default_reset_request)
6427 ops->set_default_reset_request(ae_dev, reset_type);
6428 if (ops->reset_event)
6429 ops->reset_event(pdev, NULL);
6430
6431 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6432 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6433
6434 int_work = IRQ_HANDLED;
6435 } else {
6436 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6437 }
6438
6439 return IRQ_RETVAL(int_work);
6440 }
6441
fmea_ram_ecc_query(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6442 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6443 struct fmea_ram_ecc *ecc_info)
6444 {
6445 struct hns_roce_cmq_desc desc;
6446 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6447 int ret;
6448
6449 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6450 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6451 if (ret)
6452 return ret;
6453
6454 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6455 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6456 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6457
6458 return 0;
6459 }
6460
fmea_recover_gmv(struct hns_roce_dev * hr_dev,u32 idx)6461 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6462 {
6463 struct hns_roce_cmq_desc desc;
6464 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6465 u32 addr_upper;
6466 u32 addr_low;
6467 int ret;
6468
6469 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6470 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6471
6472 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6473 if (ret) {
6474 dev_err(hr_dev->dev,
6475 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6476 return ret;
6477 }
6478
6479 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6480 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6481
6482 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6483 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6484 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6485 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6486
6487 return hns_roce_cmq_send(hr_dev, &desc, 1);
6488 }
6489
fmea_get_ram_res_addr(u32 res_type,__le64 * data)6490 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6491 {
6492 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6493 res_type == ECC_RESOURCE_CQC_TIMER ||
6494 res_type == ECC_RESOURCE_SCCC)
6495 return le64_to_cpu(*data);
6496
6497 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT;
6498 }
6499
fmea_recover_others(struct hns_roce_dev * hr_dev,u32 res_type,u32 index)6500 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6501 u32 index)
6502 {
6503 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6504 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6505 struct hns_roce_cmd_mailbox *mailbox;
6506 u64 addr;
6507 int ret;
6508
6509 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6510 if (IS_ERR(mailbox))
6511 return PTR_ERR(mailbox);
6512
6513 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6514 if (ret) {
6515 dev_err(hr_dev->dev,
6516 "failed to execute cmd to read fmea ram, ret = %d.\n",
6517 ret);
6518 goto out;
6519 }
6520
6521 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6522
6523 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6524 if (ret)
6525 dev_err(hr_dev->dev,
6526 "failed to execute cmd to write fmea ram, ret = %d.\n",
6527 ret);
6528
6529 out:
6530 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6531 return ret;
6532 }
6533
fmea_ram_ecc_recover(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6534 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6535 struct fmea_ram_ecc *ecc_info)
6536 {
6537 u32 res_type = ecc_info->res_type;
6538 u32 index = ecc_info->index;
6539 int ret;
6540
6541 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6542
6543 if (res_type >= ECC_RESOURCE_COUNT) {
6544 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6545 res_type);
6546 return;
6547 }
6548
6549 if (res_type == ECC_RESOURCE_GMV)
6550 ret = fmea_recover_gmv(hr_dev, index);
6551 else
6552 ret = fmea_recover_others(hr_dev, res_type, index);
6553 if (ret)
6554 dev_err(hr_dev->dev,
6555 "failed to recover %s, index = %u, ret = %d.\n",
6556 fmea_ram_res[res_type].name, index, ret);
6557 }
6558
fmea_ram_ecc_work(struct work_struct * ecc_work)6559 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6560 {
6561 struct hns_roce_dev *hr_dev =
6562 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6563 struct fmea_ram_ecc ecc_info = {};
6564
6565 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6566 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6567 return;
6568 }
6569
6570 if (!ecc_info.is_ecc_err) {
6571 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6572 return;
6573 }
6574
6575 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6576 }
6577
hns_roce_v2_msix_interrupt_abn(int irq,void * dev_id)6578 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6579 {
6580 struct hns_roce_dev *hr_dev = dev_id;
6581 irqreturn_t int_work = IRQ_NONE;
6582 u32 int_st;
6583
6584 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6585
6586 if (int_st) {
6587 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6588 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6589 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6590 int_work = IRQ_HANDLED;
6591 } else {
6592 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6593 }
6594
6595 return IRQ_RETVAL(int_work);
6596 }
6597
hns_roce_v2_int_mask_enable(struct hns_roce_dev * hr_dev,int eq_num,u32 enable_flag)6598 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6599 int eq_num, u32 enable_flag)
6600 {
6601 int i;
6602
6603 for (i = 0; i < eq_num; i++)
6604 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6605 i * EQ_REG_OFFSET, enable_flag);
6606
6607 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6608 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6609 }
6610
free_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6611 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6612 {
6613 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6614 }
6615
hns_roce_v2_destroy_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6616 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,
6617 struct hns_roce_eq *eq)
6618 {
6619 struct device *dev = hr_dev->dev;
6620 int eqn = eq->eqn;
6621 int ret;
6622 u8 cmd;
6623
6624 if (eqn < hr_dev->caps.num_comp_vectors)
6625 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6626 else
6627 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6628
6629 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6630 if (ret)
6631 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
6632
6633 free_eq_buf(hr_dev, eq);
6634 }
6635
init_eq_config(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6636 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6637 {
6638 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6639 eq->cons_index = 0;
6640 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6641 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6642 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6643 eq->shift = ilog2((unsigned int)eq->entries);
6644 }
6645
config_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,void * mb_buf)6646 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6647 void *mb_buf)
6648 {
6649 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6650 struct hns_roce_eq_context *eqc;
6651 u64 bt_ba = 0;
6652 int ret;
6653
6654 eqc = mb_buf;
6655 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6656
6657 init_eq_config(hr_dev, eq);
6658
6659 /* if not multi-hop, eqe buffer only use one trunk */
6660 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba,
6661 ARRAY_SIZE(eqe_ba));
6662 if (ret) {
6663 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret);
6664 return ret;
6665 }
6666
6667 bt_ba = hns_roce_get_mtr_ba(&eq->mtr);
6668
6669 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6670 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6671 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6672 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6673 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6674 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6675 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6676 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6677 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6678 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6679 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6680 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6681 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6682
6683 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6684 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6685 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6686 eq->eq_period);
6687 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6688 }
6689 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6690 }
6691
6692 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6693 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6694 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6695 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6696 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6697 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6698 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6699 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6700 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6701 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6702 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6703 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6704 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6705
6706 return 0;
6707 }
6708
alloc_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6709 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6710 {
6711 struct hns_roce_buf_attr buf_attr = {};
6712 int err;
6713
6714 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6715 eq->hop_num = 0;
6716 else
6717 eq->hop_num = hr_dev->caps.eqe_hop_num;
6718
6719 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6720 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6721 buf_attr.region[0].hopnum = eq->hop_num;
6722 buf_attr.region_count = 1;
6723
6724 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6725 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6726 0);
6727 if (err)
6728 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6729
6730 return err;
6731 }
6732
hns_roce_v2_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u8 eq_cmd)6733 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6734 struct hns_roce_eq *eq, u8 eq_cmd)
6735 {
6736 struct hns_roce_cmd_mailbox *mailbox;
6737 int ret;
6738
6739 /* Allocate mailbox memory */
6740 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6741 if (IS_ERR(mailbox))
6742 return PTR_ERR(mailbox);
6743
6744 ret = alloc_eq_buf(hr_dev, eq);
6745 if (ret)
6746 goto free_cmd_mbox;
6747
6748 ret = config_eqc(hr_dev, eq, mailbox->buf);
6749 if (ret)
6750 goto err_cmd_mbox;
6751
6752 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6753 if (ret) {
6754 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6755 goto err_cmd_mbox;
6756 }
6757
6758 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6759
6760 return 0;
6761
6762 err_cmd_mbox:
6763 free_eq_buf(hr_dev, eq);
6764
6765 free_cmd_mbox:
6766 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6767
6768 return ret;
6769 }
6770
hns_roce_ceq_work(struct work_struct * work)6771 static void hns_roce_ceq_work(struct work_struct *work)
6772 {
6773 struct hns_roce_eq *eq = from_work(eq, work, work);
6774 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6775 struct hns_roce_dev *hr_dev = eq->hr_dev;
6776 int ceqe_num = 0;
6777 u32 cqn;
6778
6779 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) {
6780 /* Make sure we read CEQ entry after we have checked the
6781 * ownership bit
6782 */
6783 dma_rmb();
6784
6785 cqn = hr_reg_read(ceqe, CEQE_CQN);
6786
6787 hns_roce_cq_completion(hr_dev, cqn);
6788
6789 ++eq->cons_index;
6790 ++ceqe_num;
6791 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]);
6792
6793 ceqe = next_ceqe_sw_v2(eq);
6794 }
6795
6796 update_eq_db(eq);
6797 }
6798
__hns_roce_request_irq(struct hns_roce_dev * hr_dev,int irq_num,int comp_num,int aeq_num,int other_num)6799 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6800 int comp_num, int aeq_num, int other_num)
6801 {
6802 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6803 int i, j;
6804 int ret;
6805
6806 for (i = 0; i < irq_num; i++) {
6807 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6808 GFP_KERNEL);
6809 if (!hr_dev->irq_names[i]) {
6810 ret = -ENOMEM;
6811 goto err_kzalloc_failed;
6812 }
6813 }
6814
6815 /* irq contains: abnormal + AEQ + CEQ */
6816 for (j = 0; j < other_num; j++)
6817 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6818 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j);
6819
6820 for (j = other_num; j < (other_num + aeq_num); j++)
6821 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6822 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num);
6823
6824 for (j = (other_num + aeq_num); j < irq_num; j++)
6825 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6826 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev),
6827 j - other_num - aeq_num);
6828
6829 for (j = 0; j < irq_num; j++) {
6830 if (j < other_num) {
6831 ret = request_irq(hr_dev->irq[j],
6832 hns_roce_v2_msix_interrupt_abn,
6833 0, hr_dev->irq_names[j], hr_dev);
6834 } else if (j < (other_num + comp_num)) {
6835 INIT_WORK(&eq_table->eq[j - other_num].work,
6836 hns_roce_ceq_work);
6837 ret = request_irq(eq_table->eq[j - other_num].irq,
6838 hns_roce_v2_msix_interrupt_eq,
6839 0, hr_dev->irq_names[j + aeq_num],
6840 &eq_table->eq[j - other_num]);
6841 } else {
6842 ret = request_irq(eq_table->eq[j - other_num].irq,
6843 hns_roce_v2_msix_interrupt_eq,
6844 0, hr_dev->irq_names[j - comp_num],
6845 &eq_table->eq[j - other_num]);
6846 }
6847
6848 if (ret) {
6849 dev_err(hr_dev->dev, "request irq error!\n");
6850 goto err_request_failed;
6851 }
6852 }
6853
6854 return 0;
6855
6856 err_request_failed:
6857 for (j -= 1; j >= 0; j--) {
6858 if (j < other_num) {
6859 free_irq(hr_dev->irq[j], hr_dev);
6860 continue;
6861 }
6862 free_irq(eq_table->eq[j - other_num].irq,
6863 &eq_table->eq[j - other_num]);
6864 if (j < other_num + comp_num)
6865 cancel_work_sync(&eq_table->eq[j - other_num].work);
6866 }
6867
6868 err_kzalloc_failed:
6869 for (i -= 1; i >= 0; i--)
6870 kfree(hr_dev->irq_names[i]);
6871
6872 return ret;
6873 }
6874
__hns_roce_free_irq(struct hns_roce_dev * hr_dev)6875 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6876 {
6877 int irq_num;
6878 int eq_num;
6879 int i;
6880
6881 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6882 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6883
6884 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6885 free_irq(hr_dev->irq[i], hr_dev);
6886
6887 for (i = 0; i < eq_num; i++) {
6888 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6889 if (i < hr_dev->caps.num_comp_vectors)
6890 cancel_work_sync(&hr_dev->eq_table.eq[i].work);
6891 }
6892
6893 for (i = 0; i < irq_num; i++)
6894 kfree(hr_dev->irq_names[i]);
6895 }
6896
hns_roce_v2_init_eq_table(struct hns_roce_dev * hr_dev)6897 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6898 {
6899 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6900 struct device *dev = hr_dev->dev;
6901 struct hns_roce_eq *eq;
6902 int other_num;
6903 int comp_num;
6904 int aeq_num;
6905 int irq_num;
6906 int eq_num;
6907 u8 eq_cmd;
6908 int ret;
6909 int i;
6910
6911 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET)
6912 return -EINVAL;
6913
6914 other_num = hr_dev->caps.num_other_vectors;
6915 comp_num = hr_dev->caps.num_comp_vectors;
6916 aeq_num = hr_dev->caps.num_aeq_vectors;
6917
6918 eq_num = comp_num + aeq_num;
6919 irq_num = eq_num + other_num;
6920
6921 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6922 if (!eq_table->eq)
6923 return -ENOMEM;
6924
6925 /* create eq */
6926 for (i = 0; i < eq_num; i++) {
6927 eq = &eq_table->eq[i];
6928 eq->hr_dev = hr_dev;
6929 eq->eqn = i;
6930 if (i < comp_num) {
6931 /* CEQ */
6932 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6933 eq->type_flag = HNS_ROCE_CEQ;
6934 eq->entries = hr_dev->caps.ceqe_depth;
6935 eq->eqe_size = hr_dev->caps.ceqe_size;
6936 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6937 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6938 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6939 } else {
6940 /* AEQ */
6941 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6942 eq->type_flag = HNS_ROCE_AEQ;
6943 eq->entries = hr_dev->caps.aeqe_depth;
6944 eq->eqe_size = hr_dev->caps.aeqe_size;
6945 eq->irq = hr_dev->irq[i - comp_num + other_num];
6946 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6947 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6948 }
6949
6950 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6951 if (ret) {
6952 dev_err(dev, "failed to create eq.\n");
6953 goto err_create_eq_fail;
6954 }
6955 }
6956
6957 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6958
6959 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6960 if (!hr_dev->irq_workq) {
6961 dev_err(dev, "failed to create irq workqueue.\n");
6962 ret = -ENOMEM;
6963 goto err_create_eq_fail;
6964 }
6965
6966 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6967 other_num);
6968 if (ret) {
6969 dev_err(dev, "failed to request irq.\n");
6970 goto err_request_irq_fail;
6971 }
6972
6973 /* enable irq */
6974 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6975
6976 return 0;
6977
6978 err_request_irq_fail:
6979 destroy_workqueue(hr_dev->irq_workq);
6980
6981 err_create_eq_fail:
6982 for (i -= 1; i >= 0; i--)
6983 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6984 kfree(eq_table->eq);
6985
6986 return ret;
6987 }
6988
hns_roce_v2_cleanup_eq_table(struct hns_roce_dev * hr_dev)6989 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6990 {
6991 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6992 int eq_num;
6993 int i;
6994
6995 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6996
6997 /* Disable irq */
6998 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6999
7000 __hns_roce_free_irq(hr_dev);
7001 destroy_workqueue(hr_dev->irq_workq);
7002
7003 for (i = 0; i < eq_num; i++)
7004 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
7005
7006 kfree(eq_table->eq);
7007 }
7008
7009 static const struct ib_device_ops hns_roce_v2_dev_ops = {
7010 .destroy_qp = hns_roce_v2_destroy_qp,
7011 .modify_cq = hns_roce_v2_modify_cq,
7012 .poll_cq = hns_roce_v2_poll_cq,
7013 .post_recv = hns_roce_v2_post_recv,
7014 .post_send = hns_roce_v2_post_send,
7015 .query_qp = hns_roce_v2_query_qp,
7016 .req_notify_cq = hns_roce_v2_req_notify_cq,
7017 };
7018
7019 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
7020 .modify_srq = hns_roce_v2_modify_srq,
7021 .post_srq_recv = hns_roce_v2_post_srq_recv,
7022 .query_srq = hns_roce_v2_query_srq,
7023 };
7024
7025 static const struct hns_roce_hw hns_roce_hw_v2 = {
7026 .cmq_init = hns_roce_v2_cmq_init,
7027 .cmq_exit = hns_roce_v2_cmq_exit,
7028 .hw_profile = hns_roce_v2_profile,
7029 .hw_init = hns_roce_v2_init,
7030 .hw_exit = hns_roce_v2_exit,
7031 .post_mbox = v2_post_mbox,
7032 .poll_mbox_done = v2_poll_mbox_done,
7033 .chk_mbox_avail = v2_chk_mbox_is_avail,
7034 .set_gid = hns_roce_v2_set_gid,
7035 .set_mac = hns_roce_v2_set_mac,
7036 .write_mtpt = hns_roce_v2_write_mtpt,
7037 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
7038 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
7039 .write_cqc = hns_roce_v2_write_cqc,
7040 .set_hem = hns_roce_v2_set_hem,
7041 .clear_hem = hns_roce_v2_clear_hem,
7042 .modify_qp = hns_roce_v2_modify_qp,
7043 .dereg_mr = hns_roce_v2_dereg_mr,
7044 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
7045 .init_eq = hns_roce_v2_init_eq_table,
7046 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
7047 .write_srqc = hns_roce_v2_write_srqc,
7048 .query_cqc = hns_roce_v2_query_cqc,
7049 .query_qpc = hns_roce_v2_query_qpc,
7050 .query_mpt = hns_roce_v2_query_mpt,
7051 .query_srqc = hns_roce_v2_query_srqc,
7052 .query_sccc = hns_roce_v2_query_sccc,
7053 .query_hw_counter = hns_roce_hw_v2_query_counter,
7054 .get_dscp = hns_roce_hw_v2_get_dscp,
7055 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
7056 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
7057 };
7058
7059 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
7060 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
7061 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
7062 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
7063 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
7064 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
7065 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
7066 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
7067 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
7068 /* required last entry */
7069 {0, }
7070 };
7071
7072 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
7073
hns_roce_hw_v2_get_cfg(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)7074 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
7075 struct hnae3_handle *handle)
7076 {
7077 struct hns_roce_v2_priv *priv = hr_dev->priv;
7078 const struct pci_device_id *id;
7079 int i;
7080
7081 hr_dev->pci_dev = handle->pdev;
7082 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
7083 hr_dev->is_vf = id->driver_data;
7084 hr_dev->dev = &handle->pdev->dev;
7085 hr_dev->hw = &hns_roce_hw_v2;
7086 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
7087 hr_dev->odb_offset = hr_dev->sdb_offset;
7088
7089 /* Get info from NIC driver. */
7090 hr_dev->reg_base = handle->rinfo.roce_io_base;
7091 hr_dev->mem_base = handle->rinfo.roce_mem_base;
7092 hr_dev->caps.num_ports = 1;
7093 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
7094 hr_dev->iboe.phy_port[0] = 0;
7095
7096 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
7097 hr_dev->iboe.netdevs[0]->dev_addr);
7098
7099 for (i = 0; i < handle->rinfo.num_vectors; i++)
7100 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
7101 i + handle->rinfo.base_vector);
7102
7103 /* cmd issue mode: 0 is poll, 1 is event */
7104 hr_dev->cmd_mod = 1;
7105 hr_dev->loop_idc = 0;
7106
7107 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
7108 priv->handle = handle;
7109 }
7110
__hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)7111 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
7112 {
7113 struct hns_roce_dev *hr_dev;
7114 int ret;
7115
7116 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
7117 if (!hr_dev)
7118 return -ENOMEM;
7119
7120 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
7121 if (!hr_dev->priv) {
7122 ret = -ENOMEM;
7123 goto error_failed_kzalloc;
7124 }
7125
7126 hns_roce_hw_v2_get_cfg(hr_dev, handle);
7127
7128 ret = hns_roce_init(hr_dev);
7129 if (ret) {
7130 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
7131 goto error_failed_roce_init;
7132 }
7133
7134 handle->priv = hr_dev;
7135
7136 return 0;
7137
7138 error_failed_roce_init:
7139 kfree(hr_dev->priv);
7140
7141 error_failed_kzalloc:
7142 ib_dealloc_device(&hr_dev->ib_dev);
7143
7144 return ret;
7145 }
7146
__hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset,bool bond_cleanup)7147 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
7148 bool reset, bool bond_cleanup)
7149 {
7150 struct hns_roce_dev *hr_dev = handle->priv;
7151
7152 if (!hr_dev)
7153 return;
7154
7155 handle->priv = NULL;
7156
7157 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
7158 hns_roce_handle_device_err(hr_dev);
7159
7160 hns_roce_exit(hr_dev, bond_cleanup);
7161 kfree(hr_dev->priv);
7162 ib_dealloc_device(&hr_dev->ib_dev);
7163 }
7164
hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)7165 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
7166 {
7167 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
7168 const struct pci_device_id *id;
7169 struct device *dev = &handle->pdev->dev;
7170 int ret;
7171
7172 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
7173
7174 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
7175 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7176 goto reset_chk_err;
7177 }
7178
7179 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
7180 if (!id)
7181 return 0;
7182
7183 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
7184 return 0;
7185
7186 ret = __hns_roce_hw_v2_init_instance(handle);
7187 if (ret) {
7188 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7189 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
7190 if (ops->ae_dev_resetting(handle) ||
7191 ops->get_hw_reset_stat(handle))
7192 goto reset_chk_err;
7193 else
7194 return ret;
7195 }
7196
7197 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
7198
7199 return 0;
7200
7201 reset_chk_err:
7202 dev_err(dev, "Device is busy in resetting state.\n"
7203 "please retry later.\n");
7204
7205 return -EBUSY;
7206 }
7207
hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)7208 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
7209 bool reset)
7210 {
7211 /* Suspend bond to avoid concurrency */
7212 hns_roce_bond_suspend(handle);
7213
7214 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
7215 goto out;
7216
7217 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
7218
7219 __hns_roce_hw_v2_uninit_instance(handle, reset, true);
7220
7221 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7222
7223 out:
7224 hns_roce_bond_resume(handle);
7225 }
7226
7227 struct hns_roce_dev
hns_roce_bond_init_client(struct hns_roce_bond_group * bond_grp,int func_idx)7228 *hns_roce_bond_init_client(struct hns_roce_bond_group *bond_grp,
7229 int func_idx)
7230 {
7231 struct hnae3_handle *handle;
7232 int ret;
7233
7234 handle = bond_grp->bond_func_info[func_idx].handle;
7235 if (!handle || !handle->client)
7236 return NULL;
7237
7238 ret = hns_roce_hw_v2_init_instance(handle);
7239 if (ret)
7240 return NULL;
7241
7242 return handle->priv;
7243 }
7244
hns_roce_bond_uninit_client(struct hns_roce_bond_group * bond_grp,int func_idx)7245 void hns_roce_bond_uninit_client(struct hns_roce_bond_group *bond_grp,
7246 int func_idx)
7247 {
7248 struct hnae3_handle *handle = bond_grp->bond_func_info[func_idx].handle;
7249
7250 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
7251 return;
7252
7253 handle->rinfo.instance_state = HNS_ROCE_STATE_BOND_UNINIT;
7254
7255 __hns_roce_hw_v2_uninit_instance(handle, false, false);
7256
7257 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7258 }
7259
hns_roce_hw_v2_reset_notify_down(struct hnae3_handle * handle)7260 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
7261 {
7262 struct hns_roce_dev *hr_dev;
7263
7264 /* Suspend bond to avoid concurrency */
7265 hns_roce_bond_suspend(handle);
7266
7267 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
7268 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
7269 return 0;
7270 }
7271
7272 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
7273 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
7274
7275 hr_dev = handle->priv;
7276 if (!hr_dev)
7277 return 0;
7278
7279 hr_dev->active = false;
7280 hr_dev->dis_db = true;
7281
7282 rdma_user_mmap_disassociate(&hr_dev->ib_dev);
7283
7284 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
7285
7286 return 0;
7287 }
7288
hns_roce_hw_v2_reset_notify_init(struct hnae3_handle * handle)7289 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
7290 {
7291 struct device *dev = &handle->pdev->dev;
7292 int ret;
7293
7294 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
7295 &handle->rinfo.state)) {
7296 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
7297 hns_roce_bond_resume(handle);
7298 return 0;
7299 }
7300
7301 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
7302
7303 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
7304 ret = __hns_roce_hw_v2_init_instance(handle);
7305 if (ret) {
7306 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
7307 * callback function, RoCE Engine reinitialize. If RoCE reinit
7308 * failed, we should inform NIC driver.
7309 */
7310 handle->priv = NULL;
7311 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
7312 } else {
7313 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
7314 dev_info(dev, "reset done, RoCE client reinit finished.\n");
7315 }
7316
7317 hns_roce_bond_resume(handle);
7318 return ret;
7319 }
7320
hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle * handle)7321 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
7322 {
7323 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
7324 return 0;
7325
7326 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
7327 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
7328 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
7329 __hns_roce_hw_v2_uninit_instance(handle, false, false);
7330
7331 return 0;
7332 }
7333
hns_roce_hw_v2_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)7334 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
7335 enum hnae3_reset_notify_type type)
7336 {
7337 int ret = 0;
7338
7339 switch (type) {
7340 case HNAE3_DOWN_CLIENT:
7341 ret = hns_roce_hw_v2_reset_notify_down(handle);
7342 break;
7343 case HNAE3_INIT_CLIENT:
7344 ret = hns_roce_hw_v2_reset_notify_init(handle);
7345 break;
7346 case HNAE3_UNINIT_CLIENT:
7347 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
7348 break;
7349 default:
7350 break;
7351 }
7352
7353 return ret;
7354 }
7355
hns_roce_hw_v2_link_status_change(struct hnae3_handle * handle,bool linkup)7356 static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle,
7357 bool linkup)
7358 {
7359 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
7360 struct net_device *netdev = handle->rinfo.netdev;
7361
7362 if (linkup || !hr_dev)
7363 return;
7364
7365 /* For bond device, the link status depends on the upper netdev,
7366 * and the upper device's link status depends on all the slaves'
7367 * netdev but not only one. So bond device cannot get a correct
7368 * link status from this path.
7369 */
7370 if (hns_roce_get_bond_grp(netdev, get_hr_bus_num(hr_dev)))
7371 return;
7372
7373 ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev);
7374 }
7375
7376 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
7377 .init_instance = hns_roce_hw_v2_init_instance,
7378 .uninit_instance = hns_roce_hw_v2_uninit_instance,
7379 .link_status_change = hns_roce_hw_v2_link_status_change,
7380 .reset_notify = hns_roce_hw_v2_reset_notify,
7381 };
7382
7383 static struct hnae3_client hns_roce_hw_v2_client = {
7384 .name = "hns_roce_hw_v2",
7385 .type = HNAE3_CLIENT_ROCE,
7386 .ops = &hns_roce_hw_v2_ops,
7387 };
7388
hns_roce_hw_v2_init(void)7389 static int __init hns_roce_hw_v2_init(void)
7390 {
7391 hns_roce_init_debugfs();
7392 return hnae3_register_client(&hns_roce_hw_v2_client);
7393 }
7394
hns_roce_hw_v2_exit(void)7395 static void __exit hns_roce_hw_v2_exit(void)
7396 {
7397 hns_roce_dealloc_bond_grp();
7398 hnae3_unregister_client(&hns_roce_hw_v2_client);
7399 hns_roce_cleanup_debugfs();
7400 }
7401
7402 module_init(hns_roce_hw_v2_init);
7403 module_exit(hns_roce_hw_v2_exit);
7404
7405 MODULE_LICENSE("Dual BSD/GPL");
7406 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
7407 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
7408 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
7409 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
7410