1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for DBRI sound chip found on Sparcs. 4 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net) 5 * 6 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl) 7 * 8 * Based entirely upon drivers/sbus/audio/dbri.c which is: 9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 10 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) 11 * 12 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO 13 * on Sun SPARCStation 10, 20, LX and Voyager models. 14 * 15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel 16 * data time multiplexer with ISDN support (aka T7259) 17 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. 18 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). 19 * Documentation: 20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from 21 * Sparc Technology Business (courtesy of Sun Support) 22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent 23 * available from the Lucent (formerly AT&T microelectronics) home 24 * page. 25 * - https://www.freesoft.org/Linux/DBRI/ 26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec 27 * Interfaces: CHI, Audio In & Out, 2 bits parallel 28 * Documentation: from the Crystal Semiconductor home page. 29 * 30 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between 31 * memory and a serial device (long pipes, no. 0-15) or between two serial 32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial 33 * device (short pipes). 34 * A timeslot defines the bit-offset and no. of bits read from a serial device. 35 * The timeslots are linked to 6 circular lists, one for each direction for 36 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes 37 * (the second one is a monitor/tee pipe, valid only for serial input). 38 * 39 * The mmcodec is connected via the CHI bus and needs the data & some 40 * parameters (volume, output selection) time multiplexed in 8 byte 41 * chunks. It also has a control mode, which serves for audio format setting. 42 * 43 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on 44 * the same CHI bus, so I thought perhaps it is possible to use the on-board 45 * & the speakerbox codec simultaneously, giving 2 (not very independent :-) 46 * audio devices. But the SUN HW group decided against it, at least on my 47 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly 48 * connected. 49 * 50 * I've tried to stick to the following function naming conventions: 51 * snd_* ALSA stuff 52 * cs4215_* CS4215 codec specific stuff 53 * dbri_* DBRI high-level stuff 54 * other DBRI low-level stuff 55 */ 56 57 #include <linux/interrupt.h> 58 #include <linux/delay.h> 59 #include <linux/irq.h> 60 #include <linux/io.h> 61 #include <linux/dma-mapping.h> 62 #include <linux/gfp.h> 63 #include <linux/string.h> 64 65 #include <sound/core.h> 66 #include <sound/pcm.h> 67 #include <sound/pcm_params.h> 68 #include <sound/info.h> 69 #include <sound/control.h> 70 #include <sound/initval.h> 71 72 #include <linux/of.h> 73 #include <linux/platform_device.h> 74 #include <linux/atomic.h> 75 #include <linux/module.h> 76 77 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); 78 MODULE_DESCRIPTION("Sun DBRI"); 79 MODULE_LICENSE("GPL"); 80 81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 82 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 83 /* Enable this card */ 84 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 85 86 module_param_array(index, int, NULL, 0444); 87 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); 88 module_param_array(id, charp, NULL, 0444); 89 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); 90 module_param_array(enable, bool, NULL, 0444); 91 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); 92 93 #undef DBRI_DEBUG 94 95 #define D_INT (1<<0) 96 #define D_GEN (1<<1) 97 #define D_CMD (1<<2) 98 #define D_MM (1<<3) 99 #define D_USR (1<<4) 100 #define D_DESC (1<<5) 101 102 static int dbri_debug; 103 module_param(dbri_debug, int, 0644); 104 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); 105 106 #ifdef DBRI_DEBUG 107 static const char * const cmds[] = { 108 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", 109 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" 110 }; 111 112 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x) 113 114 #else 115 #define dprintk(a, x...) do { } while (0) 116 117 #endif /* DBRI_DEBUG */ 118 119 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ 120 (intr << 27) | \ 121 value) 122 123 /*************************************************************************** 124 CS4215 specific definitions and structures 125 ****************************************************************************/ 126 127 struct cs4215 { 128 __u8 data[4]; /* Data mode: Time slots 5-8 */ 129 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ 130 __u8 onboard; 131 __u8 offset; /* Bit offset from frame sync to time slot 1 */ 132 volatile __u32 status; 133 volatile __u32 version; 134 __u8 precision; /* In bits, either 8 or 16 */ 135 __u8 channels; /* 1 or 2 */ 136 }; 137 138 /* 139 * Control mode first 140 */ 141 142 /* Time Slot 1, Status register */ 143 #define CS4215_CLB (1<<2) /* Control Latch Bit */ 144 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ 145 /* 0: line: 2.8V, speaker 8V */ 146 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ 147 #define CS4215_RSRVD_1 (1<<5) 148 149 /* Time Slot 2, Data Format Register */ 150 #define CS4215_DFR_LINEAR16 0 151 #define CS4215_DFR_ULAW 1 152 #define CS4215_DFR_ALAW 2 153 #define CS4215_DFR_LINEAR8 3 154 #define CS4215_DFR_STEREO (1<<2) 155 static struct { 156 unsigned short freq; 157 unsigned char xtal; 158 unsigned char csval; 159 } CS4215_FREQ[] = { 160 { 8000, (1 << 4), (0 << 3) }, 161 { 16000, (1 << 4), (1 << 3) }, 162 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ 163 { 32000, (1 << 4), (3 << 3) }, 164 /* { NA, (1 << 4), (4 << 3) }, */ 165 /* { NA, (1 << 4), (5 << 3) }, */ 166 { 48000, (1 << 4), (6 << 3) }, 167 { 9600, (1 << 4), (7 << 3) }, 168 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ 169 { 11025, (2 << 4), (1 << 3) }, 170 { 18900, (2 << 4), (2 << 3) }, 171 { 22050, (2 << 4), (3 << 3) }, 172 { 37800, (2 << 4), (4 << 3) }, 173 { 44100, (2 << 4), (5 << 3) }, 174 { 33075, (2 << 4), (6 << 3) }, 175 { 6615, (2 << 4), (7 << 3) }, 176 { 0, 0, 0} 177 }; 178 179 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ 180 181 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ 182 183 /* Time Slot 3, Serial Port Control register */ 184 #define CS4215_XEN (1<<0) /* 0: Enable serial output */ 185 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ 186 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ 187 #define CS4215_BSEL_128 (1<<2) 188 #define CS4215_BSEL_256 (2<<2) 189 #define CS4215_MCK_MAST (0<<4) /* Master clock */ 190 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ 191 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ 192 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ 193 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ 194 195 /* Time Slot 4, Test Register */ 196 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ 197 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */ 198 199 /* Time Slot 5, Parallel Port Register */ 200 /* Read only here and the same as the in data mode */ 201 202 /* Time Slot 6, Reserved */ 203 204 /* Time Slot 7, Version Register */ 205 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ 206 207 /* Time Slot 8, Reserved */ 208 209 /* 210 * Data mode 211 */ 212 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ 213 214 /* Time Slot 5, Output Setting */ 215 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ 216 #define CS4215_LE (1<<6) /* Line Out Enable */ 217 #define CS4215_HE (1<<7) /* Headphone Enable */ 218 219 /* Time Slot 6, Output Setting */ 220 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ 221 #define CS4215_SE (1<<6) /* Speaker Enable */ 222 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ 223 224 /* Time Slot 7, Input Setting */ 225 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ 226 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ 227 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */ 228 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ 229 #define CS4215_PIO1 (1<<7) 230 231 /* Time Slot 8, Input Setting */ 232 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ 233 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ 234 235 /*************************************************************************** 236 DBRI specific definitions and structures 237 ****************************************************************************/ 238 239 /* DBRI main registers */ 240 #define REG0 0x00 /* Status and Control */ 241 #define REG1 0x04 /* Mode and Interrupt */ 242 #define REG2 0x08 /* Parallel IO */ 243 #define REG3 0x0c /* Test */ 244 #define REG8 0x20 /* Command Queue Pointer */ 245 #define REG9 0x24 /* Interrupt Queue Pointer */ 246 247 #define DBRI_NO_CMDS 64 248 #define DBRI_INT_BLK 64 249 #define DBRI_NO_DESCS 64 250 #define DBRI_NO_PIPES 32 251 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) 252 253 #define DBRI_REC 0 254 #define DBRI_PLAY 1 255 #define DBRI_NO_STREAMS 2 256 257 /* One transmit/receive descriptor */ 258 /* When ba != 0 descriptor is used */ 259 struct dbri_mem { 260 volatile __u32 word1; 261 __u32 ba; /* Transmit/Receive Buffer Address */ 262 __u32 nda; /* Next Descriptor Address */ 263 volatile __u32 word4; 264 }; 265 266 /* This structure is in a DMA region where it can accessed by both 267 * the CPU and the DBRI 268 */ 269 struct dbri_dma { 270 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ 271 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */ 272 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ 273 }; 274 275 #define dbri_dma_off(member, elem) \ 276 ((u32)(unsigned long) \ 277 (&(((struct dbri_dma *)0)->member[elem]))) 278 279 enum in_or_out { PIPEinput, PIPEoutput }; 280 281 struct dbri_pipe { 282 u32 sdp; /* SDP command word */ 283 int nextpipe; /* Next pipe in linked list */ 284 int length; /* Length of timeslot (bits) */ 285 int first_desc; /* Index of first descriptor */ 286 int desc; /* Index of active descriptor */ 287 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ 288 }; 289 290 /* Per stream (playback or record) information */ 291 struct dbri_streaminfo { 292 struct snd_pcm_substream *substream; 293 u32 dvma_buffer; /* Device view of ALSA DMA buffer */ 294 int size; /* Size of DMA buffer */ 295 size_t offset; /* offset in user buffer */ 296 int pipe; /* Data pipe used */ 297 int left_gain; /* mixer elements */ 298 int right_gain; 299 }; 300 301 /* This structure holds the information for both chips (DBRI & CS4215) */ 302 struct snd_dbri { 303 int regs_size, irq; /* Needed for unload */ 304 struct platform_device *op; /* OF device info */ 305 spinlock_t lock; 306 307 struct dbri_dma *dma; /* Pointer to our DMA block */ 308 dma_addr_t dma_dvma; /* DBRI visible DMA address */ 309 310 void __iomem *regs; /* dbri HW regs */ 311 int dbri_irqp; /* intr queue pointer */ 312 313 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ 314 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */ 315 spinlock_t cmdlock; /* Protects cmd queue accesses */ 316 s32 *cmdptr; /* Pointer to the last queued cmd */ 317 318 int chi_bpf; 319 320 struct cs4215 mm; /* mmcodec special info */ 321 /* per stream (playback/record) info */ 322 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; 323 }; 324 325 #define DBRI_MAX_VOLUME 63 /* Output volume */ 326 #define DBRI_MAX_GAIN 15 /* Input gain */ 327 328 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */ 329 #define D_P (1<<15) /* Program command & queue pointer valid */ 330 #define D_G (1<<14) /* Allow 4-Word SBus Burst */ 331 #define D_S (1<<13) /* Allow 16-Word SBus Burst */ 332 #define D_E (1<<12) /* Allow 8-Word SBus Burst */ 333 #define D_X (1<<7) /* Sanity Timer Disable */ 334 #define D_T (1<<6) /* Permit activation of the TE interface */ 335 #define D_N (1<<5) /* Permit activation of the NT interface */ 336 #define D_C (1<<4) /* Permit activation of the CHI interface */ 337 #define D_F (1<<3) /* Force Sanity Timer Time-Out */ 338 #define D_D (1<<2) /* Disable Master Mode */ 339 #define D_H (1<<1) /* Halt for Analysis */ 340 #define D_R (1<<0) /* Soft Reset */ 341 342 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ 343 #define D_LITTLE_END (1<<8) /* Byte Order */ 344 #define D_BIG_END (0<<8) /* Byte Order */ 345 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */ 346 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */ 347 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */ 348 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */ 349 #define D_IR (1<<0) /* Interrupt Indicator (read only) */ 350 351 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ 352 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ 353 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ 354 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ 355 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ 356 #define D_ENPIO (0xf0) /* Enable all the pins */ 357 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ 358 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ 359 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ 360 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ 361 362 /* DBRI Commands (Page 20) */ 363 #define D_WAIT 0x0 /* Stop execution */ 364 #define D_PAUSE 0x1 /* Flush long pipes */ 365 #define D_JUMP 0x2 /* New command queue */ 366 #define D_IIQ 0x3 /* Initialize Interrupt Queue */ 367 #define D_REX 0x4 /* Report command execution via interrupt */ 368 #define D_SDP 0x5 /* Setup Data Pipe */ 369 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ 370 #define D_DTS 0x7 /* Define Time Slot */ 371 #define D_SSP 0x8 /* Set short Data Pipe */ 372 #define D_CHI 0x9 /* Set CHI Global Mode */ 373 #define D_NT 0xa /* NT Command */ 374 #define D_TE 0xb /* TE Command */ 375 #define D_CDEC 0xc /* Codec setup */ 376 #define D_TEST 0xd /* No comment */ 377 #define D_CDM 0xe /* CHI Data mode command */ 378 379 /* Special bits for some commands */ 380 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */ 381 382 /* Setup Data Pipe */ 383 /* IRM */ 384 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */ 385 #define D_SDP_CHANGE (2<<18) /* Report any changes */ 386 #define D_SDP_EVERY (3<<18) /* Report any changes */ 387 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ 388 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ 389 390 /* Pipe data MODE */ 391 #define D_SDP_MEM (0<<13) /* To/from memory */ 392 #define D_SDP_HDLC (2<<13) 393 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ 394 #define D_SDP_SER (4<<13) /* Serial to serial */ 395 #define D_SDP_FIXED (6<<13) /* Short only */ 396 #define D_SDP_MODE(v) ((v)&(7<<13)) 397 398 #define D_SDP_TO_SER (1<<12) /* Direction */ 399 #define D_SDP_FROM_SER (0<<12) /* Direction */ 400 #define D_SDP_MSB (1<<11) /* Bit order within Byte */ 401 #define D_SDP_LSB (0<<11) /* Bit order within Byte */ 402 #define D_SDP_P (1<<10) /* Pointer Valid */ 403 #define D_SDP_A (1<<8) /* Abort */ 404 #define D_SDP_C (1<<7) /* Clear */ 405 406 /* Define Time Slot */ 407 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ 408 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ 409 #define D_DTS_INS (1<<15) /* Insert Time Slot */ 410 #define D_DTS_DEL (0<<15) /* Delete Time Slot */ 411 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ 412 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ 413 414 /* Time Slot defines */ 415 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ 416 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ 417 #define D_TS_DI (1<<13) /* Data Invert */ 418 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ 419 #define D_TS_MONITOR (2<<10) /* Monitor pipe */ 420 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ 421 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ 422 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ 423 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */ 424 425 /* Concentration Highway Interface Modes */ 426 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ 427 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ 428 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ 429 #define D_CHI_OD (1<<13) /* Open Drain Enable */ 430 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ 431 #define D_CHI_FD (1<<11) /* Frame Drive */ 432 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ 433 434 /* NT: These are here for completeness */ 435 #define D_NT_FBIT (1<<17) /* Frame Bit */ 436 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ 437 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ 438 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ 439 #define D_NT_ISNT (1<<13) /* Configure interface as NT */ 440 #define D_NT_FT (1<<12) /* Fixed Timing */ 441 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ 442 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ 443 #define D_NT_ACT (1<<9) /* Activate Interface */ 444 #define D_NT_MFE (1<<8) /* Multiframe Enable */ 445 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ 446 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ 447 #define D_NT_FACT (1<<1) /* Force Activation */ 448 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ 449 450 /* Codec Setup */ 451 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ 452 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ 453 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ 454 455 /* Test */ 456 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ 457 #define D_TEST_SIZE(v) ((v)<<11) /* */ 458 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ 459 #define D_TEST_PROC 0x6 /* Microprocessor test */ 460 #define D_TEST_SER 0x7 /* Serial-Controller test */ 461 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ 462 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ 463 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ 464 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ 465 #define D_TEST_DUMP 0xe /* ROM Dump */ 466 467 /* CHI Data Mode */ 468 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */ 469 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */ 470 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */ 471 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */ 472 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */ 473 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */ 474 475 /* The Interrupts */ 476 #define D_INTR_BRDY 1 /* Buffer Ready for processing */ 477 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ 478 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ 479 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ 480 #define D_INTR_EOL 5 /* End of List */ 481 #define D_INTR_CMDI 6 /* Command has bean read */ 482 #define D_INTR_XCMP 8 /* Transmission of frame complete */ 483 #define D_INTR_SBRI 9 /* BRI status change info */ 484 #define D_INTR_FXDT 10 /* Fixed data change */ 485 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ 486 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ 487 #define D_INTR_DBYT 12 /* Dropped by frame slip */ 488 #define D_INTR_RBYT 13 /* Repeated by frame slip */ 489 #define D_INTR_LINT 14 /* Lost Interrupt */ 490 #define D_INTR_UNDR 15 /* DMA underrun */ 491 492 #define D_INTR_TE 32 493 #define D_INTR_NT 34 494 #define D_INTR_CHI 36 495 #define D_INTR_CMD 38 496 497 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) 498 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf) 499 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf) 500 #define D_INTR_GETVAL(v) ((v) & 0xffff) 501 #define D_INTR_GETRVAL(v) ((v) & 0xfffff) 502 503 #define D_P_0 0 /* TE receive anchor */ 504 #define D_P_1 1 /* TE transmit anchor */ 505 #define D_P_2 2 /* NT transmit anchor */ 506 #define D_P_3 3 /* NT receive anchor */ 507 #define D_P_4 4 /* CHI send data */ 508 #define D_P_5 5 /* CHI receive data */ 509 #define D_P_6 6 /* */ 510 #define D_P_7 7 /* */ 511 #define D_P_8 8 /* */ 512 #define D_P_9 9 /* */ 513 #define D_P_10 10 /* */ 514 #define D_P_11 11 /* */ 515 #define D_P_12 12 /* */ 516 #define D_P_13 13 /* */ 517 #define D_P_14 14 /* */ 518 #define D_P_15 15 /* */ 519 #define D_P_16 16 /* CHI anchor pipe */ 520 #define D_P_17 17 /* CHI send */ 521 #define D_P_18 18 /* CHI receive */ 522 #define D_P_19 19 /* CHI receive */ 523 #define D_P_20 20 /* CHI receive */ 524 #define D_P_21 21 /* */ 525 #define D_P_22 22 /* */ 526 #define D_P_23 23 /* */ 527 #define D_P_24 24 /* */ 528 #define D_P_25 25 /* */ 529 #define D_P_26 26 /* */ 530 #define D_P_27 27 /* */ 531 #define D_P_28 28 /* */ 532 #define D_P_29 29 /* */ 533 #define D_P_30 30 /* */ 534 #define D_P_31 31 /* */ 535 536 /* Transmit descriptor defines */ 537 #define DBRI_TD_F (1 << 31) /* End of Frame */ 538 #define DBRI_TD_D (1 << 30) /* Do not append CRC */ 539 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */ 540 #define DBRI_TD_B (1 << 15) /* Final interrupt */ 541 #define DBRI_TD_M (1 << 14) /* Marker interrupt */ 542 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */ 543 #define DBRI_TD_FCNT(v) (v) /* Flag Count */ 544 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */ 545 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */ 546 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */ 547 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */ 548 /* Maximum buffer size per TD: almost 8KB */ 549 #define DBRI_TD_MAXCNT ((1 << 13) - 4) 550 551 /* Receive descriptor defines */ 552 #define DBRI_RD_F (1 << 31) /* End of Frame */ 553 #define DBRI_RD_C (1 << 30) /* Completed buffer */ 554 #define DBRI_RD_B (1 << 15) /* Final interrupt */ 555 #define DBRI_RD_M (1 << 14) /* Marker interrupt */ 556 #define DBRI_RD_BCNT(v) (v) /* Buffer size */ 557 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */ 558 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */ 559 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */ 560 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */ 561 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */ 562 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */ 563 564 /* stream_info[] access */ 565 /* Translate the ALSA direction into the array index */ 566 #define DBRI_STREAMNO(substream) \ 567 (substream->stream == \ 568 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC) 569 570 /* Return a pointer to dbri_streaminfo */ 571 #define DBRI_STREAM(dbri, substream) \ 572 &dbri->stream_info[DBRI_STREAMNO(substream)] 573 574 /* 575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. 576 * So we have to reverse the bits. Note: not all bit lengths are supported 577 */ 578 static __u32 reverse_bytes(__u32 b, int len) 579 { 580 switch (len) { 581 case 32: 582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 583 fallthrough; 584 case 16: 585 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 586 fallthrough; 587 case 8: 588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 589 fallthrough; 590 case 4: 591 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 592 fallthrough; 593 case 2: 594 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 595 fallthrough; 596 case 1: 597 case 0: 598 break; 599 default: 600 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); 601 } 602 603 return b; 604 } 605 606 /* 607 **************************************************************************** 608 ************** DBRI initialization and command synchronization ************* 609 **************************************************************************** 610 611 Commands are sent to the DBRI by building a list of them in memory, 612 then writing the address of the first list item to DBRI register 8. 613 The list is terminated with a WAIT command, which generates a 614 CPU interrupt to signal completion. 615 616 Since the DBRI can run in parallel with the CPU, several means of 617 synchronization present themselves. The method implemented here uses 618 the dbri_cmdwait() to wait for execution of batch of sent commands. 619 620 A circular command buffer is used here. A new command is being added 621 while another can be executed. The scheme works by adding two WAIT commands 622 after each sent batch of commands. When the next batch is prepared it is 623 added after the WAIT commands then the WAITs are replaced with single JUMP 624 command to the new batch. Then the DBRI is forced to reread the last WAIT 625 command (replaced by the JUMP by then). If the DBRI is still executing 626 previous commands the request to reread the WAIT command is ignored. 627 628 Every time a routine wants to write commands to the DBRI, it must 629 first call dbri_cmdlock() and get pointer to a free space in 630 dbri->dma->cmd buffer. After this, the commands can be written to 631 the buffer, and dbri_cmdsend() is called with the final pointer value 632 to send them to the DBRI. 633 634 */ 635 636 #define MAXLOOPS 20 637 /* 638 * Wait for the current command string to execute 639 */ 640 static void dbri_cmdwait(struct snd_dbri *dbri) 641 { 642 int maxloops = MAXLOOPS; 643 unsigned long flags; 644 645 /* Delay if previous commands are still being processed */ 646 spin_lock_irqsave(&dbri->lock, flags); 647 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) { 648 spin_unlock_irqrestore(&dbri->lock, flags); 649 msleep_interruptible(1); 650 spin_lock_irqsave(&dbri->lock, flags); 651 } 652 spin_unlock_irqrestore(&dbri->lock, flags); 653 654 if (maxloops == 0) 655 printk(KERN_ERR "DBRI: Chip never completed command buffer\n"); 656 else 657 dprintk(D_CMD, "Chip completed command buffer (%d)\n", 658 MAXLOOPS - maxloops - 1); 659 } 660 /* 661 * Lock the command queue and return pointer to space for len cmd words 662 * It locks the cmdlock spinlock. 663 */ 664 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len) 665 { 666 u32 dvma_addr = (u32)dbri->dma_dvma; 667 668 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */ 669 len += 2; 670 spin_lock(&dbri->cmdlock); 671 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2) 672 return dbri->cmdptr + 2; 673 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr) 674 return dbri->dma->cmd; 675 else 676 printk(KERN_ERR "DBRI: no space for commands."); 677 678 return NULL; 679 } 680 681 /* 682 * Send prepared cmd string. It works by writing a JUMP cmd into 683 * the last WAIT cmd and force DBRI to reread the cmd. 684 * The JUMP cmd points to the new cmd string. 685 * It also releases the cmdlock spinlock. 686 * 687 * Lock must be held before calling this. 688 */ 689 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len) 690 { 691 u32 dvma_addr = (u32)dbri->dma_dvma; 692 s32 tmp, addr; 693 static int wait_id; 694 695 wait_id++; 696 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */ 697 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id); 698 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id); 699 700 /* Replace the last command with JUMP */ 701 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32); 702 *(dbri->cmdptr+1) = addr; 703 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0); 704 705 #ifdef DBRI_DEBUG 706 if (cmd > dbri->cmdptr) { 707 s32 *ptr; 708 709 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++) 710 dprintk(D_CMD, "cmd: %lx:%08x\n", 711 (unsigned long)ptr, *ptr); 712 } else { 713 s32 *ptr = dbri->cmdptr; 714 715 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 716 ptr++; 717 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 718 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) 719 dprintk(D_CMD, "cmd: %lx:%08x\n", 720 (unsigned long)ptr, *ptr); 721 } 722 #endif 723 724 /* Reread the last command */ 725 tmp = sbus_readl(dbri->regs + REG0); 726 tmp |= D_P; 727 sbus_writel(tmp, dbri->regs + REG0); 728 729 dbri->cmdptr = cmd; 730 spin_unlock(&dbri->cmdlock); 731 } 732 733 /* Lock must be held when calling this */ 734 static void dbri_reset(struct snd_dbri *dbri) 735 { 736 int i; 737 u32 tmp; 738 739 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", 740 sbus_readl(dbri->regs + REG0), 741 sbus_readl(dbri->regs + REG2), 742 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); 743 744 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ 745 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) 746 udelay(10); 747 748 /* A brute approach - DBRI falls back to working burst size by itself 749 * On SS20 D_S does not work, so do not try so high. */ 750 tmp = sbus_readl(dbri->regs + REG0); 751 tmp |= D_G | D_E; 752 tmp &= ~D_S; 753 sbus_writel(tmp, dbri->regs + REG0); 754 } 755 756 /* Lock must not be held before calling this */ 757 static void dbri_initialize(struct snd_dbri *dbri) 758 { 759 u32 dvma_addr = (u32)dbri->dma_dvma; 760 s32 *cmd; 761 u32 dma_addr; 762 int n; 763 764 scoped_guard(spinlock_irqsave, &dbri->lock) { 765 dbri_reset(dbri); 766 767 /* Initialize pipes */ 768 for (n = 0; n < DBRI_NO_PIPES; n++) 769 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; 770 771 spin_lock_init(&dbri->cmdlock); 772 /* 773 * Initialize the interrupt ring buffer. 774 */ 775 dma_addr = dvma_addr + dbri_dma_off(intr, 0); 776 dbri->dma->intr[0] = dma_addr; 777 dbri->dbri_irqp = 1; 778 /* 779 * Set up the interrupt queue 780 */ 781 scoped_guard(spinlock, &dbri->cmdlock) { 782 cmd = dbri->cmdptr = dbri->dma->cmd; 783 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); 784 *(cmd++) = dma_addr; 785 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 786 dbri->cmdptr = cmd; 787 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 788 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 789 dma_addr = dvma_addr + dbri_dma_off(cmd, 0); 790 sbus_writel(dma_addr, dbri->regs + REG8); 791 } 792 } 793 794 dbri_cmdwait(dbri); 795 } 796 797 /* 798 **************************************************************************** 799 ************************** DBRI data pipe management *********************** 800 **************************************************************************** 801 802 While DBRI control functions use the command and interrupt buffers, the 803 main data path takes the form of data pipes, which can be short (command 804 and interrupt driven), or long (attached to DMA buffers). These functions 805 provide a rudimentary means of setting up and managing the DBRI's pipes, 806 but the calling functions have to make sure they respect the pipes' linked 807 list ordering, among other things. The transmit and receive functions 808 here interface closely with the transmit and receive interrupt code. 809 810 */ 811 static inline int pipe_active(struct snd_dbri *dbri, int pipe) 812 { 813 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); 814 } 815 816 /* reset_pipe(dbri, pipe) 817 * 818 * Called on an in-use pipe to clear anything being transmitted or received 819 * Lock must be held before calling this. 820 */ 821 static void reset_pipe(struct snd_dbri *dbri, int pipe) 822 { 823 int sdp; 824 int desc; 825 s32 *cmd; 826 827 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 828 printk(KERN_ERR "DBRI: reset_pipe called with " 829 "illegal pipe number\n"); 830 return; 831 } 832 833 sdp = dbri->pipes[pipe].sdp; 834 if (sdp == 0) { 835 printk(KERN_ERR "DBRI: reset_pipe called " 836 "on uninitialized pipe\n"); 837 return; 838 } 839 840 cmd = dbri_cmdlock(dbri, 3); 841 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); 842 *(cmd++) = 0; 843 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 844 dbri_cmdsend(dbri, cmd, 3); 845 846 desc = dbri->pipes[pipe].first_desc; 847 if (desc >= 0) 848 do { 849 dbri->dma->desc[desc].ba = 0; 850 dbri->dma->desc[desc].nda = 0; 851 desc = dbri->next_desc[desc]; 852 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); 853 854 dbri->pipes[pipe].desc = -1; 855 dbri->pipes[pipe].first_desc = -1; 856 } 857 858 /* 859 * Lock must be held before calling this. 860 */ 861 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp) 862 { 863 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 864 printk(KERN_ERR "DBRI: setup_pipe called " 865 "with illegal pipe number\n"); 866 return; 867 } 868 869 if ((sdp & 0xf800) != sdp) { 870 printk(KERN_ERR "DBRI: setup_pipe called " 871 "with strange SDP value\n"); 872 /* sdp &= 0xf800; */ 873 } 874 875 /* If this is a fixed receive pipe, arrange for an interrupt 876 * every time its data changes 877 */ 878 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) 879 sdp |= D_SDP_CHANGE; 880 881 sdp |= D_PIPE(pipe); 882 dbri->pipes[pipe].sdp = sdp; 883 dbri->pipes[pipe].desc = -1; 884 dbri->pipes[pipe].first_desc = -1; 885 886 reset_pipe(dbri, pipe); 887 } 888 889 /* 890 * Lock must be held before calling this. 891 */ 892 static void link_time_slot(struct snd_dbri *dbri, int pipe, 893 int prevpipe, int nextpipe, 894 int length, int cycle) 895 { 896 s32 *cmd; 897 int val; 898 899 if (pipe < 0 || pipe > DBRI_MAX_PIPE 900 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE 901 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { 902 printk(KERN_ERR 903 "DBRI: link_time_slot called with illegal pipe number\n"); 904 return; 905 } 906 907 if (dbri->pipes[pipe].sdp == 0 908 || dbri->pipes[prevpipe].sdp == 0 909 || dbri->pipes[nextpipe].sdp == 0) { 910 printk(KERN_ERR "DBRI: link_time_slot called " 911 "on uninitialized pipe\n"); 912 return; 913 } 914 915 dbri->pipes[prevpipe].nextpipe = pipe; 916 dbri->pipes[pipe].nextpipe = nextpipe; 917 dbri->pipes[pipe].length = length; 918 919 cmd = dbri_cmdlock(dbri, 4); 920 921 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 922 /* Deal with CHI special case: 923 * "If transmission on edges 0 or 1 is desired, then cycle n 924 * (where n = # of bit times per frame...) must be used." 925 * - DBRI data sheet, page 11 926 */ 927 if (prevpipe == 16 && cycle == 0) 928 cycle = dbri->chi_bpf; 929 930 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; 931 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 932 *(cmd++) = 0; 933 *(cmd++) = 934 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 935 } else { 936 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; 937 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 938 *(cmd++) = 939 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 940 *(cmd++) = 0; 941 } 942 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 943 944 dbri_cmdsend(dbri, cmd, 4); 945 } 946 947 #if 0 948 /* 949 * Lock must be held before calling this. 950 */ 951 static void unlink_time_slot(struct snd_dbri *dbri, int pipe, 952 enum in_or_out direction, int prevpipe, 953 int nextpipe) 954 { 955 s32 *cmd; 956 int val; 957 958 if (pipe < 0 || pipe > DBRI_MAX_PIPE 959 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE 960 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { 961 printk(KERN_ERR 962 "DBRI: unlink_time_slot called with illegal pipe number\n"); 963 return; 964 } 965 966 cmd = dbri_cmdlock(dbri, 4); 967 968 if (direction == PIPEinput) { 969 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; 970 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 971 *(cmd++) = D_TS_NEXT(nextpipe); 972 *(cmd++) = 0; 973 } else { 974 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; 975 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 976 *(cmd++) = 0; 977 *(cmd++) = D_TS_NEXT(nextpipe); 978 } 979 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 980 981 dbri_cmdsend(dbri, cmd, 4); 982 } 983 #endif 984 985 /* xmit_fixed() / recv_fixed() 986 * 987 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not 988 * expected to change much, and which we don't need to buffer. 989 * The DBRI only interrupts us when the data changes (receive pipes), 990 * or only changes the data when this function is called (transmit pipes). 991 * Only short pipes (numbers 16-31) can be used in fixed data mode. 992 * 993 * These function operate on a 32-bit field, no matter how large 994 * the actual time slot is. The interrupt handler takes care of bit 995 * ordering and alignment. An 8-bit time slot will always end up 996 * in the low-order 8 bits, filled either MSB-first or LSB-first, 997 * depending on the settings passed to setup_pipe(). 998 * 999 * Lock must not be held before calling it. 1000 */ 1001 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data) 1002 { 1003 s32 *cmd; 1004 1005 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 1006 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n"); 1007 return; 1008 } 1009 1010 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { 1011 printk(KERN_ERR "DBRI: xmit_fixed: " 1012 "Uninitialized pipe %d\n", pipe); 1013 return; 1014 } 1015 1016 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1017 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); 1018 return; 1019 } 1020 1021 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { 1022 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", 1023 pipe); 1024 return; 1025 } 1026 1027 /* DBRI short pipes always transmit LSB first */ 1028 1029 if (dbri->pipes[pipe].sdp & D_SDP_MSB) 1030 data = reverse_bytes(data, dbri->pipes[pipe].length); 1031 1032 cmd = dbri_cmdlock(dbri, 3); 1033 1034 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); 1035 *(cmd++) = data; 1036 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1037 1038 scoped_guard(spinlock_irqsave, &dbri->lock) { 1039 dbri_cmdsend(dbri, cmd, 3); 1040 } 1041 1042 dbri_cmdwait(dbri); 1043 1044 } 1045 1046 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr) 1047 { 1048 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 1049 printk(KERN_ERR "DBRI: recv_fixed called with " 1050 "illegal pipe number\n"); 1051 return; 1052 } 1053 1054 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1055 printk(KERN_ERR "DBRI: recv_fixed called on " 1056 "non-fixed pipe %d\n", pipe); 1057 return; 1058 } 1059 1060 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 1061 printk(KERN_ERR "DBRI: recv_fixed called on " 1062 "transmit pipe %d\n", pipe); 1063 return; 1064 } 1065 1066 dbri->pipes[pipe].recv_fixed_ptr = ptr; 1067 } 1068 1069 /* setup_descs() 1070 * 1071 * Setup transmit/receive data on a "long" pipe - i.e, one associated 1072 * with a DMA buffer. 1073 * 1074 * Only pipe numbers 0-15 can be used in this mode. 1075 * 1076 * This function takes a stream number pointing to a data buffer, 1077 * and work by building chains of descriptors which identify the 1078 * data buffers. Buffers too large for a single descriptor will 1079 * be spread across multiple descriptors. 1080 * 1081 * All descriptors create a ring buffer. 1082 * 1083 * Lock must be held before calling this. 1084 */ 1085 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period) 1086 { 1087 struct dbri_streaminfo *info = &dbri->stream_info[streamno]; 1088 u32 dvma_addr = (u32)dbri->dma_dvma; 1089 __u32 dvma_buffer; 1090 int desc; 1091 int len; 1092 int first_desc = -1; 1093 int last_desc = -1; 1094 1095 if (info->pipe < 0 || info->pipe > 15) { 1096 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n"); 1097 return -2; 1098 } 1099 1100 if (dbri->pipes[info->pipe].sdp == 0) { 1101 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n", 1102 info->pipe); 1103 return -2; 1104 } 1105 1106 dvma_buffer = info->dvma_buffer; 1107 len = info->size; 1108 1109 if (streamno == DBRI_PLAY) { 1110 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { 1111 printk(KERN_ERR "DBRI: setup_descs: " 1112 "Called on receive pipe %d\n", info->pipe); 1113 return -2; 1114 } 1115 } else { 1116 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { 1117 printk(KERN_ERR 1118 "DBRI: setup_descs: Called on transmit pipe %d\n", 1119 info->pipe); 1120 return -2; 1121 } 1122 /* Should be able to queue multiple buffers 1123 * to receive on a pipe 1124 */ 1125 if (pipe_active(dbri, info->pipe)) { 1126 printk(KERN_ERR "DBRI: recv_on_pipe: " 1127 "Called on active pipe %d\n", info->pipe); 1128 return -2; 1129 } 1130 1131 /* Make sure buffer size is multiple of four */ 1132 len &= ~3; 1133 } 1134 1135 /* Free descriptors if pipe has any */ 1136 desc = dbri->pipes[info->pipe].first_desc; 1137 if (desc >= 0) 1138 do { 1139 dbri->dma->desc[desc].ba = 0; 1140 dbri->dma->desc[desc].nda = 0; 1141 desc = dbri->next_desc[desc]; 1142 } while (desc != -1 && 1143 desc != dbri->pipes[info->pipe].first_desc); 1144 1145 dbri->pipes[info->pipe].desc = -1; 1146 dbri->pipes[info->pipe].first_desc = -1; 1147 1148 desc = 0; 1149 while (len > 0) { 1150 int mylen; 1151 1152 for (; desc < DBRI_NO_DESCS; desc++) { 1153 if (!dbri->dma->desc[desc].ba) 1154 break; 1155 } 1156 1157 if (desc == DBRI_NO_DESCS) { 1158 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n"); 1159 return -1; 1160 } 1161 1162 if (len > DBRI_TD_MAXCNT) 1163 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */ 1164 else 1165 mylen = len; 1166 1167 if (mylen > period) 1168 mylen = period; 1169 1170 dbri->next_desc[desc] = -1; 1171 dbri->dma->desc[desc].ba = dvma_buffer; 1172 dbri->dma->desc[desc].nda = 0; 1173 1174 if (streamno == DBRI_PLAY) { 1175 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); 1176 dbri->dma->desc[desc].word4 = 0; 1177 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B; 1178 } else { 1179 dbri->dma->desc[desc].word1 = 0; 1180 dbri->dma->desc[desc].word4 = 1181 DBRI_RD_B | DBRI_RD_BCNT(mylen); 1182 } 1183 1184 if (first_desc == -1) 1185 first_desc = desc; 1186 else { 1187 dbri->next_desc[last_desc] = desc; 1188 dbri->dma->desc[last_desc].nda = 1189 dvma_addr + dbri_dma_off(desc, desc); 1190 } 1191 1192 last_desc = desc; 1193 dvma_buffer += mylen; 1194 len -= mylen; 1195 } 1196 1197 if (first_desc == -1 || last_desc == -1) { 1198 printk(KERN_ERR "DBRI: setup_descs: " 1199 " Not enough descriptors available\n"); 1200 return -1; 1201 } 1202 1203 dbri->dma->desc[last_desc].nda = 1204 dvma_addr + dbri_dma_off(desc, first_desc); 1205 dbri->next_desc[last_desc] = first_desc; 1206 dbri->pipes[info->pipe].first_desc = first_desc; 1207 dbri->pipes[info->pipe].desc = first_desc; 1208 1209 #ifdef DBRI_DEBUG 1210 for (desc = first_desc; desc != -1;) { 1211 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", 1212 desc, 1213 dbri->dma->desc[desc].word1, 1214 dbri->dma->desc[desc].ba, 1215 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); 1216 desc = dbri->next_desc[desc]; 1217 if (desc == first_desc) 1218 break; 1219 } 1220 #endif 1221 return 0; 1222 } 1223 1224 /* 1225 **************************************************************************** 1226 ************************** DBRI - CHI interface **************************** 1227 **************************************************************************** 1228 1229 The CHI is a four-wire (clock, frame sync, data in, data out) time-division 1230 multiplexed serial interface which the DBRI can operate in either master 1231 (give clock/frame sync) or slave (take clock/frame sync) mode. 1232 1233 */ 1234 1235 enum master_or_slave { CHImaster, CHIslave }; 1236 1237 /* 1238 * Lock must not be held before calling it. 1239 */ 1240 static void reset_chi(struct snd_dbri *dbri, 1241 enum master_or_slave master_or_slave, 1242 int bits_per_frame) 1243 { 1244 s32 *cmd; 1245 int val; 1246 1247 /* Set CHI Anchor: Pipe 16 */ 1248 1249 cmd = dbri_cmdlock(dbri, 4); 1250 val = D_DTS_VO | D_DTS_VI | D_DTS_INS 1251 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16); 1252 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 1253 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1254 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1255 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1256 dbri_cmdsend(dbri, cmd, 4); 1257 1258 dbri->pipes[16].sdp = 1; 1259 dbri->pipes[16].nextpipe = 16; 1260 1261 cmd = dbri_cmdlock(dbri, 4); 1262 1263 if (master_or_slave == CHIslave) { 1264 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) 1265 * 1266 * CHICM = 0 (slave mode, 8 kHz frame rate) 1267 * IR = give immediate CHI status interrupt 1268 * EN = give CHI status interrupt upon change 1269 */ 1270 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); 1271 } else { 1272 /* Setup DBRI for CHI Master - generate clock, FS 1273 * 1274 * BPF = bits per 8 kHz frame 1275 * 12.288 MHz / CHICM_divisor = clock rate 1276 * FD = 1 - drive CHIFS on rising edge of CHICK 1277 */ 1278 int clockrate = bits_per_frame * 8; 1279 int divisor = 12288 / clockrate; 1280 1281 if (divisor > 255 || divisor * clockrate != 12288) 1282 printk(KERN_ERR "DBRI: illegal bits_per_frame " 1283 "in setup_chi\n"); 1284 1285 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD 1286 | D_CHI_BPF(bits_per_frame)); 1287 } 1288 1289 dbri->chi_bpf = bits_per_frame; 1290 1291 /* CHI Data Mode 1292 * 1293 * RCE = 0 - receive on falling edge of CHICK 1294 * XCE = 1 - transmit on rising edge of CHICK 1295 * XEN = 1 - enable transmitter 1296 * REN = 1 - enable receiver 1297 */ 1298 1299 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1300 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); 1301 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1302 1303 dbri_cmdsend(dbri, cmd, 4); 1304 } 1305 1306 /* 1307 **************************************************************************** 1308 *********************** CS4215 audio codec management ********************** 1309 **************************************************************************** 1310 1311 In the standard SPARC audio configuration, the CS4215 codec is attached 1312 to the DBRI via the CHI interface and few of the DBRI's PIO pins. 1313 1314 * Lock must not be held before calling it. 1315 1316 */ 1317 static void cs4215_setup_pipes(struct snd_dbri *dbri) 1318 { 1319 scoped_guard(spinlock_irqsave, &dbri->lock) { 1320 /* 1321 * Data mode: 1322 * Pipe 4: Send timeslots 1-4 (audio data) 1323 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1324 * Pipe 6: Receive timeslots 1-4 (audio data) 1325 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1326 * interrupt, and the rest of the data (slot 5 and 8) is 1327 * not relevant for us (only for doublechecking). 1328 * 1329 * Control mode: 1330 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) 1331 * Pipe 18: Receive timeslot 1 (clb). 1332 * Pipe 19: Receive timeslot 7 (version). 1333 */ 1334 1335 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); 1336 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1337 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); 1338 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1339 1340 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1341 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1342 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1343 } 1344 1345 dbri_cmdwait(dbri); 1346 } 1347 1348 static int cs4215_init_data(struct cs4215 *mm) 1349 { 1350 /* 1351 * No action, memory resetting only. 1352 * 1353 * Data Time Slot 5-8 1354 * Speaker,Line and Headphone enable. Gain set to the half. 1355 * Input is mike. 1356 */ 1357 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; 1358 mm->data[1] = CS4215_RO(0x20) | CS4215_SE; 1359 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 1360 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); 1361 1362 /* 1363 * Control Time Slot 1-4 1364 * 0: Default I/O voltage scale 1365 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 1366 * 2: Serial enable, CHI master, 128 bits per frame, clock 1 1367 * 3: Tests disabled 1368 */ 1369 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; 1370 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 1371 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 1372 mm->ctrl[3] = 0; 1373 1374 mm->status = 0; 1375 mm->version = 0xff; 1376 mm->precision = 8; /* For ULAW */ 1377 mm->channels = 1; 1378 1379 return 0; 1380 } 1381 1382 static void cs4215_setdata(struct snd_dbri *dbri, int muted) 1383 { 1384 if (muted) { 1385 dbri->mm.data[0] |= 63; 1386 dbri->mm.data[1] |= 63; 1387 dbri->mm.data[2] &= ~15; 1388 dbri->mm.data[3] &= ~15; 1389 } else { 1390 /* Start by setting the playback attenuation. */ 1391 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1392 int left_gain = info->left_gain & 0x3f; 1393 int right_gain = info->right_gain & 0x3f; 1394 1395 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ 1396 dbri->mm.data[1] &= ~0x3f; 1397 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); 1398 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); 1399 1400 /* Now set the recording gain. */ 1401 info = &dbri->stream_info[DBRI_REC]; 1402 left_gain = info->left_gain & 0xf; 1403 right_gain = info->right_gain & 0xf; 1404 dbri->mm.data[2] |= CS4215_LG(left_gain); 1405 dbri->mm.data[3] |= CS4215_RG(right_gain); 1406 } 1407 1408 xmit_fixed(dbri, 20, *(int *)dbri->mm.data); 1409 } 1410 1411 /* 1412 * Set the CS4215 to data mode. 1413 */ 1414 static void cs4215_open(struct snd_dbri *dbri) 1415 { 1416 int data_width; 1417 u32 tmp; 1418 1419 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", 1420 dbri->mm.channels, dbri->mm.precision); 1421 1422 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1423 * to make sure this takes. This avoids clicking noises. 1424 */ 1425 1426 cs4215_setdata(dbri, 1); 1427 udelay(125); 1428 1429 /* 1430 * Data mode: 1431 * Pipe 4: Send timeslots 1-4 (audio data) 1432 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1433 * Pipe 6: Receive timeslots 1-4 (audio data) 1434 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1435 * interrupt, and the rest of the data (slot 5 and 8) is 1436 * not relevant for us (only for doublechecking). 1437 * 1438 * Just like in control mode, the time slots are all offset by eight 1439 * bits. The CS4215, it seems, observes TSIN (the delayed signal) 1440 * even if it's the CHI master. Don't ask me... 1441 */ 1442 scoped_guard(spinlock_irqsave, &dbri->lock) { 1443 tmp = sbus_readl(dbri->regs + REG0); 1444 tmp &= ~(D_C); /* Disable CHI */ 1445 sbus_writel(tmp, dbri->regs + REG0); 1446 1447 /* Switch CS4215 to data mode - set PIO3 to 1 */ 1448 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | 1449 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); 1450 1451 reset_chi(dbri, CHIslave, 128); 1452 1453 /* Note: this next doesn't work for 8-bit stereo, because the two 1454 * channels would be on timeslots 1 and 3, with 2 and 4 idle. 1455 * (See CS4215 datasheet Fig 15) 1456 * 1457 * DBRI non-contiguous mode would be required to make this work. 1458 */ 1459 data_width = dbri->mm.channels * dbri->mm.precision; 1460 1461 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset); 1462 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32); 1463 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset); 1464 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40); 1465 1466 /* FIXME: enable CHI after _setdata? */ 1467 tmp = sbus_readl(dbri->regs + REG0); 1468 tmp |= D_C; /* Enable CHI */ 1469 sbus_writel(tmp, dbri->regs + REG0); 1470 } 1471 1472 cs4215_setdata(dbri, 0); 1473 } 1474 1475 /* 1476 * Send the control information (i.e. audio format) 1477 */ 1478 static int cs4215_setctrl(struct snd_dbri *dbri) 1479 { 1480 int i, val; 1481 u32 tmp; 1482 1483 /* FIXME - let the CPU do something useful during these delays */ 1484 1485 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1486 * to make sure this takes. This avoids clicking noises. 1487 */ 1488 cs4215_setdata(dbri, 1); 1489 udelay(125); 1490 1491 /* 1492 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait 1493 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec 1494 */ 1495 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); 1496 sbus_writel(val, dbri->regs + REG2); 1497 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); 1498 udelay(34); 1499 1500 /* In Control mode, the CS4215 is a slave device, so the DBRI must 1501 * operate as CHI master, supplying clocking and frame synchronization. 1502 * 1503 * In Data mode, however, the CS4215 must be CHI master to insure 1504 * that its data stream is synchronous with its codec. 1505 * 1506 * The upshot of all this? We start by putting the DBRI into master 1507 * mode, program the CS4215 in Control mode, then switch the CS4215 1508 * into Data mode and put the DBRI into slave mode. Various timing 1509 * requirements must be observed along the way. 1510 * 1511 * Oh, and one more thing, on a SPARCStation 20 (and maybe 1512 * others?), the addressing of the CS4215's time slots is 1513 * offset by eight bits, so we add eight to all the "cycle" 1514 * values in the Define Time Slot (DTS) commands. This is 1515 * done in hardware by a TI 248 that delays the DBRI->4215 1516 * frame sync signal by eight clock cycles. Anybody know why? 1517 */ 1518 scoped_guard(spinlock_irqsave, &dbri->lock) { 1519 tmp = sbus_readl(dbri->regs + REG0); 1520 tmp &= ~D_C; /* Disable CHI */ 1521 sbus_writel(tmp, dbri->regs + REG0); 1522 1523 reset_chi(dbri, CHImaster, 128); 1524 1525 /* 1526 * Control mode: 1527 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) 1528 * Pipe 18: Receive timeslot 1 (clb). 1529 * Pipe 19: Receive timeslot 7 (version). 1530 */ 1531 1532 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset); 1533 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset); 1534 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48); 1535 } 1536 1537 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ 1538 dbri->mm.ctrl[0] &= ~CS4215_CLB; 1539 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1540 1541 scoped_guard(spinlock_irqsave, &dbri->lock) { 1542 tmp = sbus_readl(dbri->regs + REG0); 1543 tmp |= D_C; /* Enable CHI */ 1544 sbus_writel(tmp, dbri->regs + REG0); 1545 } 1546 1547 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) 1548 msleep_interruptible(1); 1549 1550 if (i == 0) { 1551 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", 1552 dbri->mm.status); 1553 return -1; 1554 } 1555 1556 /* Disable changes to our copy of the version number, as we are about 1557 * to leave control mode. 1558 */ 1559 recv_fixed(dbri, 19, NULL); 1560 1561 /* Terminate CS4215 control mode - data sheet says 1562 * "Set CLB=1 and send two more frames of valid control info" 1563 */ 1564 dbri->mm.ctrl[0] |= CS4215_CLB; 1565 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1566 1567 /* Two frames of control info @ 8kHz frame rate = 250 us delay */ 1568 udelay(250); 1569 1570 cs4215_setdata(dbri, 0); 1571 1572 return 0; 1573 } 1574 1575 /* 1576 * Setup the codec with the sampling rate, audio format and number of 1577 * channels. 1578 * As part of the process we resend the settings for the data 1579 * timeslots as well. 1580 */ 1581 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate, 1582 snd_pcm_format_t format, unsigned int channels) 1583 { 1584 int freq_idx; 1585 int ret = 0; 1586 1587 /* Lookup index for this rate */ 1588 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { 1589 if (CS4215_FREQ[freq_idx].freq == rate) 1590 break; 1591 } 1592 if (CS4215_FREQ[freq_idx].freq != rate) { 1593 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); 1594 return -1; 1595 } 1596 1597 switch (format) { 1598 case SNDRV_PCM_FORMAT_MU_LAW: 1599 dbri->mm.ctrl[1] = CS4215_DFR_ULAW; 1600 dbri->mm.precision = 8; 1601 break; 1602 case SNDRV_PCM_FORMAT_A_LAW: 1603 dbri->mm.ctrl[1] = CS4215_DFR_ALAW; 1604 dbri->mm.precision = 8; 1605 break; 1606 case SNDRV_PCM_FORMAT_U8: 1607 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; 1608 dbri->mm.precision = 8; 1609 break; 1610 case SNDRV_PCM_FORMAT_S16_BE: 1611 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; 1612 dbri->mm.precision = 16; 1613 break; 1614 default: 1615 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); 1616 return -1; 1617 } 1618 1619 /* Add rate parameters */ 1620 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; 1621 dbri->mm.ctrl[2] = CS4215_XCLK | 1622 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; 1623 1624 dbri->mm.channels = channels; 1625 if (channels == 2) 1626 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; 1627 1628 ret = cs4215_setctrl(dbri); 1629 if (ret == 0) 1630 cs4215_open(dbri); /* set codec to data mode */ 1631 1632 return ret; 1633 } 1634 1635 /* 1636 * 1637 */ 1638 static int cs4215_init(struct snd_dbri *dbri) 1639 { 1640 u32 reg2 = sbus_readl(dbri->regs + REG2); 1641 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); 1642 1643 /* Look for the cs4215 chips */ 1644 if (reg2 & D_PIO2) { 1645 dprintk(D_MM, "Onboard CS4215 detected\n"); 1646 dbri->mm.onboard = 1; 1647 } 1648 if (reg2 & D_PIO0) { 1649 dprintk(D_MM, "Speakerbox detected\n"); 1650 dbri->mm.onboard = 0; 1651 1652 if (reg2 & D_PIO2) { 1653 printk(KERN_INFO "DBRI: Using speakerbox / " 1654 "ignoring onboard mmcodec.\n"); 1655 sbus_writel(D_ENPIO2, dbri->regs + REG2); 1656 } 1657 } 1658 1659 if (!(reg2 & (D_PIO0 | D_PIO2))) { 1660 printk(KERN_ERR "DBRI: no mmcodec found.\n"); 1661 return -EIO; 1662 } 1663 1664 cs4215_setup_pipes(dbri); 1665 cs4215_init_data(&dbri->mm); 1666 1667 /* Enable capture of the status & version timeslots. */ 1668 recv_fixed(dbri, 18, &dbri->mm.status); 1669 recv_fixed(dbri, 19, &dbri->mm.version); 1670 1671 dbri->mm.offset = dbri->mm.onboard ? 0 : 8; 1672 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { 1673 dprintk(D_MM, "CS4215 failed probe at offset %d\n", 1674 dbri->mm.offset); 1675 return -EIO; 1676 } 1677 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); 1678 1679 return 0; 1680 } 1681 1682 /* 1683 **************************************************************************** 1684 *************************** DBRI interrupt handler ************************* 1685 **************************************************************************** 1686 1687 The DBRI communicates with the CPU mainly via a circular interrupt 1688 buffer. When an interrupt is signaled, the CPU walks through the 1689 buffer and calls dbri_process_one_interrupt() for each interrupt word. 1690 Complicated interrupts are handled by dedicated functions (which 1691 appear first in this file). Any pending interrupts can be serviced by 1692 calling dbri_process_interrupt_buffer(), which works even if the CPU's 1693 interrupts are disabled. 1694 1695 */ 1696 1697 /* xmit_descs() 1698 * 1699 * Starts transmitting the current TD's for recording/playing. 1700 * For playback, ALSA has filled the DMA memory with new data (we hope). 1701 */ 1702 static void xmit_descs(struct snd_dbri *dbri) 1703 { 1704 struct dbri_streaminfo *info; 1705 u32 dvma_addr; 1706 s32 *cmd; 1707 int first_td; 1708 1709 if (dbri == NULL) 1710 return; /* Disabled */ 1711 1712 dvma_addr = (u32)dbri->dma_dvma; 1713 info = &dbri->stream_info[DBRI_REC]; 1714 guard(spinlock_irqsave)(&dbri->lock); 1715 1716 if (info->pipe >= 0) { 1717 first_td = dbri->pipes[info->pipe].first_desc; 1718 1719 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); 1720 1721 /* Stream could be closed by the time we run. */ 1722 if (first_td >= 0) { 1723 cmd = dbri_cmdlock(dbri, 2); 1724 *(cmd++) = DBRI_CMD(D_SDP, 0, 1725 dbri->pipes[info->pipe].sdp 1726 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1727 *(cmd++) = dvma_addr + 1728 dbri_dma_off(desc, first_td); 1729 dbri_cmdsend(dbri, cmd, 2); 1730 1731 /* Reset our admin of the pipe. */ 1732 dbri->pipes[info->pipe].desc = first_td; 1733 } 1734 } 1735 1736 info = &dbri->stream_info[DBRI_PLAY]; 1737 1738 if (info->pipe >= 0) { 1739 first_td = dbri->pipes[info->pipe].first_desc; 1740 1741 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); 1742 1743 /* Stream could be closed by the time we run. */ 1744 if (first_td >= 0) { 1745 cmd = dbri_cmdlock(dbri, 2); 1746 *(cmd++) = DBRI_CMD(D_SDP, 0, 1747 dbri->pipes[info->pipe].sdp 1748 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1749 *(cmd++) = dvma_addr + 1750 dbri_dma_off(desc, first_td); 1751 dbri_cmdsend(dbri, cmd, 2); 1752 1753 /* Reset our admin of the pipe. */ 1754 dbri->pipes[info->pipe].desc = first_td; 1755 } 1756 } 1757 } 1758 1759 /* transmission_complete_intr() 1760 * 1761 * Called by main interrupt handler when DBRI signals transmission complete 1762 * on a pipe (interrupt triggered by the B bit in a transmit descriptor). 1763 * 1764 * Walks through the pipe's list of transmit buffer descriptors and marks 1765 * them as available. Stops when the first descriptor is found without 1766 * TBC (Transmit Buffer Complete) set, or we've run through them all. 1767 * 1768 * The DMA buffers are not released. They form a ring buffer and 1769 * they are filled by ALSA while others are transmitted by DMA. 1770 * 1771 */ 1772 1773 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe) 1774 { 1775 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1776 int td = dbri->pipes[pipe].desc; 1777 int status; 1778 1779 while (td >= 0) { 1780 if (td >= DBRI_NO_DESCS) { 1781 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); 1782 return; 1783 } 1784 1785 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); 1786 if (!(status & DBRI_TD_TBC)) 1787 break; 1788 1789 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); 1790 1791 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ 1792 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1); 1793 1794 td = dbri->next_desc[td]; 1795 dbri->pipes[pipe].desc = td; 1796 } 1797 1798 /* Notify ALSA */ 1799 spin_unlock(&dbri->lock); 1800 snd_pcm_period_elapsed(info->substream); 1801 spin_lock(&dbri->lock); 1802 } 1803 1804 static void reception_complete_intr(struct snd_dbri *dbri, int pipe) 1805 { 1806 struct dbri_streaminfo *info; 1807 int rd = dbri->pipes[pipe].desc; 1808 s32 status; 1809 1810 if (rd < 0 || rd >= DBRI_NO_DESCS) { 1811 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); 1812 return; 1813 } 1814 1815 dbri->pipes[pipe].desc = dbri->next_desc[rd]; 1816 status = dbri->dma->desc[rd].word1; 1817 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ 1818 1819 info = &dbri->stream_info[DBRI_REC]; 1820 info->offset += DBRI_RD_CNT(status); 1821 1822 /* FIXME: Check status */ 1823 1824 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", 1825 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); 1826 1827 /* Notify ALSA */ 1828 spin_unlock(&dbri->lock); 1829 snd_pcm_period_elapsed(info->substream); 1830 spin_lock(&dbri->lock); 1831 } 1832 1833 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x) 1834 { 1835 int val = D_INTR_GETVAL(x); 1836 int channel = D_INTR_GETCHAN(x); 1837 int command = D_INTR_GETCMD(x); 1838 int code = D_INTR_GETCODE(x); 1839 #ifdef DBRI_DEBUG 1840 int rval = D_INTR_GETRVAL(x); 1841 #endif 1842 1843 #ifdef DBRI_DEBUG 1844 if (channel == D_INTR_CMD) { 1845 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", 1846 cmds[command], val); 1847 } else { 1848 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", 1849 channel, code, rval); 1850 } 1851 #endif 1852 1853 switch (code) { 1854 case D_INTR_CMDI: 1855 if (command != D_WAIT) 1856 printk(KERN_ERR "DBRI: Command read interrupt\n"); 1857 break; 1858 case D_INTR_BRDY: 1859 reception_complete_intr(dbri, channel); 1860 break; 1861 case D_INTR_XCMP: 1862 case D_INTR_MINT: 1863 transmission_complete_intr(dbri, channel); 1864 break; 1865 case D_INTR_UNDR: 1866 /* UNDR - Transmission underrun 1867 * resend SDP command with clear pipe bit (C) set 1868 */ 1869 { 1870 /* FIXME: do something useful in case of underrun */ 1871 printk(KERN_ERR "DBRI: Underrun error\n"); 1872 #if 0 1873 s32 *cmd; 1874 int pipe = channel; 1875 int td = dbri->pipes[pipe].desc; 1876 1877 dbri->dma->desc[td].word4 = 0; 1878 cmd = dbri_cmdlock(dbri, NoGetLock); 1879 *(cmd++) = DBRI_CMD(D_SDP, 0, 1880 dbri->pipes[pipe].sdp 1881 | D_SDP_P | D_SDP_C | D_SDP_2SAME); 1882 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); 1883 dbri_cmdsend(dbri, cmd); 1884 #endif 1885 } 1886 break; 1887 case D_INTR_FXDT: 1888 /* FXDT - Fixed data change */ 1889 if (dbri->pipes[channel].sdp & D_SDP_MSB) 1890 val = reverse_bytes(val, dbri->pipes[channel].length); 1891 1892 if (dbri->pipes[channel].recv_fixed_ptr) 1893 *(dbri->pipes[channel].recv_fixed_ptr) = val; 1894 break; 1895 default: 1896 if (channel != D_INTR_CMD) 1897 printk(KERN_WARNING 1898 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); 1899 } 1900 } 1901 1902 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt 1903 * buffer until it finds a zero word (indicating nothing more to do 1904 * right now). Non-zero words require processing and are handed off 1905 * to dbri_process_one_interrupt AFTER advancing the pointer. 1906 */ 1907 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri) 1908 { 1909 s32 x; 1910 1911 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { 1912 dbri->dma->intr[dbri->dbri_irqp] = 0; 1913 dbri->dbri_irqp++; 1914 if (dbri->dbri_irqp == DBRI_INT_BLK) 1915 dbri->dbri_irqp = 1; 1916 1917 dbri_process_one_interrupt(dbri, x); 1918 } 1919 } 1920 1921 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id) 1922 { 1923 struct snd_dbri *dbri = dev_id; 1924 static int errcnt; 1925 int x; 1926 1927 if (dbri == NULL) 1928 return IRQ_NONE; 1929 guard(spinlock)(&dbri->lock); 1930 1931 /* 1932 * Read it, so the interrupt goes away. 1933 */ 1934 x = sbus_readl(dbri->regs + REG1); 1935 1936 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { 1937 u32 tmp; 1938 1939 if (x & D_MRR) 1940 printk(KERN_ERR 1941 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", 1942 x); 1943 if (x & D_MLE) 1944 printk(KERN_ERR 1945 "DBRI: Multiple Late Error on SBus reg1=0x%x\n", 1946 x); 1947 if (x & D_LBG) 1948 printk(KERN_ERR 1949 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); 1950 if (x & D_MBE) 1951 printk(KERN_ERR 1952 "DBRI: Burst Error on SBus reg1=0x%x\n", x); 1953 1954 /* Some of these SBus errors cause the chip's SBus circuitry 1955 * to be disabled, so just re-enable and try to keep going. 1956 * 1957 * The only one I've seen is MRR, which will be triggered 1958 * if you let a transmit pipe underrun, then try to CDP it. 1959 * 1960 * If these things persist, we reset the chip. 1961 */ 1962 if ((++errcnt) % 10 == 0) { 1963 dprintk(D_INT, "Interrupt errors exceeded.\n"); 1964 dbri_reset(dbri); 1965 } else { 1966 tmp = sbus_readl(dbri->regs + REG0); 1967 tmp &= ~(D_D); 1968 sbus_writel(tmp, dbri->regs + REG0); 1969 } 1970 } 1971 1972 dbri_process_interrupt_buffer(dbri); 1973 1974 return IRQ_HANDLED; 1975 } 1976 1977 /**************************************************************************** 1978 PCM Interface 1979 ****************************************************************************/ 1980 static const struct snd_pcm_hardware snd_dbri_pcm_hw = { 1981 .info = SNDRV_PCM_INFO_MMAP | 1982 SNDRV_PCM_INFO_INTERLEAVED | 1983 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1984 SNDRV_PCM_INFO_MMAP_VALID | 1985 SNDRV_PCM_INFO_BATCH, 1986 .formats = SNDRV_PCM_FMTBIT_MU_LAW | 1987 SNDRV_PCM_FMTBIT_A_LAW | 1988 SNDRV_PCM_FMTBIT_U8 | 1989 SNDRV_PCM_FMTBIT_S16_BE, 1990 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512, 1991 .rate_min = 5512, 1992 .rate_max = 48000, 1993 .channels_min = 1, 1994 .channels_max = 2, 1995 .buffer_bytes_max = 64 * 1024, 1996 .period_bytes_min = 1, 1997 .period_bytes_max = DBRI_TD_MAXCNT, 1998 .periods_min = 1, 1999 .periods_max = 1024, 2000 }; 2001 2002 static int snd_hw_rule_format(struct snd_pcm_hw_params *params, 2003 struct snd_pcm_hw_rule *rule) 2004 { 2005 struct snd_interval *c = hw_param_interval(params, 2006 SNDRV_PCM_HW_PARAM_CHANNELS); 2007 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 2008 struct snd_mask fmt; 2009 2010 snd_mask_any(&fmt); 2011 if (c->min > 1) { 2012 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE; 2013 return snd_mask_refine(f, &fmt); 2014 } 2015 return 0; 2016 } 2017 2018 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params, 2019 struct snd_pcm_hw_rule *rule) 2020 { 2021 struct snd_interval *c = hw_param_interval(params, 2022 SNDRV_PCM_HW_PARAM_CHANNELS); 2023 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 2024 struct snd_interval ch; 2025 2026 snd_interval_any(&ch); 2027 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) { 2028 ch.min = 1; 2029 ch.max = 1; 2030 ch.integer = 1; 2031 return snd_interval_refine(c, &ch); 2032 } 2033 return 0; 2034 } 2035 2036 static int snd_dbri_open(struct snd_pcm_substream *substream) 2037 { 2038 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2039 struct snd_pcm_runtime *runtime = substream->runtime; 2040 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2041 2042 dprintk(D_USR, "open audio output.\n"); 2043 runtime->hw = snd_dbri_pcm_hw; 2044 2045 scoped_guard(spinlock_irqsave, &dbri->lock) { 2046 info->substream = substream; 2047 info->offset = 0; 2048 info->dvma_buffer = 0; 2049 info->pipe = -1; 2050 } 2051 2052 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2053 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT, 2054 -1); 2055 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT, 2056 snd_hw_rule_channels, NULL, 2057 SNDRV_PCM_HW_PARAM_CHANNELS, 2058 -1); 2059 2060 cs4215_open(dbri); 2061 2062 return 0; 2063 } 2064 2065 static int snd_dbri_close(struct snd_pcm_substream *substream) 2066 { 2067 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2068 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2069 2070 dprintk(D_USR, "close audio output.\n"); 2071 info->substream = NULL; 2072 info->offset = 0; 2073 2074 return 0; 2075 } 2076 2077 static int snd_dbri_hw_params(struct snd_pcm_substream *substream, 2078 struct snd_pcm_hw_params *hw_params) 2079 { 2080 struct snd_pcm_runtime *runtime = substream->runtime; 2081 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2082 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2083 int direction; 2084 int ret; 2085 2086 /* set sampling rate, audio format and number of channels */ 2087 ret = cs4215_prepare(dbri, params_rate(hw_params), 2088 params_format(hw_params), 2089 params_channels(hw_params)); 2090 if (ret != 0) 2091 return ret; 2092 2093 /* hw_params can get called multiple times. Only map the DMA once. 2094 */ 2095 if (info->dvma_buffer == 0) { 2096 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2097 direction = DMA_TO_DEVICE; 2098 else 2099 direction = DMA_FROM_DEVICE; 2100 2101 info->dvma_buffer = 2102 dma_map_single(&dbri->op->dev, 2103 runtime->dma_area, 2104 params_buffer_bytes(hw_params), 2105 direction); 2106 } 2107 2108 direction = params_buffer_bytes(hw_params); 2109 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", 2110 direction, info->dvma_buffer); 2111 return 0; 2112 } 2113 2114 static int snd_dbri_hw_free(struct snd_pcm_substream *substream) 2115 { 2116 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2117 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2118 int direction; 2119 2120 dprintk(D_USR, "hw_free.\n"); 2121 2122 /* hw_free can get called multiple times. Only unmap the DMA once. 2123 */ 2124 if (info->dvma_buffer) { 2125 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2126 direction = DMA_TO_DEVICE; 2127 else 2128 direction = DMA_FROM_DEVICE; 2129 2130 dma_unmap_single(&dbri->op->dev, info->dvma_buffer, 2131 substream->runtime->buffer_size, direction); 2132 info->dvma_buffer = 0; 2133 } 2134 if (info->pipe != -1) { 2135 reset_pipe(dbri, info->pipe); 2136 info->pipe = -1; 2137 } 2138 2139 return 0; 2140 } 2141 2142 static int snd_dbri_prepare(struct snd_pcm_substream *substream) 2143 { 2144 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2145 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2146 int ret; 2147 2148 info->size = snd_pcm_lib_buffer_bytes(substream); 2149 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2150 info->pipe = 4; /* Send pipe */ 2151 else 2152 info->pipe = 6; /* Receive pipe */ 2153 2154 guard(spinlock_irq)(&dbri->lock); 2155 info->offset = 0; 2156 2157 /* Setup the all the transmit/receive descriptors to cover the 2158 * whole DMA buffer. 2159 */ 2160 ret = setup_descs(dbri, DBRI_STREAMNO(substream), 2161 snd_pcm_lib_period_bytes(substream)); 2162 2163 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); 2164 return ret; 2165 } 2166 2167 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd) 2168 { 2169 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2170 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2171 int ret = 0; 2172 2173 switch (cmd) { 2174 case SNDRV_PCM_TRIGGER_START: 2175 dprintk(D_USR, "start audio, period is %d bytes\n", 2176 (int)snd_pcm_lib_period_bytes(substream)); 2177 /* Re-submit the TDs. */ 2178 xmit_descs(dbri); 2179 break; 2180 case SNDRV_PCM_TRIGGER_STOP: 2181 dprintk(D_USR, "stop audio.\n"); 2182 reset_pipe(dbri, info->pipe); 2183 break; 2184 default: 2185 ret = -EINVAL; 2186 } 2187 2188 return ret; 2189 } 2190 2191 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream) 2192 { 2193 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2194 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2195 snd_pcm_uframes_t ret; 2196 2197 ret = bytes_to_frames(substream->runtime, info->offset) 2198 % substream->runtime->buffer_size; 2199 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n", 2200 ret, substream->runtime->buffer_size); 2201 return ret; 2202 } 2203 2204 static const struct snd_pcm_ops snd_dbri_ops = { 2205 .open = snd_dbri_open, 2206 .close = snd_dbri_close, 2207 .hw_params = snd_dbri_hw_params, 2208 .hw_free = snd_dbri_hw_free, 2209 .prepare = snd_dbri_prepare, 2210 .trigger = snd_dbri_trigger, 2211 .pointer = snd_dbri_pointer, 2212 }; 2213 2214 static int snd_dbri_pcm(struct snd_card *card) 2215 { 2216 struct snd_pcm *pcm; 2217 int err; 2218 2219 err = snd_pcm_new(card, 2220 /* ID */ "sun_dbri", 2221 /* device */ 0, 2222 /* playback count */ 1, 2223 /* capture count */ 1, &pcm); 2224 if (err < 0) 2225 return err; 2226 2227 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); 2228 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); 2229 2230 pcm->private_data = card->private_data; 2231 pcm->info_flags = 0; 2232 strscpy(pcm->name, card->shortname); 2233 2234 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, 2235 NULL, 64 * 1024, 64 * 1024); 2236 return 0; 2237 } 2238 2239 /***************************************************************************** 2240 Mixer interface 2241 *****************************************************************************/ 2242 2243 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol, 2244 struct snd_ctl_elem_info *uinfo) 2245 { 2246 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2247 uinfo->count = 2; 2248 uinfo->value.integer.min = 0; 2249 if (kcontrol->private_value == DBRI_PLAY) 2250 uinfo->value.integer.max = DBRI_MAX_VOLUME; 2251 else 2252 uinfo->value.integer.max = DBRI_MAX_GAIN; 2253 return 0; 2254 } 2255 2256 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol, 2257 struct snd_ctl_elem_value *ucontrol) 2258 { 2259 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2260 struct dbri_streaminfo *info; 2261 2262 if (snd_BUG_ON(!dbri)) 2263 return -EINVAL; 2264 info = &dbri->stream_info[kcontrol->private_value]; 2265 2266 ucontrol->value.integer.value[0] = info->left_gain; 2267 ucontrol->value.integer.value[1] = info->right_gain; 2268 return 0; 2269 } 2270 2271 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol, 2272 struct snd_ctl_elem_value *ucontrol) 2273 { 2274 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2275 struct dbri_streaminfo *info = 2276 &dbri->stream_info[kcontrol->private_value]; 2277 unsigned int vol[2]; 2278 int changed = 0; 2279 2280 vol[0] = ucontrol->value.integer.value[0]; 2281 vol[1] = ucontrol->value.integer.value[1]; 2282 if (kcontrol->private_value == DBRI_PLAY) { 2283 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME) 2284 return -EINVAL; 2285 } else { 2286 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN) 2287 return -EINVAL; 2288 } 2289 2290 if (info->left_gain != vol[0]) { 2291 info->left_gain = vol[0]; 2292 changed = 1; 2293 } 2294 if (info->right_gain != vol[1]) { 2295 info->right_gain = vol[1]; 2296 changed = 1; 2297 } 2298 if (changed) { 2299 /* First mute outputs, and wait 1/8000 sec (125 us) 2300 * to make sure this takes. This avoids clicking noises. 2301 */ 2302 cs4215_setdata(dbri, 1); 2303 udelay(125); 2304 cs4215_setdata(dbri, 0); 2305 } 2306 return changed; 2307 } 2308 2309 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol, 2310 struct snd_ctl_elem_info *uinfo) 2311 { 2312 int mask = (kcontrol->private_value >> 16) & 0xff; 2313 2314 uinfo->type = (mask == 1) ? 2315 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2316 uinfo->count = 1; 2317 uinfo->value.integer.min = 0; 2318 uinfo->value.integer.max = mask; 2319 return 0; 2320 } 2321 2322 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol, 2323 struct snd_ctl_elem_value *ucontrol) 2324 { 2325 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2326 int elem = kcontrol->private_value & 0xff; 2327 int shift = (kcontrol->private_value >> 8) & 0xff; 2328 int mask = (kcontrol->private_value >> 16) & 0xff; 2329 int invert = (kcontrol->private_value >> 24) & 1; 2330 2331 if (snd_BUG_ON(!dbri)) 2332 return -EINVAL; 2333 2334 if (elem < 4) 2335 ucontrol->value.integer.value[0] = 2336 (dbri->mm.data[elem] >> shift) & mask; 2337 else 2338 ucontrol->value.integer.value[0] = 2339 (dbri->mm.ctrl[elem - 4] >> shift) & mask; 2340 2341 if (invert == 1) 2342 ucontrol->value.integer.value[0] = 2343 mask - ucontrol->value.integer.value[0]; 2344 return 0; 2345 } 2346 2347 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol, 2348 struct snd_ctl_elem_value *ucontrol) 2349 { 2350 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2351 int elem = kcontrol->private_value & 0xff; 2352 int shift = (kcontrol->private_value >> 8) & 0xff; 2353 int mask = (kcontrol->private_value >> 16) & 0xff; 2354 int invert = (kcontrol->private_value >> 24) & 1; 2355 int changed = 0; 2356 unsigned short val; 2357 2358 if (snd_BUG_ON(!dbri)) 2359 return -EINVAL; 2360 2361 val = (ucontrol->value.integer.value[0] & mask); 2362 if (invert == 1) 2363 val = mask - val; 2364 val <<= shift; 2365 2366 if (elem < 4) { 2367 dbri->mm.data[elem] = (dbri->mm.data[elem] & 2368 ~(mask << shift)) | val; 2369 changed = (val != dbri->mm.data[elem]); 2370 } else { 2371 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & 2372 ~(mask << shift)) | val; 2373 changed = (val != dbri->mm.ctrl[elem - 4]); 2374 } 2375 2376 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " 2377 "mixer-value=%ld, mm-value=0x%x\n", 2378 mask, changed, ucontrol->value.integer.value[0], 2379 dbri->mm.data[elem & 3]); 2380 2381 if (changed) { 2382 /* First mute outputs, and wait 1/8000 sec (125 us) 2383 * to make sure this takes. This avoids clicking noises. 2384 */ 2385 cs4215_setdata(dbri, 1); 2386 udelay(125); 2387 cs4215_setdata(dbri, 0); 2388 } 2389 return changed; 2390 } 2391 2392 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control 2393 timeslots. Shift is the bit offset in the timeslot, mask defines the 2394 number of bits. invert is a boolean for use with attenuation. 2395 */ 2396 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \ 2397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 2398 .info = snd_cs4215_info_single, \ 2399 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ 2400 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \ 2401 ((invert) << 24) }, 2402 2403 static const struct snd_kcontrol_new dbri_controls[] = { 2404 { 2405 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2406 .name = "Playback Volume", 2407 .info = snd_cs4215_info_volume, 2408 .get = snd_cs4215_get_volume, 2409 .put = snd_cs4215_put_volume, 2410 .private_value = DBRI_PLAY, 2411 }, 2412 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) 2413 CS4215_SINGLE("Line out switch", 0, 6, 1, 0) 2414 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) 2415 { 2416 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2417 .name = "Capture Volume", 2418 .info = snd_cs4215_info_volume, 2419 .get = snd_cs4215_get_volume, 2420 .put = snd_cs4215_put_volume, 2421 .private_value = DBRI_REC, 2422 }, 2423 /* FIXME: mic/line switch */ 2424 CS4215_SINGLE("Line in switch", 2, 4, 1, 0) 2425 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) 2426 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) 2427 CS4215_SINGLE("Mic boost", 4, 4, 1, 1) 2428 }; 2429 2430 static int snd_dbri_mixer(struct snd_card *card) 2431 { 2432 int idx, err; 2433 struct snd_dbri *dbri; 2434 2435 if (snd_BUG_ON(!card || !card->private_data)) 2436 return -EINVAL; 2437 dbri = card->private_data; 2438 2439 strscpy(card->mixername, card->shortname); 2440 2441 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) { 2442 err = snd_ctl_add(card, 2443 snd_ctl_new1(&dbri_controls[idx], dbri)); 2444 if (err < 0) 2445 return err; 2446 } 2447 2448 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { 2449 dbri->stream_info[idx].left_gain = 0; 2450 dbri->stream_info[idx].right_gain = 0; 2451 } 2452 2453 return 0; 2454 } 2455 2456 /**************************************************************************** 2457 /proc interface 2458 ****************************************************************************/ 2459 static void dbri_regs_read(struct snd_info_entry *entry, 2460 struct snd_info_buffer *buffer) 2461 { 2462 struct snd_dbri *dbri = entry->private_data; 2463 2464 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); 2465 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); 2466 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); 2467 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); 2468 } 2469 2470 #ifdef DBRI_DEBUG 2471 static void dbri_debug_read(struct snd_info_entry *entry, 2472 struct snd_info_buffer *buffer) 2473 { 2474 struct snd_dbri *dbri = entry->private_data; 2475 int pipe; 2476 snd_iprintf(buffer, "debug=%d\n", dbri_debug); 2477 2478 for (pipe = 0; pipe < 32; pipe++) { 2479 if (pipe_active(dbri, pipe)) { 2480 struct dbri_pipe *pptr = &dbri->pipes[pipe]; 2481 snd_iprintf(buffer, 2482 "Pipe %d: %s SDP=0x%x desc=%d, " 2483 "len=%d next %d\n", 2484 pipe, 2485 (pptr->sdp & D_SDP_TO_SER) ? "output" : 2486 "input", 2487 pptr->sdp, pptr->desc, 2488 pptr->length, pptr->nextpipe); 2489 } 2490 } 2491 } 2492 #endif 2493 2494 static void snd_dbri_proc(struct snd_card *card) 2495 { 2496 struct snd_dbri *dbri = card->private_data; 2497 2498 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read); 2499 #ifdef DBRI_DEBUG 2500 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read); 2501 #endif 2502 } 2503 2504 /* 2505 **************************************************************************** 2506 **************************** Initialization ******************************** 2507 **************************************************************************** 2508 */ 2509 static void snd_dbri_free(struct snd_dbri *dbri); 2510 2511 static int snd_dbri_create(struct snd_card *card, 2512 struct platform_device *op, 2513 int irq, int dev) 2514 { 2515 struct snd_dbri *dbri = card->private_data; 2516 int err; 2517 2518 spin_lock_init(&dbri->lock); 2519 dbri->op = op; 2520 dbri->irq = irq; 2521 2522 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma), 2523 &dbri->dma_dvma, GFP_KERNEL); 2524 if (!dbri->dma) 2525 return -ENOMEM; 2526 2527 dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n", 2528 dbri->dma, dbri->dma_dvma); 2529 2530 /* Map the registers into memory. */ 2531 dbri->regs_size = resource_size(&op->resource[0]); 2532 dbri->regs = of_ioremap(&op->resource[0], 0, 2533 dbri->regs_size, "DBRI Registers"); 2534 if (!dbri->regs) { 2535 printk(KERN_ERR "DBRI: could not allocate registers\n"); 2536 dma_free_coherent(&op->dev, sizeof(struct dbri_dma), 2537 (void *)dbri->dma, dbri->dma_dvma); 2538 return -EIO; 2539 } 2540 2541 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED, 2542 "DBRI audio", dbri); 2543 if (err) { 2544 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); 2545 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size); 2546 dma_free_coherent(&op->dev, sizeof(struct dbri_dma), 2547 (void *)dbri->dma, dbri->dma_dvma); 2548 return err; 2549 } 2550 2551 /* Do low level initialization of the DBRI and CS4215 chips */ 2552 dbri_initialize(dbri); 2553 err = cs4215_init(dbri); 2554 if (err) { 2555 snd_dbri_free(dbri); 2556 return err; 2557 } 2558 2559 return 0; 2560 } 2561 2562 static void snd_dbri_free(struct snd_dbri *dbri) 2563 { 2564 dprintk(D_GEN, "snd_dbri_free\n"); 2565 dbri_reset(dbri); 2566 2567 if (dbri->irq) 2568 free_irq(dbri->irq, dbri); 2569 2570 if (dbri->regs) 2571 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size); 2572 2573 if (dbri->dma) 2574 dma_free_coherent(&dbri->op->dev, 2575 sizeof(struct dbri_dma), 2576 (void *)dbri->dma, dbri->dma_dvma); 2577 } 2578 2579 static int dbri_probe(struct platform_device *op) 2580 { 2581 struct snd_dbri *dbri; 2582 struct resource *rp; 2583 struct snd_card *card; 2584 static int dev; 2585 int irq; 2586 int err; 2587 2588 if (dev >= SNDRV_CARDS) 2589 return -ENODEV; 2590 if (!enable[dev]) { 2591 dev++; 2592 return -ENOENT; 2593 } 2594 2595 irq = op->archdata.irqs[0]; 2596 if (irq <= 0) { 2597 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev); 2598 return -ENODEV; 2599 } 2600 2601 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE, 2602 sizeof(struct snd_dbri), &card); 2603 if (err < 0) 2604 return err; 2605 2606 strscpy(card->driver, "DBRI"); 2607 strscpy(card->shortname, "Sun DBRI"); 2608 rp = &op->resource[0]; 2609 sprintf(card->longname, "%s at 0x%02lx:0x%016llx, irq %d", 2610 card->shortname, 2611 rp->flags & 0xffL, (unsigned long long)rp->start, irq); 2612 2613 err = snd_dbri_create(card, op, irq, dev); 2614 if (err < 0) { 2615 snd_card_free(card); 2616 return err; 2617 } 2618 2619 dbri = card->private_data; 2620 err = snd_dbri_pcm(card); 2621 if (err < 0) 2622 goto _err; 2623 2624 err = snd_dbri_mixer(card); 2625 if (err < 0) 2626 goto _err; 2627 2628 /* /proc file handling */ 2629 snd_dbri_proc(card); 2630 dev_set_drvdata(&op->dev, card); 2631 2632 err = snd_card_register(card); 2633 if (err < 0) 2634 goto _err; 2635 2636 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", 2637 dev, dbri->regs, 2638 dbri->irq, op->dev.of_node->name[9], dbri->mm.version); 2639 dev++; 2640 2641 return 0; 2642 2643 _err: 2644 snd_dbri_free(dbri); 2645 snd_card_free(card); 2646 return err; 2647 } 2648 2649 static void dbri_remove(struct platform_device *op) 2650 { 2651 struct snd_card *card = dev_get_drvdata(&op->dev); 2652 2653 snd_dbri_free(card->private_data); 2654 snd_card_free(card); 2655 } 2656 2657 static const struct of_device_id dbri_match[] = { 2658 { 2659 .name = "SUNW,DBRIe", 2660 }, 2661 { 2662 .name = "SUNW,DBRIf", 2663 }, 2664 {}, 2665 }; 2666 2667 MODULE_DEVICE_TABLE(of, dbri_match); 2668 2669 static struct platform_driver dbri_sbus_driver = { 2670 .driver = { 2671 .name = "dbri", 2672 .of_match_table = dbri_match, 2673 }, 2674 .probe = dbri_probe, 2675 .remove = dbri_remove, 2676 }; 2677 2678 module_platform_driver(dbri_sbus_driver); 2679