1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for DBRI sound chip found on Sparcs. 4 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net) 5 * 6 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl) 7 * 8 * Based entirely upon drivers/sbus/audio/dbri.c which is: 9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 10 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) 11 * 12 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO 13 * on Sun SPARCStation 10, 20, LX and Voyager models. 14 * 15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel 16 * data time multiplexer with ISDN support (aka T7259) 17 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. 18 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). 19 * Documentation: 20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from 21 * Sparc Technology Business (courtesy of Sun Support) 22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent 23 * available from the Lucent (formerly AT&T microelectronics) home 24 * page. 25 * - https://www.freesoft.org/Linux/DBRI/ 26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec 27 * Interfaces: CHI, Audio In & Out, 2 bits parallel 28 * Documentation: from the Crystal Semiconductor home page. 29 * 30 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between 31 * memory and a serial device (long pipes, no. 0-15) or between two serial 32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial 33 * device (short pipes). 34 * A timeslot defines the bit-offset and no. of bits read from a serial device. 35 * The timeslots are linked to 6 circular lists, one for each direction for 36 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes 37 * (the second one is a monitor/tee pipe, valid only for serial input). 38 * 39 * The mmcodec is connected via the CHI bus and needs the data & some 40 * parameters (volume, output selection) time multiplexed in 8 byte 41 * chunks. It also has a control mode, which serves for audio format setting. 42 * 43 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on 44 * the same CHI bus, so I thought perhaps it is possible to use the on-board 45 * & the speakerbox codec simultaneously, giving 2 (not very independent :-) 46 * audio devices. But the SUN HW group decided against it, at least on my 47 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly 48 * connected. 49 * 50 * I've tried to stick to the following function naming conventions: 51 * snd_* ALSA stuff 52 * cs4215_* CS4215 codec specific stuff 53 * dbri_* DBRI high-level stuff 54 * other DBRI low-level stuff 55 */ 56 57 #include <linux/interrupt.h> 58 #include <linux/delay.h> 59 #include <linux/irq.h> 60 #include <linux/io.h> 61 #include <linux/dma-mapping.h> 62 #include <linux/gfp.h> 63 #include <linux/string.h> 64 65 #include <sound/core.h> 66 #include <sound/pcm.h> 67 #include <sound/pcm_params.h> 68 #include <sound/info.h> 69 #include <sound/control.h> 70 #include <sound/initval.h> 71 72 #include <linux/of.h> 73 #include <linux/platform_device.h> 74 #include <linux/atomic.h> 75 #include <linux/module.h> 76 77 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); 78 MODULE_DESCRIPTION("Sun DBRI"); 79 MODULE_LICENSE("GPL"); 80 81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 82 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 83 /* Enable this card */ 84 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 85 86 module_param_array(index, int, NULL, 0444); 87 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); 88 module_param_array(id, charp, NULL, 0444); 89 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); 90 module_param_array(enable, bool, NULL, 0444); 91 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); 92 93 #undef DBRI_DEBUG 94 95 #define D_INT (1<<0) 96 #define D_GEN (1<<1) 97 #define D_CMD (1<<2) 98 #define D_MM (1<<3) 99 #define D_USR (1<<4) 100 #define D_DESC (1<<5) 101 102 static int dbri_debug; 103 module_param(dbri_debug, int, 0644); 104 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); 105 106 #ifdef DBRI_DEBUG 107 static const char * const cmds[] = { 108 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", 109 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" 110 }; 111 112 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x) 113 114 #else 115 #define dprintk(a, x...) do { } while (0) 116 117 #endif /* DBRI_DEBUG */ 118 119 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ 120 (intr << 27) | \ 121 value) 122 123 /*************************************************************************** 124 CS4215 specific definitions and structures 125 ****************************************************************************/ 126 127 struct cs4215 { 128 __u8 data[4]; /* Data mode: Time slots 5-8 */ 129 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ 130 __u8 onboard; 131 __u8 offset; /* Bit offset from frame sync to time slot 1 */ 132 volatile __u32 status; 133 volatile __u32 version; 134 __u8 precision; /* In bits, either 8 or 16 */ 135 __u8 channels; /* 1 or 2 */ 136 }; 137 138 /* 139 * Control mode first 140 */ 141 142 /* Time Slot 1, Status register */ 143 #define CS4215_CLB (1<<2) /* Control Latch Bit */ 144 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ 145 /* 0: line: 2.8V, speaker 8V */ 146 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ 147 #define CS4215_RSRVD_1 (1<<5) 148 149 /* Time Slot 2, Data Format Register */ 150 #define CS4215_DFR_LINEAR16 0 151 #define CS4215_DFR_ULAW 1 152 #define CS4215_DFR_ALAW 2 153 #define CS4215_DFR_LINEAR8 3 154 #define CS4215_DFR_STEREO (1<<2) 155 static struct { 156 unsigned short freq; 157 unsigned char xtal; 158 unsigned char csval; 159 } CS4215_FREQ[] = { 160 { 8000, (1 << 4), (0 << 3) }, 161 { 16000, (1 << 4), (1 << 3) }, 162 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ 163 { 32000, (1 << 4), (3 << 3) }, 164 /* { NA, (1 << 4), (4 << 3) }, */ 165 /* { NA, (1 << 4), (5 << 3) }, */ 166 { 48000, (1 << 4), (6 << 3) }, 167 { 9600, (1 << 4), (7 << 3) }, 168 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ 169 { 11025, (2 << 4), (1 << 3) }, 170 { 18900, (2 << 4), (2 << 3) }, 171 { 22050, (2 << 4), (3 << 3) }, 172 { 37800, (2 << 4), (4 << 3) }, 173 { 44100, (2 << 4), (5 << 3) }, 174 { 33075, (2 << 4), (6 << 3) }, 175 { 6615, (2 << 4), (7 << 3) }, 176 { 0, 0, 0} 177 }; 178 179 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ 180 181 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ 182 183 /* Time Slot 3, Serial Port Control register */ 184 #define CS4215_XEN (1<<0) /* 0: Enable serial output */ 185 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ 186 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ 187 #define CS4215_BSEL_128 (1<<2) 188 #define CS4215_BSEL_256 (2<<2) 189 #define CS4215_MCK_MAST (0<<4) /* Master clock */ 190 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ 191 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ 192 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ 193 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ 194 195 /* Time Slot 4, Test Register */ 196 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ 197 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */ 198 199 /* Time Slot 5, Parallel Port Register */ 200 /* Read only here and the same as the in data mode */ 201 202 /* Time Slot 6, Reserved */ 203 204 /* Time Slot 7, Version Register */ 205 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ 206 207 /* Time Slot 8, Reserved */ 208 209 /* 210 * Data mode 211 */ 212 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ 213 214 /* Time Slot 5, Output Setting */ 215 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ 216 #define CS4215_LE (1<<6) /* Line Out Enable */ 217 #define CS4215_HE (1<<7) /* Headphone Enable */ 218 219 /* Time Slot 6, Output Setting */ 220 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ 221 #define CS4215_SE (1<<6) /* Speaker Enable */ 222 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ 223 224 /* Time Slot 7, Input Setting */ 225 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ 226 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ 227 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */ 228 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ 229 #define CS4215_PIO1 (1<<7) 230 231 /* Time Slot 8, Input Setting */ 232 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ 233 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ 234 235 /*************************************************************************** 236 DBRI specific definitions and structures 237 ****************************************************************************/ 238 239 /* DBRI main registers */ 240 #define REG0 0x00 /* Status and Control */ 241 #define REG1 0x04 /* Mode and Interrupt */ 242 #define REG2 0x08 /* Parallel IO */ 243 #define REG3 0x0c /* Test */ 244 #define REG8 0x20 /* Command Queue Pointer */ 245 #define REG9 0x24 /* Interrupt Queue Pointer */ 246 247 #define DBRI_NO_CMDS 64 248 #define DBRI_INT_BLK 64 249 #define DBRI_NO_DESCS 64 250 #define DBRI_NO_PIPES 32 251 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) 252 253 #define DBRI_REC 0 254 #define DBRI_PLAY 1 255 #define DBRI_NO_STREAMS 2 256 257 /* One transmit/receive descriptor */ 258 /* When ba != 0 descriptor is used */ 259 struct dbri_mem { 260 volatile __u32 word1; 261 __u32 ba; /* Transmit/Receive Buffer Address */ 262 __u32 nda; /* Next Descriptor Address */ 263 volatile __u32 word4; 264 }; 265 266 /* This structure is in a DMA region where it can accessed by both 267 * the CPU and the DBRI 268 */ 269 struct dbri_dma { 270 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ 271 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */ 272 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ 273 }; 274 275 #define dbri_dma_off(member, elem) \ 276 ((u32)(unsigned long) \ 277 (&(((struct dbri_dma *)0)->member[elem]))) 278 279 enum in_or_out { PIPEinput, PIPEoutput }; 280 281 struct dbri_pipe { 282 u32 sdp; /* SDP command word */ 283 int nextpipe; /* Next pipe in linked list */ 284 int length; /* Length of timeslot (bits) */ 285 int first_desc; /* Index of first descriptor */ 286 int desc; /* Index of active descriptor */ 287 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ 288 }; 289 290 /* Per stream (playback or record) information */ 291 struct dbri_streaminfo { 292 struct snd_pcm_substream *substream; 293 u32 dvma_buffer; /* Device view of ALSA DMA buffer */ 294 int size; /* Size of DMA buffer */ 295 size_t offset; /* offset in user buffer */ 296 int pipe; /* Data pipe used */ 297 int left_gain; /* mixer elements */ 298 int right_gain; 299 }; 300 301 /* This structure holds the information for both chips (DBRI & CS4215) */ 302 struct snd_dbri { 303 int regs_size, irq; /* Needed for unload */ 304 struct platform_device *op; /* OF device info */ 305 spinlock_t lock; 306 307 struct dbri_dma *dma; /* Pointer to our DMA block */ 308 dma_addr_t dma_dvma; /* DBRI visible DMA address */ 309 310 void __iomem *regs; /* dbri HW regs */ 311 int dbri_irqp; /* intr queue pointer */ 312 313 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ 314 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */ 315 spinlock_t cmdlock; /* Protects cmd queue accesses */ 316 s32 *cmdptr; /* Pointer to the last queued cmd */ 317 318 int chi_bpf; 319 320 struct cs4215 mm; /* mmcodec special info */ 321 /* per stream (playback/record) info */ 322 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; 323 }; 324 325 #define DBRI_MAX_VOLUME 63 /* Output volume */ 326 #define DBRI_MAX_GAIN 15 /* Input gain */ 327 328 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */ 329 #define D_P (1<<15) /* Program command & queue pointer valid */ 330 #define D_G (1<<14) /* Allow 4-Word SBus Burst */ 331 #define D_S (1<<13) /* Allow 16-Word SBus Burst */ 332 #define D_E (1<<12) /* Allow 8-Word SBus Burst */ 333 #define D_X (1<<7) /* Sanity Timer Disable */ 334 #define D_T (1<<6) /* Permit activation of the TE interface */ 335 #define D_N (1<<5) /* Permit activation of the NT interface */ 336 #define D_C (1<<4) /* Permit activation of the CHI interface */ 337 #define D_F (1<<3) /* Force Sanity Timer Time-Out */ 338 #define D_D (1<<2) /* Disable Master Mode */ 339 #define D_H (1<<1) /* Halt for Analysis */ 340 #define D_R (1<<0) /* Soft Reset */ 341 342 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ 343 #define D_LITTLE_END (1<<8) /* Byte Order */ 344 #define D_BIG_END (0<<8) /* Byte Order */ 345 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */ 346 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */ 347 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */ 348 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */ 349 #define D_IR (1<<0) /* Interrupt Indicator (read only) */ 350 351 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ 352 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ 353 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ 354 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ 355 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ 356 #define D_ENPIO (0xf0) /* Enable all the pins */ 357 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ 358 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ 359 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ 360 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ 361 362 /* DBRI Commands (Page 20) */ 363 #define D_WAIT 0x0 /* Stop execution */ 364 #define D_PAUSE 0x1 /* Flush long pipes */ 365 #define D_JUMP 0x2 /* New command queue */ 366 #define D_IIQ 0x3 /* Initialize Interrupt Queue */ 367 #define D_REX 0x4 /* Report command execution via interrupt */ 368 #define D_SDP 0x5 /* Setup Data Pipe */ 369 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ 370 #define D_DTS 0x7 /* Define Time Slot */ 371 #define D_SSP 0x8 /* Set short Data Pipe */ 372 #define D_CHI 0x9 /* Set CHI Global Mode */ 373 #define D_NT 0xa /* NT Command */ 374 #define D_TE 0xb /* TE Command */ 375 #define D_CDEC 0xc /* Codec setup */ 376 #define D_TEST 0xd /* No comment */ 377 #define D_CDM 0xe /* CHI Data mode command */ 378 379 /* Special bits for some commands */ 380 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */ 381 382 /* Setup Data Pipe */ 383 /* IRM */ 384 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */ 385 #define D_SDP_CHANGE (2<<18) /* Report any changes */ 386 #define D_SDP_EVERY (3<<18) /* Report any changes */ 387 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ 388 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ 389 390 /* Pipe data MODE */ 391 #define D_SDP_MEM (0<<13) /* To/from memory */ 392 #define D_SDP_HDLC (2<<13) 393 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ 394 #define D_SDP_SER (4<<13) /* Serial to serial */ 395 #define D_SDP_FIXED (6<<13) /* Short only */ 396 #define D_SDP_MODE(v) ((v)&(7<<13)) 397 398 #define D_SDP_TO_SER (1<<12) /* Direction */ 399 #define D_SDP_FROM_SER (0<<12) /* Direction */ 400 #define D_SDP_MSB (1<<11) /* Bit order within Byte */ 401 #define D_SDP_LSB (0<<11) /* Bit order within Byte */ 402 #define D_SDP_P (1<<10) /* Pointer Valid */ 403 #define D_SDP_A (1<<8) /* Abort */ 404 #define D_SDP_C (1<<7) /* Clear */ 405 406 /* Define Time Slot */ 407 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ 408 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ 409 #define D_DTS_INS (1<<15) /* Insert Time Slot */ 410 #define D_DTS_DEL (0<<15) /* Delete Time Slot */ 411 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ 412 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ 413 414 /* Time Slot defines */ 415 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ 416 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ 417 #define D_TS_DI (1<<13) /* Data Invert */ 418 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ 419 #define D_TS_MONITOR (2<<10) /* Monitor pipe */ 420 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ 421 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ 422 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ 423 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */ 424 425 /* Concentration Highway Interface Modes */ 426 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ 427 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ 428 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ 429 #define D_CHI_OD (1<<13) /* Open Drain Enable */ 430 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ 431 #define D_CHI_FD (1<<11) /* Frame Drive */ 432 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ 433 434 /* NT: These are here for completeness */ 435 #define D_NT_FBIT (1<<17) /* Frame Bit */ 436 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ 437 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ 438 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ 439 #define D_NT_ISNT (1<<13) /* Configure interface as NT */ 440 #define D_NT_FT (1<<12) /* Fixed Timing */ 441 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ 442 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ 443 #define D_NT_ACT (1<<9) /* Activate Interface */ 444 #define D_NT_MFE (1<<8) /* Multiframe Enable */ 445 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ 446 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ 447 #define D_NT_FACT (1<<1) /* Force Activation */ 448 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ 449 450 /* Codec Setup */ 451 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ 452 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ 453 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ 454 455 /* Test */ 456 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ 457 #define D_TEST_SIZE(v) ((v)<<11) /* */ 458 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ 459 #define D_TEST_PROC 0x6 /* Microprocessor test */ 460 #define D_TEST_SER 0x7 /* Serial-Controller test */ 461 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ 462 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ 463 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ 464 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ 465 #define D_TEST_DUMP 0xe /* ROM Dump */ 466 467 /* CHI Data Mode */ 468 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */ 469 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */ 470 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */ 471 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */ 472 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */ 473 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */ 474 475 /* The Interrupts */ 476 #define D_INTR_BRDY 1 /* Buffer Ready for processing */ 477 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ 478 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ 479 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ 480 #define D_INTR_EOL 5 /* End of List */ 481 #define D_INTR_CMDI 6 /* Command has bean read */ 482 #define D_INTR_XCMP 8 /* Transmission of frame complete */ 483 #define D_INTR_SBRI 9 /* BRI status change info */ 484 #define D_INTR_FXDT 10 /* Fixed data change */ 485 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ 486 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ 487 #define D_INTR_DBYT 12 /* Dropped by frame slip */ 488 #define D_INTR_RBYT 13 /* Repeated by frame slip */ 489 #define D_INTR_LINT 14 /* Lost Interrupt */ 490 #define D_INTR_UNDR 15 /* DMA underrun */ 491 492 #define D_INTR_TE 32 493 #define D_INTR_NT 34 494 #define D_INTR_CHI 36 495 #define D_INTR_CMD 38 496 497 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) 498 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf) 499 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf) 500 #define D_INTR_GETVAL(v) ((v) & 0xffff) 501 #define D_INTR_GETRVAL(v) ((v) & 0xfffff) 502 503 #define D_P_0 0 /* TE receive anchor */ 504 #define D_P_1 1 /* TE transmit anchor */ 505 #define D_P_2 2 /* NT transmit anchor */ 506 #define D_P_3 3 /* NT receive anchor */ 507 #define D_P_4 4 /* CHI send data */ 508 #define D_P_5 5 /* CHI receive data */ 509 #define D_P_6 6 /* */ 510 #define D_P_7 7 /* */ 511 #define D_P_8 8 /* */ 512 #define D_P_9 9 /* */ 513 #define D_P_10 10 /* */ 514 #define D_P_11 11 /* */ 515 #define D_P_12 12 /* */ 516 #define D_P_13 13 /* */ 517 #define D_P_14 14 /* */ 518 #define D_P_15 15 /* */ 519 #define D_P_16 16 /* CHI anchor pipe */ 520 #define D_P_17 17 /* CHI send */ 521 #define D_P_18 18 /* CHI receive */ 522 #define D_P_19 19 /* CHI receive */ 523 #define D_P_20 20 /* CHI receive */ 524 #define D_P_21 21 /* */ 525 #define D_P_22 22 /* */ 526 #define D_P_23 23 /* */ 527 #define D_P_24 24 /* */ 528 #define D_P_25 25 /* */ 529 #define D_P_26 26 /* */ 530 #define D_P_27 27 /* */ 531 #define D_P_28 28 /* */ 532 #define D_P_29 29 /* */ 533 #define D_P_30 30 /* */ 534 #define D_P_31 31 /* */ 535 536 /* Transmit descriptor defines */ 537 #define DBRI_TD_F (1 << 31) /* End of Frame */ 538 #define DBRI_TD_D (1 << 30) /* Do not append CRC */ 539 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */ 540 #define DBRI_TD_B (1 << 15) /* Final interrupt */ 541 #define DBRI_TD_M (1 << 14) /* Marker interrupt */ 542 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */ 543 #define DBRI_TD_FCNT(v) (v) /* Flag Count */ 544 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */ 545 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */ 546 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */ 547 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */ 548 /* Maximum buffer size per TD: almost 8KB */ 549 #define DBRI_TD_MAXCNT ((1 << 13) - 4) 550 551 /* Receive descriptor defines */ 552 #define DBRI_RD_F (1 << 31) /* End of Frame */ 553 #define DBRI_RD_C (1 << 30) /* Completed buffer */ 554 #define DBRI_RD_B (1 << 15) /* Final interrupt */ 555 #define DBRI_RD_M (1 << 14) /* Marker interrupt */ 556 #define DBRI_RD_BCNT(v) (v) /* Buffer size */ 557 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */ 558 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */ 559 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */ 560 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */ 561 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */ 562 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */ 563 564 /* stream_info[] access */ 565 /* Translate the ALSA direction into the array index */ 566 #define DBRI_STREAMNO(substream) \ 567 (substream->stream == \ 568 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC) 569 570 /* Return a pointer to dbri_streaminfo */ 571 #define DBRI_STREAM(dbri, substream) \ 572 &dbri->stream_info[DBRI_STREAMNO(substream)] 573 574 /* 575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. 576 * So we have to reverse the bits. Note: not all bit lengths are supported 577 */ 578 static __u32 reverse_bytes(__u32 b, int len) 579 { 580 switch (len) { 581 case 32: 582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 583 fallthrough; 584 case 16: 585 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 586 fallthrough; 587 case 8: 588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 589 fallthrough; 590 case 4: 591 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 592 fallthrough; 593 case 2: 594 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 595 case 1: 596 case 0: 597 break; 598 default: 599 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); 600 } 601 602 return b; 603 } 604 605 /* 606 **************************************************************************** 607 ************** DBRI initialization and command synchronization ************* 608 **************************************************************************** 609 610 Commands are sent to the DBRI by building a list of them in memory, 611 then writing the address of the first list item to DBRI register 8. 612 The list is terminated with a WAIT command, which generates a 613 CPU interrupt to signal completion. 614 615 Since the DBRI can run in parallel with the CPU, several means of 616 synchronization present themselves. The method implemented here uses 617 the dbri_cmdwait() to wait for execution of batch of sent commands. 618 619 A circular command buffer is used here. A new command is being added 620 while another can be executed. The scheme works by adding two WAIT commands 621 after each sent batch of commands. When the next batch is prepared it is 622 added after the WAIT commands then the WAITs are replaced with single JUMP 623 command to the new batch. Then the DBRI is forced to reread the last WAIT 624 command (replaced by the JUMP by then). If the DBRI is still executing 625 previous commands the request to reread the WAIT command is ignored. 626 627 Every time a routine wants to write commands to the DBRI, it must 628 first call dbri_cmdlock() and get pointer to a free space in 629 dbri->dma->cmd buffer. After this, the commands can be written to 630 the buffer, and dbri_cmdsend() is called with the final pointer value 631 to send them to the DBRI. 632 633 */ 634 635 #define MAXLOOPS 20 636 /* 637 * Wait for the current command string to execute 638 */ 639 static void dbri_cmdwait(struct snd_dbri *dbri) 640 { 641 int maxloops = MAXLOOPS; 642 unsigned long flags; 643 644 /* Delay if previous commands are still being processed */ 645 spin_lock_irqsave(&dbri->lock, flags); 646 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) { 647 spin_unlock_irqrestore(&dbri->lock, flags); 648 msleep_interruptible(1); 649 spin_lock_irqsave(&dbri->lock, flags); 650 } 651 spin_unlock_irqrestore(&dbri->lock, flags); 652 653 if (maxloops == 0) 654 printk(KERN_ERR "DBRI: Chip never completed command buffer\n"); 655 else 656 dprintk(D_CMD, "Chip completed command buffer (%d)\n", 657 MAXLOOPS - maxloops - 1); 658 } 659 /* 660 * Lock the command queue and return pointer to space for len cmd words 661 * It locks the cmdlock spinlock. 662 */ 663 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len) 664 { 665 u32 dvma_addr = (u32)dbri->dma_dvma; 666 667 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */ 668 len += 2; 669 spin_lock(&dbri->cmdlock); 670 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2) 671 return dbri->cmdptr + 2; 672 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr) 673 return dbri->dma->cmd; 674 else 675 printk(KERN_ERR "DBRI: no space for commands."); 676 677 return NULL; 678 } 679 680 /* 681 * Send prepared cmd string. It works by writing a JUMP cmd into 682 * the last WAIT cmd and force DBRI to reread the cmd. 683 * The JUMP cmd points to the new cmd string. 684 * It also releases the cmdlock spinlock. 685 * 686 * Lock must be held before calling this. 687 */ 688 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len) 689 { 690 u32 dvma_addr = (u32)dbri->dma_dvma; 691 s32 tmp, addr; 692 static int wait_id; 693 694 wait_id++; 695 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */ 696 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id); 697 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id); 698 699 /* Replace the last command with JUMP */ 700 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32); 701 *(dbri->cmdptr+1) = addr; 702 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0); 703 704 #ifdef DBRI_DEBUG 705 if (cmd > dbri->cmdptr) { 706 s32 *ptr; 707 708 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++) 709 dprintk(D_CMD, "cmd: %lx:%08x\n", 710 (unsigned long)ptr, *ptr); 711 } else { 712 s32 *ptr = dbri->cmdptr; 713 714 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 715 ptr++; 716 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 717 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) 718 dprintk(D_CMD, "cmd: %lx:%08x\n", 719 (unsigned long)ptr, *ptr); 720 } 721 #endif 722 723 /* Reread the last command */ 724 tmp = sbus_readl(dbri->regs + REG0); 725 tmp |= D_P; 726 sbus_writel(tmp, dbri->regs + REG0); 727 728 dbri->cmdptr = cmd; 729 spin_unlock(&dbri->cmdlock); 730 } 731 732 /* Lock must be held when calling this */ 733 static void dbri_reset(struct snd_dbri *dbri) 734 { 735 int i; 736 u32 tmp; 737 738 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", 739 sbus_readl(dbri->regs + REG0), 740 sbus_readl(dbri->regs + REG2), 741 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); 742 743 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ 744 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) 745 udelay(10); 746 747 /* A brute approach - DBRI falls back to working burst size by itself 748 * On SS20 D_S does not work, so do not try so high. */ 749 tmp = sbus_readl(dbri->regs + REG0); 750 tmp |= D_G | D_E; 751 tmp &= ~D_S; 752 sbus_writel(tmp, dbri->regs + REG0); 753 } 754 755 /* Lock must not be held before calling this */ 756 static void dbri_initialize(struct snd_dbri *dbri) 757 { 758 u32 dvma_addr = (u32)dbri->dma_dvma; 759 s32 *cmd; 760 u32 dma_addr; 761 int n; 762 763 scoped_guard(spinlock_irqsave, &dbri->lock) { 764 dbri_reset(dbri); 765 766 /* Initialize pipes */ 767 for (n = 0; n < DBRI_NO_PIPES; n++) 768 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; 769 770 spin_lock_init(&dbri->cmdlock); 771 /* 772 * Initialize the interrupt ring buffer. 773 */ 774 dma_addr = dvma_addr + dbri_dma_off(intr, 0); 775 dbri->dma->intr[0] = dma_addr; 776 dbri->dbri_irqp = 1; 777 /* 778 * Set up the interrupt queue 779 */ 780 scoped_guard(spinlock, &dbri->cmdlock) { 781 cmd = dbri->cmdptr = dbri->dma->cmd; 782 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); 783 *(cmd++) = dma_addr; 784 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 785 dbri->cmdptr = cmd; 786 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 787 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); 788 dma_addr = dvma_addr + dbri_dma_off(cmd, 0); 789 sbus_writel(dma_addr, dbri->regs + REG8); 790 } 791 } 792 793 dbri_cmdwait(dbri); 794 } 795 796 /* 797 **************************************************************************** 798 ************************** DBRI data pipe management *********************** 799 **************************************************************************** 800 801 While DBRI control functions use the command and interrupt buffers, the 802 main data path takes the form of data pipes, which can be short (command 803 and interrupt driven), or long (attached to DMA buffers). These functions 804 provide a rudimentary means of setting up and managing the DBRI's pipes, 805 but the calling functions have to make sure they respect the pipes' linked 806 list ordering, among other things. The transmit and receive functions 807 here interface closely with the transmit and receive interrupt code. 808 809 */ 810 static inline int pipe_active(struct snd_dbri *dbri, int pipe) 811 { 812 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); 813 } 814 815 /* reset_pipe(dbri, pipe) 816 * 817 * Called on an in-use pipe to clear anything being transmitted or received 818 * Lock must be held before calling this. 819 */ 820 static void reset_pipe(struct snd_dbri *dbri, int pipe) 821 { 822 int sdp; 823 int desc; 824 s32 *cmd; 825 826 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 827 printk(KERN_ERR "DBRI: reset_pipe called with " 828 "illegal pipe number\n"); 829 return; 830 } 831 832 sdp = dbri->pipes[pipe].sdp; 833 if (sdp == 0) { 834 printk(KERN_ERR "DBRI: reset_pipe called " 835 "on uninitialized pipe\n"); 836 return; 837 } 838 839 cmd = dbri_cmdlock(dbri, 3); 840 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); 841 *(cmd++) = 0; 842 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 843 dbri_cmdsend(dbri, cmd, 3); 844 845 desc = dbri->pipes[pipe].first_desc; 846 if (desc >= 0) 847 do { 848 dbri->dma->desc[desc].ba = 0; 849 dbri->dma->desc[desc].nda = 0; 850 desc = dbri->next_desc[desc]; 851 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); 852 853 dbri->pipes[pipe].desc = -1; 854 dbri->pipes[pipe].first_desc = -1; 855 } 856 857 /* 858 * Lock must be held before calling this. 859 */ 860 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp) 861 { 862 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 863 printk(KERN_ERR "DBRI: setup_pipe called " 864 "with illegal pipe number\n"); 865 return; 866 } 867 868 if ((sdp & 0xf800) != sdp) { 869 printk(KERN_ERR "DBRI: setup_pipe called " 870 "with strange SDP value\n"); 871 /* sdp &= 0xf800; */ 872 } 873 874 /* If this is a fixed receive pipe, arrange for an interrupt 875 * every time its data changes 876 */ 877 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) 878 sdp |= D_SDP_CHANGE; 879 880 sdp |= D_PIPE(pipe); 881 dbri->pipes[pipe].sdp = sdp; 882 dbri->pipes[pipe].desc = -1; 883 dbri->pipes[pipe].first_desc = -1; 884 885 reset_pipe(dbri, pipe); 886 } 887 888 /* 889 * Lock must be held before calling this. 890 */ 891 static void link_time_slot(struct snd_dbri *dbri, int pipe, 892 int prevpipe, int nextpipe, 893 int length, int cycle) 894 { 895 s32 *cmd; 896 int val; 897 898 if (pipe < 0 || pipe > DBRI_MAX_PIPE 899 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE 900 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { 901 printk(KERN_ERR 902 "DBRI: link_time_slot called with illegal pipe number\n"); 903 return; 904 } 905 906 if (dbri->pipes[pipe].sdp == 0 907 || dbri->pipes[prevpipe].sdp == 0 908 || dbri->pipes[nextpipe].sdp == 0) { 909 printk(KERN_ERR "DBRI: link_time_slot called " 910 "on uninitialized pipe\n"); 911 return; 912 } 913 914 dbri->pipes[prevpipe].nextpipe = pipe; 915 dbri->pipes[pipe].nextpipe = nextpipe; 916 dbri->pipes[pipe].length = length; 917 918 cmd = dbri_cmdlock(dbri, 4); 919 920 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 921 /* Deal with CHI special case: 922 * "If transmission on edges 0 or 1 is desired, then cycle n 923 * (where n = # of bit times per frame...) must be used." 924 * - DBRI data sheet, page 11 925 */ 926 if (prevpipe == 16 && cycle == 0) 927 cycle = dbri->chi_bpf; 928 929 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; 930 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 931 *(cmd++) = 0; 932 *(cmd++) = 933 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 934 } else { 935 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; 936 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 937 *(cmd++) = 938 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 939 *(cmd++) = 0; 940 } 941 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 942 943 dbri_cmdsend(dbri, cmd, 4); 944 } 945 946 #if 0 947 /* 948 * Lock must be held before calling this. 949 */ 950 static void unlink_time_slot(struct snd_dbri *dbri, int pipe, 951 enum in_or_out direction, int prevpipe, 952 int nextpipe) 953 { 954 s32 *cmd; 955 int val; 956 957 if (pipe < 0 || pipe > DBRI_MAX_PIPE 958 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE 959 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { 960 printk(KERN_ERR 961 "DBRI: unlink_time_slot called with illegal pipe number\n"); 962 return; 963 } 964 965 cmd = dbri_cmdlock(dbri, 4); 966 967 if (direction == PIPEinput) { 968 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; 969 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 970 *(cmd++) = D_TS_NEXT(nextpipe); 971 *(cmd++) = 0; 972 } else { 973 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; 974 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 975 *(cmd++) = 0; 976 *(cmd++) = D_TS_NEXT(nextpipe); 977 } 978 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 979 980 dbri_cmdsend(dbri, cmd, 4); 981 } 982 #endif 983 984 /* xmit_fixed() / recv_fixed() 985 * 986 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not 987 * expected to change much, and which we don't need to buffer. 988 * The DBRI only interrupts us when the data changes (receive pipes), 989 * or only changes the data when this function is called (transmit pipes). 990 * Only short pipes (numbers 16-31) can be used in fixed data mode. 991 * 992 * These function operate on a 32-bit field, no matter how large 993 * the actual time slot is. The interrupt handler takes care of bit 994 * ordering and alignment. An 8-bit time slot will always end up 995 * in the low-order 8 bits, filled either MSB-first or LSB-first, 996 * depending on the settings passed to setup_pipe(). 997 * 998 * Lock must not be held before calling it. 999 */ 1000 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data) 1001 { 1002 s32 *cmd; 1003 1004 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 1005 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n"); 1006 return; 1007 } 1008 1009 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { 1010 printk(KERN_ERR "DBRI: xmit_fixed: " 1011 "Uninitialized pipe %d\n", pipe); 1012 return; 1013 } 1014 1015 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1016 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); 1017 return; 1018 } 1019 1020 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { 1021 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", 1022 pipe); 1023 return; 1024 } 1025 1026 /* DBRI short pipes always transmit LSB first */ 1027 1028 if (dbri->pipes[pipe].sdp & D_SDP_MSB) 1029 data = reverse_bytes(data, dbri->pipes[pipe].length); 1030 1031 cmd = dbri_cmdlock(dbri, 3); 1032 1033 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); 1034 *(cmd++) = data; 1035 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1036 1037 scoped_guard(spinlock_irqsave, &dbri->lock) { 1038 dbri_cmdsend(dbri, cmd, 3); 1039 } 1040 1041 dbri_cmdwait(dbri); 1042 1043 } 1044 1045 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr) 1046 { 1047 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 1048 printk(KERN_ERR "DBRI: recv_fixed called with " 1049 "illegal pipe number\n"); 1050 return; 1051 } 1052 1053 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1054 printk(KERN_ERR "DBRI: recv_fixed called on " 1055 "non-fixed pipe %d\n", pipe); 1056 return; 1057 } 1058 1059 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 1060 printk(KERN_ERR "DBRI: recv_fixed called on " 1061 "transmit pipe %d\n", pipe); 1062 return; 1063 } 1064 1065 dbri->pipes[pipe].recv_fixed_ptr = ptr; 1066 } 1067 1068 /* setup_descs() 1069 * 1070 * Setup transmit/receive data on a "long" pipe - i.e, one associated 1071 * with a DMA buffer. 1072 * 1073 * Only pipe numbers 0-15 can be used in this mode. 1074 * 1075 * This function takes a stream number pointing to a data buffer, 1076 * and work by building chains of descriptors which identify the 1077 * data buffers. Buffers too large for a single descriptor will 1078 * be spread across multiple descriptors. 1079 * 1080 * All descriptors create a ring buffer. 1081 * 1082 * Lock must be held before calling this. 1083 */ 1084 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period) 1085 { 1086 struct dbri_streaminfo *info = &dbri->stream_info[streamno]; 1087 u32 dvma_addr = (u32)dbri->dma_dvma; 1088 __u32 dvma_buffer; 1089 int desc; 1090 int len; 1091 int first_desc = -1; 1092 int last_desc = -1; 1093 1094 if (info->pipe < 0 || info->pipe > 15) { 1095 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n"); 1096 return -2; 1097 } 1098 1099 if (dbri->pipes[info->pipe].sdp == 0) { 1100 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n", 1101 info->pipe); 1102 return -2; 1103 } 1104 1105 dvma_buffer = info->dvma_buffer; 1106 len = info->size; 1107 1108 if (streamno == DBRI_PLAY) { 1109 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { 1110 printk(KERN_ERR "DBRI: setup_descs: " 1111 "Called on receive pipe %d\n", info->pipe); 1112 return -2; 1113 } 1114 } else { 1115 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { 1116 printk(KERN_ERR 1117 "DBRI: setup_descs: Called on transmit pipe %d\n", 1118 info->pipe); 1119 return -2; 1120 } 1121 /* Should be able to queue multiple buffers 1122 * to receive on a pipe 1123 */ 1124 if (pipe_active(dbri, info->pipe)) { 1125 printk(KERN_ERR "DBRI: recv_on_pipe: " 1126 "Called on active pipe %d\n", info->pipe); 1127 return -2; 1128 } 1129 1130 /* Make sure buffer size is multiple of four */ 1131 len &= ~3; 1132 } 1133 1134 /* Free descriptors if pipe has any */ 1135 desc = dbri->pipes[info->pipe].first_desc; 1136 if (desc >= 0) 1137 do { 1138 dbri->dma->desc[desc].ba = 0; 1139 dbri->dma->desc[desc].nda = 0; 1140 desc = dbri->next_desc[desc]; 1141 } while (desc != -1 && 1142 desc != dbri->pipes[info->pipe].first_desc); 1143 1144 dbri->pipes[info->pipe].desc = -1; 1145 dbri->pipes[info->pipe].first_desc = -1; 1146 1147 desc = 0; 1148 while (len > 0) { 1149 int mylen; 1150 1151 for (; desc < DBRI_NO_DESCS; desc++) { 1152 if (!dbri->dma->desc[desc].ba) 1153 break; 1154 } 1155 1156 if (desc == DBRI_NO_DESCS) { 1157 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n"); 1158 return -1; 1159 } 1160 1161 if (len > DBRI_TD_MAXCNT) 1162 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */ 1163 else 1164 mylen = len; 1165 1166 if (mylen > period) 1167 mylen = period; 1168 1169 dbri->next_desc[desc] = -1; 1170 dbri->dma->desc[desc].ba = dvma_buffer; 1171 dbri->dma->desc[desc].nda = 0; 1172 1173 if (streamno == DBRI_PLAY) { 1174 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); 1175 dbri->dma->desc[desc].word4 = 0; 1176 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B; 1177 } else { 1178 dbri->dma->desc[desc].word1 = 0; 1179 dbri->dma->desc[desc].word4 = 1180 DBRI_RD_B | DBRI_RD_BCNT(mylen); 1181 } 1182 1183 if (first_desc == -1) 1184 first_desc = desc; 1185 else { 1186 dbri->next_desc[last_desc] = desc; 1187 dbri->dma->desc[last_desc].nda = 1188 dvma_addr + dbri_dma_off(desc, desc); 1189 } 1190 1191 last_desc = desc; 1192 dvma_buffer += mylen; 1193 len -= mylen; 1194 } 1195 1196 if (first_desc == -1 || last_desc == -1) { 1197 printk(KERN_ERR "DBRI: setup_descs: " 1198 " Not enough descriptors available\n"); 1199 return -1; 1200 } 1201 1202 dbri->dma->desc[last_desc].nda = 1203 dvma_addr + dbri_dma_off(desc, first_desc); 1204 dbri->next_desc[last_desc] = first_desc; 1205 dbri->pipes[info->pipe].first_desc = first_desc; 1206 dbri->pipes[info->pipe].desc = first_desc; 1207 1208 #ifdef DBRI_DEBUG 1209 for (desc = first_desc; desc != -1;) { 1210 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", 1211 desc, 1212 dbri->dma->desc[desc].word1, 1213 dbri->dma->desc[desc].ba, 1214 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); 1215 desc = dbri->next_desc[desc]; 1216 if (desc == first_desc) 1217 break; 1218 } 1219 #endif 1220 return 0; 1221 } 1222 1223 /* 1224 **************************************************************************** 1225 ************************** DBRI - CHI interface **************************** 1226 **************************************************************************** 1227 1228 The CHI is a four-wire (clock, frame sync, data in, data out) time-division 1229 multiplexed serial interface which the DBRI can operate in either master 1230 (give clock/frame sync) or slave (take clock/frame sync) mode. 1231 1232 */ 1233 1234 enum master_or_slave { CHImaster, CHIslave }; 1235 1236 /* 1237 * Lock must not be held before calling it. 1238 */ 1239 static void reset_chi(struct snd_dbri *dbri, 1240 enum master_or_slave master_or_slave, 1241 int bits_per_frame) 1242 { 1243 s32 *cmd; 1244 int val; 1245 1246 /* Set CHI Anchor: Pipe 16 */ 1247 1248 cmd = dbri_cmdlock(dbri, 4); 1249 val = D_DTS_VO | D_DTS_VI | D_DTS_INS 1250 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16); 1251 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 1252 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1253 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1254 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1255 dbri_cmdsend(dbri, cmd, 4); 1256 1257 dbri->pipes[16].sdp = 1; 1258 dbri->pipes[16].nextpipe = 16; 1259 1260 cmd = dbri_cmdlock(dbri, 4); 1261 1262 if (master_or_slave == CHIslave) { 1263 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) 1264 * 1265 * CHICM = 0 (slave mode, 8 kHz frame rate) 1266 * IR = give immediate CHI status interrupt 1267 * EN = give CHI status interrupt upon change 1268 */ 1269 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); 1270 } else { 1271 /* Setup DBRI for CHI Master - generate clock, FS 1272 * 1273 * BPF = bits per 8 kHz frame 1274 * 12.288 MHz / CHICM_divisor = clock rate 1275 * FD = 1 - drive CHIFS on rising edge of CHICK 1276 */ 1277 int clockrate = bits_per_frame * 8; 1278 int divisor = 12288 / clockrate; 1279 1280 if (divisor > 255 || divisor * clockrate != 12288) 1281 printk(KERN_ERR "DBRI: illegal bits_per_frame " 1282 "in setup_chi\n"); 1283 1284 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD 1285 | D_CHI_BPF(bits_per_frame)); 1286 } 1287 1288 dbri->chi_bpf = bits_per_frame; 1289 1290 /* CHI Data Mode 1291 * 1292 * RCE = 0 - receive on falling edge of CHICK 1293 * XCE = 1 - transmit on rising edge of CHICK 1294 * XEN = 1 - enable transmitter 1295 * REN = 1 - enable receiver 1296 */ 1297 1298 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1299 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); 1300 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1301 1302 dbri_cmdsend(dbri, cmd, 4); 1303 } 1304 1305 /* 1306 **************************************************************************** 1307 *********************** CS4215 audio codec management ********************** 1308 **************************************************************************** 1309 1310 In the standard SPARC audio configuration, the CS4215 codec is attached 1311 to the DBRI via the CHI interface and few of the DBRI's PIO pins. 1312 1313 * Lock must not be held before calling it. 1314 1315 */ 1316 static void cs4215_setup_pipes(struct snd_dbri *dbri) 1317 { 1318 scoped_guard(spinlock_irqsave, &dbri->lock) { 1319 /* 1320 * Data mode: 1321 * Pipe 4: Send timeslots 1-4 (audio data) 1322 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1323 * Pipe 6: Receive timeslots 1-4 (audio data) 1324 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1325 * interrupt, and the rest of the data (slot 5 and 8) is 1326 * not relevant for us (only for doublechecking). 1327 * 1328 * Control mode: 1329 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) 1330 * Pipe 18: Receive timeslot 1 (clb). 1331 * Pipe 19: Receive timeslot 7 (version). 1332 */ 1333 1334 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); 1335 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1336 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); 1337 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1338 1339 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1340 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1341 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1342 } 1343 1344 dbri_cmdwait(dbri); 1345 } 1346 1347 static int cs4215_init_data(struct cs4215 *mm) 1348 { 1349 /* 1350 * No action, memory resetting only. 1351 * 1352 * Data Time Slot 5-8 1353 * Speaker,Line and Headphone enable. Gain set to the half. 1354 * Input is mike. 1355 */ 1356 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; 1357 mm->data[1] = CS4215_RO(0x20) | CS4215_SE; 1358 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 1359 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); 1360 1361 /* 1362 * Control Time Slot 1-4 1363 * 0: Default I/O voltage scale 1364 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 1365 * 2: Serial enable, CHI master, 128 bits per frame, clock 1 1366 * 3: Tests disabled 1367 */ 1368 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; 1369 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 1370 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 1371 mm->ctrl[3] = 0; 1372 1373 mm->status = 0; 1374 mm->version = 0xff; 1375 mm->precision = 8; /* For ULAW */ 1376 mm->channels = 1; 1377 1378 return 0; 1379 } 1380 1381 static void cs4215_setdata(struct snd_dbri *dbri, int muted) 1382 { 1383 if (muted) { 1384 dbri->mm.data[0] |= 63; 1385 dbri->mm.data[1] |= 63; 1386 dbri->mm.data[2] &= ~15; 1387 dbri->mm.data[3] &= ~15; 1388 } else { 1389 /* Start by setting the playback attenuation. */ 1390 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1391 int left_gain = info->left_gain & 0x3f; 1392 int right_gain = info->right_gain & 0x3f; 1393 1394 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ 1395 dbri->mm.data[1] &= ~0x3f; 1396 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); 1397 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); 1398 1399 /* Now set the recording gain. */ 1400 info = &dbri->stream_info[DBRI_REC]; 1401 left_gain = info->left_gain & 0xf; 1402 right_gain = info->right_gain & 0xf; 1403 dbri->mm.data[2] |= CS4215_LG(left_gain); 1404 dbri->mm.data[3] |= CS4215_RG(right_gain); 1405 } 1406 1407 xmit_fixed(dbri, 20, *(int *)dbri->mm.data); 1408 } 1409 1410 /* 1411 * Set the CS4215 to data mode. 1412 */ 1413 static void cs4215_open(struct snd_dbri *dbri) 1414 { 1415 int data_width; 1416 u32 tmp; 1417 1418 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", 1419 dbri->mm.channels, dbri->mm.precision); 1420 1421 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1422 * to make sure this takes. This avoids clicking noises. 1423 */ 1424 1425 cs4215_setdata(dbri, 1); 1426 udelay(125); 1427 1428 /* 1429 * Data mode: 1430 * Pipe 4: Send timeslots 1-4 (audio data) 1431 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1432 * Pipe 6: Receive timeslots 1-4 (audio data) 1433 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1434 * interrupt, and the rest of the data (slot 5 and 8) is 1435 * not relevant for us (only for doublechecking). 1436 * 1437 * Just like in control mode, the time slots are all offset by eight 1438 * bits. The CS4215, it seems, observes TSIN (the delayed signal) 1439 * even if it's the CHI master. Don't ask me... 1440 */ 1441 scoped_guard(spinlock_irqsave, &dbri->lock) { 1442 tmp = sbus_readl(dbri->regs + REG0); 1443 tmp &= ~(D_C); /* Disable CHI */ 1444 sbus_writel(tmp, dbri->regs + REG0); 1445 1446 /* Switch CS4215 to data mode - set PIO3 to 1 */ 1447 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | 1448 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); 1449 1450 reset_chi(dbri, CHIslave, 128); 1451 1452 /* Note: this next doesn't work for 8-bit stereo, because the two 1453 * channels would be on timeslots 1 and 3, with 2 and 4 idle. 1454 * (See CS4215 datasheet Fig 15) 1455 * 1456 * DBRI non-contiguous mode would be required to make this work. 1457 */ 1458 data_width = dbri->mm.channels * dbri->mm.precision; 1459 1460 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset); 1461 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32); 1462 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset); 1463 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40); 1464 1465 /* FIXME: enable CHI after _setdata? */ 1466 tmp = sbus_readl(dbri->regs + REG0); 1467 tmp |= D_C; /* Enable CHI */ 1468 sbus_writel(tmp, dbri->regs + REG0); 1469 } 1470 1471 cs4215_setdata(dbri, 0); 1472 } 1473 1474 /* 1475 * Send the control information (i.e. audio format) 1476 */ 1477 static int cs4215_setctrl(struct snd_dbri *dbri) 1478 { 1479 int i, val; 1480 u32 tmp; 1481 1482 /* FIXME - let the CPU do something useful during these delays */ 1483 1484 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1485 * to make sure this takes. This avoids clicking noises. 1486 */ 1487 cs4215_setdata(dbri, 1); 1488 udelay(125); 1489 1490 /* 1491 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait 1492 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec 1493 */ 1494 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); 1495 sbus_writel(val, dbri->regs + REG2); 1496 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); 1497 udelay(34); 1498 1499 /* In Control mode, the CS4215 is a slave device, so the DBRI must 1500 * operate as CHI master, supplying clocking and frame synchronization. 1501 * 1502 * In Data mode, however, the CS4215 must be CHI master to insure 1503 * that its data stream is synchronous with its codec. 1504 * 1505 * The upshot of all this? We start by putting the DBRI into master 1506 * mode, program the CS4215 in Control mode, then switch the CS4215 1507 * into Data mode and put the DBRI into slave mode. Various timing 1508 * requirements must be observed along the way. 1509 * 1510 * Oh, and one more thing, on a SPARCStation 20 (and maybe 1511 * others?), the addressing of the CS4215's time slots is 1512 * offset by eight bits, so we add eight to all the "cycle" 1513 * values in the Define Time Slot (DTS) commands. This is 1514 * done in hardware by a TI 248 that delays the DBRI->4215 1515 * frame sync signal by eight clock cycles. Anybody know why? 1516 */ 1517 scoped_guard(spinlock_irqsave, &dbri->lock) { 1518 tmp = sbus_readl(dbri->regs + REG0); 1519 tmp &= ~D_C; /* Disable CHI */ 1520 sbus_writel(tmp, dbri->regs + REG0); 1521 1522 reset_chi(dbri, CHImaster, 128); 1523 1524 /* 1525 * Control mode: 1526 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) 1527 * Pipe 18: Receive timeslot 1 (clb). 1528 * Pipe 19: Receive timeslot 7 (version). 1529 */ 1530 1531 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset); 1532 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset); 1533 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48); 1534 } 1535 1536 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ 1537 dbri->mm.ctrl[0] &= ~CS4215_CLB; 1538 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1539 1540 scoped_guard(spinlock_irqsave, &dbri->lock) { 1541 tmp = sbus_readl(dbri->regs + REG0); 1542 tmp |= D_C; /* Enable CHI */ 1543 sbus_writel(tmp, dbri->regs + REG0); 1544 } 1545 1546 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) 1547 msleep_interruptible(1); 1548 1549 if (i == 0) { 1550 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", 1551 dbri->mm.status); 1552 return -1; 1553 } 1554 1555 /* Disable changes to our copy of the version number, as we are about 1556 * to leave control mode. 1557 */ 1558 recv_fixed(dbri, 19, NULL); 1559 1560 /* Terminate CS4215 control mode - data sheet says 1561 * "Set CLB=1 and send two more frames of valid control info" 1562 */ 1563 dbri->mm.ctrl[0] |= CS4215_CLB; 1564 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1565 1566 /* Two frames of control info @ 8kHz frame rate = 250 us delay */ 1567 udelay(250); 1568 1569 cs4215_setdata(dbri, 0); 1570 1571 return 0; 1572 } 1573 1574 /* 1575 * Setup the codec with the sampling rate, audio format and number of 1576 * channels. 1577 * As part of the process we resend the settings for the data 1578 * timeslots as well. 1579 */ 1580 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate, 1581 snd_pcm_format_t format, unsigned int channels) 1582 { 1583 int freq_idx; 1584 int ret = 0; 1585 1586 /* Lookup index for this rate */ 1587 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { 1588 if (CS4215_FREQ[freq_idx].freq == rate) 1589 break; 1590 } 1591 if (CS4215_FREQ[freq_idx].freq != rate) { 1592 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); 1593 return -1; 1594 } 1595 1596 switch (format) { 1597 case SNDRV_PCM_FORMAT_MU_LAW: 1598 dbri->mm.ctrl[1] = CS4215_DFR_ULAW; 1599 dbri->mm.precision = 8; 1600 break; 1601 case SNDRV_PCM_FORMAT_A_LAW: 1602 dbri->mm.ctrl[1] = CS4215_DFR_ALAW; 1603 dbri->mm.precision = 8; 1604 break; 1605 case SNDRV_PCM_FORMAT_U8: 1606 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; 1607 dbri->mm.precision = 8; 1608 break; 1609 case SNDRV_PCM_FORMAT_S16_BE: 1610 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; 1611 dbri->mm.precision = 16; 1612 break; 1613 default: 1614 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); 1615 return -1; 1616 } 1617 1618 /* Add rate parameters */ 1619 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; 1620 dbri->mm.ctrl[2] = CS4215_XCLK | 1621 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; 1622 1623 dbri->mm.channels = channels; 1624 if (channels == 2) 1625 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; 1626 1627 ret = cs4215_setctrl(dbri); 1628 if (ret == 0) 1629 cs4215_open(dbri); /* set codec to data mode */ 1630 1631 return ret; 1632 } 1633 1634 /* 1635 * 1636 */ 1637 static int cs4215_init(struct snd_dbri *dbri) 1638 { 1639 u32 reg2 = sbus_readl(dbri->regs + REG2); 1640 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); 1641 1642 /* Look for the cs4215 chips */ 1643 if (reg2 & D_PIO2) { 1644 dprintk(D_MM, "Onboard CS4215 detected\n"); 1645 dbri->mm.onboard = 1; 1646 } 1647 if (reg2 & D_PIO0) { 1648 dprintk(D_MM, "Speakerbox detected\n"); 1649 dbri->mm.onboard = 0; 1650 1651 if (reg2 & D_PIO2) { 1652 printk(KERN_INFO "DBRI: Using speakerbox / " 1653 "ignoring onboard mmcodec.\n"); 1654 sbus_writel(D_ENPIO2, dbri->regs + REG2); 1655 } 1656 } 1657 1658 if (!(reg2 & (D_PIO0 | D_PIO2))) { 1659 printk(KERN_ERR "DBRI: no mmcodec found.\n"); 1660 return -EIO; 1661 } 1662 1663 cs4215_setup_pipes(dbri); 1664 cs4215_init_data(&dbri->mm); 1665 1666 /* Enable capture of the status & version timeslots. */ 1667 recv_fixed(dbri, 18, &dbri->mm.status); 1668 recv_fixed(dbri, 19, &dbri->mm.version); 1669 1670 dbri->mm.offset = dbri->mm.onboard ? 0 : 8; 1671 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { 1672 dprintk(D_MM, "CS4215 failed probe at offset %d\n", 1673 dbri->mm.offset); 1674 return -EIO; 1675 } 1676 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); 1677 1678 return 0; 1679 } 1680 1681 /* 1682 **************************************************************************** 1683 *************************** DBRI interrupt handler ************************* 1684 **************************************************************************** 1685 1686 The DBRI communicates with the CPU mainly via a circular interrupt 1687 buffer. When an interrupt is signaled, the CPU walks through the 1688 buffer and calls dbri_process_one_interrupt() for each interrupt word. 1689 Complicated interrupts are handled by dedicated functions (which 1690 appear first in this file). Any pending interrupts can be serviced by 1691 calling dbri_process_interrupt_buffer(), which works even if the CPU's 1692 interrupts are disabled. 1693 1694 */ 1695 1696 /* xmit_descs() 1697 * 1698 * Starts transmitting the current TD's for recording/playing. 1699 * For playback, ALSA has filled the DMA memory with new data (we hope). 1700 */ 1701 static void xmit_descs(struct snd_dbri *dbri) 1702 { 1703 struct dbri_streaminfo *info; 1704 u32 dvma_addr; 1705 s32 *cmd; 1706 int first_td; 1707 1708 if (dbri == NULL) 1709 return; /* Disabled */ 1710 1711 dvma_addr = (u32)dbri->dma_dvma; 1712 info = &dbri->stream_info[DBRI_REC]; 1713 guard(spinlock_irqsave)(&dbri->lock); 1714 1715 if (info->pipe >= 0) { 1716 first_td = dbri->pipes[info->pipe].first_desc; 1717 1718 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); 1719 1720 /* Stream could be closed by the time we run. */ 1721 if (first_td >= 0) { 1722 cmd = dbri_cmdlock(dbri, 2); 1723 *(cmd++) = DBRI_CMD(D_SDP, 0, 1724 dbri->pipes[info->pipe].sdp 1725 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1726 *(cmd++) = dvma_addr + 1727 dbri_dma_off(desc, first_td); 1728 dbri_cmdsend(dbri, cmd, 2); 1729 1730 /* Reset our admin of the pipe. */ 1731 dbri->pipes[info->pipe].desc = first_td; 1732 } 1733 } 1734 1735 info = &dbri->stream_info[DBRI_PLAY]; 1736 1737 if (info->pipe >= 0) { 1738 first_td = dbri->pipes[info->pipe].first_desc; 1739 1740 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); 1741 1742 /* Stream could be closed by the time we run. */ 1743 if (first_td >= 0) { 1744 cmd = dbri_cmdlock(dbri, 2); 1745 *(cmd++) = DBRI_CMD(D_SDP, 0, 1746 dbri->pipes[info->pipe].sdp 1747 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1748 *(cmd++) = dvma_addr + 1749 dbri_dma_off(desc, first_td); 1750 dbri_cmdsend(dbri, cmd, 2); 1751 1752 /* Reset our admin of the pipe. */ 1753 dbri->pipes[info->pipe].desc = first_td; 1754 } 1755 } 1756 } 1757 1758 /* transmission_complete_intr() 1759 * 1760 * Called by main interrupt handler when DBRI signals transmission complete 1761 * on a pipe (interrupt triggered by the B bit in a transmit descriptor). 1762 * 1763 * Walks through the pipe's list of transmit buffer descriptors and marks 1764 * them as available. Stops when the first descriptor is found without 1765 * TBC (Transmit Buffer Complete) set, or we've run through them all. 1766 * 1767 * The DMA buffers are not released. They form a ring buffer and 1768 * they are filled by ALSA while others are transmitted by DMA. 1769 * 1770 */ 1771 1772 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe) 1773 { 1774 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1775 int td = dbri->pipes[pipe].desc; 1776 int status; 1777 1778 while (td >= 0) { 1779 if (td >= DBRI_NO_DESCS) { 1780 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); 1781 return; 1782 } 1783 1784 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); 1785 if (!(status & DBRI_TD_TBC)) 1786 break; 1787 1788 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); 1789 1790 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ 1791 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1); 1792 1793 td = dbri->next_desc[td]; 1794 dbri->pipes[pipe].desc = td; 1795 } 1796 1797 /* Notify ALSA */ 1798 spin_unlock(&dbri->lock); 1799 snd_pcm_period_elapsed(info->substream); 1800 spin_lock(&dbri->lock); 1801 } 1802 1803 static void reception_complete_intr(struct snd_dbri *dbri, int pipe) 1804 { 1805 struct dbri_streaminfo *info; 1806 int rd = dbri->pipes[pipe].desc; 1807 s32 status; 1808 1809 if (rd < 0 || rd >= DBRI_NO_DESCS) { 1810 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); 1811 return; 1812 } 1813 1814 dbri->pipes[pipe].desc = dbri->next_desc[rd]; 1815 status = dbri->dma->desc[rd].word1; 1816 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ 1817 1818 info = &dbri->stream_info[DBRI_REC]; 1819 info->offset += DBRI_RD_CNT(status); 1820 1821 /* FIXME: Check status */ 1822 1823 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", 1824 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); 1825 1826 /* Notify ALSA */ 1827 spin_unlock(&dbri->lock); 1828 snd_pcm_period_elapsed(info->substream); 1829 spin_lock(&dbri->lock); 1830 } 1831 1832 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x) 1833 { 1834 int val = D_INTR_GETVAL(x); 1835 int channel = D_INTR_GETCHAN(x); 1836 int command = D_INTR_GETCMD(x); 1837 int code = D_INTR_GETCODE(x); 1838 #ifdef DBRI_DEBUG 1839 int rval = D_INTR_GETRVAL(x); 1840 #endif 1841 1842 if (channel == D_INTR_CMD) { 1843 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", 1844 cmds[command], val); 1845 } else { 1846 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", 1847 channel, code, rval); 1848 } 1849 1850 switch (code) { 1851 case D_INTR_CMDI: 1852 if (command != D_WAIT) 1853 printk(KERN_ERR "DBRI: Command read interrupt\n"); 1854 break; 1855 case D_INTR_BRDY: 1856 reception_complete_intr(dbri, channel); 1857 break; 1858 case D_INTR_XCMP: 1859 case D_INTR_MINT: 1860 transmission_complete_intr(dbri, channel); 1861 break; 1862 case D_INTR_UNDR: 1863 /* UNDR - Transmission underrun 1864 * resend SDP command with clear pipe bit (C) set 1865 */ 1866 { 1867 /* FIXME: do something useful in case of underrun */ 1868 printk(KERN_ERR "DBRI: Underrun error\n"); 1869 #if 0 1870 s32 *cmd; 1871 int pipe = channel; 1872 int td = dbri->pipes[pipe].desc; 1873 1874 dbri->dma->desc[td].word4 = 0; 1875 cmd = dbri_cmdlock(dbri, NoGetLock); 1876 *(cmd++) = DBRI_CMD(D_SDP, 0, 1877 dbri->pipes[pipe].sdp 1878 | D_SDP_P | D_SDP_C | D_SDP_2SAME); 1879 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); 1880 dbri_cmdsend(dbri, cmd); 1881 #endif 1882 } 1883 break; 1884 case D_INTR_FXDT: 1885 /* FXDT - Fixed data change */ 1886 if (dbri->pipes[channel].sdp & D_SDP_MSB) 1887 val = reverse_bytes(val, dbri->pipes[channel].length); 1888 1889 if (dbri->pipes[channel].recv_fixed_ptr) 1890 *(dbri->pipes[channel].recv_fixed_ptr) = val; 1891 break; 1892 default: 1893 if (channel != D_INTR_CMD) 1894 printk(KERN_WARNING 1895 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); 1896 } 1897 } 1898 1899 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt 1900 * buffer until it finds a zero word (indicating nothing more to do 1901 * right now). Non-zero words require processing and are handed off 1902 * to dbri_process_one_interrupt AFTER advancing the pointer. 1903 */ 1904 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri) 1905 { 1906 s32 x; 1907 1908 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { 1909 dbri->dma->intr[dbri->dbri_irqp] = 0; 1910 dbri->dbri_irqp++; 1911 if (dbri->dbri_irqp == DBRI_INT_BLK) 1912 dbri->dbri_irqp = 1; 1913 1914 dbri_process_one_interrupt(dbri, x); 1915 } 1916 } 1917 1918 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id) 1919 { 1920 struct snd_dbri *dbri = dev_id; 1921 static int errcnt; 1922 int x; 1923 1924 if (dbri == NULL) 1925 return IRQ_NONE; 1926 guard(spinlock)(&dbri->lock); 1927 1928 /* 1929 * Read it, so the interrupt goes away. 1930 */ 1931 x = sbus_readl(dbri->regs + REG1); 1932 1933 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { 1934 u32 tmp; 1935 1936 if (x & D_MRR) 1937 printk(KERN_ERR 1938 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", 1939 x); 1940 if (x & D_MLE) 1941 printk(KERN_ERR 1942 "DBRI: Multiple Late Error on SBus reg1=0x%x\n", 1943 x); 1944 if (x & D_LBG) 1945 printk(KERN_ERR 1946 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); 1947 if (x & D_MBE) 1948 printk(KERN_ERR 1949 "DBRI: Burst Error on SBus reg1=0x%x\n", x); 1950 1951 /* Some of these SBus errors cause the chip's SBus circuitry 1952 * to be disabled, so just re-enable and try to keep going. 1953 * 1954 * The only one I've seen is MRR, which will be triggered 1955 * if you let a transmit pipe underrun, then try to CDP it. 1956 * 1957 * If these things persist, we reset the chip. 1958 */ 1959 if ((++errcnt) % 10 == 0) { 1960 dprintk(D_INT, "Interrupt errors exceeded.\n"); 1961 dbri_reset(dbri); 1962 } else { 1963 tmp = sbus_readl(dbri->regs + REG0); 1964 tmp &= ~(D_D); 1965 sbus_writel(tmp, dbri->regs + REG0); 1966 } 1967 } 1968 1969 dbri_process_interrupt_buffer(dbri); 1970 1971 return IRQ_HANDLED; 1972 } 1973 1974 /**************************************************************************** 1975 PCM Interface 1976 ****************************************************************************/ 1977 static const struct snd_pcm_hardware snd_dbri_pcm_hw = { 1978 .info = SNDRV_PCM_INFO_MMAP | 1979 SNDRV_PCM_INFO_INTERLEAVED | 1980 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1981 SNDRV_PCM_INFO_MMAP_VALID | 1982 SNDRV_PCM_INFO_BATCH, 1983 .formats = SNDRV_PCM_FMTBIT_MU_LAW | 1984 SNDRV_PCM_FMTBIT_A_LAW | 1985 SNDRV_PCM_FMTBIT_U8 | 1986 SNDRV_PCM_FMTBIT_S16_BE, 1987 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512, 1988 .rate_min = 5512, 1989 .rate_max = 48000, 1990 .channels_min = 1, 1991 .channels_max = 2, 1992 .buffer_bytes_max = 64 * 1024, 1993 .period_bytes_min = 1, 1994 .period_bytes_max = DBRI_TD_MAXCNT, 1995 .periods_min = 1, 1996 .periods_max = 1024, 1997 }; 1998 1999 static int snd_hw_rule_format(struct snd_pcm_hw_params *params, 2000 struct snd_pcm_hw_rule *rule) 2001 { 2002 struct snd_interval *c = hw_param_interval(params, 2003 SNDRV_PCM_HW_PARAM_CHANNELS); 2004 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 2005 struct snd_mask fmt; 2006 2007 snd_mask_any(&fmt); 2008 if (c->min > 1) { 2009 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE; 2010 return snd_mask_refine(f, &fmt); 2011 } 2012 return 0; 2013 } 2014 2015 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params, 2016 struct snd_pcm_hw_rule *rule) 2017 { 2018 struct snd_interval *c = hw_param_interval(params, 2019 SNDRV_PCM_HW_PARAM_CHANNELS); 2020 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 2021 struct snd_interval ch; 2022 2023 snd_interval_any(&ch); 2024 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) { 2025 ch.min = 1; 2026 ch.max = 1; 2027 ch.integer = 1; 2028 return snd_interval_refine(c, &ch); 2029 } 2030 return 0; 2031 } 2032 2033 static int snd_dbri_open(struct snd_pcm_substream *substream) 2034 { 2035 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2036 struct snd_pcm_runtime *runtime = substream->runtime; 2037 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2038 2039 dprintk(D_USR, "open audio output.\n"); 2040 runtime->hw = snd_dbri_pcm_hw; 2041 2042 scoped_guard(spinlock_irqsave, &dbri->lock) { 2043 info->substream = substream; 2044 info->offset = 0; 2045 info->dvma_buffer = 0; 2046 info->pipe = -1; 2047 } 2048 2049 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2050 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT, 2051 -1); 2052 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT, 2053 snd_hw_rule_channels, NULL, 2054 SNDRV_PCM_HW_PARAM_CHANNELS, 2055 -1); 2056 2057 cs4215_open(dbri); 2058 2059 return 0; 2060 } 2061 2062 static int snd_dbri_close(struct snd_pcm_substream *substream) 2063 { 2064 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2065 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2066 2067 dprintk(D_USR, "close audio output.\n"); 2068 info->substream = NULL; 2069 info->offset = 0; 2070 2071 return 0; 2072 } 2073 2074 static int snd_dbri_hw_params(struct snd_pcm_substream *substream, 2075 struct snd_pcm_hw_params *hw_params) 2076 { 2077 struct snd_pcm_runtime *runtime = substream->runtime; 2078 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2079 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2080 int direction; 2081 int ret; 2082 2083 /* set sampling rate, audio format and number of channels */ 2084 ret = cs4215_prepare(dbri, params_rate(hw_params), 2085 params_format(hw_params), 2086 params_channels(hw_params)); 2087 if (ret != 0) 2088 return ret; 2089 2090 /* hw_params can get called multiple times. Only map the DMA once. 2091 */ 2092 if (info->dvma_buffer == 0) { 2093 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2094 direction = DMA_TO_DEVICE; 2095 else 2096 direction = DMA_FROM_DEVICE; 2097 2098 info->dvma_buffer = 2099 dma_map_single(&dbri->op->dev, 2100 runtime->dma_area, 2101 params_buffer_bytes(hw_params), 2102 direction); 2103 } 2104 2105 direction = params_buffer_bytes(hw_params); 2106 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", 2107 direction, info->dvma_buffer); 2108 return 0; 2109 } 2110 2111 static int snd_dbri_hw_free(struct snd_pcm_substream *substream) 2112 { 2113 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2114 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2115 int direction; 2116 2117 dprintk(D_USR, "hw_free.\n"); 2118 2119 /* hw_free can get called multiple times. Only unmap the DMA once. 2120 */ 2121 if (info->dvma_buffer) { 2122 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2123 direction = DMA_TO_DEVICE; 2124 else 2125 direction = DMA_FROM_DEVICE; 2126 2127 dma_unmap_single(&dbri->op->dev, info->dvma_buffer, 2128 substream->runtime->buffer_size, direction); 2129 info->dvma_buffer = 0; 2130 } 2131 if (info->pipe != -1) { 2132 reset_pipe(dbri, info->pipe); 2133 info->pipe = -1; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int snd_dbri_prepare(struct snd_pcm_substream *substream) 2140 { 2141 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2142 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2143 int ret; 2144 2145 info->size = snd_pcm_lib_buffer_bytes(substream); 2146 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2147 info->pipe = 4; /* Send pipe */ 2148 else 2149 info->pipe = 6; /* Receive pipe */ 2150 2151 guard(spinlock_irq)(&dbri->lock); 2152 info->offset = 0; 2153 2154 /* Setup the all the transmit/receive descriptors to cover the 2155 * whole DMA buffer. 2156 */ 2157 ret = setup_descs(dbri, DBRI_STREAMNO(substream), 2158 snd_pcm_lib_period_bytes(substream)); 2159 2160 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); 2161 return ret; 2162 } 2163 2164 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd) 2165 { 2166 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2167 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2168 int ret = 0; 2169 2170 switch (cmd) { 2171 case SNDRV_PCM_TRIGGER_START: 2172 dprintk(D_USR, "start audio, period is %d bytes\n", 2173 (int)snd_pcm_lib_period_bytes(substream)); 2174 /* Re-submit the TDs. */ 2175 xmit_descs(dbri); 2176 break; 2177 case SNDRV_PCM_TRIGGER_STOP: 2178 dprintk(D_USR, "stop audio.\n"); 2179 reset_pipe(dbri, info->pipe); 2180 break; 2181 default: 2182 ret = -EINVAL; 2183 } 2184 2185 return ret; 2186 } 2187 2188 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream) 2189 { 2190 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2191 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2192 snd_pcm_uframes_t ret; 2193 2194 ret = bytes_to_frames(substream->runtime, info->offset) 2195 % substream->runtime->buffer_size; 2196 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n", 2197 ret, substream->runtime->buffer_size); 2198 return ret; 2199 } 2200 2201 static const struct snd_pcm_ops snd_dbri_ops = { 2202 .open = snd_dbri_open, 2203 .close = snd_dbri_close, 2204 .hw_params = snd_dbri_hw_params, 2205 .hw_free = snd_dbri_hw_free, 2206 .prepare = snd_dbri_prepare, 2207 .trigger = snd_dbri_trigger, 2208 .pointer = snd_dbri_pointer, 2209 }; 2210 2211 static int snd_dbri_pcm(struct snd_card *card) 2212 { 2213 struct snd_pcm *pcm; 2214 int err; 2215 2216 err = snd_pcm_new(card, 2217 /* ID */ "sun_dbri", 2218 /* device */ 0, 2219 /* playback count */ 1, 2220 /* capture count */ 1, &pcm); 2221 if (err < 0) 2222 return err; 2223 2224 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); 2225 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); 2226 2227 pcm->private_data = card->private_data; 2228 pcm->info_flags = 0; 2229 strscpy(pcm->name, card->shortname); 2230 2231 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, 2232 NULL, 64 * 1024, 64 * 1024); 2233 return 0; 2234 } 2235 2236 /***************************************************************************** 2237 Mixer interface 2238 *****************************************************************************/ 2239 2240 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol, 2241 struct snd_ctl_elem_info *uinfo) 2242 { 2243 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2244 uinfo->count = 2; 2245 uinfo->value.integer.min = 0; 2246 if (kcontrol->private_value == DBRI_PLAY) 2247 uinfo->value.integer.max = DBRI_MAX_VOLUME; 2248 else 2249 uinfo->value.integer.max = DBRI_MAX_GAIN; 2250 return 0; 2251 } 2252 2253 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol, 2254 struct snd_ctl_elem_value *ucontrol) 2255 { 2256 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2257 struct dbri_streaminfo *info; 2258 2259 if (snd_BUG_ON(!dbri)) 2260 return -EINVAL; 2261 info = &dbri->stream_info[kcontrol->private_value]; 2262 2263 ucontrol->value.integer.value[0] = info->left_gain; 2264 ucontrol->value.integer.value[1] = info->right_gain; 2265 return 0; 2266 } 2267 2268 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol, 2269 struct snd_ctl_elem_value *ucontrol) 2270 { 2271 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2272 struct dbri_streaminfo *info = 2273 &dbri->stream_info[kcontrol->private_value]; 2274 unsigned int vol[2]; 2275 int changed = 0; 2276 2277 vol[0] = ucontrol->value.integer.value[0]; 2278 vol[1] = ucontrol->value.integer.value[1]; 2279 if (kcontrol->private_value == DBRI_PLAY) { 2280 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME) 2281 return -EINVAL; 2282 } else { 2283 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN) 2284 return -EINVAL; 2285 } 2286 2287 if (info->left_gain != vol[0]) { 2288 info->left_gain = vol[0]; 2289 changed = 1; 2290 } 2291 if (info->right_gain != vol[1]) { 2292 info->right_gain = vol[1]; 2293 changed = 1; 2294 } 2295 if (changed) { 2296 /* First mute outputs, and wait 1/8000 sec (125 us) 2297 * to make sure this takes. This avoids clicking noises. 2298 */ 2299 cs4215_setdata(dbri, 1); 2300 udelay(125); 2301 cs4215_setdata(dbri, 0); 2302 } 2303 return changed; 2304 } 2305 2306 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol, 2307 struct snd_ctl_elem_info *uinfo) 2308 { 2309 int mask = (kcontrol->private_value >> 16) & 0xff; 2310 2311 uinfo->type = (mask == 1) ? 2312 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2313 uinfo->count = 1; 2314 uinfo->value.integer.min = 0; 2315 uinfo->value.integer.max = mask; 2316 return 0; 2317 } 2318 2319 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol, 2320 struct snd_ctl_elem_value *ucontrol) 2321 { 2322 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2323 int elem = kcontrol->private_value & 0xff; 2324 int shift = (kcontrol->private_value >> 8) & 0xff; 2325 int mask = (kcontrol->private_value >> 16) & 0xff; 2326 int invert = (kcontrol->private_value >> 24) & 1; 2327 2328 if (snd_BUG_ON(!dbri)) 2329 return -EINVAL; 2330 2331 if (elem < 4) 2332 ucontrol->value.integer.value[0] = 2333 (dbri->mm.data[elem] >> shift) & mask; 2334 else 2335 ucontrol->value.integer.value[0] = 2336 (dbri->mm.ctrl[elem - 4] >> shift) & mask; 2337 2338 if (invert == 1) 2339 ucontrol->value.integer.value[0] = 2340 mask - ucontrol->value.integer.value[0]; 2341 return 0; 2342 } 2343 2344 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol, 2345 struct snd_ctl_elem_value *ucontrol) 2346 { 2347 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2348 int elem = kcontrol->private_value & 0xff; 2349 int shift = (kcontrol->private_value >> 8) & 0xff; 2350 int mask = (kcontrol->private_value >> 16) & 0xff; 2351 int invert = (kcontrol->private_value >> 24) & 1; 2352 int changed = 0; 2353 unsigned short val; 2354 2355 if (snd_BUG_ON(!dbri)) 2356 return -EINVAL; 2357 2358 val = (ucontrol->value.integer.value[0] & mask); 2359 if (invert == 1) 2360 val = mask - val; 2361 val <<= shift; 2362 2363 if (elem < 4) { 2364 dbri->mm.data[elem] = (dbri->mm.data[elem] & 2365 ~(mask << shift)) | val; 2366 changed = (val != dbri->mm.data[elem]); 2367 } else { 2368 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & 2369 ~(mask << shift)) | val; 2370 changed = (val != dbri->mm.ctrl[elem - 4]); 2371 } 2372 2373 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " 2374 "mixer-value=%ld, mm-value=0x%x\n", 2375 mask, changed, ucontrol->value.integer.value[0], 2376 dbri->mm.data[elem & 3]); 2377 2378 if (changed) { 2379 /* First mute outputs, and wait 1/8000 sec (125 us) 2380 * to make sure this takes. This avoids clicking noises. 2381 */ 2382 cs4215_setdata(dbri, 1); 2383 udelay(125); 2384 cs4215_setdata(dbri, 0); 2385 } 2386 return changed; 2387 } 2388 2389 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control 2390 timeslots. Shift is the bit offset in the timeslot, mask defines the 2391 number of bits. invert is a boolean for use with attenuation. 2392 */ 2393 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \ 2394 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 2395 .info = snd_cs4215_info_single, \ 2396 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ 2397 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \ 2398 ((invert) << 24) }, 2399 2400 static const struct snd_kcontrol_new dbri_controls[] = { 2401 { 2402 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2403 .name = "Playback Volume", 2404 .info = snd_cs4215_info_volume, 2405 .get = snd_cs4215_get_volume, 2406 .put = snd_cs4215_put_volume, 2407 .private_value = DBRI_PLAY, 2408 }, 2409 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) 2410 CS4215_SINGLE("Line out switch", 0, 6, 1, 0) 2411 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) 2412 { 2413 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2414 .name = "Capture Volume", 2415 .info = snd_cs4215_info_volume, 2416 .get = snd_cs4215_get_volume, 2417 .put = snd_cs4215_put_volume, 2418 .private_value = DBRI_REC, 2419 }, 2420 /* FIXME: mic/line switch */ 2421 CS4215_SINGLE("Line in switch", 2, 4, 1, 0) 2422 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) 2423 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) 2424 CS4215_SINGLE("Mic boost", 4, 4, 1, 1) 2425 }; 2426 2427 static int snd_dbri_mixer(struct snd_card *card) 2428 { 2429 int idx, err; 2430 struct snd_dbri *dbri; 2431 2432 if (snd_BUG_ON(!card || !card->private_data)) 2433 return -EINVAL; 2434 dbri = card->private_data; 2435 2436 strscpy(card->mixername, card->shortname); 2437 2438 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) { 2439 err = snd_ctl_add(card, 2440 snd_ctl_new1(&dbri_controls[idx], dbri)); 2441 if (err < 0) 2442 return err; 2443 } 2444 2445 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { 2446 dbri->stream_info[idx].left_gain = 0; 2447 dbri->stream_info[idx].right_gain = 0; 2448 } 2449 2450 return 0; 2451 } 2452 2453 /**************************************************************************** 2454 /proc interface 2455 ****************************************************************************/ 2456 static void dbri_regs_read(struct snd_info_entry *entry, 2457 struct snd_info_buffer *buffer) 2458 { 2459 struct snd_dbri *dbri = entry->private_data; 2460 2461 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); 2462 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); 2463 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); 2464 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); 2465 } 2466 2467 #ifdef DBRI_DEBUG 2468 static void dbri_debug_read(struct snd_info_entry *entry, 2469 struct snd_info_buffer *buffer) 2470 { 2471 struct snd_dbri *dbri = entry->private_data; 2472 int pipe; 2473 snd_iprintf(buffer, "debug=%d\n", dbri_debug); 2474 2475 for (pipe = 0; pipe < 32; pipe++) { 2476 if (pipe_active(dbri, pipe)) { 2477 struct dbri_pipe *pptr = &dbri->pipes[pipe]; 2478 snd_iprintf(buffer, 2479 "Pipe %d: %s SDP=0x%x desc=%d, " 2480 "len=%d next %d\n", 2481 pipe, 2482 (pptr->sdp & D_SDP_TO_SER) ? "output" : 2483 "input", 2484 pptr->sdp, pptr->desc, 2485 pptr->length, pptr->nextpipe); 2486 } 2487 } 2488 } 2489 #endif 2490 2491 static void snd_dbri_proc(struct snd_card *card) 2492 { 2493 struct snd_dbri *dbri = card->private_data; 2494 2495 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read); 2496 #ifdef DBRI_DEBUG 2497 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read); 2498 #endif 2499 } 2500 2501 /* 2502 **************************************************************************** 2503 **************************** Initialization ******************************** 2504 **************************************************************************** 2505 */ 2506 static void snd_dbri_free(struct snd_dbri *dbri); 2507 2508 static int snd_dbri_create(struct snd_card *card, 2509 struct platform_device *op, 2510 int irq, int dev) 2511 { 2512 struct snd_dbri *dbri = card->private_data; 2513 int err; 2514 2515 spin_lock_init(&dbri->lock); 2516 dbri->op = op; 2517 dbri->irq = irq; 2518 2519 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma), 2520 &dbri->dma_dvma, GFP_KERNEL); 2521 if (!dbri->dma) 2522 return -ENOMEM; 2523 2524 dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n", 2525 dbri->dma, dbri->dma_dvma); 2526 2527 /* Map the registers into memory. */ 2528 dbri->regs_size = resource_size(&op->resource[0]); 2529 dbri->regs = of_ioremap(&op->resource[0], 0, 2530 dbri->regs_size, "DBRI Registers"); 2531 if (!dbri->regs) { 2532 printk(KERN_ERR "DBRI: could not allocate registers\n"); 2533 dma_free_coherent(&op->dev, sizeof(struct dbri_dma), 2534 (void *)dbri->dma, dbri->dma_dvma); 2535 return -EIO; 2536 } 2537 2538 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED, 2539 "DBRI audio", dbri); 2540 if (err) { 2541 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); 2542 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size); 2543 dma_free_coherent(&op->dev, sizeof(struct dbri_dma), 2544 (void *)dbri->dma, dbri->dma_dvma); 2545 return err; 2546 } 2547 2548 /* Do low level initialization of the DBRI and CS4215 chips */ 2549 dbri_initialize(dbri); 2550 err = cs4215_init(dbri); 2551 if (err) { 2552 snd_dbri_free(dbri); 2553 return err; 2554 } 2555 2556 return 0; 2557 } 2558 2559 static void snd_dbri_free(struct snd_dbri *dbri) 2560 { 2561 dprintk(D_GEN, "snd_dbri_free\n"); 2562 dbri_reset(dbri); 2563 2564 if (dbri->irq) 2565 free_irq(dbri->irq, dbri); 2566 2567 if (dbri->regs) 2568 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size); 2569 2570 if (dbri->dma) 2571 dma_free_coherent(&dbri->op->dev, 2572 sizeof(struct dbri_dma), 2573 (void *)dbri->dma, dbri->dma_dvma); 2574 } 2575 2576 static int dbri_probe(struct platform_device *op) 2577 { 2578 struct snd_dbri *dbri; 2579 struct resource *rp; 2580 struct snd_card *card; 2581 static int dev; 2582 int irq; 2583 int err; 2584 2585 if (dev >= SNDRV_CARDS) 2586 return -ENODEV; 2587 if (!enable[dev]) { 2588 dev++; 2589 return -ENOENT; 2590 } 2591 2592 irq = op->archdata.irqs[0]; 2593 if (irq <= 0) { 2594 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev); 2595 return -ENODEV; 2596 } 2597 2598 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE, 2599 sizeof(struct snd_dbri), &card); 2600 if (err < 0) 2601 return err; 2602 2603 strscpy(card->driver, "DBRI"); 2604 strscpy(card->shortname, "Sun DBRI"); 2605 rp = &op->resource[0]; 2606 sprintf(card->longname, "%s at 0x%02lx:0x%016llx, irq %d", 2607 card->shortname, 2608 rp->flags & 0xffL, (unsigned long long)rp->start, irq); 2609 2610 err = snd_dbri_create(card, op, irq, dev); 2611 if (err < 0) { 2612 snd_card_free(card); 2613 return err; 2614 } 2615 2616 dbri = card->private_data; 2617 err = snd_dbri_pcm(card); 2618 if (err < 0) 2619 goto _err; 2620 2621 err = snd_dbri_mixer(card); 2622 if (err < 0) 2623 goto _err; 2624 2625 /* /proc file handling */ 2626 snd_dbri_proc(card); 2627 dev_set_drvdata(&op->dev, card); 2628 2629 err = snd_card_register(card); 2630 if (err < 0) 2631 goto _err; 2632 2633 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", 2634 dev, dbri->regs, 2635 dbri->irq, op->dev.of_node->name[9], dbri->mm.version); 2636 dev++; 2637 2638 return 0; 2639 2640 _err: 2641 snd_dbri_free(dbri); 2642 snd_card_free(card); 2643 return err; 2644 } 2645 2646 static void dbri_remove(struct platform_device *op) 2647 { 2648 struct snd_card *card = dev_get_drvdata(&op->dev); 2649 2650 snd_dbri_free(card->private_data); 2651 snd_card_free(card); 2652 } 2653 2654 static const struct of_device_id dbri_match[] = { 2655 { 2656 .name = "SUNW,DBRIe", 2657 }, 2658 { 2659 .name = "SUNW,DBRIf", 2660 }, 2661 {}, 2662 }; 2663 2664 MODULE_DEVICE_TABLE(of, dbri_match); 2665 2666 static struct platform_driver dbri_sbus_driver = { 2667 .driver = { 2668 .name = "dbri", 2669 .of_match_table = dbri_match, 2670 }, 2671 .probe = dbri_probe, 2672 .remove = dbri_remove, 2673 }; 2674 2675 module_platform_driver(dbri_sbus_driver); 2676