1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11
12 #include <linux/bits.h>
13 #include <linux/completion.h>
14 #include <linux/errno.h>
15 #include <linux/i2c.h>
16 #include <linux/pm.h>
17 #include <linux/regmap.h>
18 #include <linux/types.h>
19
20 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
21 I2C_FUNC_SMBUS_BYTE | \
22 I2C_FUNC_SMBUS_BYTE_DATA | \
23 I2C_FUNC_SMBUS_WORD_DATA | \
24 I2C_FUNC_SMBUS_BLOCK_DATA | \
25 I2C_FUNC_SMBUS_I2C_BLOCK)
26
27 #define DW_IC_CON_MASTER BIT(0)
28 #define DW_IC_CON_SPEED_STD (1 << 1)
29 #define DW_IC_CON_SPEED_FAST (2 << 1)
30 #define DW_IC_CON_SPEED_HIGH (3 << 1)
31 #define DW_IC_CON_SPEED_MASK GENMASK(2, 1)
32 #define DW_IC_CON_10BITADDR_SLAVE BIT(3)
33 #define DW_IC_CON_10BITADDR_MASTER BIT(4)
34 #define DW_IC_CON_RESTART_EN BIT(5)
35 #define DW_IC_CON_SLAVE_DISABLE BIT(6)
36 #define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7)
37 #define DW_IC_CON_TX_EMPTY_CTRL BIT(8)
38 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
39 #define DW_IC_CON_BUS_CLEAR_CTRL BIT(11)
40
41 #define DW_IC_DATA_CMD_DAT GENMASK(7, 0)
42 #define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11)
43
44 /*
45 * Registers offset
46 */
47 #define DW_IC_CON 0x00
48 #define DW_IC_TAR 0x04
49 #define DW_IC_SAR 0x08
50 #define DW_IC_DATA_CMD 0x10
51 #define DW_IC_SS_SCL_HCNT 0x14
52 #define DW_IC_SS_SCL_LCNT 0x18
53 #define DW_IC_FS_SCL_HCNT 0x1c
54 #define DW_IC_FS_SCL_LCNT 0x20
55 #define DW_IC_HS_SCL_HCNT 0x24
56 #define DW_IC_HS_SCL_LCNT 0x28
57 #define DW_IC_INTR_STAT 0x2c
58 #define DW_IC_INTR_MASK 0x30
59 #define DW_IC_RAW_INTR_STAT 0x34
60 #define DW_IC_RX_TL 0x38
61 #define DW_IC_TX_TL 0x3c
62 #define DW_IC_CLR_INTR 0x40
63 #define DW_IC_CLR_RX_UNDER 0x44
64 #define DW_IC_CLR_RX_OVER 0x48
65 #define DW_IC_CLR_TX_OVER 0x4c
66 #define DW_IC_CLR_RD_REQ 0x50
67 #define DW_IC_CLR_TX_ABRT 0x54
68 #define DW_IC_CLR_RX_DONE 0x58
69 #define DW_IC_CLR_ACTIVITY 0x5c
70 #define DW_IC_CLR_STOP_DET 0x60
71 #define DW_IC_CLR_START_DET 0x64
72 #define DW_IC_CLR_GEN_CALL 0x68
73 #define DW_IC_ENABLE 0x6c
74 #define DW_IC_STATUS 0x70
75 #define DW_IC_TXFLR 0x74
76 #define DW_IC_RXFLR 0x78
77 #define DW_IC_SDA_HOLD 0x7c
78 #define DW_IC_TX_ABRT_SOURCE 0x80
79 #define DW_IC_ENABLE_STATUS 0x9c
80 #define DW_IC_CLR_RESTART_DET 0xa8
81 #define DW_IC_SMBUS_INTR_MASK 0xcc
82 #define DW_IC_COMP_PARAM_1 0xf4
83 #define DW_IC_COMP_VERSION 0xf8
84 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */
85 #define DW_IC_COMP_TYPE 0xfc
86 #define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */
87
88 #define DW_IC_INTR_RX_UNDER BIT(0)
89 #define DW_IC_INTR_RX_OVER BIT(1)
90 #define DW_IC_INTR_RX_FULL BIT(2)
91 #define DW_IC_INTR_TX_OVER BIT(3)
92 #define DW_IC_INTR_TX_EMPTY BIT(4)
93 #define DW_IC_INTR_RD_REQ BIT(5)
94 #define DW_IC_INTR_TX_ABRT BIT(6)
95 #define DW_IC_INTR_RX_DONE BIT(7)
96 #define DW_IC_INTR_ACTIVITY BIT(8)
97 #define DW_IC_INTR_STOP_DET BIT(9)
98 #define DW_IC_INTR_START_DET BIT(10)
99 #define DW_IC_INTR_GEN_CALL BIT(11)
100 #define DW_IC_INTR_RESTART_DET BIT(12)
101 #define DW_IC_INTR_MST_ON_HOLD BIT(13)
102
103 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
104 DW_IC_INTR_TX_ABRT | \
105 DW_IC_INTR_STOP_DET)
106 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
107 DW_IC_INTR_TX_EMPTY)
108 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
109 DW_IC_INTR_RX_UNDER | \
110 DW_IC_INTR_RD_REQ)
111
112 #define DW_IC_ENABLE_ENABLE BIT(0)
113 #define DW_IC_ENABLE_ABORT BIT(1)
114
115 #define DW_IC_STATUS_ACTIVITY BIT(0)
116 #define DW_IC_STATUS_TFE BIT(2)
117 #define DW_IC_STATUS_RFNE BIT(3)
118 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
119 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
120 #define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7)
121
122 #define DW_IC_SDA_HOLD_RX_SHIFT 16
123 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
124
125 #define DW_IC_ERR_TX_ABRT 0x1
126
127 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
128
129 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
130 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
131
132 /*
133 * Sofware status flags
134 */
135 #define STATUS_ACTIVE BIT(0)
136 #define STATUS_WRITE_IN_PROGRESS BIT(1)
137 #define STATUS_READ_IN_PROGRESS BIT(2)
138 #define STATUS_MASK GENMASK(2, 0)
139
140 /*
141 * operation modes
142 */
143 #define DW_IC_MASTER 0
144 #define DW_IC_SLAVE 1
145
146 /*
147 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register.
148 *
149 * Only expected abort codes are listed here,
150 * refer to the datasheet for the full list.
151 */
152 #define ABRT_7B_ADDR_NOACK 0
153 #define ABRT_10ADDR1_NOACK 1
154 #define ABRT_10ADDR2_NOACK 2
155 #define ABRT_TXDATA_NOACK 3
156 #define ABRT_GCALL_NOACK 4
157 #define ABRT_GCALL_READ 5
158 #define ABRT_SBYTE_ACKDET 7
159 #define ABRT_SBYTE_NORSTRT 9
160 #define ABRT_10B_RD_NORSTRT 10
161 #define ABRT_MASTER_DIS 11
162 #define ARB_LOST 12
163 #define ABRT_SLAVE_FLUSH_TXFIFO 13
164 #define ABRT_SLAVE_ARBLOST 14
165 #define ABRT_SLAVE_RD_INTX 15
166
167 #define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK)
168 #define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK)
169 #define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK)
170 #define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK)
171 #define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK)
172 #define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ)
173 #define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET)
174 #define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT)
175 #define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT)
176 #define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS)
177 #define DW_IC_TX_ARB_LOST BIT(ARB_LOST)
178 #define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX)
179 #define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST)
180 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO)
181
182 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
183 DW_IC_TX_ABRT_10ADDR1_NOACK | \
184 DW_IC_TX_ABRT_10ADDR2_NOACK | \
185 DW_IC_TX_ABRT_TXDATA_NOACK | \
186 DW_IC_TX_ABRT_GCALL_NOACK)
187
188 struct clk;
189 struct device;
190 struct reset_control;
191
192 /**
193 * struct dw_i2c_dev - private i2c-designware data
194 * @dev: driver model device node
195 * @map: IO registers map
196 * @sysmap: System controller registers map
197 * @base: IO registers pointer
198 * @ext: Extended IO registers pointer
199 * @cmd_complete: tx completion indicator
200 * @clk: input reference clock
201 * @pclk: clock required to access the registers
202 * @rst: optional reset for the controller
203 * @slave: represent an I2C slave device
204 * @get_clk_rate_khz: callback to retrieve IP specific bus speed
205 * @cmd_err: run time hardware error code
206 * @msgs: points to an array of messages currently being transferred
207 * @msgs_num: the number of elements in msgs
208 * @msg_write_idx: the element index of the current tx message in the msgs array
209 * @tx_buf_len: the length of the current tx buffer
210 * @tx_buf: the current tx buffer
211 * @msg_read_idx: the element index of the current rx message in the msgs array
212 * @rx_buf_len: the length of the current rx buffer
213 * @rx_buf: the current rx buffer
214 * @msg_err: error status of the current transfer
215 * @status: i2c master status, one of STATUS_*
216 * @abort_source: copy of the TX_ABRT_SOURCE register
217 * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode
218 * @irq: interrupt number for the i2c master
219 * @flags: platform specific flags like type of IO accessors or model
220 * @adapter: i2c subsystem adapter node
221 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
222 * @master_cfg: configuration for the master device
223 * @slave_cfg: configuration for the slave device
224 * @tx_fifo_depth: depth of the hardware tx fifo
225 * @rx_fifo_depth: depth of the hardware rx fifo
226 * @rx_outstanding: current master-rx elements in tx fifo
227 * @timings: bus clock frequency, SDA hold and other timings
228 * @sda_hold_time: SDA hold value
229 * @ss_hcnt: standard speed HCNT value
230 * @ss_lcnt: standard speed LCNT value
231 * @fs_hcnt: fast speed HCNT value
232 * @fs_lcnt: fast speed LCNT value
233 * @fp_hcnt: fast plus HCNT value
234 * @fp_lcnt: fast plus LCNT value
235 * @hs_hcnt: high speed HCNT value
236 * @hs_lcnt: high speed LCNT value
237 * @acquire_lock: function to acquire a hardware lock on the bus
238 * @release_lock: function to release a hardware lock on the bus
239 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's
240 * -1 if there is no semaphore.
241 * @shared_with_punit: true if this bus is shared with the SoC's PUNIT
242 * @init: function to initialize the I2C hardware
243 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
244 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
245 * @rinfo: I²C GPIO recovery information
246 * @bus_capacitance_pF: bus capacitance in picofarads
247 * @clk_freq_optimized: if this value is true, it means the hardware reduces
248 * its internal clock frequency by reducing the internal latency required
249 * to generate the high period and low period of SCL line.
250 *
251 * HCNT and LCNT parameters can be used if the platform knows more accurate
252 * values than the one computed based only on the input clock frequency.
253 * Leave them to be %0 if not used.
254 */
255 struct dw_i2c_dev {
256 struct device *dev;
257 struct regmap *map;
258 struct regmap *sysmap;
259 void __iomem *base;
260 void __iomem *ext;
261 struct completion cmd_complete;
262 struct clk *clk;
263 struct clk *pclk;
264 struct reset_control *rst;
265 struct i2c_client *slave;
266 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
267 int cmd_err;
268 struct i2c_msg *msgs;
269 int msgs_num;
270 int msg_write_idx;
271 u32 tx_buf_len;
272 u8 *tx_buf;
273 int msg_read_idx;
274 u32 rx_buf_len;
275 u8 *rx_buf;
276 int msg_err;
277 unsigned int status;
278 unsigned int abort_source;
279 unsigned int sw_mask;
280 int irq;
281 u32 flags;
282 struct i2c_adapter adapter;
283 u32 functionality;
284 u32 master_cfg;
285 u32 slave_cfg;
286 unsigned int tx_fifo_depth;
287 unsigned int rx_fifo_depth;
288 int rx_outstanding;
289 struct i2c_timings timings;
290 u32 sda_hold_time;
291 u16 ss_hcnt;
292 u16 ss_lcnt;
293 u16 fs_hcnt;
294 u16 fs_lcnt;
295 u16 fp_hcnt;
296 u16 fp_lcnt;
297 u16 hs_hcnt;
298 u16 hs_lcnt;
299 int (*acquire_lock)(void);
300 void (*release_lock)(void);
301 int semaphore_idx;
302 bool shared_with_punit;
303 int (*init)(struct dw_i2c_dev *dev);
304 int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
305 int mode;
306 struct i2c_bus_recovery_info rinfo;
307 u32 bus_capacitance_pF;
308 bool clk_freq_optimized;
309 };
310
311 #define ACCESS_INTR_MASK BIT(0)
312 #define ACCESS_NO_IRQ_SUSPEND BIT(1)
313 #define ARBITRATION_SEMAPHORE BIT(2)
314 #define ACCESS_POLLING BIT(3)
315
316 #define MODEL_MSCC_OCELOT BIT(8)
317 #define MODEL_BAIKAL_BT1 BIT(9)
318 #define MODEL_AMD_NAVI_GPU BIT(10)
319 #define MODEL_WANGXUN_SP BIT(11)
320 #define MODEL_MASK GENMASK(11, 8)
321
322 /*
323 * Enable UCSI interrupt by writing 0xd at register
324 * offset 0x474 specified in hardware specification.
325 */
326 #define AMD_UCSI_INTR_REG 0x474
327 #define AMD_UCSI_INTR_EN 0xd
328
329 #define TXGBE_TX_FIFO_DEPTH 4
330 #define TXGBE_RX_FIFO_DEPTH 1
331
332 struct i2c_dw_semaphore_callbacks {
333 int (*probe)(struct dw_i2c_dev *dev);
334 };
335
336 int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
337 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
338 u32 tSYMBOL, u32 tf, int offset);
339 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
340 u32 tLOW, u32 tf, int offset);
341 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
342 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev);
343 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
344 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
345 void i2c_dw_release_lock(struct dw_i2c_dev *dev);
346 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
347 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
348 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
349 u32 i2c_dw_func(struct i2c_adapter *adap);
350
351 extern const struct dev_pm_ops i2c_dw_dev_pm_ops;
352
__i2c_dw_enable(struct dw_i2c_dev * dev)353 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
354 {
355 dev->status |= STATUS_ACTIVE;
356 regmap_write(dev->map, DW_IC_ENABLE, 1);
357 }
358
__i2c_dw_disable_nowait(struct dw_i2c_dev * dev)359 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
360 {
361 regmap_write(dev->map, DW_IC_ENABLE, 0);
362 dev->status &= ~STATUS_ACTIVE;
363 }
364
__i2c_dw_write_intr_mask(struct dw_i2c_dev * dev,unsigned int intr_mask)365 static inline void __i2c_dw_write_intr_mask(struct dw_i2c_dev *dev,
366 unsigned int intr_mask)
367 {
368 unsigned int val = dev->flags & ACCESS_POLLING ? 0 : intr_mask;
369
370 regmap_write(dev->map, DW_IC_INTR_MASK, val);
371 dev->sw_mask = intr_mask;
372 }
373
__i2c_dw_read_intr_mask(struct dw_i2c_dev * dev,unsigned int * intr_mask)374 static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev,
375 unsigned int *intr_mask)
376 {
377 if (!(dev->flags & ACCESS_POLLING))
378 regmap_read(dev->map, DW_IC_INTR_MASK, intr_mask);
379 else
380 *intr_mask = dev->sw_mask;
381 }
382
383 void __i2c_dw_disable(struct dw_i2c_dev *dev);
384 void i2c_dw_disable(struct dw_i2c_dev *dev);
385
386 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
387 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
388
389 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
390 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
391 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
392 #else
i2c_dw_configure_slave(struct dw_i2c_dev * dev)393 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
i2c_dw_probe_slave(struct dw_i2c_dev * dev)394 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
395 #endif
396
i2c_dw_configure(struct dw_i2c_dev * dev)397 static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
398 {
399 if (i2c_detect_slave_mode(dev->dev))
400 i2c_dw_configure_slave(dev);
401 else
402 i2c_dw_configure_master(dev);
403 }
404
405 int i2c_dw_probe(struct dw_i2c_dev *dev);
406
407 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
408 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
409 #endif
410
411 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP)
412 int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev);
413 #endif
414
415 int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev);
416