1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Synopsys DesignWare I2C register definitions 4 * 5 * Copyright (C) 2026, Intel Corporation 6 */ 7 8 #ifndef __LINUX_DESIGNWARE_I2C_H 9 #define __LINUX_DESIGNWARE_I2C_H 10 11 #include <linux/bits.h> 12 13 /* 14 * Registers offset 15 */ 16 #define DW_IC_CON 0x00 17 #define DW_IC_TAR 0x04 18 #define DW_IC_SAR 0x08 19 #define DW_IC_DATA_CMD 0x10 20 #define DW_IC_SS_SCL_HCNT 0x14 21 #define DW_IC_SS_SCL_LCNT 0x18 22 #define DW_IC_FS_SCL_HCNT 0x1c 23 #define DW_IC_FS_SCL_LCNT 0x20 24 #define DW_IC_HS_SCL_HCNT 0x24 25 #define DW_IC_HS_SCL_LCNT 0x28 26 #define DW_IC_INTR_STAT 0x2c 27 #define DW_IC_INTR_MASK 0x30 28 #define DW_IC_RAW_INTR_STAT 0x34 29 #define DW_IC_RX_TL 0x38 30 #define DW_IC_TX_TL 0x3c 31 #define DW_IC_CLR_INTR 0x40 32 #define DW_IC_CLR_RX_UNDER 0x44 33 #define DW_IC_CLR_RX_OVER 0x48 34 #define DW_IC_CLR_TX_OVER 0x4c 35 #define DW_IC_CLR_RD_REQ 0x50 36 #define DW_IC_CLR_TX_ABRT 0x54 37 #define DW_IC_CLR_RX_DONE 0x58 38 #define DW_IC_CLR_ACTIVITY 0x5c 39 #define DW_IC_CLR_STOP_DET 0x60 40 #define DW_IC_CLR_START_DET 0x64 41 #define DW_IC_CLR_GEN_CALL 0x68 42 #define DW_IC_ENABLE 0x6c 43 #define DW_IC_STATUS 0x70 44 #define DW_IC_TXFLR 0x74 45 #define DW_IC_RXFLR 0x78 46 #define DW_IC_SDA_HOLD 0x7c 47 #define DW_IC_TX_ABRT_SOURCE 0x80 48 #define DW_IC_ENABLE_STATUS 0x9c 49 #define DW_IC_CLR_RESTART_DET 0xa8 50 #define DW_IC_SMBUS_INTR_STAT 0xc8 51 #define DW_IC_SMBUS_INTR_MASK 0xcc 52 #define DW_IC_CLR_SMBUS_INTR 0xd4 53 #define DW_IC_COMP_PARAM_1 0xf4 54 #define DW_IC_COMP_VERSION 0xf8 55 #define DW_IC_COMP_TYPE 0xfc 56 57 /* DW_IC_CON bits */ 58 #define DW_IC_CON_MASTER BIT(0) 59 #define DW_IC_CON_SPEED_STD (1 << 1) 60 #define DW_IC_CON_SPEED_FAST (2 << 1) 61 #define DW_IC_CON_SPEED_HIGH (3 << 1) 62 #define DW_IC_CON_SPEED_MASK GENMASK(2, 1) 63 #define DW_IC_CON_10BITADDR_SLAVE BIT(3) 64 #define DW_IC_CON_10BITADDR_MASTER BIT(4) 65 #define DW_IC_CON_RESTART_EN BIT(5) 66 #define DW_IC_CON_SLAVE_DISABLE BIT(6) 67 #define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) 68 #define DW_IC_CON_TX_EMPTY_CTRL BIT(8) 69 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) 70 #define DW_IC_CON_BUS_CLEAR_CTRL BIT(11) 71 72 /* DW_IC_DATA_CMD bits */ 73 #define DW_IC_DATA_CMD_DAT GENMASK(7, 0) 74 #define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) 75 76 /* DW_IC_INTR_* bits */ 77 #define DW_IC_INTR_RX_UNDER BIT(0) 78 #define DW_IC_INTR_RX_OVER BIT(1) 79 #define DW_IC_INTR_RX_FULL BIT(2) 80 #define DW_IC_INTR_TX_OVER BIT(3) 81 #define DW_IC_INTR_TX_EMPTY BIT(4) 82 #define DW_IC_INTR_RD_REQ BIT(5) 83 #define DW_IC_INTR_TX_ABRT BIT(6) 84 #define DW_IC_INTR_RX_DONE BIT(7) 85 #define DW_IC_INTR_ACTIVITY BIT(8) 86 #define DW_IC_INTR_STOP_DET BIT(9) 87 #define DW_IC_INTR_START_DET BIT(10) 88 #define DW_IC_INTR_GEN_CALL BIT(11) 89 #define DW_IC_INTR_RESTART_DET BIT(12) 90 #define DW_IC_INTR_MST_ON_HOLD BIT(13) 91 92 /* DW_IC_ENABLE bits */ 93 #define DW_IC_ENABLE_ENABLE BIT(0) 94 #define DW_IC_ENABLE_ABORT BIT(1) 95 96 /* DW_IC_STATUS bits */ 97 #define DW_IC_STATUS_ACTIVITY BIT(0) 98 #define DW_IC_STATUS_TFE BIT(2) 99 #define DW_IC_STATUS_RFNE BIT(3) 100 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 101 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 102 #define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7) 103 104 /* DW_IC_SMBUS_INTR_* bits */ 105 #define DW_IC_SMBUS_INTR_ALERT BIT(10) 106 107 #endif /* __LINUX_DESIGNWARE_I2C_H */ 108