1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare Cores DisplayPort Transmitter Controller
4 *
5 * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
6 *
7 * Author: Andy Yan <andy.yan@rock-chips.com>
8 */
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/iopoll.h>
12 #include <linux/irq.h>
13 #include <linux/media-bus-format.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/phy/phy.h>
19 #include <linux/unaligned.h>
20
21 #include <drm/bridge/dw_dp.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_bridge_connector.h>
25 #include <drm/display/drm_dp_helper.h>
26 #include <drm/drm_edid.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_print.h>
29 #include <drm/drm_probe_helper.h>
30 #include <drm/drm_simple_kms_helper.h>
31
32 #define DW_DP_VERSION_NUMBER 0x0000
33 #define DW_DP_VERSION_TYPE 0x0004
34 #define DW_DP_ID 0x0008
35
36 #define DW_DP_CONFIG_REG1 0x0100
37 #define DW_DP_CONFIG_REG2 0x0104
38 #define DW_DP_CONFIG_REG3 0x0108
39
40 #define DW_DP_CCTL 0x0200
41 #define FORCE_HPD BIT(4)
42 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2)
43 #define ENHANCE_FRAMING_EN BIT(1)
44 #define SCRAMBLE_DIS BIT(0)
45 #define DW_DP_SOFT_RESET_CTRL 0x0204
46 #define VIDEO_RESET BIT(5)
47 #define AUX_RESET BIT(4)
48 #define AUDIO_SAMPLER_RESET BIT(3)
49 #define HDCP_MODULE_RESET BIT(2)
50 #define PHY_SOFT_RESET BIT(1)
51 #define CONTROLLER_RESET BIT(0)
52
53 #define DW_DP_VSAMPLE_CTRL 0x0300
54 #define PIXEL_MODE_SELECT GENMASK(22, 21)
55 #define VIDEO_MAPPING GENMASK(20, 16)
56 #define VIDEO_STREAM_ENABLE BIT(5)
57
58 #define DW_DP_VSAMPLE_STUFF_CTRL1 0x0304
59
60 #define DW_DP_VSAMPLE_STUFF_CTRL2 0x0308
61
62 #define DW_DP_VINPUT_POLARITY_CTRL 0x030c
63 #define DE_IN_POLARITY BIT(2)
64 #define HSYNC_IN_POLARITY BIT(1)
65 #define VSYNC_IN_POLARITY BIT(0)
66
67 #define DW_DP_VIDEO_CONFIG1 0x0310
68 #define HACTIVE GENMASK(31, 16)
69 #define HBLANK GENMASK(15, 2)
70 #define I_P BIT(1)
71 #define R_V_BLANK_IN_OSC BIT(0)
72
73 #define DW_DP_VIDEO_CONFIG2 0x0314
74 #define VBLANK GENMASK(31, 16)
75 #define VACTIVE GENMASK(15, 0)
76
77 #define DW_DP_VIDEO_CONFIG3 0x0318
78 #define H_SYNC_WIDTH GENMASK(31, 16)
79 #define H_FRONT_PORCH GENMASK(15, 0)
80
81 #define DW_DP_VIDEO_CONFIG4 0x031c
82 #define V_SYNC_WIDTH GENMASK(31, 16)
83 #define V_FRONT_PORCH GENMASK(15, 0)
84
85 #define DW_DP_VIDEO_CONFIG5 0x0320
86 #define INIT_THRESHOLD_HI GENMASK(22, 21)
87 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16)
88 #define INIT_THRESHOLD GENMASK(13, 7)
89 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0)
90
91 #define DW_DP_VIDEO_MSA1 0x0324
92 #define VSTART GENMASK(31, 16)
93 #define HSTART GENMASK(15, 0)
94
95 #define DW_DP_VIDEO_MSA2 0x0328
96 #define MISC0 GENMASK(31, 24)
97
98 #define DW_DP_VIDEO_MSA3 0x032c
99 #define MISC1 GENMASK(31, 24)
100
101 #define DW_DP_VIDEO_HBLANK_INTERVAL 0x0330
102 #define HBLANK_INTERVAL_EN BIT(16)
103 #define HBLANK_INTERVAL GENMASK(15, 0)
104
105 #define DW_DP_AUD_CONFIG1 0x0400
106 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24)
107 #define AUDIO_PACKET_ID GENMASK(23, 16)
108 #define AUDIO_MUTE BIT(15)
109 #define NUM_CHANNELS GENMASK(14, 12)
110 #define HBR_MODE_ENABLE BIT(10)
111 #define AUDIO_DATA_WIDTH GENMASK(9, 5)
112 #define AUDIO_DATA_IN_EN GENMASK(4, 1)
113 #define AUDIO_INF_SELECT BIT(0)
114
115 #define DW_DP_SDP_VERTICAL_CTRL 0x0500
116 #define EN_VERTICAL_SDP BIT(2)
117 #define EN_AUDIO_STREAM_SDP BIT(1)
118 #define EN_AUDIO_TIMESTAMP_SDP BIT(0)
119 #define DW_DP_SDP_HORIZONTAL_CTRL 0x0504
120 #define EN_HORIZONTAL_SDP BIT(2)
121 #define DW_DP_SDP_STATUS_REGISTER 0x0508
122 #define DW_DP_SDP_MANUAL_CTRL 0x050c
123 #define DW_DP_SDP_STATUS_EN 0x0510
124
125 #define DW_DP_SDP_REGISTER_BANK 0x0600
126 #define SDP_REGS GENMASK(31, 0)
127
128 #define DW_DP_PHYIF_CTRL 0x0a00
129 #define PHY_WIDTH BIT(25)
130 #define PHY_POWERDOWN GENMASK(20, 17)
131 #define PHY_BUSY GENMASK(15, 12)
132 #define SSC_DIS BIT(16)
133 #define XMIT_ENABLE GENMASK(11, 8)
134 #define PHY_LANES GENMASK(7, 6)
135 #define PHY_RATE GENMASK(5, 4)
136 #define TPS_SEL GENMASK(3, 0)
137
138 #define DW_DP_PHY_TX_EQ 0x0a04
139 #define DW_DP_CUSTOMPAT0 0x0a08
140 #define DW_DP_CUSTOMPAT1 0x0a0c
141 #define DW_DP_CUSTOMPAT2 0x0a10
142 #define DW_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14
143 #define DW_DP_PHYIF_PWRDOWN_CTRL 0x0a18
144
145 #define DW_DP_AUX_CMD 0x0b00
146 #define AUX_CMD_TYPE GENMASK(31, 28)
147 #define AUX_ADDR GENMASK(27, 8)
148 #define I2C_ADDR_ONLY BIT(4)
149 #define AUX_LEN_REQ GENMASK(3, 0)
150
151 #define DW_DP_AUX_STATUS 0x0b04
152 #define AUX_TIMEOUT BIT(17)
153 #define AUX_BYTES_READ GENMASK(23, 19)
154 #define AUX_STATUS GENMASK(7, 4)
155
156 #define DW_DP_AUX_DATA0 0x0b08
157 #define DW_DP_AUX_DATA1 0x0b0c
158 #define DW_DP_AUX_DATA2 0x0b10
159 #define DW_DP_AUX_DATA3 0x0b14
160
161 #define DW_DP_GENERAL_INTERRUPT 0x0d00
162 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6)
163 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5)
164 #define SDP_EVENT_STREAM0 BIT(4)
165 #define AUX_CMD_INVALID BIT(3)
166 #define HDCP_EVENT BIT(2)
167 #define AUX_REPLY_EVENT BIT(1)
168 #define HPD_EVENT BIT(0)
169
170 #define DW_DP_GENERAL_INTERRUPT_ENABLE 0x0d04
171 #define HDCP_EVENT_EN BIT(2)
172 #define AUX_REPLY_EVENT_EN BIT(1)
173 #define HPD_EVENT_EN BIT(0)
174
175 #define DW_DP_HPD_STATUS 0x0d08
176 #define HPD_STATE GENMASK(11, 9)
177 #define HPD_STATUS BIT(8)
178 #define HPD_HOT_UNPLUG BIT(2)
179 #define HPD_HOT_PLUG BIT(1)
180 #define HPD_IRQ BIT(0)
181
182 #define DW_DP_HPD_INTERRUPT_ENABLE 0x0d0c
183 #define HPD_UNPLUG_ERR_EN BIT(3)
184 #define HPD_UNPLUG_EN BIT(2)
185 #define HPD_PLUG_EN BIT(1)
186 #define HPD_IRQ_EN BIT(0)
187
188 #define DW_DP_HDCP_CFG 0x0e00
189 #define DPCD12PLUS BIT(7)
190 #define CP_IRQ BIT(6)
191 #define BYPENCRYPTION BIT(5)
192 #define HDCP_LOCK BIT(4)
193 #define ENCRYPTIONDISABLE BIT(3)
194 #define ENABLE_HDCP_13 BIT(2)
195 #define ENABLE_HDCP BIT(1)
196
197 #define DW_DP_HDCP_OBS 0x0e04
198 #define HDCP22_RE_AUTHENTICATION_REQ BIT(31)
199 #define HDCP22_AUTHENTICATION_FAILED BIT(30)
200 #define HDCP22_AUTHENTICATION_SUCCESS BIT(29)
201 #define HDCP22_CAPABLE_SINK BIT(28)
202 #define HDCP22_SINK_CAP_CHECK_COMPLETE BIT(27)
203 #define HDCP22_STATE GENMASK(26, 24)
204 #define HDCP22_BOOTED BIT(23)
205 #define HDCP13_BSTATUS GENMASK(22, 19)
206 #define REPEATER BIT(18)
207 #define HDCP_CAPABLE BIT(17)
208 #define STATEE GENMASK(16, 14)
209 #define STATEOEG GENMASK(13, 11)
210 #define STATER GENMASK(10, 8)
211 #define STATEA GENMASK(7, 4)
212 #define SUBSTATEA GENMASK(3, 1)
213 #define HDCPENGAGED BIT(0)
214
215 #define DW_DP_HDCP_APIINTCLR 0x0e08
216 #define DW_DP_HDCP_APIINTSTAT 0x0e0c
217 #define DW_DP_HDCP_APIINTMSK 0x0e10
218 #define HDCP22_GPIOINT BIT(8)
219 #define HDCP_ENGAGED BIT(7)
220 #define HDCP_FAILED BIT(6)
221 #define KSVSHA1CALCDONEINT BIT(5)
222 #define AUXRESPNACK7TIMES BIT(4)
223 #define AUXRESPTIMEOUT BIT(3)
224 #define AUXRESPDEFER7TIMES BIT(2)
225 #define KSVACCESSINT BIT(0)
226
227 #define DW_DP_HDCP_KSVMEMCTRL 0x0e18
228 #define KSVSHA1STATUS BIT(4)
229 #define KSVMEMACCESS BIT(1)
230 #define KSVMEMREQUEST BIT(0)
231
232 #define DW_DP_HDCP_REG_BKSV0 0x3600
233 #define DW_DP_HDCP_REG_BKSV1 0x3604
234 #define DW_DP_HDCP_REG_ANCONF 0x3608
235 #define AN_BYPASS BIT(0)
236
237 #define DW_DP_HDCP_REG_AN0 0x360c
238 #define DW_DP_HDCP_REG_AN1 0x3610
239 #define DW_DP_HDCP_REG_RMLCTL 0x3614
240 #define ODPK_DECRYPT_ENABLE BIT(0)
241
242 #define DW_DP_HDCP_REG_RMLSTS 0x3618
243 #define IDPK_WR_OK_STS BIT(6)
244 #define IDPK_DATA_INDEX GENMASK(5, 0)
245 #define DW_DP_HDCP_REG_SEED 0x361c
246 #define DW_DP_HDCP_REG_DPK0 0x3620
247 #define DW_DP_HDCP_REG_DPK1 0x3624
248 #define DW_DP_HDCP22_GPIOSTS 0x3628
249 #define DW_DP_HDCP22_GPIOCHNGSTS 0x362c
250 #define DW_DP_HDCP_REG_DPK_CRC 0x3630
251
252 #define DW_DP_MAX_REGISTER DW_DP_HDCP_REG_DPK_CRC
253
254 #define SDP_REG_BANK_SIZE 16
255
256 struct dw_dp_link_caps {
257 bool enhanced_framing;
258 bool tps3_supported;
259 bool tps4_supported;
260 bool fast_training;
261 bool channel_coding;
262 bool ssc;
263 };
264
265 struct dw_dp_link_train_set {
266 unsigned int voltage_swing[4];
267 unsigned int pre_emphasis[4];
268 bool voltage_max_reached[4];
269 bool pre_max_reached[4];
270 };
271
272 struct dw_dp_link_train {
273 struct dw_dp_link_train_set adjust;
274 bool clock_recovered;
275 bool channel_equalized;
276 };
277
278 struct dw_dp_link {
279 u8 dpcd[DP_RECEIVER_CAP_SIZE];
280 unsigned char revision;
281 unsigned int rate;
282 unsigned int lanes;
283 u8 sink_count;
284 u8 vsc_sdp_supported;
285 struct dw_dp_link_caps caps;
286 struct dw_dp_link_train train;
287 struct drm_dp_desc desc;
288 };
289
290 struct dw_dp_bridge_state {
291 struct drm_bridge_state base;
292 struct drm_display_mode mode;
293 u8 video_mapping;
294 u8 color_format;
295 u8 bpc;
296 u8 bpp;
297 };
298
299 struct dw_dp_sdp {
300 struct dp_sdp base;
301 unsigned long flags;
302 };
303
304 struct dw_dp_hotplug {
305 bool long_hpd;
306 };
307
308 struct dw_dp {
309 struct drm_bridge bridge;
310 struct device *dev;
311 struct regmap *regmap;
312 struct phy *phy;
313 struct clk *apb_clk;
314 struct clk *aux_clk;
315 struct clk *i2s_clk;
316 struct clk *spdif_clk;
317 struct clk *hdcp_clk;
318 struct reset_control *rstc;
319 struct completion complete;
320 int irq;
321 struct work_struct hpd_work;
322 struct dw_dp_hotplug hotplug;
323 /* Serialize hpd status access */
324 struct mutex irq_lock;
325
326 struct drm_dp_aux aux;
327
328 struct dw_dp_link link;
329 struct dw_dp_plat_data plat_data;
330 u8 pixel_mode;
331
332 DECLARE_BITMAP(sdp_reg_bank, SDP_REG_BANK_SIZE);
333 };
334
335 enum {
336 DW_DP_RGB_6BIT,
337 DW_DP_RGB_8BIT,
338 DW_DP_RGB_10BIT,
339 DW_DP_RGB_12BIT,
340 DW_DP_RGB_16BIT,
341 DW_DP_YCBCR444_8BIT,
342 DW_DP_YCBCR444_10BIT,
343 DW_DP_YCBCR444_12BIT,
344 DW_DP_YCBCR444_16BIT,
345 DW_DP_YCBCR422_8BIT,
346 DW_DP_YCBCR422_10BIT,
347 DW_DP_YCBCR422_12BIT,
348 DW_DP_YCBCR422_16BIT,
349 DW_DP_YCBCR420_8BIT,
350 DW_DP_YCBCR420_10BIT,
351 DW_DP_YCBCR420_12BIT,
352 DW_DP_YCBCR420_16BIT,
353 };
354
355 enum {
356 DW_DP_SDP_VERTICAL_INTERVAL = BIT(0),
357 DW_DP_SDP_HORIZONTAL_INTERVAL = BIT(1),
358 };
359
360 enum {
361 DW_DP_HPD_STATE_IDLE,
362 DW_DP_HPD_STATE_UNPLUG,
363 DP_DP_HPD_STATE_TIMEOUT = 4,
364 DW_DP_HPD_STATE_PLUG = 7
365 };
366
367 enum {
368 DW_DP_PHY_PATTERN_NONE,
369 DW_DP_PHY_PATTERN_TPS_1,
370 DW_DP_PHY_PATTERN_TPS_2,
371 DW_DP_PHY_PATTERN_TPS_3,
372 DW_DP_PHY_PATTERN_TPS_4,
373 DW_DP_PHY_PATTERN_SERM,
374 DW_DP_PHY_PATTERN_PBRS7,
375 DW_DP_PHY_PATTERN_CUSTOM_80BIT,
376 DW_DP_PHY_PATTERN_CP2520_1,
377 DW_DP_PHY_PATTERN_CP2520_2,
378 };
379
380 struct dw_dp_output_format {
381 u32 bus_format;
382 enum drm_output_color_format color_format;
383 u8 video_mapping;
384 u8 bpc;
385 u8 bpp;
386 };
387
388 #define to_dw_dp_bridge_state(s) container_of(s, struct dw_dp_bridge_state, base)
389
390 static const struct dw_dp_output_format dw_dp_output_formats[] = {
391 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_OUTPUT_COLOR_FORMAT_RGB444, DW_DP_RGB_10BIT, 10, 30 },
392 { MEDIA_BUS_FMT_RGB888_1X24, DRM_OUTPUT_COLOR_FORMAT_RGB444, DW_DP_RGB_8BIT, 8, 24 },
393 { MEDIA_BUS_FMT_YUV10_1X30, DRM_OUTPUT_COLOR_FORMAT_YCBCR444, DW_DP_YCBCR444_10BIT, 10, 30 },
394 { MEDIA_BUS_FMT_YUV8_1X24, DRM_OUTPUT_COLOR_FORMAT_YCBCR444, DW_DP_YCBCR444_8BIT, 8, 24},
395 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_OUTPUT_COLOR_FORMAT_YCBCR422, DW_DP_YCBCR422_10BIT, 10, 20 },
396 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_OUTPUT_COLOR_FORMAT_YCBCR422, DW_DP_YCBCR422_8BIT, 8, 16 },
397 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_OUTPUT_COLOR_FORMAT_YCBCR420, DW_DP_YCBCR420_10BIT, 10, 15 },
398 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_OUTPUT_COLOR_FORMAT_YCBCR420, DW_DP_YCBCR420_8BIT, 8, 12 },
399 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_OUTPUT_COLOR_FORMAT_RGB444, DW_DP_RGB_6BIT, 6, 18 },
400 };
401
dw_dp_get_output_format(u32 bus_format)402 static const struct dw_dp_output_format *dw_dp_get_output_format(u32 bus_format)
403 {
404 unsigned int i;
405
406 for (i = 0; i < ARRAY_SIZE(dw_dp_output_formats); i++)
407 if (dw_dp_output_formats[i].bus_format == bus_format)
408 return &dw_dp_output_formats[i];
409
410 return NULL;
411 }
412
bridge_to_dp(struct drm_bridge * b)413 static inline struct dw_dp *bridge_to_dp(struct drm_bridge *b)
414 {
415 return container_of(b, struct dw_dp, bridge);
416 }
417
dw_dp_get_bridge_state(struct dw_dp * dp)418 static struct dw_dp_bridge_state *dw_dp_get_bridge_state(struct dw_dp *dp)
419 {
420 struct dw_dp_bridge_state *dw_bridge_state;
421 struct drm_bridge_state *state;
422
423 state = drm_priv_to_bridge_state(dp->bridge.base.state);
424 if (!state)
425 return NULL;
426
427 dw_bridge_state = to_dw_dp_bridge_state(state);
428 if (!dw_bridge_state)
429 return NULL;
430
431 return dw_bridge_state;
432 }
433
dw_dp_phy_set_pattern(struct dw_dp * dp,u32 pattern)434 static inline void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern)
435 {
436 regmap_update_bits(dp->regmap, DW_DP_PHYIF_CTRL, TPS_SEL,
437 FIELD_PREP(TPS_SEL, pattern));
438 }
439
dw_dp_phy_xmit_enable(struct dw_dp * dp,u32 lanes)440 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes)
441 {
442 u32 xmit_enable;
443
444 switch (lanes) {
445 case 4:
446 case 2:
447 case 1:
448 xmit_enable = GENMASK(lanes - 1, 0);
449 break;
450 case 0:
451 default:
452 xmit_enable = 0;
453 break;
454 }
455
456 regmap_update_bits(dp->regmap, DW_DP_PHYIF_CTRL, XMIT_ENABLE,
457 FIELD_PREP(XMIT_ENABLE, xmit_enable));
458 }
459
dw_dp_bandwidth_ok(struct dw_dp * dp,const struct drm_display_mode * mode,u32 bpp,unsigned int lanes,unsigned int rate)460 static bool dw_dp_bandwidth_ok(struct dw_dp *dp,
461 const struct drm_display_mode *mode, u32 bpp,
462 unsigned int lanes, unsigned int rate)
463 {
464 u32 max_bw, req_bw;
465
466 req_bw = mode->clock * bpp / 8;
467 max_bw = lanes * rate;
468 if (req_bw > max_bw)
469 return false;
470
471 return true;
472 }
473
dw_dp_hpd_detect(struct dw_dp * dp)474 static bool dw_dp_hpd_detect(struct dw_dp *dp)
475 {
476 u32 value;
477
478 regmap_read(dp->regmap, DW_DP_HPD_STATUS, &value);
479
480 return FIELD_GET(HPD_STATE, value) == DW_DP_HPD_STATE_PLUG;
481 }
482
dw_dp_link_caps_reset(struct dw_dp_link_caps * caps)483 static void dw_dp_link_caps_reset(struct dw_dp_link_caps *caps)
484 {
485 caps->enhanced_framing = false;
486 caps->tps3_supported = false;
487 caps->tps4_supported = false;
488 caps->fast_training = false;
489 caps->channel_coding = false;
490 }
491
dw_dp_link_reset(struct dw_dp_link * link)492 static void dw_dp_link_reset(struct dw_dp_link *link)
493 {
494 link->vsc_sdp_supported = 0;
495 link->sink_count = 0;
496 link->revision = 0;
497 link->rate = 0;
498 link->lanes = 0;
499
500 dw_dp_link_caps_reset(&link->caps);
501 memset(link->dpcd, 0, sizeof(link->dpcd));
502 }
503
dw_dp_link_parse(struct dw_dp * dp,struct drm_connector * connector)504 static int dw_dp_link_parse(struct dw_dp *dp, struct drm_connector *connector)
505 {
506 struct dw_dp_link *link = &dp->link;
507 int ret;
508
509 dw_dp_link_reset(link);
510
511 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);
512 if (ret < 0)
513 return ret;
514
515 drm_dp_read_desc(&dp->aux, &link->desc, drm_dp_is_branch(link->dpcd));
516
517 if (drm_dp_read_sink_count_cap(connector, link->dpcd, &link->desc)) {
518 ret = drm_dp_read_sink_count(&dp->aux);
519 if (ret < 0)
520 return ret;
521
522 link->sink_count = ret;
523
524 /* Dongle connected, but no display */
525 if (!link->sink_count)
526 return -ENODEV;
527 }
528
529 link->vsc_sdp_supported = drm_dp_vsc_sdp_supported(&dp->aux, link->dpcd);
530
531 link->revision = link->dpcd[DP_DPCD_REV];
532 link->rate = min_t(u32, min(dp->plat_data.max_link_rate,
533 dp->phy->attrs.max_link_rate * 100),
534 drm_dp_max_link_rate(link->dpcd));
535 link->lanes = min_t(u8, phy_get_bus_width(dp->phy),
536 drm_dp_max_lane_count(link->dpcd));
537
538 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd);
539 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd);
540 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd);
541 link->caps.fast_training = drm_dp_fast_training_cap(link->dpcd);
542 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd);
543 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
544
545 return 0;
546 }
547
dw_dp_link_train_update_vs_emph(struct dw_dp * dp)548 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp)
549 {
550 struct dw_dp_link *link = &dp->link;
551 struct dw_dp_link_train_set *train_set = &link->train.adjust;
552 unsigned int lanes = dp->link.lanes;
553 union phy_configure_opts phy_cfg;
554 unsigned int *vs, *pe;
555 int i, ret;
556 u8 buf[4];
557
558 vs = train_set->voltage_swing;
559 pe = train_set->pre_emphasis;
560
561 for (i = 0; i < lanes; i++) {
562 phy_cfg.dp.voltage[i] = vs[i];
563 phy_cfg.dp.pre[i] = pe[i];
564 }
565
566 phy_cfg.dp.set_lanes = false;
567 phy_cfg.dp.set_rate = false;
568 phy_cfg.dp.set_voltages = true;
569
570 ret = phy_configure(dp->phy, &phy_cfg);
571 if (ret)
572 return ret;
573
574 for (i = 0; i < lanes; i++) {
575 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) |
576 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT);
577 if (train_set->voltage_max_reached[i])
578 buf[i] |= DP_TRAIN_MAX_SWING_REACHED;
579 if (train_set->pre_max_reached[i])
580 buf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
581 }
582
583 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes);
584 if (ret < 0)
585 return ret;
586
587 return 0;
588 }
589
dw_dp_phy_configure(struct dw_dp * dp,unsigned int rate,unsigned int lanes,bool ssc)590 static int dw_dp_phy_configure(struct dw_dp *dp, unsigned int rate,
591 unsigned int lanes, bool ssc)
592 {
593 union phy_configure_opts phy_cfg;
594 int ret;
595
596 /* Move PHY to P3 */
597 regmap_update_bits(dp->regmap, DW_DP_PHYIF_CTRL, PHY_POWERDOWN,
598 FIELD_PREP(PHY_POWERDOWN, 0x3));
599
600 phy_cfg.dp.lanes = lanes;
601 phy_cfg.dp.link_rate = rate / 100;
602 phy_cfg.dp.ssc = ssc;
603 phy_cfg.dp.set_lanes = true;
604 phy_cfg.dp.set_rate = true;
605 phy_cfg.dp.set_voltages = false;
606 ret = phy_configure(dp->phy, &phy_cfg);
607 if (ret)
608 return ret;
609
610 regmap_update_bits(dp->regmap, DW_DP_PHYIF_CTRL, PHY_LANES,
611 FIELD_PREP(PHY_LANES, lanes / 2));
612
613 /* Move PHY to P0 */
614 regmap_update_bits(dp->regmap, DW_DP_PHYIF_CTRL, PHY_POWERDOWN,
615 FIELD_PREP(PHY_POWERDOWN, 0x0));
616
617 dw_dp_phy_xmit_enable(dp, lanes);
618
619 return 0;
620 }
621
dw_dp_link_configure(struct dw_dp * dp)622 static int dw_dp_link_configure(struct dw_dp *dp)
623 {
624 struct dw_dp_link *link = &dp->link;
625 u8 buf[2];
626 int ret;
627
628 ret = dw_dp_phy_configure(dp, link->rate, link->lanes, link->caps.ssc);
629 if (ret)
630 return ret;
631
632 buf[0] = drm_dp_link_rate_to_bw_code(link->rate);
633 buf[1] = link->lanes;
634
635 if (link->caps.enhanced_framing) {
636 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
637 regmap_update_bits(dp->regmap, DW_DP_CCTL, ENHANCE_FRAMING_EN,
638 FIELD_PREP(ENHANCE_FRAMING_EN, 1));
639 } else {
640 regmap_update_bits(dp->regmap, DW_DP_CCTL, ENHANCE_FRAMING_EN,
641 FIELD_PREP(ENHANCE_FRAMING_EN, 0));
642 }
643
644 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
645 if (ret < 0)
646 return ret;
647
648 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0;
649 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0;
650
651 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));
652 if (ret < 0)
653 return ret;
654
655 return 0;
656 }
657
dw_dp_link_train_init(struct dw_dp_link_train * train)658 static void dw_dp_link_train_init(struct dw_dp_link_train *train)
659 {
660 struct dw_dp_link_train_set *adj = &train->adjust;
661 unsigned int i;
662
663 for (i = 0; i < 4; i++) {
664 adj->voltage_swing[i] = 0;
665 adj->pre_emphasis[i] = 0;
666 adj->voltage_max_reached[i] = false;
667 adj->pre_max_reached[i] = false;
668 }
669
670 train->clock_recovered = false;
671 train->channel_equalized = false;
672 }
673
dw_dp_link_train_valid(const struct dw_dp_link_train * train)674 static bool dw_dp_link_train_valid(const struct dw_dp_link_train *train)
675 {
676 return train->clock_recovered && train->channel_equalized;
677 }
678
dw_dp_link_train_set_pattern(struct dw_dp * dp,u32 pattern)679 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern)
680 {
681 u8 buf = 0;
682 int ret;
683
684 if (pattern && pattern != DP_TRAINING_PATTERN_4) {
685 buf |= DP_LINK_SCRAMBLING_DISABLE;
686
687 regmap_update_bits(dp->regmap, DW_DP_CCTL, SCRAMBLE_DIS,
688 FIELD_PREP(SCRAMBLE_DIS, 1));
689 } else {
690 regmap_update_bits(dp->regmap, DW_DP_CCTL, SCRAMBLE_DIS,
691 FIELD_PREP(SCRAMBLE_DIS, 0));
692 }
693
694 switch (pattern) {
695 case DP_TRAINING_PATTERN_DISABLE:
696 dw_dp_phy_set_pattern(dp, DW_DP_PHY_PATTERN_NONE);
697 break;
698 case DP_TRAINING_PATTERN_1:
699 dw_dp_phy_set_pattern(dp, DW_DP_PHY_PATTERN_TPS_1);
700 break;
701 case DP_TRAINING_PATTERN_2:
702 dw_dp_phy_set_pattern(dp, DW_DP_PHY_PATTERN_TPS_2);
703 break;
704 case DP_TRAINING_PATTERN_3:
705 dw_dp_phy_set_pattern(dp, DW_DP_PHY_PATTERN_TPS_3);
706 break;
707 case DP_TRAINING_PATTERN_4:
708 dw_dp_phy_set_pattern(dp, DW_DP_PHY_PATTERN_TPS_4);
709 break;
710 default:
711 return -EINVAL;
712 }
713
714 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
715 buf | pattern);
716 if (ret < 0)
717 return ret;
718
719 return 0;
720 }
721
dw_dp_voltage_max(u8 preemph)722 static u8 dw_dp_voltage_max(u8 preemph)
723 {
724 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
725 case DP_TRAIN_PRE_EMPH_LEVEL_0:
726 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
727 case DP_TRAIN_PRE_EMPH_LEVEL_1:
728 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
729 case DP_TRAIN_PRE_EMPH_LEVEL_2:
730 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
731 case DP_TRAIN_PRE_EMPH_LEVEL_3:
732 default:
733 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
734 }
735 }
736
dw_dp_link_get_adjustments(struct dw_dp_link * link,u8 status[DP_LINK_STATUS_SIZE])737 static bool dw_dp_link_get_adjustments(struct dw_dp_link *link,
738 u8 status[DP_LINK_STATUS_SIZE])
739 {
740 struct dw_dp_link_train_set *adj = &link->train.adjust;
741 unsigned int i;
742 bool changed = false;
743 u8 v = 0;
744 u8 p = 0;
745
746 for (i = 0; i < link->lanes; i++) {
747 v = drm_dp_get_adjust_request_voltage(status, i);
748 v >>= DP_TRAIN_VOLTAGE_SWING_SHIFT;
749 p = drm_dp_get_adjust_request_pre_emphasis(status, i);
750 p >>= DP_TRAIN_PRE_EMPHASIS_SHIFT;
751
752 if (v != adj->voltage_swing[i] || p != adj->pre_emphasis[i])
753 changed = true;
754
755 if (p >= (DP_TRAIN_PRE_EMPH_LEVEL_3 >> DP_TRAIN_PRE_EMPHASIS_SHIFT)) {
756 adj->pre_emphasis[i] = DP_TRAIN_PRE_EMPH_LEVEL_3 >>
757 DP_TRAIN_PRE_EMPHASIS_SHIFT;
758 adj->pre_max_reached[i] = true;
759 } else {
760 adj->pre_emphasis[i] = p;
761 adj->pre_max_reached[i] = false;
762 }
763
764 v = min(v, dw_dp_voltage_max(p));
765 if (v >= (DP_TRAIN_VOLTAGE_SWING_LEVEL_3 >> DP_TRAIN_VOLTAGE_SWING_SHIFT)) {
766 adj->voltage_swing[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 >>
767 DP_TRAIN_VOLTAGE_SWING_SHIFT;
768 adj->voltage_max_reached[i] = true;
769 } else {
770 adj->voltage_swing[i] = v;
771 adj->voltage_max_reached[i] = false;
772 }
773 }
774
775 return changed;
776 }
777
dw_dp_link_clock_recovery(struct dw_dp * dp)778 static int dw_dp_link_clock_recovery(struct dw_dp *dp)
779 {
780 struct dw_dp_link *link = &dp->link;
781 u8 status[DP_LINK_STATUS_SIZE];
782 unsigned int tries = 0;
783 int ret;
784 bool adj_changed;
785
786 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
787 if (ret)
788 return ret;
789
790 for (;;) {
791 ret = dw_dp_link_train_update_vs_emph(dp);
792 if (ret)
793 return ret;
794
795 drm_dp_link_train_clock_recovery_delay(&dp->aux, link->dpcd);
796
797 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
798 if (ret < 0) {
799 dev_err(dp->dev, "failed to read link status: %d\n", ret);
800 return ret;
801 }
802
803 if (drm_dp_clock_recovery_ok(status, link->lanes)) {
804 link->train.clock_recovered = true;
805 break;
806 }
807
808 /*
809 * According to DP spec 1.4, if current ADJ is the same
810 * with previous REQ, we need to retry 5 times.
811 */
812 adj_changed = dw_dp_link_get_adjustments(link, status);
813 if (!adj_changed)
814 tries++;
815 else
816 tries = 0;
817
818 if (tries == 5)
819 break;
820 }
821
822 return 0;
823 }
824
dw_dp_link_channel_equalization(struct dw_dp * dp)825 static int dw_dp_link_channel_equalization(struct dw_dp *dp)
826 {
827 struct dw_dp_link *link = &dp->link;
828 u8 status[DP_LINK_STATUS_SIZE], pattern;
829 unsigned int tries;
830 int ret;
831
832 if (link->caps.tps4_supported)
833 pattern = DP_TRAINING_PATTERN_4;
834 else if (link->caps.tps3_supported)
835 pattern = DP_TRAINING_PATTERN_3;
836 else
837 pattern = DP_TRAINING_PATTERN_2;
838 ret = dw_dp_link_train_set_pattern(dp, pattern);
839 if (ret)
840 return ret;
841
842 for (tries = 1; tries < 5; tries++) {
843 ret = dw_dp_link_train_update_vs_emph(dp);
844 if (ret)
845 return ret;
846
847 drm_dp_link_train_channel_eq_delay(&dp->aux, link->dpcd);
848
849 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
850 if (ret < 0)
851 return ret;
852
853 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
854 dev_err(dp->dev, "clock recovery lost while equalizing channel\n");
855 link->train.clock_recovered = false;
856 break;
857 }
858
859 if (drm_dp_channel_eq_ok(status, link->lanes)) {
860 link->train.channel_equalized = true;
861 break;
862 }
863
864 dw_dp_link_get_adjustments(link, status);
865 }
866
867 return 0;
868 }
869
dw_dp_link_downgrade(struct dw_dp * dp)870 static int dw_dp_link_downgrade(struct dw_dp *dp)
871 {
872 struct dw_dp_link *link = &dp->link;
873 struct dw_dp_bridge_state *state;
874
875 state = dw_dp_get_bridge_state(dp);
876
877 switch (link->rate) {
878 case 162000:
879 return -EINVAL;
880 case 270000:
881 link->rate = 162000;
882 break;
883 case 540000:
884 link->rate = 270000;
885 break;
886 case 810000:
887 link->rate = 540000;
888 break;
889 }
890
891 if (!dw_dp_bandwidth_ok(dp, &state->mode, state->bpp, link->lanes,
892 link->rate))
893 return -E2BIG;
894
895 return 0;
896 }
897
dw_dp_link_train_full(struct dw_dp * dp)898 static int dw_dp_link_train_full(struct dw_dp *dp)
899 {
900 struct dw_dp_link *link = &dp->link;
901 int ret;
902
903 retry:
904 dw_dp_link_train_init(&link->train);
905
906 dev_dbg(dp->dev, "full-training link: %u lane%s at %u MHz\n",
907 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100);
908
909 ret = dw_dp_link_configure(dp);
910 if (ret < 0) {
911 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
912 return ret;
913 }
914
915 ret = dw_dp_link_clock_recovery(dp);
916 if (ret < 0) {
917 dev_err(dp->dev, "clock recovery failed: %d\n", ret);
918 goto out;
919 }
920
921 if (!link->train.clock_recovered) {
922 dev_err(dp->dev, "clock recovery failed, downgrading link\n");
923
924 ret = dw_dp_link_downgrade(dp);
925 if (ret < 0)
926 goto out;
927 else
928 goto retry;
929 }
930
931 dev_dbg(dp->dev, "clock recovery succeeded\n");
932
933 ret = dw_dp_link_channel_equalization(dp);
934 if (ret < 0) {
935 dev_err(dp->dev, "channel equalization failed: %d\n", ret);
936 goto out;
937 }
938
939 if (!link->train.channel_equalized) {
940 dev_err(dp->dev, "channel equalization failed, downgrading link\n");
941
942 ret = dw_dp_link_downgrade(dp);
943 if (ret < 0)
944 goto out;
945 else
946 goto retry;
947 }
948
949 dev_dbg(dp->dev, "channel equalization succeeded\n");
950
951 out:
952 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
953 return ret;
954 }
955
dw_dp_link_train_fast(struct dw_dp * dp)956 static int dw_dp_link_train_fast(struct dw_dp *dp)
957 {
958 struct dw_dp_link *link = &dp->link;
959 int ret;
960 u8 status[DP_LINK_STATUS_SIZE];
961 u8 pattern;
962
963 dw_dp_link_train_init(&link->train);
964
965 dev_dbg(dp->dev, "fast-training link: %u lane%s at %u MHz\n",
966 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100);
967
968 ret = dw_dp_link_configure(dp);
969 if (ret < 0) {
970 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
971 return ret;
972 }
973
974 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
975 if (ret)
976 goto out;
977
978 usleep_range(500, 1000);
979
980 if (link->caps.tps4_supported)
981 pattern = DP_TRAINING_PATTERN_4;
982 else if (link->caps.tps3_supported)
983 pattern = DP_TRAINING_PATTERN_3;
984 else
985 pattern = DP_TRAINING_PATTERN_2;
986 ret = dw_dp_link_train_set_pattern(dp, pattern);
987 if (ret)
988 goto out;
989
990 usleep_range(500, 1000);
991
992 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
993 if (ret < 0) {
994 dev_err(dp->dev, "failed to read link status: %d\n", ret);
995 goto out;
996 }
997
998 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
999 dev_err(dp->dev, "clock recovery failed\n");
1000 ret = -EIO;
1001 goto out;
1002 }
1003
1004 if (!drm_dp_channel_eq_ok(status, link->lanes)) {
1005 dev_err(dp->dev, "channel equalization failed\n");
1006 ret = -EIO;
1007 goto out;
1008 }
1009
1010 out:
1011 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1012 return ret;
1013 }
1014
dw_dp_link_train(struct dw_dp * dp)1015 static int dw_dp_link_train(struct dw_dp *dp)
1016 {
1017 struct dw_dp_link *link = &dp->link;
1018 int ret;
1019
1020 if (link->caps.fast_training) {
1021 if (dw_dp_link_train_valid(&link->train)) {
1022 ret = dw_dp_link_train_fast(dp);
1023 if (ret < 0)
1024 dev_err(dp->dev, "fast link training failed: %d\n", ret);
1025 else
1026 return 0;
1027 }
1028 }
1029
1030 ret = dw_dp_link_train_full(dp);
1031 if (ret < 0) {
1032 dev_err(dp->dev, "full link training failed: %d\n", ret);
1033 return ret;
1034 }
1035
1036 return 0;
1037 }
1038
dw_dp_send_sdp(struct dw_dp * dp,struct dw_dp_sdp * sdp)1039 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp)
1040 {
1041 const u8 *payload = sdp->base.db;
1042 u32 reg;
1043 int i, nr;
1044
1045 nr = find_first_zero_bit(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1046 if (nr < SDP_REG_BANK_SIZE)
1047 set_bit(nr, dp->sdp_reg_bank);
1048 else
1049 return -EBUSY;
1050
1051 reg = DW_DP_SDP_REGISTER_BANK + nr * 9 * 4;
1052
1053 /* SDP header */
1054 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->base.sdp_header));
1055
1056 /* SDP data payload */
1057 for (i = 1; i < 9; i++, payload += 4)
1058 regmap_write(dp->regmap, reg + i * 4,
1059 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload)));
1060
1061 if (sdp->flags & DW_DP_SDP_VERTICAL_INTERVAL)
1062 regmap_update_bits(dp->regmap, DW_DP_SDP_VERTICAL_CTRL,
1063 EN_VERTICAL_SDP << nr,
1064 EN_VERTICAL_SDP << nr);
1065
1066 if (sdp->flags & DW_DP_SDP_HORIZONTAL_INTERVAL)
1067 regmap_update_bits(dp->regmap, DW_DP_SDP_HORIZONTAL_CTRL,
1068 EN_HORIZONTAL_SDP << nr,
1069 EN_HORIZONTAL_SDP << nr);
1070
1071 return 0;
1072 }
1073
dw_dp_send_vsc_sdp(struct dw_dp * dp)1074 static int dw_dp_send_vsc_sdp(struct dw_dp *dp)
1075 {
1076 struct dw_dp_bridge_state *state;
1077 struct dw_dp_sdp sdp = {};
1078 struct drm_dp_vsc_sdp vsc = {};
1079
1080 state = dw_dp_get_bridge_state(dp);
1081 if (!state)
1082 return -EINVAL;
1083
1084 vsc.bpc = state->bpc;
1085
1086 vsc.sdp_type = DP_SDP_VSC;
1087 vsc.revision = 0x5;
1088 vsc.length = 0x13;
1089 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1090
1091 sdp.flags = DW_DP_SDP_VERTICAL_INTERVAL;
1092
1093 switch (state->color_format) {
1094 case DRM_OUTPUT_COLOR_FORMAT_YCBCR444:
1095 vsc.pixelformat = DP_PIXELFORMAT_YUV444;
1096 break;
1097 case DRM_OUTPUT_COLOR_FORMAT_YCBCR420:
1098 vsc.pixelformat = DP_PIXELFORMAT_YUV420;
1099 break;
1100 case DRM_OUTPUT_COLOR_FORMAT_YCBCR422:
1101 vsc.pixelformat = DP_PIXELFORMAT_YUV422;
1102 break;
1103 case DRM_OUTPUT_COLOR_FORMAT_RGB444:
1104 default:
1105 vsc.pixelformat = DP_PIXELFORMAT_RGB;
1106 break;
1107 }
1108
1109 if (state->color_format == DRM_OUTPUT_COLOR_FORMAT_RGB444) {
1110 vsc.colorimetry = DP_COLORIMETRY_DEFAULT;
1111 vsc.dynamic_range = DP_DYNAMIC_RANGE_VESA;
1112 } else {
1113 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC;
1114 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA;
1115 }
1116
1117 drm_dp_vsc_sdp_pack(&vsc, &sdp.base);
1118
1119 return dw_dp_send_sdp(dp, &sdp);
1120 }
1121
dw_dp_video_set_pixel_mode(struct dw_dp * dp)1122 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp)
1123 {
1124 switch (dp->pixel_mode) {
1125 case DW_DP_MP_SINGLE_PIXEL:
1126 case DW_DP_MP_DUAL_PIXEL:
1127 case DW_DP_MP_QUAD_PIXEL:
1128 break;
1129 default:
1130 return -EINVAL;
1131 }
1132
1133 regmap_update_bits(dp->regmap, DW_DP_VSAMPLE_CTRL, PIXEL_MODE_SELECT,
1134 FIELD_PREP(PIXEL_MODE_SELECT, dp->pixel_mode));
1135
1136 return 0;
1137 }
1138
dw_dp_video_need_vsc_sdp(struct dw_dp * dp)1139 static bool dw_dp_video_need_vsc_sdp(struct dw_dp *dp)
1140 {
1141 struct dw_dp_link *link = &dp->link;
1142 struct dw_dp_bridge_state *state;
1143
1144 state = dw_dp_get_bridge_state(dp);
1145 if (!state)
1146 return -EINVAL;
1147
1148 if (!link->vsc_sdp_supported)
1149 return false;
1150
1151 if (state->color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
1152 return true;
1153
1154 return false;
1155 }
1156
dw_dp_video_set_msa(struct dw_dp * dp,enum drm_output_color_format color_format,u8 bpc,u16 vstart,u16 hstart)1157 static int dw_dp_video_set_msa(struct dw_dp *dp,
1158 enum drm_output_color_format color_format,
1159 u8 bpc, u16 vstart, u16 hstart)
1160 {
1161 u16 misc = 0;
1162
1163 if (dw_dp_video_need_vsc_sdp(dp))
1164 misc |= DP_MSA_MISC_COLOR_VSC_SDP;
1165
1166 switch (color_format) {
1167 case DRM_OUTPUT_COLOR_FORMAT_RGB444:
1168 misc |= DP_MSA_MISC_COLOR_RGB;
1169 break;
1170 case DRM_OUTPUT_COLOR_FORMAT_YCBCR444:
1171 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1172 break;
1173 case DRM_OUTPUT_COLOR_FORMAT_YCBCR422:
1174 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709;
1175 break;
1176 case DRM_OUTPUT_COLOR_FORMAT_YCBCR420:
1177 break;
1178 default:
1179 return -EINVAL;
1180 }
1181
1182 switch (bpc) {
1183 case 6:
1184 misc |= DP_MSA_MISC_6_BPC;
1185 break;
1186 case 8:
1187 misc |= DP_MSA_MISC_8_BPC;
1188 break;
1189 case 10:
1190 misc |= DP_MSA_MISC_10_BPC;
1191 break;
1192 case 12:
1193 misc |= DP_MSA_MISC_12_BPC;
1194 break;
1195 case 16:
1196 misc |= DP_MSA_MISC_16_BPC;
1197 break;
1198 default:
1199 return -EINVAL;
1200 }
1201
1202 regmap_write(dp->regmap, DW_DP_VIDEO_MSA1,
1203 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart));
1204 regmap_write(dp->regmap, DW_DP_VIDEO_MSA2, FIELD_PREP(MISC0, misc));
1205 regmap_write(dp->regmap, DW_DP_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8));
1206
1207 return 0;
1208 }
1209
dw_dp_video_disable(struct dw_dp * dp)1210 static void dw_dp_video_disable(struct dw_dp *dp)
1211 {
1212 regmap_update_bits(dp->regmap, DW_DP_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,
1213 FIELD_PREP(VIDEO_STREAM_ENABLE, 0));
1214 }
1215
dw_dp_video_enable(struct dw_dp * dp)1216 static int dw_dp_video_enable(struct dw_dp *dp)
1217 {
1218 struct dw_dp_link *link = &dp->link;
1219 struct dw_dp_bridge_state *state;
1220 struct drm_display_mode *mode;
1221 u8 color_format, bpc, bpp;
1222 u8 init_threshold, vic;
1223 u32 hstart, hactive, hblank, h_sync_width, h_front_porch;
1224 u32 vstart, vactive, vblank, v_sync_width, v_front_porch;
1225 u32 peak_stream_bandwidth, link_bandwidth;
1226 u32 average_bytes_per_tu, average_bytes_per_tu_frac;
1227 u32 ts, hblank_interval;
1228 u32 value;
1229 int ret;
1230
1231 state = dw_dp_get_bridge_state(dp);
1232 if (!state)
1233 return -EINVAL;
1234
1235 bpc = state->bpc;
1236 bpp = state->bpp;
1237 color_format = state->color_format;
1238 mode = &state->mode;
1239
1240 vstart = mode->vtotal - mode->vsync_start;
1241 hstart = mode->htotal - mode->hsync_start;
1242
1243 ret = dw_dp_video_set_pixel_mode(dp);
1244 if (ret)
1245 return ret;
1246
1247 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart);
1248 if (ret)
1249 return ret;
1250
1251 regmap_update_bits(dp->regmap, DW_DP_VSAMPLE_CTRL, VIDEO_MAPPING,
1252 FIELD_PREP(VIDEO_MAPPING, state->video_mapping));
1253
1254 /* Configure DW_DP_VINPUT_POLARITY_CTRL register */
1255 value = 0;
1256 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1257 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1);
1258 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1259 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1);
1260 regmap_write(dp->regmap, DW_DP_VINPUT_POLARITY_CTRL, value);
1261
1262 /* Configure DW_DP_VIDEO_CONFIG1 register */
1263 hactive = mode->hdisplay;
1264 hblank = mode->htotal - mode->hdisplay;
1265 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank);
1266 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1267 value |= FIELD_PREP(I_P, 1);
1268 vic = drm_match_cea_mode(mode);
1269 if (vic == 5 || vic == 6 || vic == 7 ||
1270 vic == 10 || vic == 11 || vic == 20 ||
1271 vic == 21 || vic == 22 || vic == 39 ||
1272 vic == 25 || vic == 26 || vic == 40 ||
1273 vic == 44 || vic == 45 || vic == 46 ||
1274 vic == 50 || vic == 51 || vic == 54 ||
1275 vic == 55 || vic == 58 || vic == 59)
1276 value |= R_V_BLANK_IN_OSC;
1277 regmap_write(dp->regmap, DW_DP_VIDEO_CONFIG1, value);
1278
1279 /* Configure DW_DP_VIDEO_CONFIG2 register */
1280 vblank = mode->vtotal - mode->vdisplay;
1281 vactive = mode->vdisplay;
1282 regmap_write(dp->regmap, DW_DP_VIDEO_CONFIG2,
1283 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive));
1284
1285 /* Configure DW_DP_VIDEO_CONFIG3 register */
1286 h_sync_width = mode->hsync_end - mode->hsync_start;
1287 h_front_porch = mode->hsync_start - mode->hdisplay;
1288 regmap_write(dp->regmap, DW_DP_VIDEO_CONFIG3,
1289 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) |
1290 FIELD_PREP(H_FRONT_PORCH, h_front_porch));
1291
1292 /* Configure DW_DP_VIDEO_CONFIG4 register */
1293 v_sync_width = mode->vsync_end - mode->vsync_start;
1294 v_front_porch = mode->vsync_start - mode->vdisplay;
1295 regmap_write(dp->regmap, DW_DP_VIDEO_CONFIG4,
1296 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) |
1297 FIELD_PREP(V_FRONT_PORCH, v_front_porch));
1298
1299 /* Configure DW_DP_VIDEO_CONFIG5 register */
1300 peak_stream_bandwidth = mode->clock * bpp / 8;
1301 link_bandwidth = (link->rate / 1000) * link->lanes;
1302 ts = peak_stream_bandwidth * 64 / link_bandwidth;
1303 average_bytes_per_tu = ts / 1000;
1304 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10;
1305 if (dp->pixel_mode == DW_DP_MP_SINGLE_PIXEL) {
1306 if (average_bytes_per_tu < 6)
1307 init_threshold = 32;
1308 else if (hblank <= 80 && color_format != DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
1309 init_threshold = 12;
1310 else if (hblank <= 40 && color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
1311 init_threshold = 3;
1312 else
1313 init_threshold = 16;
1314 } else {
1315 u32 t1 = 0, t2 = 0, t3 = 0;
1316
1317 switch (bpc) {
1318 case 6:
1319 t1 = (4 * 1000 / 9) * link->lanes;
1320 break;
1321 case 8:
1322 if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422) {
1323 t1 = (1000 / 2) * link->lanes;
1324 } else {
1325 if (dp->pixel_mode == DW_DP_MP_DUAL_PIXEL)
1326 t1 = (1000 / 3) * link->lanes;
1327 else
1328 t1 = (3000 / 16) * link->lanes;
1329 }
1330 break;
1331 case 10:
1332 if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422)
1333 t1 = (2000 / 5) * link->lanes;
1334 else
1335 t1 = (4000 / 15) * link->lanes;
1336 break;
1337 case 12:
1338 if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422) {
1339 if (dp->pixel_mode == DW_DP_MP_DUAL_PIXEL)
1340 t1 = (1000 / 6) * link->lanes;
1341 else
1342 t1 = (1000 / 3) * link->lanes;
1343 } else {
1344 t1 = (2000 / 9) * link->lanes;
1345 }
1346 break;
1347 case 16:
1348 if (color_format != DRM_OUTPUT_COLOR_FORMAT_YCBCR422 &&
1349 dp->pixel_mode == DW_DP_MP_DUAL_PIXEL)
1350 t1 = (1000 / 6) * link->lanes;
1351 else
1352 t1 = (1000 / 4) * link->lanes;
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357
1358 if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
1359 t2 = (link->rate / 4) * 1000 / (mode->clock / 2);
1360 else
1361 t2 = (link->rate / 4) * 1000 / mode->clock;
1362
1363 if (average_bytes_per_tu_frac)
1364 t3 = average_bytes_per_tu + 1;
1365 else
1366 t3 = average_bytes_per_tu;
1367 init_threshold = t1 * t2 * t3 / (1000 * 1000);
1368 if (init_threshold <= 16 || average_bytes_per_tu < 10)
1369 init_threshold = 40;
1370 }
1371
1372 regmap_write(dp->regmap, DW_DP_VIDEO_CONFIG5,
1373 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) |
1374 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, average_bytes_per_tu_frac) |
1375 FIELD_PREP(INIT_THRESHOLD, init_threshold) |
1376 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu));
1377
1378 /* Configure DW_DP_VIDEO_HBLANK_INTERVAL register */
1379 hblank_interval = hblank * (link->rate / 4) / mode->clock;
1380 regmap_write(dp->regmap, DW_DP_VIDEO_HBLANK_INTERVAL,
1381 FIELD_PREP(HBLANK_INTERVAL_EN, 1) |
1382 FIELD_PREP(HBLANK_INTERVAL, hblank_interval));
1383
1384 /* Video stream enable */
1385 regmap_update_bits(dp->regmap, DW_DP_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,
1386 FIELD_PREP(VIDEO_STREAM_ENABLE, 1));
1387
1388 if (dw_dp_video_need_vsc_sdp(dp))
1389 dw_dp_send_vsc_sdp(dp);
1390
1391 return 0;
1392 }
1393
dw_dp_hpd_init(struct dw_dp * dp)1394 static void dw_dp_hpd_init(struct dw_dp *dp)
1395 {
1396 /* Enable all HPD interrupts */
1397 regmap_update_bits(dp->regmap, DW_DP_HPD_INTERRUPT_ENABLE,
1398 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN,
1399 FIELD_PREP(HPD_UNPLUG_EN, 1) |
1400 FIELD_PREP(HPD_PLUG_EN, 1) |
1401 FIELD_PREP(HPD_IRQ_EN, 1));
1402
1403 /* Enable all top-level interrupts */
1404 regmap_update_bits(dp->regmap, DW_DP_GENERAL_INTERRUPT_ENABLE,
1405 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1));
1406 }
1407
dw_dp_aux_init(struct dw_dp * dp)1408 static void dw_dp_aux_init(struct dw_dp *dp)
1409 {
1410 regmap_update_bits(dp->regmap, DW_DP_GENERAL_INTERRUPT_ENABLE,
1411 AUX_REPLY_EVENT_EN, FIELD_PREP(AUX_REPLY_EVENT_EN, 1));
1412 }
1413
dw_dp_init_hw(struct dw_dp * dp)1414 static void dw_dp_init_hw(struct dw_dp *dp)
1415 {
1416 regmap_update_bits(dp->regmap, DW_DP_CCTL, DEFAULT_FAST_LINK_TRAIN_EN,
1417 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0));
1418
1419 dw_dp_hpd_init(dp);
1420 dw_dp_aux_init(dp);
1421 }
1422
dw_dp_aux_write_data(struct dw_dp * dp,const u8 * buffer,size_t size)1423 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size)
1424 {
1425 size_t i, j;
1426
1427 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
1428 size_t num = min_t(size_t, size - i * 4, 4);
1429 u32 value = 0;
1430
1431 for (j = 0; j < num; j++)
1432 value |= buffer[i * 4 + j] << (j * 8);
1433
1434 regmap_write(dp->regmap, DW_DP_AUX_DATA0 + i * 4, value);
1435 }
1436
1437 return size;
1438 }
1439
dw_dp_aux_read_data(struct dw_dp * dp,u8 * buffer,size_t size)1440 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size)
1441 {
1442 size_t i, j;
1443
1444 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
1445 size_t num = min_t(size_t, size - i * 4, 4);
1446 u32 value;
1447
1448 regmap_read(dp->regmap, DW_DP_AUX_DATA0 + i * 4, &value);
1449
1450 for (j = 0; j < num; j++)
1451 buffer[i * 4 + j] = value >> (j * 8);
1452 }
1453
1454 return size;
1455 }
1456
dw_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1457 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux,
1458 struct drm_dp_aux_msg *msg)
1459 {
1460 struct dw_dp *dp = container_of(aux, struct dw_dp, aux);
1461 unsigned long timeout = msecs_to_jiffies(10);
1462 u32 status, value;
1463 ssize_t ret = 0;
1464
1465 if (WARN_ON(msg->size > 16))
1466 return -E2BIG;
1467
1468 switch (msg->request & ~DP_AUX_I2C_MOT) {
1469 case DP_AUX_NATIVE_WRITE:
1470 case DP_AUX_I2C_WRITE:
1471 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1472 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size);
1473 if (ret < 0)
1474 return ret;
1475 break;
1476 case DP_AUX_NATIVE_READ:
1477 case DP_AUX_I2C_READ:
1478 break;
1479 default:
1480 return -EINVAL;
1481 }
1482
1483 if (msg->size > 0)
1484 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1);
1485 else
1486 value = FIELD_PREP(I2C_ADDR_ONLY, 1);
1487 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request);
1488 value |= FIELD_PREP(AUX_ADDR, msg->address);
1489 regmap_write(dp->regmap, DW_DP_AUX_CMD, value);
1490
1491 status = wait_for_completion_timeout(&dp->complete, timeout);
1492 if (!status) {
1493 dev_err(dp->dev, "timeout waiting for AUX reply\n");
1494 return -ETIMEDOUT;
1495 }
1496
1497 regmap_read(dp->regmap, DW_DP_AUX_STATUS, &value);
1498 if (value & AUX_TIMEOUT)
1499 return -ETIMEDOUT;
1500
1501 msg->reply = FIELD_GET(AUX_STATUS, value);
1502
1503 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) {
1504 if (msg->request & DP_AUX_I2C_READ) {
1505 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1;
1506
1507 if (count != msg->size)
1508 return -EBUSY;
1509
1510 ret = dw_dp_aux_read_data(dp, msg->buffer, count);
1511 if (ret < 0)
1512 return ret;
1513 }
1514 }
1515
1516 return ret;
1517 }
1518
1519 /*
1520 * Limits for the video timing for DP:
1521 * 1. the hfp should be 2 pixels aligned;
1522 * 2. the minimum hsync should be 9 pixel;
1523 * 3. the minimum hbp should be 16 pixel;
1524 */
dw_dp_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1525 static int dw_dp_bridge_atomic_check(struct drm_bridge *bridge,
1526 struct drm_bridge_state *bridge_state,
1527 struct drm_crtc_state *crtc_state,
1528 struct drm_connector_state *conn_state)
1529 {
1530 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1531 struct dw_dp *dp = bridge_to_dp(bridge);
1532 struct dw_dp_bridge_state *state;
1533 const struct dw_dp_output_format *fmt;
1534 struct drm_display_mode *mode;
1535 int min_hbp = 16;
1536 int min_hsync = 9;
1537
1538 state = to_dw_dp_bridge_state(bridge_state);
1539 mode = &state->mode;
1540
1541 fmt = dw_dp_get_output_format(bridge_state->output_bus_cfg.format);
1542 if (!fmt)
1543 return -EINVAL;
1544
1545 state->video_mapping = fmt->video_mapping;
1546 state->color_format = fmt->color_format;
1547 state->bpc = fmt->bpc;
1548 state->bpp = fmt->bpp;
1549
1550 if ((adjusted_mode->hsync_start - adjusted_mode->hdisplay) & 0x1) {
1551 adjusted_mode->hsync_start += 1;
1552 dev_warn(dp->dev, "hfp is not 2 pixeel aligned, fixup to aligned hfp\n");
1553 }
1554
1555 if (adjusted_mode->hsync_end - adjusted_mode->hsync_start < min_hsync) {
1556 adjusted_mode->hsync_end = adjusted_mode->hsync_start + min_hsync;
1557 dev_warn(dp->dev, "hsync is too narrow, fixup to min hsync:%d\n", min_hsync);
1558 }
1559
1560 if (adjusted_mode->htotal - adjusted_mode->hsync_end < min_hbp) {
1561 adjusted_mode->htotal = adjusted_mode->hsync_end + min_hbp;
1562 dev_warn(dp->dev, "hbp is too narrow, fixup to min hbp:%d\n", min_hbp);
1563 }
1564
1565 drm_mode_copy(mode, adjusted_mode);
1566
1567 return 0;
1568 }
1569
dw_dp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1570 static enum drm_mode_status dw_dp_bridge_mode_valid(struct drm_bridge *bridge,
1571 const struct drm_display_info *info,
1572 const struct drm_display_mode *mode)
1573 {
1574 struct dw_dp *dp = bridge_to_dp(bridge);
1575 struct dw_dp_link *link = &dp->link;
1576 u32 min_bpp;
1577
1578 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420) &&
1579 link->vsc_sdp_supported &&
1580 (drm_mode_is_420_only(info, mode) || drm_mode_is_420_also(info, mode)))
1581 min_bpp = 12;
1582 else if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422))
1583 min_bpp = 16;
1584 else if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444))
1585 min_bpp = 18;
1586 else
1587 min_bpp = 24;
1588
1589 if (!link->vsc_sdp_supported &&
1590 drm_mode_is_420_only(info, mode))
1591 return MODE_NO_420;
1592
1593 if (!dw_dp_bandwidth_ok(dp, mode, min_bpp, link->lanes, link->rate))
1594 return MODE_CLOCK_HIGH;
1595
1596 return MODE_OK;
1597 }
1598
dw_dp_needs_link_retrain(struct dw_dp * dp)1599 static bool dw_dp_needs_link_retrain(struct dw_dp *dp)
1600 {
1601 struct dw_dp_link *link = &dp->link;
1602 u8 link_status[DP_LINK_STATUS_SIZE];
1603
1604 if (!dw_dp_link_train_valid(&link->train))
1605 return false;
1606
1607 if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) < 0)
1608 return false;
1609
1610 /* Retrain if Channel EQ or CR not ok */
1611 return !drm_dp_channel_eq_ok(link_status, dp->link.lanes);
1612 }
1613
dw_dp_link_disable(struct dw_dp * dp)1614 static void dw_dp_link_disable(struct dw_dp *dp)
1615 {
1616 struct dw_dp_link *link = &dp->link;
1617
1618 if (dw_dp_hpd_detect(dp))
1619 drm_dp_link_power_down(&dp->aux, dp->link.revision);
1620
1621 dw_dp_phy_xmit_enable(dp, 0);
1622
1623 phy_power_off(dp->phy);
1624
1625 link->train.clock_recovered = false;
1626 link->train.channel_equalized = false;
1627 }
1628
dw_dp_link_enable(struct dw_dp * dp)1629 static int dw_dp_link_enable(struct dw_dp *dp)
1630 {
1631 int ret;
1632
1633 ret = phy_power_on(dp->phy);
1634 if (ret)
1635 return ret;
1636
1637 ret = drm_dp_link_power_up(&dp->aux, dp->link.revision);
1638 if (ret < 0)
1639 return ret;
1640
1641 ret = dw_dp_link_train(dp);
1642
1643 return ret;
1644 }
1645
dw_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1646 static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1647 struct drm_atomic_state *state)
1648 {
1649 struct dw_dp *dp = bridge_to_dp(bridge);
1650 struct drm_connector *connector;
1651 struct drm_connector_state *conn_state;
1652 int ret;
1653
1654 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
1655 if (!connector) {
1656 dev_err(dp->dev, "failed to get connector\n");
1657 return;
1658 }
1659
1660 conn_state = drm_atomic_get_new_connector_state(state, connector);
1661 if (!conn_state) {
1662 dev_err(dp->dev, "failed to get connector state\n");
1663 return;
1664 }
1665
1666 set_bit(0, dp->sdp_reg_bank);
1667
1668 ret = dw_dp_link_enable(dp);
1669 if (ret < 0) {
1670 dev_err(dp->dev, "failed to enable link: %d\n", ret);
1671 return;
1672 }
1673
1674 ret = dw_dp_video_enable(dp);
1675 if (ret < 0) {
1676 dev_err(dp->dev, "failed to enable video: %d\n", ret);
1677 return;
1678 }
1679 }
1680
dw_dp_reset(struct dw_dp * dp)1681 static void dw_dp_reset(struct dw_dp *dp)
1682 {
1683 int val;
1684
1685 disable_irq(dp->irq);
1686 regmap_update_bits(dp->regmap, DW_DP_SOFT_RESET_CTRL, CONTROLLER_RESET,
1687 FIELD_PREP(CONTROLLER_RESET, 1));
1688 usleep_range(10, 20);
1689 regmap_update_bits(dp->regmap, DW_DP_SOFT_RESET_CTRL, CONTROLLER_RESET,
1690 FIELD_PREP(CONTROLLER_RESET, 0));
1691
1692 dw_dp_init_hw(dp);
1693 regmap_read_poll_timeout(dp->regmap, DW_DP_HPD_STATUS, val,
1694 FIELD_GET(HPD_HOT_PLUG, val), 200, 200000);
1695 regmap_write(dp->regmap, DW_DP_HPD_STATUS, HPD_HOT_PLUG);
1696 enable_irq(dp->irq);
1697 }
1698
dw_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1699 static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1700 struct drm_atomic_state *state)
1701 {
1702 struct dw_dp *dp = bridge_to_dp(bridge);
1703
1704 dw_dp_video_disable(dp);
1705 dw_dp_link_disable(dp);
1706 bitmap_zero(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1707 dw_dp_reset(dp);
1708 }
1709
dw_dp_hpd_detect_link(struct dw_dp * dp,struct drm_connector * connector)1710 static bool dw_dp_hpd_detect_link(struct dw_dp *dp, struct drm_connector *connector)
1711 {
1712 int ret;
1713
1714 ret = phy_power_on(dp->phy);
1715 if (ret < 0)
1716 return false;
1717 ret = dw_dp_link_parse(dp, connector);
1718 phy_power_off(dp->phy);
1719
1720 return !ret;
1721 }
1722
dw_dp_bridge_detect(struct drm_bridge * bridge,struct drm_connector * connector)1723 static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge,
1724 struct drm_connector *connector)
1725 {
1726 struct dw_dp *dp = bridge_to_dp(bridge);
1727
1728 if (!dw_dp_hpd_detect(dp))
1729 return connector_status_disconnected;
1730
1731 if (!dw_dp_hpd_detect_link(dp, connector))
1732 return connector_status_disconnected;
1733
1734 return connector_status_connected;
1735 }
1736
dw_dp_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)1737 static const struct drm_edid *dw_dp_bridge_edid_read(struct drm_bridge *bridge,
1738 struct drm_connector *connector)
1739 {
1740 struct dw_dp *dp = bridge_to_dp(bridge);
1741 const struct drm_edid *edid;
1742 int ret;
1743
1744 ret = phy_power_on(dp->phy);
1745 if (ret)
1746 return NULL;
1747
1748 edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
1749
1750 phy_power_off(dp->phy);
1751
1752 return edid;
1753 }
1754
dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)1755 static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
1756 struct drm_bridge_state *bridge_state,
1757 struct drm_crtc_state *crtc_state,
1758 struct drm_connector_state *conn_state,
1759 unsigned int *num_output_fmts)
1760 {
1761 struct dw_dp *dp = bridge_to_dp(bridge);
1762 struct dw_dp_link *link = &dp->link;
1763 struct drm_display_info *di = &conn_state->connector->display_info;
1764 struct drm_display_mode mode = crtc_state->mode;
1765 const struct dw_dp_output_format *fmt;
1766 u32 i, j = 0;
1767 u32 *output_fmts;
1768
1769 *num_output_fmts = 0;
1770
1771 output_fmts = kcalloc(ARRAY_SIZE(dw_dp_output_formats), sizeof(*output_fmts), GFP_KERNEL);
1772 if (!output_fmts)
1773 return NULL;
1774
1775 for (i = 0; i < ARRAY_SIZE(dw_dp_output_formats); i++) {
1776 fmt = &dw_dp_output_formats[i];
1777
1778 if (fmt->bpc > conn_state->max_bpc)
1779 continue;
1780
1781 if (!(BIT(fmt->color_format) & di->color_formats))
1782 continue;
1783
1784 if (fmt->color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420 &&
1785 !link->vsc_sdp_supported)
1786 continue;
1787
1788 if (fmt->color_format != DRM_OUTPUT_COLOR_FORMAT_YCBCR420 &&
1789 drm_mode_is_420_only(di, &mode))
1790 continue;
1791
1792 if (!dw_dp_bandwidth_ok(dp, &mode, fmt->bpp, link->lanes, link->rate))
1793 continue;
1794
1795 output_fmts[j++] = fmt->bus_format;
1796 }
1797
1798 *num_output_fmts = j;
1799
1800 return output_fmts;
1801 }
1802
dw_dp_bridge_atomic_duplicate_state(struct drm_bridge * bridge)1803 static struct drm_bridge_state *dw_dp_bridge_atomic_duplicate_state(struct drm_bridge *bridge)
1804 {
1805 struct dw_dp_bridge_state *state;
1806
1807 state = kzalloc_obj(*state);
1808 if (!state)
1809 return NULL;
1810
1811 __drm_atomic_helper_bridge_duplicate_state(bridge, &state->base);
1812
1813 return &state->base;
1814 }
1815
1816 static const struct drm_bridge_funcs dw_dp_bridge_funcs = {
1817 .atomic_duplicate_state = dw_dp_bridge_atomic_duplicate_state,
1818 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1819 .atomic_reset = drm_atomic_helper_bridge_reset,
1820 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
1821 .atomic_get_output_bus_fmts = dw_dp_bridge_atomic_get_output_bus_fmts,
1822 .atomic_check = dw_dp_bridge_atomic_check,
1823 .mode_valid = dw_dp_bridge_mode_valid,
1824 .atomic_enable = dw_dp_bridge_atomic_enable,
1825 .atomic_disable = dw_dp_bridge_atomic_disable,
1826 .detect = dw_dp_bridge_detect,
1827 .edid_read = dw_dp_bridge_edid_read,
1828 };
1829
dw_dp_link_retrain(struct dw_dp * dp)1830 static int dw_dp_link_retrain(struct dw_dp *dp)
1831 {
1832 struct drm_device *dev = dp->bridge.dev;
1833 struct drm_modeset_acquire_ctx ctx;
1834 int ret;
1835
1836 if (!dw_dp_needs_link_retrain(dp))
1837 return 0;
1838
1839 dev_dbg(dp->dev, "Retraining link\n");
1840
1841 drm_modeset_acquire_init(&ctx, 0);
1842 for (;;) {
1843 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1844 if (ret != -EDEADLK)
1845 break;
1846
1847 drm_modeset_backoff(&ctx);
1848 }
1849
1850 if (!ret)
1851 ret = dw_dp_link_train(dp);
1852
1853 drm_modeset_drop_locks(&ctx);
1854 drm_modeset_acquire_fini(&ctx);
1855
1856 return ret;
1857 }
1858
dw_dp_hpd_work(struct work_struct * work)1859 static void dw_dp_hpd_work(struct work_struct *work)
1860 {
1861 struct dw_dp *dp = container_of(work, struct dw_dp, hpd_work);
1862 bool long_hpd;
1863 int ret;
1864
1865 mutex_lock(&dp->irq_lock);
1866 long_hpd = dp->hotplug.long_hpd;
1867 mutex_unlock(&dp->irq_lock);
1868
1869 dev_dbg(dp->dev, "[drm] Get hpd irq - %s\n", long_hpd ? "long" : "short");
1870
1871 if (!long_hpd) {
1872 if (dw_dp_needs_link_retrain(dp)) {
1873 ret = dw_dp_link_retrain(dp);
1874 if (ret)
1875 dev_warn(dp->dev, "Retrain link failed\n");
1876 }
1877 } else {
1878 drm_helper_hpd_irq_event(dp->bridge.dev);
1879 }
1880 }
1881
dw_dp_handle_hpd_event(struct dw_dp * dp)1882 static void dw_dp_handle_hpd_event(struct dw_dp *dp)
1883 {
1884 u32 value;
1885
1886 mutex_lock(&dp->irq_lock);
1887 regmap_read(dp->regmap, DW_DP_HPD_STATUS, &value);
1888
1889 if (value & HPD_IRQ) {
1890 dev_dbg(dp->dev, "IRQ from the HPD\n");
1891 dp->hotplug.long_hpd = false;
1892 regmap_write(dp->regmap, DW_DP_HPD_STATUS, HPD_IRQ);
1893 }
1894
1895 if (value & HPD_HOT_PLUG) {
1896 dev_dbg(dp->dev, "Hot plug detected\n");
1897 dp->hotplug.long_hpd = true;
1898 regmap_write(dp->regmap, DW_DP_HPD_STATUS, HPD_HOT_PLUG);
1899 }
1900
1901 if (value & HPD_HOT_UNPLUG) {
1902 dev_dbg(dp->dev, "Unplug detected\n");
1903 dp->hotplug.long_hpd = true;
1904 regmap_write(dp->regmap, DW_DP_HPD_STATUS, HPD_HOT_UNPLUG);
1905 }
1906 mutex_unlock(&dp->irq_lock);
1907
1908 schedule_work(&dp->hpd_work);
1909 }
1910
dw_dp_irq(int irq,void * data)1911 static irqreturn_t dw_dp_irq(int irq, void *data)
1912 {
1913 struct dw_dp *dp = data;
1914 u32 value;
1915
1916 regmap_read(dp->regmap, DW_DP_GENERAL_INTERRUPT, &value);
1917 if (!value)
1918 return IRQ_NONE;
1919
1920 if (value & HPD_EVENT)
1921 dw_dp_handle_hpd_event(dp);
1922
1923 if (value & AUX_REPLY_EVENT) {
1924 regmap_write(dp->regmap, DW_DP_GENERAL_INTERRUPT, AUX_REPLY_EVENT);
1925 complete(&dp->complete);
1926 }
1927
1928 return IRQ_HANDLED;
1929 }
1930
1931 static const struct regmap_range dw_dp_readable_ranges[] = {
1932 regmap_reg_range(DW_DP_VERSION_NUMBER, DW_DP_ID),
1933 regmap_reg_range(DW_DP_CONFIG_REG1, DW_DP_CONFIG_REG3),
1934 regmap_reg_range(DW_DP_CCTL, DW_DP_SOFT_RESET_CTRL),
1935 regmap_reg_range(DW_DP_VSAMPLE_CTRL, DW_DP_VIDEO_HBLANK_INTERVAL),
1936 regmap_reg_range(DW_DP_AUD_CONFIG1, DW_DP_AUD_CONFIG1),
1937 regmap_reg_range(DW_DP_SDP_VERTICAL_CTRL, DW_DP_SDP_STATUS_EN),
1938 regmap_reg_range(DW_DP_PHYIF_CTRL, DW_DP_PHYIF_PWRDOWN_CTRL),
1939 regmap_reg_range(DW_DP_AUX_CMD, DW_DP_AUX_DATA3),
1940 regmap_reg_range(DW_DP_GENERAL_INTERRUPT, DW_DP_HPD_INTERRUPT_ENABLE),
1941 };
1942
1943 static const struct regmap_access_table dw_dp_readable_table = {
1944 .yes_ranges = dw_dp_readable_ranges,
1945 .n_yes_ranges = ARRAY_SIZE(dw_dp_readable_ranges),
1946 };
1947
1948 static const struct regmap_config dw_dp_regmap_config = {
1949 .reg_bits = 32,
1950 .reg_stride = 4,
1951 .val_bits = 32,
1952 .fast_io = true,
1953 .max_register = DW_DP_MAX_REGISTER,
1954 .rd_table = &dw_dp_readable_table,
1955 };
1956
dw_dp_phy_exit(void * data)1957 static void dw_dp_phy_exit(void *data)
1958 {
1959 struct dw_dp *dp = data;
1960
1961 phy_exit(dp->phy);
1962 }
1963
dw_dp_bind(struct device * dev,struct drm_encoder * encoder,const struct dw_dp_plat_data * plat_data)1964 struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
1965 const struct dw_dp_plat_data *plat_data)
1966 {
1967 struct platform_device *pdev = to_platform_device(dev);
1968 struct dw_dp *dp;
1969 struct drm_bridge *bridge;
1970 void __iomem *res;
1971 int ret;
1972
1973 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
1974 if (!dp)
1975 return ERR_PTR(-ENOMEM);
1976
1977 dp = devm_drm_bridge_alloc(dev, struct dw_dp, bridge, &dw_dp_bridge_funcs);
1978 if (IS_ERR(dp))
1979 return ERR_CAST(dp);
1980
1981 dp->dev = dev;
1982 dp->pixel_mode = plat_data->pixel_mode;
1983
1984 dp->plat_data.max_link_rate = plat_data->max_link_rate;
1985 bridge = &dp->bridge;
1986 mutex_init(&dp->irq_lock);
1987 INIT_WORK(&dp->hpd_work, dw_dp_hpd_work);
1988 init_completion(&dp->complete);
1989
1990 res = devm_platform_ioremap_resource(pdev, 0);
1991 if (IS_ERR(res))
1992 return ERR_CAST(res);
1993
1994 dp->regmap = devm_regmap_init_mmio(dev, res, &dw_dp_regmap_config);
1995 if (IS_ERR(dp->regmap)) {
1996 dev_err_probe(dev, PTR_ERR(dp->regmap), "failed to create regmap\n");
1997 return ERR_CAST(dp->regmap);
1998 }
1999
2000 dp->phy = devm_of_phy_get(dev, dev->of_node, NULL);
2001 if (IS_ERR(dp->phy)) {
2002 dev_err_probe(dev, PTR_ERR(dp->phy), "failed to get phy\n");
2003 return ERR_CAST(dp->phy);
2004 }
2005
2006 dp->apb_clk = devm_clk_get_enabled(dev, "apb");
2007 if (IS_ERR(dp->apb_clk)) {
2008 dev_err_probe(dev, PTR_ERR(dp->apb_clk), "failed to get apb clock\n");
2009 return ERR_CAST(dp->apb_clk);
2010 }
2011
2012 dp->aux_clk = devm_clk_get_enabled(dev, "aux");
2013 if (IS_ERR(dp->aux_clk)) {
2014 dev_err_probe(dev, PTR_ERR(dp->aux_clk), "failed to get aux clock\n");
2015 return ERR_CAST(dp->aux_clk);
2016 }
2017
2018 dp->i2s_clk = devm_clk_get_optional(dev, "i2s");
2019 if (IS_ERR(dp->i2s_clk)) {
2020 dev_err_probe(dev, PTR_ERR(dp->i2s_clk), "failed to get i2s clock\n");
2021 return ERR_CAST(dp->i2s_clk);
2022 }
2023
2024 dp->spdif_clk = devm_clk_get_optional(dev, "spdif");
2025 if (IS_ERR(dp->spdif_clk)) {
2026 dev_err_probe(dev, PTR_ERR(dp->spdif_clk), "failed to get spdif clock\n");
2027 return ERR_CAST(dp->spdif_clk);
2028 }
2029
2030 dp->hdcp_clk = devm_clk_get(dev, "hdcp");
2031 if (IS_ERR(dp->hdcp_clk)) {
2032 dev_err_probe(dev, PTR_ERR(dp->hdcp_clk), "failed to get hdcp clock\n");
2033 return ERR_CAST(dp->hdcp_clk);
2034 }
2035
2036 dp->rstc = devm_reset_control_get(dev, NULL);
2037 if (IS_ERR(dp->rstc)) {
2038 dev_err_probe(dev, PTR_ERR(dp->rstc), "failed to get reset control\n");
2039 return ERR_CAST(dp->rstc);
2040 }
2041
2042 bridge->of_node = dev->of_node;
2043 bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
2044 bridge->type = DRM_MODE_CONNECTOR_DisplayPort;
2045 bridge->ycbcr_420_allowed = true;
2046
2047 ret = devm_drm_bridge_add(dev, bridge);
2048 if (ret)
2049 return ERR_PTR(ret);
2050
2051 dp->aux.dev = dev;
2052 dp->aux.drm_dev = encoder->dev;
2053 dp->aux.name = dev_name(dev);
2054 dp->aux.transfer = dw_dp_aux_transfer;
2055 ret = drm_dp_aux_register(&dp->aux);
2056 if (ret) {
2057 dev_err_probe(dev, ret, "Aux register failed\n");
2058 return ERR_PTR(ret);
2059 }
2060
2061 ret = drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2062 if (ret) {
2063 dev_err_probe(dev, ret, "Failed to attach bridge\n");
2064 goto unregister_aux;
2065 }
2066
2067 dw_dp_init_hw(dp);
2068
2069 ret = phy_init(dp->phy);
2070 if (ret) {
2071 dev_err_probe(dev, ret, "phy init failed\n");
2072 goto unregister_aux;
2073 }
2074
2075 ret = devm_add_action_or_reset(dev, dw_dp_phy_exit, dp);
2076 if (ret)
2077 goto unregister_aux;
2078
2079 dp->irq = platform_get_irq(pdev, 0);
2080 if (dp->irq < 0) {
2081 ret = dp->irq;
2082 goto unregister_aux;
2083 }
2084
2085 ret = devm_request_threaded_irq(dev, dp->irq, NULL, dw_dp_irq,
2086 IRQF_ONESHOT, dev_name(dev), dp);
2087 if (ret) {
2088 dev_err_probe(dev, ret, "failed to request irq\n");
2089 goto unregister_aux;
2090 }
2091
2092 return dp;
2093
2094 unregister_aux:
2095 drm_dp_aux_unregister(&dp->aux);
2096 return ERR_PTR(ret);
2097 }
2098 EXPORT_SYMBOL_GPL(dw_dp_bind);
2099
2100 MODULE_AUTHOR("Andy Yan <andyshrk@163.com>");
2101 MODULE_DESCRIPTION("DW DP Core Library");
2102 MODULE_LICENSE("GPL");
2103